Integrated chip

Abstract

The utility model provides an integrated chip comprising a test line structure arranged on a semiconductor workpiece. The test line structure includes a plurality of optical input / output (I / O) structures disposed within and / or on the semiconductor workpiece. The test line structure further includes a plurality of electrical input / output structures on the semiconductor workpiece. The plurality of optical input / output structures and the plurality of electrical input / output structures are laterally spaced apart from each other along a line extending in a first direction.

Description

Technical Field

[0001] The utility model relates to an integrated chip. Background Art

[0002] Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor workpiece (e.g., a silicon substrate). Before the semiconductor workpiece is packaged, the semiconductor devices on the workpiece are tested for functional defects. For example, wafer acceptance test (WAT) is a test in which a wafer prober sends electrical and / or optical test signals to the semiconductor devices. The electrical and / or optical test signals check the functionality of the semiconductor devices and identify devices that do not meet design specifications. Utility Model Content

[0003] The utility model provides an integrated chip, comprising: a semiconductor workpiece; and a test line structure, which is arranged on the semiconductor workpiece, wherein the test line structure comprises: a plurality of optical input / output structures, which are arranged in and / or on the semiconductor workpiece; and a plurality of electrical input / output structures, which are located on the semiconductor workpiece, wherein the plurality of optical input / output structures and the plurality of electrical input / output structures are separated from each other laterally along a line extending in a first direction.

[0004] The utility model provides an integrated chip, comprising: a first device area, which is arranged on a semiconductor workpiece and includes a first plurality of optical devices; a second device area, which is arranged on the semiconductor workpiece and includes a second plurality of optical devices, wherein the first device area is adjacent to the second device area; and a test line structure, which is arranged in the test line area, and the test line area is laterally separated and located between the first device area and the second device area, wherein the test line structure includes a plurality of optical input / output structures and a plurality of electrical input / output structures adjacent to the plurality of optical input / output structures, wherein the plurality of electrical input / output structures are offset in a vertical direction relative to the plurality of optical input / output structures.

[0005] An integrated chip may include a test line structure having an electrical input / output (I / O) structure, the test line structure being configured to receive an electrical test signal from a wafer prober and provide the electrical test signal to different parts of the integrated chip to test its functionality. For example, a plurality of probes of the wafer prober may physically contact the electrical I / O structure to provide the electrical test signal to the electrical I / O structure. The electrical I / O structure provides the electrical test signal to the device on the integrated chip, so that the device can be tested at an intermediate manufacturing stage. This enables the manufacturing process to be accurately characterized, so that problems can be quickly identified and resolved. This also enables defective wafers to be discarded early in the manufacturing process to help improve manufacturing yields. As the size of integrated chips continues to decrease, optical devices (e.g., photonic devices) may be increasingly used in integrated chips to enable the semiconductor industry to continue to improve the performance of integrated chips relative to traditional integrated chips (e.g., because photons can provide a higher bandwidth than the electrons used in traditional integrated chips). Optical devices can be used in integrated chips for many applications including communications, information processing, optical computing, etc. Optical devices can use light waves (e.g., generated by lasers or light sources) for data processing, data storage, and / or data communication. Although the electrical I / O structure in the test line structure of the integrated chip can test some electrical functions of the optical device, the electrical I / O structure may not provide optical test signals to the optical device. The inability to supply optical test signals to different parts of the integrated chip significantly reduces the test function of the optical device on the integrated chip. Therefore, the accurate characterization of the optical device during production is reduced. In addition, the identification of a wafer with a large number of defective optical devices may not be accurately determined, thereby reducing the production yield.

[0006] Therefore, the utility model relates to an integrated chip with a test line structure, wherein the test line structure includes a plurality of optical I / O structures that are laterally adjacent to a plurality of electrical input / output (I / O) structures disposed in a test line area. In some embodiments, the optical I / O structure is disposed on a semiconductor workpiece (e.g., a semiconductor substrate, a semiconductor wafer, etc.). In addition, an internal connection structure overlies the semiconductor workpiece, and the electrical I / O structure is disposed on the internal connection structure. One or more optical devices are disposed on and / or in the semiconductor workpiece. The plurality of electrical I / O structures and the plurality of optical I / O structures are respectively configured to receive one or more electrical test signals and one or more optical test signals from a wafer prober and / or a control circuit. The plurality of optical I / O structures are configured to provide the one or more optical test signals to the one or more optical devices, and the plurality of electrical I / O structures are configured to provide electrical test signals to the one or more optical devices. The one or more optical devices may generate one or more output test signals in response to the one or more optical test signals and the electrical test signals. The one or more output test signals may be provided to a wafer prober and / or control circuitry via one or more of the electrical I / O structures and / or the optical I / O structures. Thus, accurate characterization of the one or more optical devices during fabrication is improved. Additionally, identification of semiconductor workpieces having a large number of defective optical devices may be accurately determined, thereby enabling defective semiconductor workpieces to be discarded early in the fabrication process. This may increase fabrication throughput and / or device yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 Block diagrams of some embodiments of an integrated chip including a testline structure having a plurality of optical input / output (I / O) structures laterally adjacent to a plurality of electrical I / O structures are shown.

[0009] Figure 2 Block diagrams of some embodiments of an integrated chip including a testline structure having a plurality of optical I / O structures, a plurality of electrical I / O structures, and one or more optical devices are shown.

[0010] Figures 3 to 5 Show Figure 1 Various block diagrams of some other embodiments of integrated chips are shown.

[0011] Fig. 6A and Figure 6BVarious diagrams showing some embodiments of an integrated chip including a testline structure having a plurality of optical I / O structures, a plurality of electrical I / O structures, and a plurality of optical devices.

[0012] Fig. 7A and Figure 7B Various diagrams showing some embodiments of optical devices that may be used in some embodiments of test line structures.

[0013] Fig. 8A and Figure 8B Show Fig. 7A and Figure 7B Various cross-sectional views of some other embodiments of optical devices are shown.

[0014] Fig. 9 A top view of some embodiments of another optical device that may be used in some embodiments of a test line structure is shown.

[0015] Fig. 10A and Fig. 10B Various diagrams showing some embodiments of yet another optical device that may be used in some embodiments of a test line structure.

[0016] Fig.11 A top view of some other embodiments of an integrated chip including a testline structure having a plurality of optical I / O structures, a plurality of electrical I / O structures, and one or more optical devices is shown.

[0017] Fig.12 A top view of some embodiments of another optical device that may be used in some embodiments of a test line structure is shown.

[0018] FIG. 13A to FIG. 13C Various diagrams showing some additional embodiments of an integrated chip including a testline structure having a plurality of optical I / O structures, a plurality of electrical I / O structures, and one or more optical devices.

[0019] Fig.14A and Fig. 14B Various diagrams showing some other embodiments of optical devices that may be used in some embodiments of test line structures.

[0020] Fig.15A and Fig. 15B Various diagrams showing further embodiments of an integrated chip including a testline structure having one or more optical I / O structures, a plurality of electrical I / O structures, and one or more optical devices.

[0021] FIG. 16A to FIG. 16CVarious diagrams showing some embodiments of an integrated chip including a testline structure laterally disposed between a first device area and a second device area, wherein the first device area and the second device area each include one or more optical devices.

[0022] Fig.17 A top view of some embodiments of an integrated chip including one or more testline structures disposed between adjacent semiconductor dies is shown.

[0023] Fig.18 , Fig.19A , Fig.19B , Fig. 20 , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A ,and Fig. 23B Various diagrams illustrating some embodiments of methods for forming an integrated chip including a testline structure including a plurality of optical I / O structures and a plurality of electrical I / O structures.

[0024] Fig.24 A flow chart illustrating some embodiments of a method for forming an integrated chip including a testline structure comprising a plurality of optical I / O structures and a plurality of electrical I / O structures.

[0025] [Description of Figure Numbers]

[0026] 100, 200, 300, 400, 500: block diagram;

[0027] 102: Semiconductor workpieces;

[0028] 104a: a first semiconductor die;

[0029] 104b: a second semiconductor die;

[0030] 106: test line area;

[0031] 108: Test line structure;

[0032] 110: optical testing area;

[0033] 112: Electrical test area;

[0034] 114: Optical I / O structure;

[0035] 114a: first optical I / O structure / optical I / O structure;

[0036] 114b: second optical I / O structure / optical I / O structure;

[0037] 114c: third optical I / O structure;

[0038] 116: electrical input / output (I / O) structure;

[0039] 202, 1102, 1202, 1302, 1502: optical device;

[0040] 202a: first optical device;

[0041] 204, 1602: installation area;

[0042] 204a, 1602a: first device area;

[0043] 204b, 1602b: second device area;

[0044] 206: test line length;

[0045] 208: test line width;

[0046] 210, 214, 1028, 1314: spacing;

[0047] 212, 710, 712, 714, 716, 718, 720, 722, 724, 1022, 1024, 1026, 1032, 1508: width;

[0048] 600a, 700a, 900, 1000a, 1100, 1200, 1300a, 1300b, 1400a, 1500a, 1600c, 1700: top views;

[0049] 600b, 700b, 800a, 800b, 1000b, 1300c, 1400b, 1500b, 1600a, 1600b: cross-sectional views;

[0050] 601, 1104, 1204: first waveguide;

[0051] 602: optical device / first optical device;

[0052] 603, 1106, 1206: second waveguide;

[0053] 604: optical device / second optical device;

[0054] 606: optical device / third optical device;

[0055] 608: optical device / fourth optical device;

[0056] 610: beam splitter;

[0057] 614: Dummy beam splitter;

[0058] 618: second MZI waveguide;

[0059] 620: second MZI waveguide;

[0060] 622: first modulator waveguide;

[0061] 624: second modulator waveguide;

[0062] 626: beam combiner;

[0063] 628: Dummy beam combiner;

[0064] 630: Basic substrate;

[0065] 632: Insulator structure;

[0066] 634: active layer;

[0067] 634us: upper surface;

[0068] 636: grating coupler segment;

[0069] 638: base segment;

[0070] 640: tapered section;

[0071] 642: tip segment;

[0072] 643: Internal connection structure;

[0073] 646: Inner connection dielectric structure;

[0074] 648: optical I / O channel;

[0075] 650: passivation structure;

[0076] 652: Conductive wiring;

[0077] 654: via;

[0078] 656: optical signal;

[0079] 702: first doped contact region;

[0080] 704: second doped contact region;

[0081] 706: first doped region;

[0082] 708: second doping region;

[0083] 726: first height;

[0084] 728: Second height;

[0085] 802: third height;

[0086] 804: fourth height;

[0087] 902: waveguide extension region;

[0088] 904: waveguide extension;

[0089] 1002: optical separator input structure;

[0090] 1004: optical separator body;

[0091] 1006: first optical separator output structure;

[0092] 1008: second optical separator output structure;

[0093] 1010: separator tip section;

[0094] 1012: separator cone section;

[0095] 1013, 1014, 1016, 1018, 1020, 1110: length;

[0096] 1030: distance;

[0097] 1034: lateral distance;

[0098] 1036, 1038, 1510: height;

[0099] 1201: input waveguide;

[0100] 1203: output waveguide;

[0101] 1304: Ring waveguide;

[0102] 1306: first I / O waveguide;

[0103] 1308: second I / O waveguide;

[0104] 1310: Test line letter structure;

[0105] 1312: test line letters;

[0106] 1316: outer radius;

[0107] 1318: size;

[0108] 1402: Heater structure;

[0109] 1501, 1618: waveguide;

[0110] 1504, 1614: light sensor layer;

[0111] 1604: first plurality of optical devices / optical device / first optical device;

[0112] 1606: first plurality of optical devices / optical device / second optical device;

[0113] 1608: second plurality of optical devices / optical devices / third optical devices;

[0114] 1610: second plurality of optical devices / optical devices / fourth optical device;

[0115] 1612: Optical waveguides;

[0116] 1616: Optical sensor waveguide;

[0117] 1620: a first plurality of bonding pads;

[0118] 1622: a second plurality of bonding pads;

[0119] 1702, 1704: cutting path;

[0120] 1702a: first cutting path;

[0121] 1800, 1900a, 2000, 2100a, 2100b, 2200a, 2200b, 2300a: cross-sectional views;

[0122] 1900b, 2100c, 2200c, 2300b: top views;

[0123] 2400: Flowchart;

[0124] 2402, 2404, 2406, 2408, 2410: action;

[0125] A-A', B-B': line;

[0126] x, y: axis. DETAILED DESCRIPTION

[0127] Many different embodiments or examples for implementing the different features of the present invention are provided herein. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, reference numbers and / or letters may be reused in various examples herein. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0128] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0129] The integrated chip may include a test line structure having an electrical input / output (I / O) structure, wherein the test line structure is configured to receive an electrical test signal from a wafer prober and provide the electrical test signal to different parts of the integrated chip to test its function. For example, a plurality of probes of the wafer prober may physically contact the electrical I / O structure to provide an electrical test signal to the electrical I / O structure. The electrical I / O structure provides an electrical test signal to a device on the integrated chip, so that the device can be tested at an intermediate manufacturing stage. This enables the manufacturing process to be accurately characterized, so that problems can be quickly identified and resolved. This also enables defective wafers to be discarded early in the manufacturing process to help increase manufacturing yields.

[0130] As the size of integrated chips continues to decrease, optical devices (e.g., photonic devices) can be increasingly used in integrated chips to enable the semiconductor industry to continue to improve the performance of integrated chips relative to traditional integrated chips (e.g., because photons can provide higher bandwidth than electrons used in traditional integrated chips). Optical devices can be used in integrated chips for many applications including communications, information processing, optical computing, etc. Optical devices can use light waves (e.g., generated by lasers or light sources) for data processing, data storage, and / or data communication. Although the electrical I / O structure in the test line structure of the integrated chip can test some electrical functions of the optical device, the electrical I / O structure may not provide optical test signals to the optical device. The inability to supply optical test signals to different parts of the integrated chip significantly reduces the test function of the optical device on the integrated chip. Therefore, the accurate characterization of the optical device during production is reduced. In addition, the identification of a wafer with a large number of defective optical devices may not be accurately determined, thereby reducing the production yield.

[0131] Therefore, in some embodiments, the utility model relates to an integrated chip with a test line structure, wherein the test line structure includes a plurality of optical I / O structures that are laterally adjacent to a plurality of electrical input / output (I / O) structures disposed in a test line area. In some embodiments, the optical I / O structure is disposed on a semiconductor workpiece (e.g., a semiconductor substrate, a semiconductor wafer, etc.). In addition, an internal connection structure overlies the semiconductor workpiece, and the electrical I / O structure is disposed on the internal connection structure. One or more optical devices are disposed on and / or in the semiconductor workpiece. The plurality of electrical I / O structures and the plurality of optical I / O structures are respectively configured to receive one or more electrical test signals and one or more optical test signals from a wafer prober and / or a control circuit. The plurality of optical I / O structures are configured to provide the one or more optical test signals to the one or more optical devices, and the plurality of electrical I / O structures are configured to provide electrical test signals to the one or more optical devices. The one or more optical devices may generate one or more output test signals in response to the one or more optical test signals and the electrical test signals. The one or more output test signals may be provided to a wafer prober and / or control circuitry via one or more of the electrical I / O structures and / or the optical I / O structures. Thus, accurate characterization of the one or more optical devices during fabrication is improved. Additionally, identification of semiconductor workpieces having a large number of defective optical devices may be accurately determined, thereby enabling defective semiconductor workpieces to be discarded early in the fabrication process. This may increase fabrication throughput and / or device yield.

[0132] Figure 1Block diagram 100 shows some embodiments of an integrated chip including a testline structure 108 having a plurality of optical input / output (I / O) structures 114 laterally adjacent to a plurality of electrical I / O structures 116 .

[0133] In some embodiments, the integrated chip includes a first semiconductor die 104a, a second semiconductor die 104b, and a test line structure 108 disposed laterally between the first semiconductor die 104a and the second semiconductor die 104b. The first semiconductor die 104a and the second semiconductor die 104b are disposed on a semiconductor workpiece 102. The semiconductor workpiece 102 may be or may include, for example, a semiconductor substrate (e.g., a silicon substrate, a semiconductor-on-insulator (SOI) substrate, etc.), a semiconductor wafer (e.g., a silicon wafer), or a similar structure. The first semiconductor die 104a and the second semiconductor die 104b each include a device region, the device region including one or more semiconductor devices (e.g., transistors, optical devices (e.g., photodetectors, optical modulators, optical interferometers, waveguides, etc.) disposed in and / or on the semiconductor workpiece 102. In various embodiments, the test line structure 108 is laterally disposed within a test line region 106 that is laterally spaced apart between the first semiconductor die 104 a and the second semiconductor die 104 b .

[0134] In various embodiments, the test line structure 108 includes the plurality of optical I / O structures 114 and the plurality of electrical I / O structures 116 that are laterally adjacent to each other. The plurality of optical I / O structures 114 are disposed in an optical test region 110 of the test line structure 108, and the plurality of electrical I / O structures 116 are disposed in an electrical test region 112 of the test line structure 108. One or more optical devices (e.g., optical sensors, optical modulators, optical interferometers, waveguides, etc.) (not shown) are disposed in and / or on the semiconductor workpiece 102. In some embodiments, the one or more optical devices are disposed in the first semiconductor die 104a, the second semiconductor die 104b, and / or the test line structure 108. The plurality of optical I / O structures 114 are configured to receive one or more optical test signals, and the plurality of electrical I / O structures 116 are configured to receive one or more electrical test signals. For example, the optical I / O structure 114 and the electrical I / O structure 116 may receive corresponding optical test signals and electrical test signals from a wafer prober and / or a control circuit (not shown). The multiple optical I / O structures 114 and the multiple electrical I / O structures 116 are configured to transmit the one or more optical test signals and the one or more electrical test signals to the one or more optical devices to characterize the performance of the one or more optical devices. Since the test line structure 108 includes both the optical I / O structure 114 and the electrical I / O structure 116, accurate characterization of the one or more optical devices can be achieved during the manufacture of the integrated chip. This is conducive to verifying whether the one or more optical devices meet the design specifications and function properly. In addition, semiconductor workpieces with a large number of defective optical devices can be identified early in the manufacturing process, thereby improving the manufacturing yield.

[0135] In various embodiments, a wafer acceptance test (WAT) may be performed on the integrated chip before the dicing process and / or packaging process is performed on the integrated chip. In some embodiments, the WAT includes using a wafer prober (e.g., having both optical and electrical testing capabilities) to send one or more input optical test signals and / or one or more input electrical test signals to the one or more optical devices via the optical I / O structure 114 and the electrical I / O structure 116. The output optical test signals and / or output electrical test signals generated by the one or more optical devices in response to the input optical test signals and / or electrical test signals may be sent to the wafer prober and / or control circuit (not shown) via the optical I / O structure 114 and the electrical I / O structure 116 to characterize the performance of the one or more optical devices. Therefore, the functionality of the one or more optical devices may be verified. In other embodiments, semiconductor workpieces having a large number of optical devices that do not meet design specifications may be discarded before the dicing process and / or packaging process is performed.

[0136] In some embodiments, the plurality of optical I / O structures 114 may each be configured as a grating coupler or some other suitable optical I / O structure. In still other embodiments, the plurality of electrical I / O structures 116 may each be configured as a conductive bonding pad, a conductive contact pad, a conductive wire, a conductive line, or some other suitable electrical I / O structure.

[0137] Figure 2 Some embodiments of a block diagram 200 of an integrated chip having a testline structure 108 including a plurality of optical I / O structures 114 , a plurality of electrical I / O structures 116 , and one or more optical devices 202 are shown.

[0138] In some embodiments, the first semiconductor die 104a and the second semiconductor die 104b each include a plurality of device regions 204, each of which includes one or more semiconductor devices. For example, the one or more semiconductor devices include optical devices, such as optical sensors, optical modulators, optical interferometers, waveguides, grating couplers, some other suitable semiconductor devices, or any combination of the foregoing. In various embodiments, the plurality of device regions 204 of the first semiconductor die 104a include: a first device region 204a, which may include one or more optical modulators; and a second device region 204b, which may include one or more optical sensors. In various embodiments, the test line structure 108 includes the plurality of optical I / O structures 114, the plurality of electrical I / O structures 116, and the one or more optical devices 202 disposed in the test line region 106. The one or more optical devices 202 are disposed in the optical test region 110 of the test line structure 108. In various embodiments, the one or more optical devices 202 of the testline structure 108 are respectively configured to receive one or more optical test signals from the plurality of optical I / O structures 114 and one or more electrical test signals from the plurality of electrical I / O structures 116 .

[0139] In some embodiments, the one or more optical devices 202 include a first optical device 202a, and the first optical device 202a is laterally adjacent to a pair of optical I / O structures 114a, 114b in the plurality of optical I / O structures 114. The first optical I / O structure 114a in the pair of optical I / O structures 114a, 114b is configured to provide an input optical test signal to the first optical device 202a. The second optical I / O structure 114b in the pair of optical I / O structures 114a, 114b is configured to receive an output optical test signal from the first optical device 202a. In some further embodiments, at least one electrical I / O structure in the plurality of electrical I / O structures 116 may be electrically coupled to the first optical device 202a and configured to provide an input electrical test signal to the first optical device 202a. In such an embodiment, the first optical device 202a generates an output optical test signal based on the input optical test signal and the input electrical test signal. In various embodiments, input optical test signals and input electrical test signals may be provided by a wafer prober and / or control circuit (not shown), and output optical test signals may be provided to the wafer prober and / or control circuit to characterize the performance and / or functionality of the first optical device 202a. In various embodiments, the plurality of optical I / O structures 114, the one or more optical devices 202, and the plurality of electrical I / O structures 116 are arranged along a line extending in a first direction (e.g., along the x-axis) and are directly between the first semiconductor die 104a and the second semiconductor die 104b.

[0140] In some embodiments, the test line structure 108 may be located within a scribe line disposed between the first semiconductor die 104a and the second semiconductor die 104b, wherein the semiconductor workpiece 102 is configured as a semiconductor wafer (eg, Fig.17 104a and 104b). In such an embodiment, the scribe line is removed during the dicing of the semiconductor workpiece 102 to singulate the first semiconductor die 104a and the second semiconductor die 104b. In other embodiments, the test line structure 108 may be located outside the scribe line (not shown) within the first semiconductor die 104a or the second semiconductor die 104b. In such an embodiment, after the singulation (i.e., dicing) is completed, the test line structure 108 exists on the first semiconductor die 104a or the second semiconductor die 104b. In other embodiments, the test line structure 108 may be integrated in any area of ​​the integrated chip (e.g., within any of the device areas 204 of the first semiconductor die 104a or the second semiconductor die 104b) (not shown).

[0141] The test line structure 108 has a test line length 206, which can be defined between an outermost optical I / O structure in the plurality of optical I / O structures 114 and an outermost electrical I / O structure in the plurality of electrical I / O structures 116. In addition, the test line structure 108 has a test line width 208. In various embodiments, the test line width 208 is in a range of about 20 micrometers (μm) to about 240 micrometers or some other suitable value. In yet other embodiments, the test line length 206 is in a range of about 1 millimeter (mm) to about 20 millimeters or some other suitable value. In some embodiments, because the test line length 206 is 20 mm or less and / or the test line width 208 is 240 μm or less, the area of ​​the test line structure 108 on the semiconductor workpiece 102 is reduced, thereby increasing the area of ​​semiconductor devices disposed in other areas of the semiconductor workpiece 102 (for example, disposed in the first semiconductor die 104 a and the second semiconductor die 104 b ) on and / or the semiconductor workpiece 102.

[0142] In various embodiments, the spacing 210 between adjacent optical I / O structures in the plurality of optical I / O structures 114 is in a range of about 100 microns to 250 microns or some other suitable value. In addition, the number of optical I / O structures 114 disposed within the test line structure 108 may be in a range of 1 to 64 or some other suitable number of optical I / O structures. In some embodiments, the width 212 of the electrical I / O structure 116 is in a range of about 20 microns to 240 microns or some other suitable value. In other embodiments, the spacing 214 between adjacent electrical I / O structures in the plurality of electrical I / O structures 116 is in a range of about 50 microns to 150 microns or some other suitable value. In addition, the number of electrical I / O structures 116 disposed within the test line structure 108 may be in a range of 1 to 64 or some other suitable number of electrical I / O structures.

[0143] Figure 3 Shown with Figure 2 Some other embodiments of the integrated chip shown are block diagrams 300 of some embodiments of the integrated chip, wherein the plurality of optical I / O structures 114 are respectively configured as grating couplers optically coupled to corresponding waveguides. In various embodiments, the waveguides optically coupled to the corresponding optical I / O structures 114 are respectively configured to transmit optical signals in a direction toward the plurality of electrical I / O structures 116 (e.g., along the x-axis).

[0144] Figure 4 Shown with Figure 2 Some other embodiments of the integrated chip shown are block diagrams 400 of some embodiments of the integrated chip, wherein the plurality of optical I / O structures 114 are respectively configured as grating couplers optically coupled to corresponding waveguides. In various embodiments, the waveguides optically coupled to the corresponding optical I / O structures 114 are respectively configured to transmit optical signals in a direction away from the plurality of electrical I / O structures 116 (e.g., along the y-axis).

[0145] Figure 5 Shown with Figure 2 Some other embodiments of the illustrated integrated chip correspond to a block diagram 500 of some embodiments of the integrated chip, wherein the test line structure 108 is disposed along a line extending in a cross-sectional direction (eg, along the y-axis) and is spaced apart between the first semiconductor die 104a and the second semiconductor die 104b.

[0146] Fig. 6AA top view 600a of some embodiments of an integrated chip having a test line structure 108 includes a plurality of optical I / O structures 114, a plurality of electrical I / O structures 116, and a plurality of optical devices 602 to 608. In various embodiments, Figures 1 to 5 The test line structure 108 shown may be configured as follows Fig. 6A The test line structure 108 is shown and / or described.

[0147] In some embodiments, the test line structure 108 includes the plurality of optical I / O structures 114 and the plurality of optical devices 602 to 608 disposed in the optical test area 110, and the plurality of electrical I / O structures 116 disposed in the electrical test area 112. The plurality of optical I / O structures 114 include a first optical I / O structure 114a that is laterally adjacent to a second optical I / O structure 114b. The plurality of optical devices 602 to 608 are laterally spaced between the first optical I / O structure 114a and the second optical I / O structure 114b and the plurality of electrical I / O structures 116. The first optical I / O structure 114a is optically coupled to a first waveguide 601. In some embodiments, the first optical I / O structure 114a is configured to receive one or more input optical test signals (e.g., from a wafer prober and / or a control circuit) and provide the one or more input optical test signals to the first waveguide 601. The first waveguide 601 is configured to transmit or transfer the one or more input optical test signals to the plurality of optical devices 602 to 608. In various embodiments, the plurality of optical devices 602 to 608 include a first optical device 602, a second optical device 604, a third optical device 606, and a fourth optical device 608.

[0148] In some embodiments, the first optical device 602 is configured as or includes an optical beamsplitter 610, which is configured to split the input optical test signal provided by the first waveguide 601 and / or the first optical I / O structure 114a into a first optical signal and a second optical signal. In some other embodiments, the first optical device 602 further includes a plurality of dummy optical beamsplitters 614 disposed on opposite sides of the beamsplitter 610. The first optical device 602 is optically coupled to the second optical device 604. In various embodiments, the second optical device 604 is configured as or includes a Mach-Zehnder interferometer (MZI), which includes a first MZI waveguide 618 and a second MZI waveguide 620. In such an embodiment, the optical path (e.g., total length) of the first MZI waveguide 618 is different from (e.g., smaller than) the optical path (e.g., total length) of the second MZI waveguide 620. The first optical signal from the beam splitter 610 is provided to the first MZI waveguide 618, and the second optical signal from the beam splitter 610 is provided to the second MZI waveguide 620. The second optical device 604 is optically coupled to the third optical device 606.

[0149] In various embodiments, the third optical device 606 is configured as an optical modulator, a Mach-Zehnder modulator (MZM), or some other suitable device. The third optical device 606 includes a first modulator waveguide 622 optically coupled to the first MZI waveguide 618 and a second modulator waveguide 624 optically coupled to the second MZI waveguide 620. The third optical device 606 is configured to receive the first optical signal and the second optical signal from the second optical device 604, and apply one or more phase shifts to the first optical signal and / or the second optical signal. In various embodiments, the third optical device 606 includes one or more doped regions (e.g., disposed along the first modulator waveguide 622 and / or the second modulator waveguide 624) (e.g., 7A to 8BIn some embodiments, the fourth optical device 608 is configured as or includes an optical beam combiner 626 configured to combine optical signals from the third optical device 606 into an output optical test signal. In some embodiments, the fourth optical device 608 further includes a plurality of dummy optical beam combiners 628 disposed on opposite sides of the beam combiner 626.

[0150] In various embodiments, the fourth optical device 608 is configured to combine the first optical signal and the second optical signal from the first modulator waveguide 622 and the second modulator waveguide 624 into an output optical test signal. The output optical test signal can be transmitted or transferred from the fourth optical device 608 to the second optical I / O structure 114b via the second waveguide 603. In various embodiments, the output optical test signal can be output to a wafer prober and / or an output optical fiber by the second optical I / O structure 114b. Therefore, the wafer prober and / or the control circuit can be configured to perform a comparison between the input optical test signal and the output optical test signal to characterize the performance and / or function of the plurality of optical devices 602 to 608. Since the test line structure 108 includes the plurality of optical I / O structures 114, the plurality of optical devices 602 to 608, and the plurality of electrical I / O structures 116, accurate characterization and / or monitoring of the performance of the optical devices disposed on the semiconductor workpiece 102 can be achieved. This helps verify that the optical device meets design specifications and functions properly.

[0151] Figure 6B Show Fig. 6A A cross-sectional view 600b of some embodiments of a portion of an integrated chip is shown. In various embodiments, a first side of the cross-sectional view 600b may be along Fig. 6A The second side of the cross-sectional view 600b can be taken along the line AA'. Fig. 6A The line BB' is shown.

[0152] In some embodiments, the semiconductor workpiece 102 is configured as a semiconductor-on-insulator (SOI) substrate, which includes a base substrate 630 separated from an active layer 634 by an insulator structure 632. For example, the active layer 634 can be or include silicon, polycrystalline silicon, some other suitable substrate material, or any combination of the foregoing materials. An interconnect structure 643 overlies the semiconductor workpiece 102. The interconnect structure 643 includes an interconnect dielectric structure 646, a plurality of conductive wires 652, and a plurality of conductive vias 654. In addition, a dielectric layer 644 can be disposed between the interconnect dielectric structure 646 and the active layer 634.

[0153] The first optical I / O structure 114a can be disposed within the active layer 634. In various embodiments, the first optical I / O structure 114a is configured as a grating coupler structure and includes a base segment 638, a tapered segment 640 adjacent to the base segment 638, and a tip segment 642 adjacent to the tapered segment 640. In some embodiments, the base segment 638 includes a plurality of grating coupler segments 636 spaced apart from each other in the laterally direction, and when viewed from above the base segment 638 in a direction toward the tip segment 642, the width of the tapered segment 640 continuously decreases (e.g., Fig. 6A 64a). The tip segment 642 is disposed between the tapered segment 640 and the first waveguide 601. In some other embodiments, the first optical I / O structure 114a extends continuously upward from the upper surface 634us of the active layer 634. The dielectric layer 644 is disposed on and around the first optical I / O structure 114a. The dielectric layer 644 may be, for example, or include silicon dioxide, a metal oxide, or some other suitable dielectric material. In various embodiments, the dielectric layer 644 may be configured to be used for the test line structure ( Fig. 6A 108) of the component's covering material.

[0154] The interconnect structure 643 overlies the semiconductor workpiece 102 and the first optical I / O structure 114a. The conductive wires 652 and the vias 654 are disposed within the interconnect dielectric structure 646 and are configured to provide electrical coupling between structures and / or devices disposed on the semiconductor workpiece 102. The passivation structure 650 overlies the interconnect structure 643. The plurality of electrical I / O structures 116 are disposed within the passivation structure 650 and directly overlie the topmost layer of the conductive wires in the plurality of conductive wires 652. In some embodiments, the plurality of electrical I / O structures 116 are directly electrically coupled to the test line structure ( Fig. 6A For example, the plurality of electrical I / O structures 116 may be electrically coupled to a third optical device ( Fig. 6A For example, the plurality of electrical I / O structures 116 may each be or may include titanium, aluminum, copper, tungsten, gold, silver, some other suitable material, or any combination of the foregoing materials. In various embodiments, the plurality of optical I / O structures ( Fig. 6A 114) includes a first material (e.g., silicon), and the plurality of electrical I / O structures 116 include a second material different from the first material (e.g., metal (e.g., aluminum, tungsten, gold, silver, copper, etc.)). In other embodiments, the plurality of optical I / O structures ( Fig. 6A 114) is separated from the plurality of electrical I / O structures 116 in a vertical direction.

[0155] An optical I / O channel 648 is disposed within the passivation structure 650 and / or the interconnect dielectric structure 646 and directly overlies the first optical I / O structure 114a. In various embodiments, the optical I / O channel 648 can be optically coupled to an optical fiber, a light pipe structure, or the like configured to transmit and / or receive an optical signal. In other embodiments, the optical I / O channel 648 is configured as a fiber optic waveguide, a light pipe structure, or the like. In some embodiments, the optical I / O channel 648 is configured to direct an optical signal 656 (e.g., an input optical test signal) to the first optical I / O structure 114a, wherein the optical signal 656 is provided to a test line structure ( Fig. 6A The plurality of optical devices (108) Fig. 6A 602 to 608).

[0156] Fig. 7A Show Fig. 6AA top view 700a of some embodiments of the third optical device 606 of the integrated chip is shown.

[0157] As shown in top view 700a, the third optical device 606 is configured as an MZM, an optical modulator, or some other suitable device. In some embodiments, the third optical device 606 includes a first modulator waveguide 622 and a second modulator waveguide 624. The first modulator waveguide 622 and the second modulator waveguide 624 each include a first doped region 706 having a first doping type (e.g., p-type) and a second doped region 708 having a second doping type (e.g., n-type) opposite to the first doping type. In some examples, the first doping type is p-type and the second doping type is n-type, or vice versa. The first doped region 706 is adjacent to the second doped region 708 along a pn junction. In addition, a first doped contact region 702 is adjacent to the first doped region 706, and a second doped contact region 704 is adjacent to the second doped region 708. In various embodiments, the first doped contact region 702 includes a first doping type (eg, p-type), and the second doped contact region 704 includes a second doping type (eg, n-type).

[0158] The first doped contact region 702 is electrically coupled to the first doped region 706 and is configured to supply a first bias voltage to the first doped region 706. In addition, the second doped contact region 704 is electrically coupled to the second doped region 708 and is configured to supply a second bias voltage to the second doped region 708. For example, the plurality of conductive wires 652 directly overlie the first doped contact region 702 and the second doped contact region 704, and are configured to supply corresponding bias voltages to the first doped region 706 and the second doped region 708 via the first doped contact region 702 and the second doped contact region 704. By supplying appropriate bias conditions to the first doped region 706 and the second doped region 708, the refractive index of the first modulator waveguide 622 and the second modulator waveguide 624 is adjusted, thereby introducing a phase shift along the first modulator waveguide 622 and the second modulator waveguide 624. In various embodiments, the plurality of electrical I / O structures ( Fig. 6A and Figure 6B 116) is directly electrically coupled to the first doped region 706 and the second doped region 708 via the plurality of conductive wirings 652 and the first doped contact region 702 and the second doped contact region 704. Therefore, the plurality of electrical I / O structures ( Fig. 6A and Figure 6B116) can supply one or more electrical test signals to the first doped region 706 and the second doped region 708 during, for example, a wafer acceptance test (WAT), a device monitoring process, or the like.

[0159] Figure 7B Shown along Fig. 7A The third optical device ( Fig. 6A 606) of some embodiments of the cross-sectional view 700b.

[0160] As shown in the cross-sectional view 700b, the via 654 overlies the first doped contact region 702 and the second doped contact region 704. The via 654 electrically couples the first doped contact region 702 and the second doped contact region 704 to the conductive wiring 652. In various embodiments, the first doped contact region 702 and the second doped contact region 704 and the first doped region 706 and the second doped region 708 are disposed in the active layer 634 of the semiconductor workpiece 102. The first doped contact region 702 and the second doped contact region 704 respectively include a contact pillar structure having a first height 726 and a lateral contact segment having a second height 728, the lateral contact segment continuously extending from the contact pillar structure to a corresponding one of the first doped region 706 or the second doped region 708. In some embodiments, the first height 726 is greater than the second height 728. In other embodiments, the first doped region 706 and the second doped region 708 include a doped column structure having a first height 726 and a lateral doped segment having a second height 728, respectively. The first height 726 may be, for example, in the range of about 0.01 micrometers to 10 micrometers or some other suitable value. The second height 728 may be, for example, in the range of about 0.01 micrometers to 10 micrometers, in the range of about 0.01 micrometers to 8 micrometers, or some other suitable value.

[0161] The doped pillar structures of the first doped region 706 and the second doped region 708 have widths 710 and 712, respectively. In some embodiments, the widths 710 and 712 may be in the range of about 0.01 micrometers to 10 micrometers or some other suitable value. The lateral doped segments of the first doped region 706 and the second doped region 708 have widths 714 and 720, respectively, which may be, for example, in the range of about 0 to 5 micrometers, about 0.01 micrometers to 10 micrometers, or some other suitable value. The contact pillar structures of the first doped contact region 702 and the second doped contact region 704 have widths 718 and 724, respectively, which may be, for example, in the range of about 0.01 micrometers to 10 micrometers or some other suitable value. In addition, the lateral contact segments of the first doped contact region 702 and the second doped contact region 704 have widths 716 and 722, respectively, which may be, for example, in the range of about 0 to 10 micrometers or some other suitable value.

[0162] Fig. 8A Shown along Fig. 7A The third optical device ( Fig. 6A 606), wherein a portion of the second doped region 708 directly overlies at least a portion of the first doped region 706. In various embodiments, a third height 802 of the portion of the second doped region 708 directly overlying the at least a portion of the first doped region 706 is in a range of approximately 0.01 microns to 10 microns or some other suitable value.

[0163] Figure 8B Shown along Fig. 7A The third optical device ( Fig. 6A 606), wherein a portion of the first doped region 706 directly overlies at least a portion of the second doped region 708. In various embodiments, a fourth height 804 of the portion of the first doped region 706 is in a range of approximately 0.01 microns to 10 microns or some other suitable value.

[0164] Fig. 9 Show Fig. 6A A top view 900 of some embodiments of the second optical device 604 of the integrated chip is shown.

[0165] As shown in the top view 900, the second optical device 604 includes a first MZI waveguide 618 and a second MZI waveguide 620. In various embodiments, the optical path (e.g., total length) of the first MZI waveguide 618 is less than the optical path (e.g., total length) of the second MZI waveguide 620. In various embodiments, the second MZI waveguide 620 includes a plurality of waveguide extension segments 904 disposed within a waveguide extension region 902 of the second MZI waveguide 620. Each waveguide extension segment 904 is adjacent to a curved waveguide segment of the second MZI waveguide 620. The plurality of waveguide extension segments 904 increase the optical path of the second MZI waveguide 620 to a value greater than the optical path of the first MZI waveguide 618. In various embodiments, the lengths 906 of the waveguide extension segments 904 are each in the range of about 1 micrometer to 100 micrometers or some other suitable value. In other embodiments, the second MZI waveguide 620 includes 2 to 128 waveguide extensions 904. It should be understood that other numbers of waveguide extensions 904 are also within the scope of the present invention.

[0166] FIG. 10A to FIG. 10B Show Fig. 6A Various diagrams of some embodiments of an integrated chip beam splitter 610 are shown. Fig. 10A A top view 1000a of some embodiments of the beam splitter 610 is shown. Fig. 10B Shown along Fig. 10A A cross-sectional view 1000b of some embodiments of the beam splitter 610 is shown taken along line AA'.

[0167] like Fig. 10AAs shown, in some embodiments, the beam splitter 610 includes an optical splitter input structure 1002, an optical splitter body 1004, a first optical splitter output structure 1006, and a second optical splitter output structure 1008. In various embodiments, the optical splitter input structure 1002, the first optical splitter output structure 1006, and the second optical splitter output structure 1008 respectively include a splitter tip segment 1010 adjacent to a splitter tapered segment 1012. The width of the splitter tapered segment 1012 increases continuously from the corresponding splitter tip segment 1010 in a direction toward the optical splitter body 1004. The splitter tip segment 1010 can be configured as or optically coupled to a corresponding waveguide. In various embodiments, the length 1013 of the separator tip segment 1010 of the optical separator input structure 1002 and the length 1014 of the separator tapered segment 1012 of the optical separator input structure 1002 are respectively in the range of about 0.01 micrometers to 100 micrometers or some other suitable value. In addition, the length 1016 of the optical separator body 1004 is in the range of about 0.01 micrometers to 100 micrometers or some other suitable value. In yet other embodiments, the lengths 1018, 1020 of the separator tapered segment 1012 and the separator tip segment 1010 of the first optical separator output structure 1006 and the second optical separator output structure 1008 are respectively in the range of about 0.01 micrometers to 100 micrometers or some other suitable value.

[0168] In other embodiments, the widths 1022, 1024 of the separator tip segment 1010 and the separator tapered segment 1012 of the optical separator input structure 1002 are respectively in the range of about 0.01 micrometers to 10 micrometers or some other suitable values. In still other embodiments, the width 1026 of the optical separator body 1004 is in the range of about 0.01 micrometers to 10 micrometers or some other suitable values. In various embodiments, the widths 1022, 1024 of the separator tip segment 1010 and the separator tapered segment 1012 of the first optical separator output structure 1006 and the second optical separator output structure 1008 are respectively in the range of about 0.01 micrometers to 10 micrometers or some other suitable values. The distance 1030 between the first optical separator output structure 1006 and the second optical separator output structure 1008 is in the range of about 0 to 10 micrometers or some other suitable value. Furthermore, the spacing 1028 between the first optical separator output structure 1006 and the second optical separator output structure 1008 and the corresponding outer sidewalls of the optical separator body 1004 is in the range of approximately 0 to 10 microns or some other suitable value.

[0169] like Fig. 10B As shown, the beam splitter 610 is laterally spaced apart from the dummy beam splitter 614 by a lateral distance 1034. In various embodiments, the lateral distance 1034 is in a range of about 0.01 microns to 10 microns or some other suitable value. In some embodiments, the width 1032 of the beam splitter body of the dummy beam splitter 614 can be in a range of about 0.01 microns to 10 microns or some other suitable value. In other embodiments, the height 1038 of the lateral section of the active layer 634 between the beam splitter 610 and the dummy beam splitter 614 is in a range of about 0 to 10 microns or some other suitable value. In still other embodiments, the height 1036 of the beam splitter 610 and / or the dummy beam splitter 614 is in a range of about 0.01 microns to 10 microns or some other suitable value.

[0170] Fig.11 A top view 1100 of some embodiments of an integrated chip having a testline structure 108 including a plurality of optical I / O structures 114 , a plurality of electrical I / O structures 116 , and an optical device 1102 is shown.

[0171] In various embodiments, the plurality of optical I / O structures 114 include a first optical I / O structure 114a and a second optical I / O structure 114b. The optical device 1102 may be configured, for example, as an optical modulator or some other suitable optical device. In various embodiments, the optical device 1102 may be configured as FIG. 7A to FIG. 7B The optical device 1102 includes a first waveguide 1104 optically coupled to a first optical I / O structure 114a and a second waveguide 1106 optically coupled to a second optical I / O structure 114b. In some embodiments, the optical device 1102 includes one or more doped regions (e.g., disposed along the first waveguide 1104 and / or the second waveguide 1106) (not shown), the one or more doped regions being configured to adjust the properties of the first waveguide 1104 and the second waveguide 1106 (e.g., adjust the refractive index). A bias voltage may be applied to the one or more doped regions by the plurality of electrical I / O structures 116 to introduce a phase shift along the first waveguide 1104 and / or the second waveguide 1106. In yet other embodiments, the plurality of electrical I / O structures 116 directly overlie at least a portion of the optical device 1102. In various embodiments, the bias voltage applied to the one or more doped regions by the electrical I / O structure 116 may be in the range of approximately 0 to 10 volts or some other suitable value.

[0172] In some embodiments, an input optical signal may be received at a first optical I / O structure 114a and provided to a first waveguide 1104 of an optical device 1102. The optical device 1102 may apply one or more phase shifts to the input optical signal along the first waveguide 1104 and / or the second waveguide 1106 by a bias voltage applied by the electrical I / O structure 116. The optical device 1102 generates an output optical signal based on the one or more phase shifts and the input optical signal. The output optical signal is provided to a second optical I / O structure 114b. In various embodiments, a wafer prober and / or control circuit may compare the input optical signal to the output optical signal to determine an insertion loss of the optical device 1102. In various embodiments, the test line length 206 of the test line structure 108 is in a range of approximately 1 mm to 32 mm or some other suitable value. In other embodiments, the test line width 208 of the test line structure 108 is in a range of approximately 40 microns to 240 microns or some other suitable value. In yet other embodiments, the length 1110 of the first waveguide 1104 and the second waveguide 1106 is in a range of approximately 10 microns to 1 millimeter or some other suitable value.

[0173] Fig.12 A top view 1200 of some embodiments of an optical device 1202 that can be used in some embodiments of a test line structure is shown. For example, Fig.11 The optical device 1102 shown may be configured as Fig.12 Optical device 1202 is shown.

[0174] like Fig.12As shown, the optical device 1202 includes an input waveguide 1201, which is split into a first waveguide 1204 and a second waveguide 1206 by, for example, a beam splitter at a first end of the optical device 1202. In addition, the first waveguide 1204 and the second waveguide 1206 are combined into an output waveguide 1203 by, for example, a beam combiner disposed at a second end of the optical device 1202. The optical device 1202 can be configured as an MZM, an optical modulator, or the like. The first waveguide 1204 and the second waveguide 1206 respectively include: a first doped region 706 having a first doping type (e.g., p-type); and a second doped region 708 having a second doping type opposite to the first doping type (e.g., n-type). The first doped contact region 702 is adjacent to the first doped region 706, and the second doped contact region 704 is adjacent to the second doped region 708. The first doped contact region 702 includes a first doping type (eg, p-type), and the second doped contact region 704 includes a second doping type (eg, n-type).

[0175] The first doped contact region 702 is electrically coupled to the first doped region 706 and is configured to supply a first bias voltage to the first doped region 706. In addition, the second doped contact region 704 is electrically coupled to the second doped region 708 and is configured to supply a second bias voltage to the second doped region 708. By supplying appropriate bias conditions to the first doped region 706 and the second doped region 708, the refractive index of the first waveguide 1204 and / or the second waveguide 1206 can be adjusted, thereby introducing one or more phase shifts along the first waveguide 1204 and / or the second waveguide 1206. In various embodiments, the plurality of electrical I / O structures ( Fig.11 116) is electrically coupled to the first doped region 706 and the second doped region 708 via the first doped contact region 702 and the second doped contact region 704. In some other embodiments, the first optical I / O structure ( Fig.11 114a) is optically coupled to the input waveguide 1201 and is configured to supply an input optical test signal to the input waveguide 1201. In this embodiment, the second optical I / O structure ( Fig.11 114b) is optically coupled to the output waveguide 1203 and is configured to receive the output optical test signal from the optical device 1202.

[0176] Fig.13A A top view 1300 a of some other embodiments of an integrated chip having a testline structure 108 including a plurality of optical I / O structures 114 , a plurality of electrical I / O structures 116 , and an optical device 1302 is shown.

[0177] In some embodiments, the plurality of optical I / O structures 114 include a first optical I / O structure 114a, a second optical I / O structure 114b, and a third optical I / O structure 114c. The optical device 1302 may be configured, for example, as an optical modulator, a micro-ring modulator (MRM), or some other suitable optical device. In various embodiments, the optical device 1302 includes a first I / O waveguide 1306 optically coupled to the first optical I / O structure 114a, a second I / O waveguide 1308 optically coupled to the second optical I / O structure 114b and the third optical I / O structure 114c, and a ring-shaped waveguide 1304 laterally disposed between a segment of the first I / O waveguide 1306 and a plurality of segments of the second I / O waveguide 1308. The first I / O waveguide 1306 and the second I / O waveguide 1308 are sufficiently close to the ring waveguide 1304 so that the first I / O waveguide 1306 and / or the second I / O waveguide 1308 are optically coupled to the ring waveguide 1304. In some embodiments, an input optical test signal is provided to the second optical I / O structure 114b and is transmitted to the ring waveguide 1304 through the second I / O waveguide 1308. The ring waveguide 1304 is configured to receive the input optical test signal, apply a phase shift to the input optical test signal, and generate a corresponding output optical test signal based on the phase shift and the input optical test signal. In various embodiments, the ring waveguide 1304 is configured to generate an output optical test signal based on a phase shift applied to one or more doping regions (not shown) disposed along the ring waveguide 1304 (e.g., see Fig. 13B and Fig. 13C ) to apply a phase shift. The bias voltage is applied to the one or more doped regions of the ring waveguide 1304 by the plurality of electrical I / O structures 116. The output optical test signal may be provided to the third optical I / O structure 114c by the second I / O waveguide 1308. In yet other embodiments, the first I / O waveguide 1306 is configured to receive an optical signal from the ring waveguide 1304 or to transmit an optical signal to the ring waveguide 1304. In various embodiments, the bias voltage applied to the one or more doped regions by the electrical I / O structures 116 may be in the range of approximately 0 to 10 volts or some other suitable value.

[0178] In some embodiments, the test line structure 108 further includes a test line letter structure 1310 including one or more test line letters 1312 configured to optically identify the test line structure 108. For example, the one or more test line letters 1312 may be used to identify an optical device 1302 configured as a micro-ring modulator (MRM) or some other suitable device of the test line structure 108. In various embodiments, the one or more test line letters 1312 are configured as a plurality of alpha numberic characters disposed in and / or on the semiconductor workpiece 102. For example, the one or more test line letters 1312 may be or may include one or more trenches extending into the semiconductor workpiece 102 and / or may be or may include one or more protrusions extending from the upper surface of the semiconductor workpiece 102. In addition, the test line structure 108 may be part of an array of test line structures disposed across the semiconductor workpiece 102. In various embodiments, each test line structure in the array may include a corresponding test line letter structure configured to optically identify each test line structure in the array. For example, each test line structure in the array may be configured to include a different optical device and / or may be configured to perform a different test. In such an embodiment, one or more first test line structures in the array may be configured to perform a wafer acceptance test (WAT), while a different one or more second test line structures may be used as monitoring structures configured to monitor the performance of semiconductor devices (e.g., optical devices) disposed within a device region on the semiconductor workpiece 102. In yet other embodiments, the test line structure 108 is directly adjacent to a corresponding optical I / O structure in the plurality of optical I / O structures 114.

[0179] Fig. 13B and Fig. 13C Show Fig.13A Various diagrams of some embodiments of chip-on-chip optical device 1302 are shown. Fig. 13B Show Fig.13A A top view 1300b of some embodiments of an optical device 1302 is shown. Fig. 13C Shown along Fig. 13B A cross-sectional view 1300c of some embodiments of the optical device 1302 is shown taken along line AA'.

[0180] like Fig. 13BAs shown in the top view 1300b of FIG. 1300 , the ring waveguide 1304 includes a first doped region 706 having a first doping type (e.g., p-type) and a second doped region 708 having a second doping type (e.g., n-type) opposite to the first doping type. The first doped region 706 adjoins the second doped region 708 along a pn junction. In addition, the first doped contact region 702 adjoins the first doped region 706, and the second doped contact region 704 adjoins the second doped region 708. In various embodiments, the first doped contact region 702 includes a first doping type (e.g., p-type), and the second doped contact region 704 includes a second doping type (e.g., n-type).

[0181] The first doped contact region 702 is electrically coupled to the first doped region 706 and is configured to supply a first bias voltage to the first doped region 706. In addition, the second doped contact region 704 is electrically coupled to the second doped region 708 and is configured to supply a second bias voltage to the second doped region 708. By supplying appropriate bias conditions to the first doped region 706 and the second doped region 708, the refractive index of the ring waveguide 1304 is adjusted, thereby introducing one or more phase shifts along the ring waveguide 1304. In various embodiments, the plurality of electrical I / O structures ( Fig.13A 116) is electrically coupled to the first doped region 706 and the second doped region 708 via the first doped contact region 702 and the second doped contact region 704. Therefore, the plurality of electrical I / O structures ( Fig.13A 116) can supply one or more electrical test signals to the first doped region 706 and the second doped region 708 during, for example, a wafer acceptance test (WAT), a device monitoring process, or the like.

[0182] In various embodiments, the outer radius 1316 of the ring waveguide 1304 is in the range of about 0.1 micrometers to 30 micrometers or some other suitable value. In other embodiments, the size 1318 of the ring waveguide 1304 is in the range of about 0.01 micrometers to 10 micrometers or some other suitable value. In some embodiments, the width of the first I / O waveguide 1306 and / or the second I / O waveguide 1308 is respectively in the range of about 0.01 micrometers to 10 micrometers or some other suitable value. In still other embodiments, the spacing 1314 between the ring waveguide 1304 and the first I / O waveguide 1306 and / or the second I / O waveguide 1308 is in the range of about 0.01 micrometers to 10 micrometers or some other suitable value.

[0183] like Fig. 13CAs shown in the cross-sectional view 1300c of FIG. 1300, one or more vias 654 overlie the first doped contact region 702 and the second doped contact region 704 and are electrically coupled to the first doped contact region 702 and the second doped contact region 704. The first doped region 706 and the second doped region 708 of the ring waveguide 1304 are adjacent to each other and are laterally disposed between the first doped contact region 702 and the second doped contact region 704. In various embodiments, the first doped contact region 702 and the second doped contact region 704 and the first doped region 706 and the second doped region 708 may have the following configurations: Figure 7B Height and width as shown and / or described.

[0184] Fig.14A and Fig. 14B Show Fig.13A Various diagrams of some other embodiments of optical device 1302 are shown. Fig.14A Show Fig.13A A top view 1400a of some embodiments of optical device 1302 is shown. Fig. 14B Shown along Fig.14A A cross-sectional view 1400b of some embodiments of the optical device 1302 is shown taken along line AA'.

[0185] like Fig.14A As shown, a heater structure 1402 directly overlies the ring waveguide 1304. The heater structure 1402 is configured to generate heat that propagates toward the ring waveguide 1304 and changes (e.g., increases) the temperature of the ring waveguide 1304. The change in the temperature of the ring waveguide 1304 adjusts the characteristics of the ring waveguide 1304 (e.g., adjusts the refractive index of the ring waveguide 1304) and introduces one or more phase shifts to the optical signal transmitted along the ring waveguide 1304 and / or within the ring waveguide 1304. In various embodiments, the heater structure 1402 is configured to generate heat that propagates toward the ring waveguide 1304 and changes (e.g., increases) the temperature of the ring waveguide 1304. The change in the temperature of the ring waveguide 1304 adjusts the characteristics of the ring waveguide 1304 (e.g., adjusts the refractive index of the ring waveguide 1304) and introduces one or more phase shifts to the optical signal transmitted along the ring waveguide 1304 and / or within the ring waveguide 1304. Fig.13A 116) applies one or more bias voltages to the heater structure 1402 to generate heat.

[0186] like Fig. 14B As shown, the heater structure 1402 is disposed within the interconnect dielectric structure 646 and is vertically spaced apart from the ring waveguide 1304. In various embodiments, the distance between the heater structure 1402 and the ring waveguide 1304 is in a range of approximately 0.01 microns to 10 microns or some other suitable value.

[0187] Fig.15A and Fig. 15B Various diagrams illustrating some other embodiments of an integrated chip having a testline structure 108 including an optical I / O structure 114 , a plurality of electrical I / O structures 116 , and an optical device 1502 . Fig.15A A top view 1500a of some embodiments of an integrated chip is shown. Fig. 15B Shown along Fig.15A A cross-sectional view 1500b of some embodiments of an integrated chip is shown taken along line AA′.

[0188] like Fig.15A As shown, in various embodiments, the optical device 1502 is configured as a light sensor (e.g., a photodiode) or some other suitable device. In some embodiments, the optical device 1502 includes a photodetector layer 1504 disposed within the waveguide 1501. The optical I / O structure 114 is optically coupled to the waveguide 1501 and is configured to receive an input optical signal. The input optical signal is provided to the optical device 1502 by the waveguide 1501 and the optical I / O structure 114. In some embodiments, the electrical I / O structure 116 is configured to receive an output electrical signal from the optical device 1502 based on the response of the optical device 1502 to the input optical signal. In some embodiments, the waveguide 1501 includes a first semiconductor material (e.g., silicon), and the photodetector layer 1504 includes a second semiconductor material (e.g., germanium) different from the first semiconductor material.

[0189] like Fig. 15B As shown, in various embodiments, the first doped contact region 702 and the second doped contact region 704 are disposed in the active layer 634 on opposite sides of the optical device 1502. The first doped contact region 702 includes a first doping type (e.g., p-type), and the second doped contact region 704 includes a second doping type (e.g., n-type) opposite to the first doping type. In various embodiments, the first doped contact region 702 and the second doped contact region 704 are electrically coupled to the electrical I / O structure ( Fig.15A In some embodiments, the output electrical signal from the optical device 1502 can be provided to the electrical I / O structure ( Fig.15A 116). In some embodiments, the width 1506 of the waveguide 1501 is in the range of about 0.01 microns to 10 microns or some other suitable value. In various embodiments, the width 1508 of the light sensor layer 1504 can be in the range of about 0.01 microns to 10 microns or some other suitable value. In other embodiments, the height 1510 of the light sensor layer 1504 can be in the range of 0.01 microns to 10 microns or some other suitable value.

[0190] FIG. 16A to FIG. 16CVarious diagrams of some embodiments of an integrated chip including a test line structure 108 disposed between a first device region 1602a and a second device region 1602b are shown. Fig. 16C A top view 1600c of some embodiments of an integrated chip is shown. Fig.16A A cross-sectional view 1600a of some embodiments of an integrated chip is shown, wherein Fig.16A The portion of the cross-sectional view 1600a is shown along Fig. 16C The top view 1600c is taken along line AA'. Fig. 16B A cross-sectional view 1600b of some embodiments of an integrated chip is shown, wherein Fig. 16B The portion of the cross-sectional view 1600b shown is along Fig. 16C The top view 1600c is taken along line BB'.

[0191] The first device area 1602a includes a first plurality of optical devices 1604, 1606, and the second device area 1602b includes a second plurality of optical devices 1608, 1610. In various embodiments, the first plurality of optical devices 1604, 1606 and the second plurality of optical devices 1608, 1610 are each configured as or include an optical sensor, an optical modulator, an optical interferometer, a waveguide, a grating coupler, some other suitable optical device, or any combination of the foregoing. The test line structure 108 includes a plurality of optical I / O structures 114, a plurality of electrical I / O structures 116, and a plurality of optical devices 602-608. In various embodiments, the test line structure 108 may be configured as Fig. 6A and Figure 6B It should be understood that although the test line structure 108 is configured as shown and / or described. FIG. 6A to FIG. 6B 1 and / or described, but the test line structure 108 may also be configured as Figure 11 to Figure 12 , FIG. 13A to FIG. 13C or FIG. 15A to FIG. 15B Configuration as shown and / or described.

[0192] like Fig.16AAs shown, the interconnect structure 643 overlies the semiconductor workpiece 102. In some embodiments, the first device area 1602a is part of the first semiconductor die, and the second device area 1602b is part of the second semiconductor die. The first plurality of optical devices 1604, 1606 are disposed in and / or on the semiconductor workpiece 102 and include a first optical device 1604 and a second optical device 1606. In some embodiments, the first optical device 1604 is configured as a grating coupler and can receive optical signals from and / or transmit optical signals to other optical devices disposed in the first device area 1602a. In other embodiments, the second optical device 1606 includes two or more optical waveguides 1612, which can be part of or configured as an optical modulator or some other suitable optical device. In various embodiments, the first optical device 1604 may be configured to receive an input optical signal and provide the input optical signal to at least one of the optical waveguides 1612 .

[0193] Test line structure ( Fig. 16C 108) is disposed in the test line area 106. In some embodiments, the test line area 106 is directly located between the first device area 1602a and the second device area 1602b. At least one of the optical I / O structures 114 is disposed in the test line area 106 and optically coupled to the first waveguide 601. A plurality of optical I / O channels 648 extend through the passivation structure 650 and the interconnect structure 643. The optical I / O channels 648 overlie the first optical device 1604 and the optical I / O structures 114. In various embodiments, the optical I / O channels 648 can be configured as a fiber optic waveguide, a light pipe structure, or the like, and the optical I / O channels 648 are configured to provide input optical signals and / or receive output optical signals.

[0194] The second plurality of optical devices 1608, 1610 are disposed within and / or on the semiconductor workpiece 102 and include a third optical device 1608 and a fourth optical device 1610. In various embodiments, the third optical device 1608 is configured as a photo sensor (e.g., a photodiode) or some other optical device, and / or the fourth optical device 1610 is configured as a waveguide, an optical core structure, or some other optical device. In other embodiments, the third optical device 1608 includes a photodetector waveguide 1616 and a photodetector layer 1614 disposed within the photodetector waveguide 1616. In yet other embodiments, the fourth optical device 1610 includes a waveguide 1618. The conductive traces 652 and the vias 654 overlie the third optical device 1608 and / or the fourth optical device 1610 and can be electrically coupled to the third optical device 1608 and / or the fourth optical device 1610.

[0195] like Fig. 16B As shown, the electrical I / O structure 116 is disposed in the test line area 106. In addition, the first plurality of bonding pads 1620 is disposed in the first device area 1602a, and the second plurality of bonding pads 1622 is disposed in the second device area 1602b. In some embodiments, the electrical I / O structure 116, the first plurality of bonding pads 1620, and the second plurality of bonding pads 1622 respectively include conductive materials (e.g., titanium, platinum, gold, some other conductive material, or any combination of the foregoing materials). The electrical I / O structure 116, the first plurality of bonding pads 1620, and the second plurality of bonding pads 1622 are electrically coupled to corresponding devices (e.g., optical devices) disposed on the semiconductor workpiece 102 by means of the plurality of conductive wires 652 and the vias 654. For example, the second plurality of bonding pads 1622 can be directly electrically coupled to the third optical device 1608 and the fourth optical device 1610 by means of the conductive wires 652 and the vias 654.

[0196] Fig.17 A top view 1700 of some embodiments of an integrated chip with a plurality of semiconductor dies 104 laterally adjacent to each other is shown.

[0197] In some embodiments, each semiconductor die 104 includes a device region 1602 that includes a plurality of semiconductor devices (e.g., optical devices) disposed within and / or on the semiconductor workpiece 102. In some embodiments, during fabrication, the semiconductor dies 104 are separated from one another by "dicing" the semiconductor workpiece 102 along orthogonal scribe lines (or saw "streets") 1702, 1704 using a singulation process. In various embodiments, the singulation process includes cutting through the scribe lines 1702, 1704 using a saw blade and / or a cutting laser. In other embodiments, one or more test line structures 108 are disposed along each of the scribe lines 1702, 1704. For example, the test line structure 108 may be disposed within a first scribe line 1702a between a first semiconductor die 104a and a second semiconductor die 104b, wherein the first semiconductor die 104a and the second semiconductor die 104b include a first device region 1602a and a second device region 1602b, respectively. The one or more test line structures 108 each include one or more optical I / O structures 114 and one or more electrical I / O structures 116, and the one or more optical I / O structures 114 and the one or more electrical I / O structures 116 are respectively configured to receive one or more optical test signals and one or more electrical test signals. In various embodiments, the one or more test line structures 108 are configured to perform wafer acceptance testing, device monitoring processes, or similar stages during the fabrication of semiconductor dies before performing a singulation process. In yet other embodiments, the one or more test line structures 108 include one or more optical devices (e.g., Fig. 6A , Fig.11 , Fig.13A or Fig.15A shown and / or described).

[0198] Figures 18 to 23B Various cross-sectional views 1800 to top views 2300b are shown in accordance with some embodiments of a method for forming an integrated chip having a test line structure according to the present invention, wherein the test line structure includes an electrical I / O structure and an optical I / O structure. Figures 18 to 23B The various cross-sectional views 1800 to the top view 2300b shown in FIG. 1 are described with reference to one method, but it should be understood that Figures 18 to 23B The structure shown in is not limited to the method, but can exist independently of the method. Figures 18 to 23B It is described as a series of actions, but it should be understood that these actions are not restrictive, the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0199] like Fig.18As shown in the cross-sectional view 1800 of FIG. 1 , a semiconductor workpiece 102 is provided. In various embodiments, the semiconductor workpiece 102 may be or may include a semiconductor body (e.g., silicon, silicon germanium, etc.), such as a semiconductor wafer and / or one or more semiconductor dies on the wafer, any other type of semiconductor and / or epitaxial layer or similar components. In some embodiments, the semiconductor workpiece 102 includes an SOI substrate having a base substrate 630 separated from an active layer 634 by an insulator structure 632. In addition, the semiconductor workpiece 102 includes a first device region 1602a separated from a second device region 1602b by a test line region 106.

[0200] like Fig.19A The cross-sectional view 1900a and Fig.19B As shown in the top view 1900b of FIG. 1 , a first plurality of optical devices 1604, 1606 are formed in the first device area 1602a, a plurality of optical I / O structures 114 are formed in the testline area 106, and a second plurality of optical devices 1608, 1610 are formed in the second device area 1602b. In various embodiments, a plurality of optical devices 602 to 608 are formed adjacent to the plurality of optical I / O structures 114 in the testline area 106. In some embodiments, the process for forming the optical devices 1604 to 1610, 602 to 608 includes performing one or more patterning processes, performing one or more deposition processes, performing one or more selective ion implantation processes, or the like on the active layer 634. In various embodiments, the process for forming the plurality of optical I / O structures 114 includes: forming a masking layer (not shown) over the active layer 634; performing an etching process (e.g., a wet etching process, a dry etching process, or any combination of the foregoing processes) on the active layer 634 with the masking layer in place; and performing a removal process to remove the patterned masking layer. In still other embodiments, the plurality of optical I / O structures 114 and / or the plurality of optical devices 602 to 608 may be formed simultaneously with each other and / or may be formed simultaneously with one or more of the first plurality of optical devices in the first device area 1602a and the second device area 1602b and the optical devices in the second plurality of optical devices 1604 to 1610.

[0201] Fig.19B Shown with Fig.19A The cross-sectional view 1900a corresponds to a top view 1900b of the test line area 106 . Fig.19A A portion of the cross-sectional view 1900a is taken along Fig.19B The top view 1900b is taken along line AA'.

[0202] like Fig. 20As shown in the cross-sectional view 2000 of FIG. 2 , a dielectric layer 644 is formed on the semiconductor workpiece 102. The dielectric layer 644 may be formed by depositing the dielectric layer 644 on the semiconductor workpiece 102 by, for example, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or some other suitable deposition or growth process.

[0203] like Fig.21A A cross-sectional view 2100a, Fig. 21B The cross-sectional view 2100b and Fig. 21C As shown in the top view 2100c of the semiconductor workpiece 102, an interconnect structure 643 and a passivation structure 650 are formed on the semiconductor workpiece 102. The interconnect structure 643 includes a plurality of conductive wires 652 and a plurality of vias 654 disposed in the interconnect dielectric structure 646. The interconnect structure 643 can be formed by one or more patterning processes, one or more deposition processes, some other suitable manufacturing processes, or any combination of the foregoing processes. The passivation structure 650 can be formed by depositing the passivation structure 650 on the interconnect structure 643, for example, by a PVD process, a CVD process, an ALD process, or some other suitable deposition or growth process.

[0204] Fig. 21C Shown with Fig.21A The cross-sectional view 2100a and Fig. 21B The cross-sectional view 2100b is shown in a corresponding top view 2100c of the test line area 106 . Fig.21A The portion of the cross-sectional view 2100a shown is along Fig. 21C The top view 2100c is taken along line AA'. Fig. 21B The portion of the cross-sectional view 2100b shown is along Fig. 21C The top view 2100c is taken along line BB'.

[0205] like Fig.22A 2200a, Fig. 22B The cross-sectional view 2200b and Fig. 22CAs shown in the top view 2200c, a first plurality of bonding pads 1620 are formed in the first device area 1602a, a second plurality of bonding pads 1622 are formed in the second device area 1602b, and a plurality of electrical I / O structures 116 are formed in the test line area 106, thereby forming a test line structure 108 in the test line area 106. In some embodiments, the process for forming the first plurality of bonding pads 1620 and the second plurality of bonding pads 1622 and the plurality of electrical I / O structures 116 includes: forming a shielding layer (not shown) on the passivation structure 650; performing an etching process (e.g., a dry etching process, a wet etching process, etc.) on the passivation structure 650 according to the shielding layer to form a plurality of openings in the passivation structure 650; depositing (e.g., by CVD, PVD, sputtering, electroplating, electroless plating, etc.) a conductive material (e.g., titanium, platinum, gold, some other conductive material, or any combination of the foregoing materials) in the plurality of openings; and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) on the conductive material. It should be understood that although the test line structure 108 is formed as FIG. 16A to FIG. 16C As shown and / or described above, the test line structure 108 may also be formed as Fig.11 , FIG. 13A to FIG. 13C or FIG. 15A to FIG. 15B Configuration as shown and / or described.

[0206] Fig. 22C Shown with Fig.22A The cross-sectional view 2200a and Fig. 21B The cross-sectional view 2200b corresponds to the top view 2200c of the test line area 106. Fig.22A The portion of the cross-sectional view 2200a shown is along Fig. 22C The top view 2200c is taken along line AA'. Fig. 22B The portion of the cross-sectional view 2200b shown is along Fig. 22C The top view 2200c is taken along line BB'.

[0207] like Fig.23A The cross-sectional view 2300a and Fig. 23B As shown in the top view 2300b of FIG. 2300, a plurality of optical I / O channels 648 are formed in the interconnect structure 643 and the passivation structure 650. In some embodiments, the process for forming the optical I / O channels 648 includes: etching the passivation structure 650 and the interconnect dielectric structure 646 to form a plurality of openings extending through the passivation structure 650 and the interconnect dielectric structure 646; and depositing optical channel materials in the plurality of openings.

[0208] Fig. 23B Shown with Fig.23AThe cross-sectional view 2300a corresponds to the top view 2300b of the test line area 106. Fig.23A The portion of the cross-sectional view 2300a shown is taken along Fig. 23B The top view 2300b is taken along line AA'.

[0209] Fig.24 Flowchart 2400 showing some embodiments of a method for forming an integrated chip including a test line structure, wherein the test line structure includes multiple optical I / O structures and multiple electrical I / O structures. Although the method shows and / or describes a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be performed in a different order than shown and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0210] At act 2402, a plurality of optical input / output (I / O) structures are formed within a testline region of a semiconductor workpiece. Fig.19A and Fig.19B Various diagrams corresponding to some embodiments of act 2402 are shown.

[0211] At act 2404, a first plurality of optical devices is formed in a first device region laterally adjacent to the testline region. Fig.19A and Fig.19B Various diagrams corresponding to some embodiments of act 2404 are shown.

[0212] At act 2406, an interconnect structure is formed over the semiconductor workpiece, wherein the interconnect structure overlies the plurality of optical I / O structures. FIG. 21A to FIG. 21C Various diagrams corresponding to some embodiments of act 2406 are shown.

[0213] At act 2408, a passivation structure is deposited over the interconnect structure. FIG. 21A to FIG. 21C Various diagrams corresponding to some embodiments of act 2408 are shown.

[0214] At act 2410, a plurality of electrical I / O structures are formed in the passivation structure. The plurality of electrical I / O structures are laterally spaced apart within the test line region and laterally adjacent to the optical I / O structure. FIG. 22A to FIG. 22C Various diagrams corresponding to some embodiments of act 2410 are shown.

[0215] Therefore, in some embodiments, the present invention is related to an integrated chip having a test line structure, wherein the test line structure includes a plurality of optical I / O structures and a plurality of electrical I / O structures disposed in a test line area.

[0216] In some embodiments, the utility model provides an integrated chip, comprising: a semiconductor workpiece; a test line structure disposed on the semiconductor workpiece, wherein the test line structure comprises a plurality of optical input / output (I / O) structures disposed in and / or on the semiconductor workpiece; and a plurality of electrical I / O structures located on the semiconductor workpiece, wherein the plurality of optical I / O structures and the plurality of electrical I / O structures are laterally separated from each other along a line extending in a first direction.

[0217] In one embodiment, in the integrated chip, the plurality of electrical input / output structures are configured to receive one or more electrical test signals from a wafer prober, and the plurality of optical input / output structures are configured to receive one or more optical test signals from the wafer prober. In one embodiment, in the integrated chip, the test line structure further comprises one or more optical devices, wherein the one or more optical devices are laterally spaced between a first optical input / output structure of the plurality of optical input / output structures and the plurality of electrical input / output structures. In one embodiment, in the integrated chip, the plurality of optical input / output structures comprises a second optical input / output structure, wherein the one or more optical devices comprises a first optical device, wherein the first optical input / output structure and the second optical input / output structure are optically coupled to the first optical device, wherein the first optical input / output structure is configured to receive an input optical signal and provide the input optical signal to the first optical device, wherein the first optical device is configured to generate an output optical signal based at least in part on the input optical signal, and wherein the second optical input / output structure is configured to receive the output optical signal. In one embodiment, in the integrated chip, the one or more optical devices include one or more doped regions, and the multiple electrical input / output structures include a first electrical input / output structure directly electrically coupled to the one or more doped regions. In one embodiment, in the integrated chip, the one or more optical devices include at least one of a beam splitter, a beam combiner, a Mach-Jand interferometer, and / or an optical modulator. In one embodiment, in the integrated chip, a first electrical input / output structure among the multiple electrical input / output structures directly overlies the one or more optical devices. In one embodiment, the integrated chip further includes: an interconnect structure overlying the semiconductor workpiece, wherein the multiple optical input / output structures are located below the interconnect structure and the multiple electrical input / output structures overlie the interconnect structure.

[0218] In some embodiments, the utility model provides an integrated chip, which includes: a first device area, which is arranged on a semiconductor workpiece and includes a first plurality of optical devices; a second device area, which is arranged on the semiconductor workpiece and includes a second plurality of optical devices, wherein the first device area is adjacent to the second device area; and a test line structure, which is arranged in the test line area, and the test line area is laterally separated between the first device area and the second device area, wherein the test line structure includes a plurality of optical input / output (I / O) structures and a plurality of electrical I / O structures adjacent to the plurality of optical I / O structures, wherein the plurality of electrical I / O structures are offset in a vertical direction relative to the plurality of electrical I / O structures.

[0219] In one embodiment, in the integrated chip, the test line structure further includes one or more third optical devices, the one or more third optical devices are optically coupled to at least one of the multiple optical input / output structures, and electrically coupled to at least one of the multiple electrical input / output structures. In one embodiment, in the integrated chip, the one or more third optical devices include a ring waveguide disposed between a first input / output waveguide and a second input / output waveguide. In one embodiment, in the integrated chip, the one or more third optical devices include a first waveguide separated from a second waveguide in a laterally direction, wherein the first waveguide includes a first doped region and a second doped region, wherein the at least one electrical input / output structure is electrically coupled to the first doped region. In one embodiment, in the integrated chip, the one or more third optical devices include a light sensor disposed in a first waveguide, wherein the light sensor includes a first material, and the first waveguide includes a second material different from the first material. In one embodiment, in the integrated chip, the test line structure further comprises a test line letter structure comprising one or more alphanumeric characters, wherein the test line letter structure is laterally adjacent to the plurality of optical input / output structures. In one embodiment, in the integrated chip, at least one of the plurality of optical input / output structures is optically coupled to at least one of the first plurality of optical devices, and at least one of the plurality of electrical input / output structures is electrically coupled to the at least one of the first plurality of optical devices.

[0220] In some embodiments, the present invention provides a method for forming an integrated chip, the method comprising: forming a plurality of optical input / output (I / O) structures in a test line region of a semiconductor workpiece; forming an internal connection structure on the semiconductor workpiece; and forming a plurality of electrical I / O structures on the internal connection structure and in the test line region, wherein the plurality of electrical I / O structures are laterally adjacent to the plurality of optical I / O structures.

[0221] In one embodiment, in the method, the semiconductor workpiece includes a base substrate separated from an active layer by an insulator structure, and wherein forming the plurality of optical input / output structures includes etching the active layer to form a plurality of grating coupler elements and grating tapered structures in the active layer. In one embodiment, in the method, forming the plurality of electrical input / output structures includes: depositing a passivation structure on the interconnect structure; etching the passivation structure to form a plurality of openings in the passivation structure; depositing a conductive material in the plurality of openings; and performing a planarization process on the conductive material, wherein the plurality of electrical input / output structures include a first material, and the plurality of optical input / output structures include a second material different from the first material. In one embodiment, the method further includes: forming one or more optical devices in the test line area, wherein the one or more optical devices are laterally spaced between the plurality of optical input / output structures and the plurality of electrical input / output structures. In one embodiment, the method further comprises: forming a first plurality of optical devices in a first device region laterally adjacent to the testline region, wherein the one or more optical devices in the testline region are formed simultaneously with the first plurality of optical devices.

[0222] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. An integrated chip, characterized in that: include: Semiconductor workpieces; as well as A test line structure is arranged on the semiconductor workpiece, wherein the test line structure comprises: a plurality of optical input / output structures disposed in and / or on the semiconductor workpiece; as well as A plurality of electrical input / output structures are located on the semiconductor workpiece, wherein the plurality of optical input / output structures and the plurality of electrical input / output structures are laterally spaced apart from each other along a line extending in a first direction.

2. The integrated chip according to claim 1, characterized in that: The test line structure further includes one or more optical devices, wherein the one or more optical devices are laterally spaced between a first optical input / output structure of the plurality of optical input / output structures and the plurality of electrical input / output structures.

3. The integrated chip according to claim 2, characterized in that: wherein the plurality of optical input / output structures include a second optical input / output structure, wherein the one or more optical devices include a first optical device, wherein the first optical input / output structure and the second optical input / output structure are optically coupled to the first optical device, wherein the first optical input / output structure is configured to receive an input optical signal and provide the input optical signal to the first optical device, wherein the first optical device is configured to generate an output optical signal based at least in part on the input optical signal, and wherein the second optical input / output structure is configured to receive the output optical signal.

4. The integrated chip according to claim 2, characterized in that: The one or more optical devices include one or more doped regions, and the plurality of electrical input / output structures include a first electrical input / output structure directly electrically coupled to the one or more doped regions.

5. The integrated chip according to claim 2, characterized in that: A first electrical input / output structure among the plurality of electrical input / output structures directly overlies the one or more optical devices.

6. An integrated chip, characterized in that: include: A first device region disposed on the semiconductor workpiece and comprising a first plurality of optical devices; a second device area disposed on the semiconductor workpiece and comprising a second plurality of optical devices, wherein the first device area is adjacent to the second device area; as well as A test line structure is arranged in a test line area, and the test line area is laterally separated between the first device area and the second device area, wherein the test line structure includes a plurality of optical input / output structures and a plurality of electrical input / output structures adjacent to the plurality of optical input / output structures, wherein the plurality of electrical input / output structures are offset in a vertical direction relative to the plurality of optical input / output structures.

7. The integrated chip according to claim 6, characterized in that: The test line structure further includes one or more third optical devices, which are optically coupled to at least one of the multiple optical input / output structures and electrically coupled to at least one of the multiple electrical input / output structures.

8. The integrated chip according to claim 7, characterized in that: The one or more third optical devices include a ring waveguide disposed between the first input / output waveguide and the second input / output waveguide.

9. The integrated chip according to claim 7, characterized in that: The one or more third optical devices include a first waveguide laterally separated from a second waveguide, wherein the first waveguide includes a first doped region and a second doped region, and wherein the at least one electrical input / output structure is electrically coupled to the first doped region.

10. The integrated chip according to claim 6, characterized in that: The test line structure further comprises a test line letter structure including one or more alphanumeric characters, wherein the test line letter structure is laterally adjacent to the plurality of optical input / output structures.

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