Package structure
By setting trenches in the top conductive layer of the substrate, the orthoprojection part of the inductor is located in the trenches, the electromagnetic interference problem caused by on-chip inductor is solved, the electrical performance of the package structure is improved and the manufacturing process is simplified.
Patent Information
- Application Number
- CN202421444291.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-21
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2034-06-21
AI Technical Summary
After mounting a chip with a planar spiral inductance onto the substrate, the electronic components on the substrate are susceptible to electromagnetic interference, affecting the electrical performance of the packaging structure.
A through groove is provided in the top conductive layer of the substrate, and the orthogonal projection of the inductor on the functional chip on the substrate is at least partially located in the groove, thereby blocking the transmission path of the inductive eddy current.
The electromagnetic interference of induction eddy current on electronic components in the package structure is effectively avoided, the electrical performance of the package structure is improved, and the manufacturing process is simplified and the integration is improved.
Smart Images
Figure CN222705519U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuits, and in particular to a packaging structure. Background Art
[0002] Inductors are commonly used passive devices in packaging structures, and are often used to implement functions such as filtering, choking, and energy storage. On-chip inductors are inductors prepared on chips. Planar spiral inductors are a common on-chip inductor structure. However, after the chip with a planar spiral inductor is mounted on a substrate, it is very easy for the electronic components on the substrate to be subject to electromagnetic interference (EMI), thereby affecting the performance of the packaging structure. Specifically, after the chip with an inductor is mounted (for example, flip-chip) on the substrate, the top metal layer on the substrate will affect the magnetic field of the inductor, and the change in the inductor magnetic flux will generate eddy currents, which will be transmitted through the top metal layer on the substrate to other electronic components in the packaging structure (such as electronic components on the substrate or electronic components in the functional chip), thereby affecting the overall electrical performance of the packaging structure.
[0003] Therefore, how to reduce the electromagnetic interference problem in a packaging structure with an on-chip inductor, thereby improving the electrical performance of the packaging structure, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The utility model provides a packaging structure, which is used for reducing the electromagnetic interference problem in the packaging structure with on-chip inductance, thereby improving the electrical performance of the packaging structure.
[0005] According to some embodiments, the utility model provides a packaging structure, including:
[0006] A substrate, the substrate comprising a substrate body, a top conductive layer exposed on a top surface of the substrate body, and a groove located in the top conductive layer, the groove penetrating the top conductive layer;
[0007] A functional chip is flip-mounted on the substrate, wherein the functional chip includes an inductor, and an orthographic projection of the inductor on the substrate is at least partially located in the groove.
[0008] In some embodiments, the functional chip further includes pads distributed around the periphery of the inductor; and the packaging structure further includes:
[0009] An electrical connection bump is located between the functional chip and the substrate, one end of the electrical connection bump is electrically connected to the pad, and the other end of the electrical connection bump is electrically connected to the top conductive layer.
[0010] In some embodiments, at least the orthographic projection of a center position of the inductor on the substrate is located within the trench.
[0011] In some embodiments, an orthographic projection of the inductor on the substrate is entirely located within the trench.
[0012] In some embodiments, the orthographic projection of the inductor on the substrate is only partially located in the groove, and the groove extends outward from the center position of the orthographic projection of the inductor on the substrate to a side edge position of the orthographic projection of the inductor on the substrate.
[0013] In some embodiments, an orthographic projection of the inductor on the substrate is only partially located within the trench, and the trench crosses the orthographic projection of the inductor on the substrate.
[0014] In some embodiments, the groove is in the shape of an elongated strip, and the width of the groove is 5 μm to 10 μm.
[0015] In some embodiments, the top conductive layer has a plurality of the grooves, and an orthographic projection of the inductor on the substrate at least partially overlaps with each of the grooves.
[0016] In some embodiments, the functional chip further includes a grounding structure, and the grounding structure is distributed around the periphery of the inductor.
[0017] In some embodiments, the inductor is a planar spiral inductor, an 8-shaped inductor, or a four-leaf clover-shaped inductor.
[0018] The packaging structure provided by the utility model includes a substrate and a functional chip flipped on the substrate, and the functional chip has an inductor. By setting a groove in the top conductive layer of the substrate and making the groove penetrate the top conductive layer, the positive projection of the inductor on the substrate is at least partially located in the groove, thereby destroying the induced eddy current generated by the on-chip inductor due to flipping on the top surface of the substrate, blocking the transmission path of the induced eddy current in the top conductive layer, and thus avoiding the electromagnetic interference of the induced eddy current on the electronic components in the packaging structure, thereby effectively improving the electrical performance of the packaging structure. The utility model only needs to make a groove in the top conductive layer, and does not need to occupy the area on the functional chip, which not only helps to simplify the manufacturing process of the packaging structure, but also helps to improve the integration of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Attached Figure 1 It is a cross-sectional schematic diagram of a packaging structure in a specific implementation mode of the utility model;
[0020] Attached Figure 2This is a schematic diagram of the relative position relationship between the inductor and the groove in a specific implementation manner of the utility model;
[0021] Attached Figure 3 is another schematic diagram of the relative position relationship between the inductor and the groove in a specific implementation manner of the utility model;
[0022] Attached Figure 4 It is another schematic diagram of the relative position relationship between the inductor and the groove in a specific implementation manner of the utility model;
[0023] Attached Figure 5 is another schematic diagram of the relative position relationship between the inductor and the groove in a specific implementation manner of the utility model;
[0024] Attached Figure 6 It is a partial structural diagram of a functional chip in another packaging structure in a specific implementation manner of the utility model. DETAILED DESCRIPTION
[0025] The specific implementation of the packaging structure provided by the utility model is described in detail below with reference to the accompanying drawings.
[0026] This specific implementation provides a packaging structure, Figure 1 is a schematic cross-sectional view of a packaging structure in a specific implementation mode of the utility model, Figure 2 Schematic diagram of the relative position relationship between the inductor and the groove in a specific implementation mode of the utility model. Figure 1 and Figure 2 As shown, the packaging structure includes:
[0027] A substrate, the substrate comprising a substrate body 10, a top conductive layer 11 exposed on a top surface of the substrate body 10, and a groove 15 located in the top conductive layer 11, wherein the groove 15 penetrates the top conductive layer 11;
[0028] The function chip 13 is flip-chip mounted on the substrate. The function chip 13 includes an inductor 131 . The orthographic projection of the inductor 131 on the substrate is at least partially located in the groove 15 .
[0029] Specifically, the substrate includes a top surface and a bottom surface that are relatively distributed, and a solder ball 12 is provided on the bottom surface of the substrate. The substrate includes the substrate body 10, and the substrate body 10 has multiple conductive layers, and the multiple conductive layers are arranged in sequence along the direction from the bottom surface of the substrate to the top surface of the substrate, wherein the conductive layer located at the top layer serves as the top conductive layer 11, and the top conductive layer 11 is exposed on the top surface of the substrate body 10. In one example, the top conductive layer 11 is a metal layer. The groove 15 passing through the top conductive layer 11 means that the groove 15 passes through the top conductive layer 11 in the direction from the bottom surface of the substrate to the top surface of the substrate. In one example, the inductor 131 is located on the surface of the functional chip 13 facing the substrate. The inductor 131 can be integrated on the functional chip 13 to form an on-chip inductor structure.
[0030] This specific embodiment sets the groove 15 penetrating the top conductive layer 11 in the top conductive layer 11 of the substrate, and makes the orthographic projection of the inductor 131 in the functional chip 13 on the substrate at least partially located in the groove 15, so that even if the top conductive layer 11 affects the inductor 131 and forms an induced eddy current, the transmission path of the induced eddy current in the top conductive layer can be blocked by the groove 15, thereby destroying the induced eddy current, thereby avoiding the electromagnetic interference of the induced eddy current on the electronic components in the packaging structure, thereby effectively improving the electrical performance of the packaging structure. This specific embodiment only needs to groove the top conductive layer, does not need to occupy the area on the functional chip, and is applicable to inductors of various shapes, which not only helps to simplify the manufacturing process of the packaging structure, but also helps to improve the integration of the packaging structure.
[0031] In some embodiments, the functional chip 13 further includes pads 132 distributed on the periphery of the inductor 131; the packaging structure further includes:
[0032] The electrical connection bump 14 is located between the functional chip 13 and the substrate. One end of the electrical connection bump 14 is electrically connected to the pad 132 , and the other end of the electrical connection bump 14 is electrically connected to the top conductive layer 11 .
[0033] For example, if Figure 1 and Figure 2As shown, the solder pads 132 are distributed around the periphery of the inductor 131. In one example, the solder pads 132 are arranged in the same layer as the inductor 131, and the material of the solder pads 132 is the same as the material of the inductor 131, so that the solder pads 132 and the inductor 131 can be formed simultaneously to simplify the manufacturing process of the functional chip 13. In one example, the material of the solder pads 132 and the material of the inductor 131 are both metal aluminum. A plurality of electrical connection bumps 14 are distributed between the functional chip 13 and the substrate, and one end of the electrical connection bump 14 is electrically connected to the solder pad 132 and the other end is electrically connected to the top conductive layer 11 to achieve electrical connection between the functional chip 13 and the substrate.
[0034] In one example, the inductor 131 is located at the edge of the functional chip 13, so that the groove 15 is also located at the edge of the top conductive layer 11, so as to avoid the groove 15 occupying the space in the middle area of the top conductive layer 11, thereby avoiding affecting the electrical performance of the top conductive layer 11 and the electrical connection performance between the top conductive layer 11 and the functional chip 13. In another example, the inductor 131 is located in the middle of the functional chip 13, and a plurality of electrical connection bumps 14 are distributed around the periphery of the inductor 131 to improve the design flexibility of the functional chip 13.
[0035] In some embodiments, at least the orthographic projection of the center position of the inductor 131 on the substrate is located within the groove 15 .
[0036] Specifically, since the induced eddy current generated at the center position of the inductor 131 is the strongest, by making at least the orthographic projection of the center position of the inductor 131 on the substrate located within the groove 15, the induced eddy current at the strongest point can be directly blocked, thereby further effectively avoiding the electromagnetic interference of the induced eddy current on the electronic components in the packaging structure, thereby effectively improving the electrical performance of the packaging structure.
[0037] Attached Figure 5 FIG. 1 is another schematic diagram of the relative position relationship between the inductor and the groove in a specific embodiment of the present invention. Figure 5 As shown, the orthographic projection of the inductor 131 on the substrate is entirely located within the groove 15 .
[0038] For example, if Figure 5As shown, the orthographic projection of the inductor 131 on the substrate is entirely located in the groove 15, that is, the cross-sectional area of the groove 15 is greater than or equal to the area of the orthographic projection of the inductor 131 on the substrate, so that the transmission of the induced eddy current in the top conductive layer 11 can be fully and thoroughly blocked, so as to completely avoid the electromagnetic interference of the induced eddy current generated by the inductor 131 on the electronic components in the packaging structure. In one example, the cross-sectional shape of the groove 15 can be rectangular, circular, elliptical or any polygon.
[0039] In some embodiments, the orthographic projection of the inductor 131 on the substrate is only partially located in the groove 15 , and the groove 15 extends from the edge position of the orthographic projection of the inductor 131 on the substrate to the center position of the orthographic projection of the inductor 131 on the substrate.
[0040] In some embodiments, the orthographic projection of the inductor 131 on the substrate is only partially located in the groove 15 , and the groove 15 crosses the orthographic projection of the inductor 131 on the substrate.
[0041] Specifically, if Figure 2 As shown, the groove 15 is in the shape of an elongated strip, and the cross-sectional area of the groove 15 is smaller than the orthographic projection area of the inductor 131 on the substrate, so that the orthographic projection of the inductor 131 on the substrate is only partially located in the groove 15, and the groove 15 crosses the orthographic projection of the inductor on the substrate. In one example, the groove 15 is in the shape of an elongated strip, and the groove 15 extends in a direction parallel to the top surface of the substrate, and the groove 15 passes through the orthographic projection of the inductor 131 on the substrate along its extension direction, and the center position of the orthographic projection of the inductor 131 on the substrate is located in the groove 15. Using the method as shown in FIG. Figure 2 The structure shown can not only effectively block the transmission path of the induced eddy current in the top conductive layer 11 , but also reduce the space occupied on the top conductive layer 11 , thereby avoiding affecting the structure and function of the top conductive layer 11 .
[0042] Attached Figure 4 1 is another schematic diagram of the relative position relationship between the inductor and the groove in a specific embodiment of the utility model. In some other embodiments, the orthographic projection of the inductor 131 on the substrate is only partially located in the groove 15, and the groove 15 extends outward from the center position of the orthographic projection of the inductor 131 on the substrate to the edge position of one side of the orthographic projection of the inductor 131 on the substrate.
[0043] For example, if Figure 4As shown, the groove 15 is in the shape of a long strip and extends in a direction parallel to the top surface of the substrate. The groove 15 includes a first end and a second end that are relatively distributed along the extension direction. The center position of the orthographic projection of the inductor 131 on the substrate is located in the first end of the groove 15, and one side edge of the orthographic projection of the inductor 131 on the substrate is located in the groove 15, that is, the second end of the groove 15 is located outside one side edge of the orthographic projection of the inductor 131 on the substrate. Figure 4 The structure shown can not only effectively block the transmission path of the induced eddy current in the top conductive layer 11 , but also further reduce the space occupied by the groove 15 in the top conductive layer 11 , thereby further avoiding affecting the structure and function of the top conductive layer 11 .
[0044] The width of the groove 15 should not be too wide, otherwise it will occupy too much space in the top conductive layer 11; the width of the groove 15 should not be too narrow, otherwise it cannot effectively block the transmission of the induced eddy current. In some embodiments, the groove 15 is long and has a width of 5 μm to 10 μm, so as to effectively block the transmission of the induced eddy current while avoiding occupying too much space in the top conductive layer 11.
[0045] Attached Figure 3 FIG. 1 is another schematic diagram of the relative position relationship between the inductor and the groove in a specific embodiment of the utility model. Figure 3 As shown, the top conductive layer 11 has a plurality of grooves 15 , and the orthographic projection of the inductor 131 on the substrate at least partially overlaps with each groove 15 .
[0046] In one example, if Figure 3 As shown, the plurality of grooves 15 are arranged in parallel and at intervals, and the orthographic projection of the inductor 131 on the substrate at least partially overlaps with each groove 15, thereby further effectively blocking the transmission of the induced eddy current and simplifying the manufacturing process of the packaging structure. In other examples, the plurality of grooves 15 can also be arranged to intersect to increase the flexibility of the groove 15 design.
[0047] In some embodiments, the function chip 13 further includes a grounding structure, and the grounding structure is distributed around the periphery of the inductor 131 .
[0048] Specifically, the grounding structure can block electromagnetic propagation. In one example, the grounding structure can be a grounding bump. The setting of the grounding structure and the setting of the groove 15 cooperate to further avoid electromagnetic interference problems in the packaging structure.
[0049] In some embodiments, the inductor 131 is a planar spiral inductor, an 8-shaped inductor, or a four-leaf clover-shaped inductor.
[0050] Attached Figure 6 FIG. 1 is a schematic diagram of a portion of a functional chip in another package structure in a specific embodiment of the present invention. For example, by setting the inductor 131 as follows Figure 6 The figure-8-shaped inductor shown balances the magnetic flux on both sides of the inductor 131 to reduce the generation of the induced eddy current, thereby also helping to reduce the electromagnetic interference in the packaging structure.
[0051] The packaging structure provided in this specific embodiment includes a substrate and a functional chip flipped on the substrate, and the functional chip has an inductor. By setting a groove in the top conductive layer of the substrate and making the groove penetrate the top conductive layer, the orthographic projection of the inductor on the substrate is at least partially located in the groove, thereby destroying the induced eddy current generated by the on-chip inductor due to flipping on the top surface of the packaging substrate, blocking the transmission path of the induced eddy current in the top conductive layer, and thus avoiding the electromagnetic interference of the induced eddy current on the electronic components in the packaging structure, thereby effectively improving the electrical performance of the packaging structure. This specific embodiment only needs to make a groove in the top conductive layer, and does not need to occupy the area on the functional chip, which not only helps to simplify the manufacturing process of the packaging structure, but also helps to improve the integration of the packaging structure.
[0052] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A packaging structure, characterized in that: include: A substrate, the substrate comprising a substrate body, a top conductive layer exposed on a top surface of the substrate body, and a groove located in the top conductive layer, the groove penetrating the top conductive layer; A functional chip is flip-mounted on the substrate, wherein the functional chip includes an inductor, and an orthographic projection of the inductor on the substrate is at least partially located in the groove.
2. The packaging structure according to claim 1, characterized in that: The functional chip further includes pads distributed on the periphery of the inductor; and the packaging structure further includes: An electrical connection bump is located between the functional chip and the substrate, one end of the electrical connection bump is electrically connected to the pad, and the other end of the electrical connection bump is electrically connected to the top conductive layer.
3. The packaging structure according to claim 1, characterized in that: At least the orthographic projection of the center position of the inductor on the substrate is located in the groove.
4. The packaging structure according to claim 3, characterized in that: The orthographic projection of the inductor on the substrate is entirely located in the groove.
5. The packaging structure according to claim 3, characterized in that: The orthographic projection of the inductor on the substrate is only partially located in the groove, and the groove extends outward from the center position of the orthographic projection of the inductor on the substrate to a side edge position of the orthographic projection of the inductor on the substrate.
6. The packaging structure according to claim 3, characterized in that: The orthographic projection of the inductor on the substrate is only partially located in the trench, and the trench crosses the orthographic projection of the inductor on the substrate.
7. The packaging structure according to claim 1, characterized in that: The groove is in the shape of an elongated strip, and the width of the groove is 5 μm to 10 μm.
8. The packaging structure according to claim 7, characterized in that: The top conductive layer has a plurality of grooves, and the orthographic projection of the inductor on the substrate at least partially overlaps with each of the grooves.
9. The packaging structure according to claim 1, characterized in that: The functional chip also includes a grounding structure, and the grounding structure is distributed around the periphery of the inductor.
10. The packaging structure according to claim 1, characterized in that: The inductor is a planar spiral inductor, an 8-shaped inductor or a four-leaf clover-shaped inductor.