Multi-chip package structure
By setting a multi-chip packaging structure of re-wiring adapter layer and bridge chip on the substrate, the problems of large space occupation and high manufacturing process difficulty in the prior art are solved, and a multi-chip packaging with high integration and low manufacturing difficulty are achieved.
Patent Information
- Application Number
- CN202421307741.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2034-06-07
AI Technical Summary
The existing multi-chip stacking technology has the problem of large space occupation and high manufacturing process difficulty, making it difficult to achieve efficient integration in limited space.
Using a multi-chip packaging structure including a rewiring adapter layer and a bridge chip, electrical connection and stacking of multi-chip is achieved by providing a parallel and spaced chip stacking structure and a bridge chip on the substrate.
It improves the integration of the packaging structure, reduces space occupation, and reduces the difficulty of the manufacturing process, and realizes improvement of the performance of the packaging structure and expansion of functions.
Smart Images
Figure CN222705521U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuit manufacturing, in particular to a multi-chip packaging structure. Background Art
[0002] In the existing process, the multi-chip stacking structure adopts wire bonding technology or through silicon via (TSV) process. Wire bonding uses metal wires to weld the pads between chips to achieve electrical conduction between chips. This technology is relatively mature and is the mainstream chip interconnection method currently used by memory chips. However, this technology has certain limitations. Wire bonding requires sufficient space between chips to form a stable wire arc for the welding wire, so the chips need to be staggered layer by layer when stacked, and stacked in a stepped manner to leave space for wire bonding, which brings the problem that chips cannot be stacked in multiple layers. Using through silicon via technology, multiple identical chips are stacked vertically together and interconnected through TSVs that pass through the chip stack. Compared with wire bonding, TSV technology greatly reduces the length of the interconnection line, but TSV technology is difficult and costly.
[0003] Therefore, how to integrate a packaging structure of multiple chips with the same or different functions in a limited space has become an urgent problem to be solved. Summary of the invention
[0004] The utility model provides a multi-chip packaging structure, which is used to solve the problem that the current multi-chip integration process is difficult and occupies more space, so as to improve the performance of the packaging structure and expand the function of the packaging structure.
[0005] According to some embodiments, the utility model provides a multi-chip packaging structure, including:
[0006] substrate;
[0007] A chip stacking structure, located on the top surface of the substrate, and a plurality of the chip stacking structures are arranged at intervals in a direction parallel to the top surface of the substrate, the chip stacking structure comprising a rewiring transfer layer and a plurality of chips located on the surface of the rewiring transfer layer and electrically connected to the rewiring transfer layer;
[0008] A bridge chip is provided, wherein the bridge chip electrically connects the rewiring transfer layers in two adjacent chip stacking structures.
[0009] In some embodiments, the rewiring transfer layer includes a top surface and a bottom surface that are oppositely distributed along a first direction and a plurality of side surfaces between the top surface of the rewiring transfer layer and the bottom surface of the rewiring transfer layer;
[0010] The plurality of chips are respectively distributed on the top surface of the rewiring transfer layer and on a plurality of side surfaces of the rewiring transfer layer.
[0011] In some embodiments, the chip stacking structure further includes: a passive component located on a top surface of the redistribution transfer layer and electrically connected to the redistribution transfer layer.
[0012] In some embodiments, the chip stacking structure includes a plurality of the rewiring transfer layers sequentially arranged along a first direction, and the plurality of the chips are at least electrically connected to side surfaces of the plurality of the rewiring transfer layers, respectively.
[0013] In some embodiments, the plurality of rerouting via layers have different sizes.
[0014] In some embodiments, it also includes:
[0015] The heat dissipation cover is located on the substrate and covers the chip on the surface of the rewiring transfer layer.
[0016] In some embodiments, it also includes:
[0017] A plastic encapsulation layer is located on the substrate, the plastic encapsulation layer encapsulates the chip stacking structure and the bridge chip, and the chip surface electrically connected to the rewiring transfer layer is exposed on the surface of the plastic encapsulation layer;
[0018] The heat dissipation cover is covered on the surface of the chip through heat dissipation glue.
[0019] In some embodiments, the plurality of chips in the chip stacking structure are different chips.
[0020] In some embodiments, the chip in the chip stacking structure is a memory chip, and a logic chip is also provided on the surface of the substrate.
[0021] In some embodiments, the bridge chip has a through silicon via, the through silicon via is filled with metal, and two adjacent chip stacking structures are electrically connected via the metal in the through silicon via.
[0022] The multi-chip packaging structure provided by the utility model is achieved by arranging a plurality of chip stacking structures and bridge chips which are arranged in parallel and at intervals on a substrate. The chip stacking structure includes a rewiring transfer layer and a plurality of chips which are located on the surface of the rewiring transfer layer and are electrically connected to the rewiring transfer layer. The bridge chip electrically connects the rewiring transfer layers in two adjacent chip stacking structures. This not only realizes multi-chip stacking and improves the integration of the packaging structure, but also occupies a small space and has a low manufacturing process difficulty, thereby achieving improved performance of the packaging structure and expanded functionality of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] AttachedFigure 1 It is a cross-sectional schematic diagram of a multi-chip packaging structure in a specific implementation manner of the utility model;
[0024] Attached Figure 2 It is a top view schematic diagram of a multi-chip packaging structure in a specific implementation mode of the utility model;
[0025] Attached Figure 3 is another cross-sectional schematic diagram of a multi-chip packaging structure in a specific implementation manner of the utility model;
[0026] Attached Figure 4 It is another cross-sectional schematic diagram of the multi-chip packaging structure in a specific implementation manner of the utility model. DETAILED DESCRIPTION
[0027] The specific implementation of the multi-chip packaging structure provided by the utility model is described in detail below with reference to the accompanying drawings.
[0028] This specific embodiment provides a multi-chip packaging structure. Figure 1 is a cross-sectional schematic diagram of a multi-chip packaging structure in a specific implementation mode of the utility model, Figure 2 FIG. 1 is a top view of a multi-chip packaging structure in a specific embodiment of the utility model. Figure 1 and Figure 2 As shown, the multi-chip packaging structure includes:
[0029] substrate 10;
[0030] A chip stacking structure, located on the top surface of the substrate 10, and a plurality of the chip stacking structures are arranged in a direction parallel to the top surface of the substrate 10, the chip stacking structure comprising a rewiring transfer layer and a plurality of chips located on the surface of the rewiring transfer layer and electrically connected to the rewiring transfer layer;
[0031] A bridge chip 15 , wherein the bridge chip 15 electrically connects the rewiring transfer layers in two adjacent chip stacking structures.
[0032] Specifically, the substrate 10 may be, but is not limited to, a printed circuit board. In one example, the substrate 10 includes a top surface and a bottom surface that are relatively distributed along a first direction D1, a plurality of the chip stacking structures and the bridge chip 15 are located on the top surface of the substrate 10, and the bottom surface of the substrate 10 has lead-out solder balls 19. Each of the chip stacking structures includes the rewiring transfer layer and a plurality of the chips located on the surface of the rewiring transfer and electrically connected to the rewiring transfer, so that a plurality of the chips can be integrated in the packaging structure, thereby improving the integration of the multi-chip packaging structure. The chip in the chip stacking structure is located on the surface of the rewiring transfer layer and is electrically connected to the rewiring transfer layer. The bridge chip 15 electrically connects the rewiring transfer layers in two adjacent chip stacking structures. On the one hand, there is no need to perform wire bonding on the chip and the substrate 10 through a wire bonding process, thereby reducing the occupation of the internal space of the multi-chip packaging structure and contributing to further miniaturization of the size of the multi-chip packaging structure. On the other hand, there is no need to perform TSV interconnection through silicon via technology, thereby simplifying the manufacturing process of the packaging structure and reducing the manufacturing difficulty of the multi-chip packaging structure.
[0033] In some embodiments, a plurality of the chip stacking structures are arranged along a second direction D2, and the second direction D2 intersects with the first direction D1;
[0034] The bridge chip 15 is located between adjacent chip stacking structures along the second direction D2.
[0035] In some embodiments, the bridge chip 15 has a through silicon via 151 , the through silicon via 151 is filled with metal, and two adjacent chip stacking structures are electrically connected via the metal in the through silicon via 151 .
[0036] For example, the bridge chip 15 is located between the chip stacking structures adjacent to each other along the second direction D2, so as to shorten the electrical connection path between the bridge chip 15 and the chip stacking structure, and make the structure of the multi-chip packaging structure more compact. In one example, the bridge chip 15 is provided with a through silicon via 151, and the fifth electrical connection structure 18 is provided on both sides of the bridge chip 15 that are relatively distributed along the second direction D2. The rewiring transfer layer in the chip stacking structure located on one side of the bridge chip 15 is electrically connected to the metal in the through silicon via 151 through a part of the fifth electrical connection structure 18, and the rewiring transfer layer in the chip stacking structure located on the other side of the bridge chip 15 is electrically connected to the metal in the through silicon via 151 through another part of the fifth electrical connection structure 18.
[0037] In one example, at least one of the plurality of chip stacking structures is an input-end structure, the rewiring transfer layer in the input-end structure is an input-end transfer layer 13, and the chip in the input-end structure is an input-end chip 11;
[0038] At least one of the plurality of chip stacking structures is an output end structure, the rewiring transfer layer in the output end structure is an output end transfer layer 14, and the chip in the output end structure is an output end chip 12;
[0039] The bridge chip 15 is electrically connected to the input-end switching layer 13 and the output-end switching layer 14 .
[0040] For example, the input end structure includes the input end transfer layer 13 and a plurality of input end chips 11, the input end transfer layer 13 is mounted on the top surface of the substrate 10, and is electrically connected to the circuit layer in the substrate 10 through a first electrical connection structure. In one example, the first electrical connection structure can be a conductive bump. The input end transfer layer 13 includes a first dielectric layer and a first wiring layer 131 located in the first dielectric layer. The input end chip 11 is mounted on the surface of the input end transfer layer 13, and is electrically connected to the first wiring layer 131 in the input end transfer layer 13. The output end structure includes the output end transfer layer 14 and a plurality of output end chips 12, the output end transfer layer 14 is mounted on the top surface of the substrate 10, and is electrically connected to the circuit layer in the substrate 10 through a second electrical connection structure. In one example, the second electrical connection structure can also be a conductive bump. The output end transfer layer 14 includes a second dielectric layer and a second wiring layer 141 located in the second dielectric layer. The output terminal chip 12 is mounted on the surface of the output terminal switching layer 14 and is electrically connected to the second wiring layer 141 in the output terminal switching layer 14. The bridge chip 15 is electrically connected to the first wiring layer 131 in the input terminal switching layer 13 and the second wiring layer 141 in the output terminal switching layer 14. The bridge chip 15 is used for signal conversion processing. In one example, the bridge chip 15 can be a video signal conversion processing chip. The multiple mentioned in this specific embodiment refers to more than two.
[0041] In this specific embodiment, a plurality of input-end chips 11 are arranged in the input-end structure, and the plurality of input-end chips 11 are electrically connected to the bridge chip 15 through the input-end switching layer 13, and a plurality of output-end chips 12 are arranged in the output-end structure, and the plurality of output-end chips 12 are electrically connected to the bridge chip 15 through the output-end switching layer 14, so that a plurality of input-end chips 11 can simultaneously receive a plurality of input signals, and a plurality of output-end chips 12 can simultaneously output a plurality of signals converted by the bridge chip 15, so that the multi-chip packaging structure can realize multi-input and multi-output signal conversion, breaking the limitation that the packaging structure can only realize single-input and single-output signal conversion, thereby expanding the application field of the packaging structure, realizing the improvement of the performance of the packaging structure, and expanding the function of the packaging structure.
[0042] In order to further improve the space utilization rate inside the multi-chip package structure and simplify the electrical connection process between the chip and the rewiring transfer layer in the chip stacking structure, in some embodiments, the rewiring transfer layer includes a top surface and a bottom surface relatively distributed along the first direction D1 and a plurality of side surfaces located between the top surface of the rewiring transfer layer and the bottom surface of the rewiring transfer layer;
[0043] The multiple chips are respectively distributed on the top surface of the rewiring transfer layer and multiple side surfaces of the rewiring transfer layer.
[0044] For example, if Figure 1 and Figure 2As shown, the rewiring transfer layer includes a top surface and a bottom surface relatively distributed along the first direction D1, a left side surface and a right side surface relatively distributed along the second direction D2, and a front side surface and a rear side surface relatively distributed along the third direction D3, wherein the second direction D2 and the third direction D3 both intersect with the first direction D1 (for example, intersect vertically or intersect obliquely), and the second direction D2 intersects with the third direction D3 (for example, intersects vertically or intersects obliquely). The rewiring transfer layer includes four chips 11, and the four chips 11 are respectively distributed on the top surface of the rewiring transfer layer, the front side surface of the rewiring transfer layer, the rear side surface of the rewiring transfer layer, and the left side surface of the rewiring transfer layer. By arranging the chips on the top surface of the rewiring transfer layer and on multiple side surfaces of the rewiring transfer layer, not only can multi-chip stacking be realized on the rewiring transfer layer, thereby improving the function and integration of the multi-chip packaging structure, but also the space on the substrate 10 can be fully utilized, thereby improving the space utilization rate inside the multi-chip packaging structure. Moreover, by dispersing multiple chips on the top surface and multiple side surfaces of the rewiring transfer layer, it is also helpful to reduce the size of the rewiring transfer layer and reduce the difficulty of mounting the chip. The multiple chips are memory chips, for example, each chip is a dynamic random access memory chip, a static random access memory chip or a magnetoresistive random access memory chip. In other embodiments, the multiple chips may include different types of chips. For example, some of the multiple chips 11 may be logic chips, and other chips 11 may be memory chips. For example, each of the logic chips may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip or an application processor (AP) chip.
[0045] In one example, the side of the rewiring transfer layer has a pad, the pad is electrically connected to the first wiring layer 131 in the rewiring transfer layer, and the chip 11 is electrically connected to the pad through the third electrical connection structure 16. In one example, the third electrical connection structure 16 is a conductive bump.
[0046] In one example, the side of the rewiring transfer layer has a pad, the pad is electrically connected to the second wiring layer 141 in the rewiring transfer layer, and the chip 12 is electrically connected to the pad through a fourth electrical connection structure 17. In one example, the fourth electrical connection structure 17 is a conductive bump.
[0047] In some embodiments, the chip stacking structure further includes:
[0048] The passive component is located on the top surface of the rewiring transfer layer and is electrically connected to the rewiring transfer layer.
[0049] Specifically, by distributing the plurality of chips on the top surface and multiple side surfaces of the rewiring transition layer, it is possible to provide a space for mounting the passive components on the top surface of the rewiring transition layer, which helps to further improve the integration of the multi-chip packaging structure.
[0050] Attached Figure 3 FIG. 1 is another cross-sectional schematic diagram of a multi-chip packaging structure in a specific embodiment of the utility model. In order to further improve the integration of the multi-chip packaging structure, in some embodiments, as Figure 3 As shown, the chip stacking structure includes a plurality of the rewiring transfer layers sequentially arranged along a first direction D1, and a plurality of the chips are at least electrically connected to side surfaces of the plurality of the rewiring transfer layers, respectively.
[0051] In some embodiments, the plurality of rerouting via layers have different sizes.
[0052] Specifically, by setting the sizes of the multiple rewiring transfer layers in the same chip stacking structure to be different, the rewiring transfer layers of different sizes can be matched with the chips of different structures or functions, so as to improve the flexibility of the multi-chip packaging structure design. The size of the rewiring transfer layer includes any one of the length, width and thickness of the rewiring transfer layer. In addition, rewiring transfer layers with different wiring densities can be set according to the needs of the functional chip.
[0053] Attached Figure 4 FIG. 1 is another cross-sectional schematic diagram of a multi-chip packaging structure in a specific embodiment of the present invention. Figure 4 As shown, the multi-chip packaging structure also includes:
[0054] The heat dissipation cover 40 is located on the substrate 10 and covers the chip on the surface of the redistribution transfer layer.
[0055] In some embodiments, the multi-chip package structure further includes:
[0056] A plastic encapsulation layer, located on the substrate 10, the plastic encapsulation layer encapsulates the chip stacking structure and the bridge chip 15, and the chip surface electrically connected to the rewiring transfer layer is exposed on the surface of the plastic encapsulation layer;
[0057] The heat dissipation cover 40 is covered on the surface of the chip by heat dissipation glue.
[0058] Specifically, the heat dissipation cover 40 is located on the substrate 10, and covers the chip stacking structure and the bridge chip 15. The heat dissipation cover 40 directly covers the surface of the chip (including the input end chip 11 and the output end chip 12) exposed outside the plastic packaging layer, reducing the accumulation of heat inside the multi-chip packaging structure, thereby improving the heat dissipation performance of the multi-chip packaging structure.
[0059] In some embodiments, the plurality of chips in the chip stacking structure are different chips, so as to further expand the function of the multi-chip packaging structure and improve the integration of the multi-chip packaging structure.
[0060] In some embodiments, the chips in the chip stacking structure are memory chips, and a logic chip is also disposed on the surface of the substrate 10 .
[0061] The multi-chip packaging structure provided in this specific embodiment is achieved by arranging multiple chip stacking structures and bridge chips that are arranged in parallel and at intervals on a substrate, and the chip stacking structure includes a rewiring transfer layer and multiple chips located on the surface of the rewiring transfer layer and electrically connected to the rewiring transfer layer, and the bridge chip electrically connects the rewiring transfer layers in two adjacent chip stacking structures, which not only realizes multi-chip stacking and improves the integration of the packaging structure, but also occupies a small space and has a low manufacturing process difficulty, thereby achieving improved performance of the packaging structure and expanded functionality of the packaging structure.
[0062] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A multi-chip packaging structure, characterized in that: include: substrate; A chip stacking structure, located on the top surface of the substrate, and a plurality of the chip stacking structures are arranged in a direction parallel to the top surface of the substrate, the chip stacking structure comprising a rewiring transfer layer and a plurality of chips located on the surface of the rewiring transfer layer and electrically connected to the rewiring transfer layer; A bridge chip is provided, wherein the bridge chip electrically connects the rewiring transfer layers in two adjacent chip stacking structures.
2. The multi-chip package structure according to claim 1, characterized in that: The rewiring transfer layer comprises a top surface and a bottom surface that are oppositely distributed along a first direction and a plurality of side surfaces that are located between the top surface of the rewiring transfer layer and the bottom surface of the rewiring transfer layer; The plurality of chips are respectively distributed on the top surface of the rewiring transfer layer and on a plurality of side surfaces of the rewiring transfer layer.
3. The multi-chip package structure according to claim 2, characterized in that: The chip stacking structure further includes: a passive component, which is located on the top surface of the rewiring transfer layer and is electrically connected to the rewiring transfer layer.
4. The multi-chip package structure according to claim 3, characterized in that: The chip stacking structure includes a plurality of the rewiring transfer layers sequentially arranged along a first direction, and the plurality of chips are at least electrically connected to side surfaces of the plurality of the rewiring transfer layers, respectively.
5. The multi-chip package structure according to claim 4, characterized in that: The plurality of rewiring transfer layers have different sizes.
6. The multi-chip package structure according to claim 3, characterized in that: Also includes: The heat dissipation cover is located on the substrate and covers the chip on the surface of the rewiring transfer layer.
7. The multi-chip package structure according to claim 6, characterized in that: Also includes: A plastic encapsulation layer is located on the substrate, the plastic encapsulation layer encapsulates the chip stacking structure and the bridge chip, and the chip surface electrically connected to the rewiring transfer layer is exposed on the surface of the plastic encapsulation layer; The heat dissipation cover is covered on the surface of the chip through heat dissipation glue.
8. The multi-chip package structure according to claim 2, characterized in that: The plurality of chips in the chip stacking structure are different chips from each other.
9. The multi-chip package structure according to claim 8, characterized in that: The chips in the chip stacking structure are memory chips, and a logic chip is also arranged on the surface of the substrate.
10. The multi-chip package structure according to claim 1, characterized in that: The bridge chip has a through silicon via, the through silicon via is filled with metal, and two adjacent chip stacking structures are electrically connected via the metal in the through silicon via.