A CAN bus interface circuit

Abstract

This application discloses a CAN bus interface circuit. The interface circuit includes pull-up resistors R1, current-limiting resistors R2 and R3, terminating resistors R4 and R5; a transceiver U1; power port filter capacitors C1 and C2; the transmitting pin connection of inductor L1; an RC filter circuit C3; ESD capacitors C4 and C5; and transient voltage suppressors D1 and D2. Furthermore, by designing a controllable power supply connected to the CAN bus, which floats in standby mode, it can stabilize the common-mode output. The auxiliary circuit stabilizes the recessive common-mode voltage, thus stabilizing the bus recessive voltage, reducing resonance problems introduced by the use of common-mode inductors, improving the CAN differential waveform, and also reducing conducted emission interference on the CAN bus.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a CAN bus interface circuit. Background Art

[0002] CAN is the abbreviation of Controller Area Network (CAN), which belongs to the field bus category. It is a serial communication network that effectively supports distributed control and real-time control. Compared with general communication buses, CAN bus has outstanding reliability, real-time and flexibility in long-distance data communication.

[0003] In the prior art, common-mode inductors are usually used to filter out common-mode electromagnetic interference of signal lines, attenuate the high-frequency part of differential signals, and suppress the electromagnetic interference emitted by the CAN interface itself. However, common-mode inductors inevitably have parasitic inductance and DC resistance. Considering factors such as the number of bus nodes and communication distance, resonance will occur, affecting the bus quality. Summary of the invention

[0004] Based on this, an embodiment of the present application provides a CAN bus interface circuit that can stabilize the common-mode output and improve the conducted emission interference of the CAN bus.

[0005] The present application provides a CAN bus interface circuit, the CAN interface circuit comprising:

[0006] The bus transmitting end CAN_TX is connected to one end of the current limiting resistor R2, and the other end of the current limiting resistor R2 is connected to the transmitting end pin of the transceiver U1; the bus receiving end CAN_RX is respectively connected to one end of the pull-up resistor R1 and one end of the current limiting resistor R3, the other end of the pull-up resistor R1 is connected to the 5V power supply, and the other end of the current limiting resistor R3 is connected to the receiving end pin of the transceiver U1; the STB pin is connected to the STB pin of the transceiver U1;

[0007] The power pin of the transceiver U1 is connected to the 5V power supply and one end of the power port filter capacitor C2 respectively, and the other end of the power port filter capacitor C2 is grounded; the VIO pin of the transceiver U1 is connected to the 5V power supply and one end of the power port filter capacitor C1 respectively, and the other end of the power port filter capacitor C1 is connected to the ground pin of the transceiver U1 and the ground respectively; the CANH pin of the transceiver U1 is connected to the transmitting end pin of the inductor L1, and the CANL pin of the transceiver U1 is connected to the ground pin of the inductor L1;

[0008] Pin 4 of the inductor L1 is respectively connected to one end of the terminal resistor R5, pin 1 of the transient voltage suppressor D1, and one end of the ESD electrostatic capacitor C4; pin 3 of the inductor L1 is respectively connected to one end of the terminal resistor R4, pin 1 of the transient voltage suppressor D2, and one end of the ESD electrostatic capacitor C5; the other end of the terminal resistor R5 and the other end of the terminal resistor R4 are connected to one end of the RC filter circuit C3, and the other end of the RC filter circuit C3 is grounded; pin 2 of the transient voltage suppressor D1, pin 2 of the transient voltage suppressor D2, the other end of the ESD electrostatic capacitor C4, and the other end of the ESD electrostatic capacitor C5 are grounded.

[0009] Optionally, the other ends of the terminal resistor R4 and the terminal resistor R5 are connected to a peripheral circuit.

[0010] Optionally, the peripheral circuit specifically includes:

[0011] The other ends of the terminal resistors R4 and R5 are connected to the two branches of the current limiting resistor R6 and the current limiting resistor R7 respectively, wherein the other end of the current limiting resistor R6 is connected to the 3rd pin of the transistor Q1, the 2nd pin of the transistor Q1 is connected to the power supply, and the 1st pin of the transistor Q1 is connected to the resistor and the GPIO pin in sequence;

[0012] The other end of the current limiting resistor R7 is connected to the 3rd pin of the transistor Q2, the 2nd pin of the transistor Q2 is grounded, and the 1st pin of the transistor Q1 is connected to the resistor and the power supply in sequence.

[0013] Optionally, a connecting branch is provided between pin 1 and pin 2 of the transistor Q1, and a resistor is provided on the connecting branch; a connecting branch is provided between pin 1 and pin 2 of the transistor Q2, and a resistor is provided on the connecting branch.

[0014] Optionally, pin 1 of the transistor Q1 is the base, pin 2 is the emitter, and pin 3 is the collector.

[0015] Optionally, pin 1 of the transistor Q2 is the base, pin 2 is the emitter, and pin 3 is the collector.

[0016] The technical solution provided by the embodiment of the present application is to design a controllable power supply connected to the CAN bus, which is floating in standby mode, so as to stabilize the common mode output, stabilize the invisible common mode voltage of the auxiliary circuit, stabilize the invisible voltage of the bus, reduce the resonance and other problems introduced by the use of common mode inductors, improve the CAN differential waveform, and also improve the conducted emission interference of the CAN bus. The beneficial effects brought include at least:

[0017] (1) Stabilize the invisible common-mode voltage of the CAN bus through controllable voltage.

[0018] (2) Improve the EME performance of the CAN bus through peripheral circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0020] Figure 1 A CAN bus interface circuit diagram provided in an embodiment of the present application;

[0021] Figure 2 The CAN bus interface circuit diagram after adding peripheral circuits for this application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] In the description of the present invention, the terms "comprises", "has" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may also include other steps or units that are not explicitly listed but are inherent to these processes, methods, products or apparatuses, or steps or units added based on further optimization schemes conceived by the present invention.

[0024] CAN is the abbreviation of Controller Area Network (CAN), which has become an international standard (ISO11898) and is one of the most widely used field buses in the world.

[0025] Among them, the CAN communication circuit structure of the controller has the following types: Type 1, the circuit structure is as follows Figure 1 As shown, R1 is a pull-up resistor, R2 and R3 are current-limiting resistors to prevent the CAN chip from overcurrent and burning out the MCU; R4 and R5 are terminal resistors; C1 and C2 are power port filter capacitors; C3 is an RC filter circuit; C4 and C5 are ESD electrostatic capacitors; D1 and D2 are TVS, which can prevent the CAN chip from malfunctioning due to momentary pulses such as electrostatic discharge.

[0026] In the CAN bus, TVS stands for "Transient Voltage Suppressor". It is a circuit protection device used to protect the CAN bus interface, mainly used to limit the impact of voltage transients and overvoltage on CAN bus signals.

[0027] Since the CAN bus is mainly used in industrial automation and automotive electronics, in these environments, the CAN bus is often subject to voltage peaks caused by motors, relays, pulse interference, etc. These voltage peaks may cause damage or failure of the transceiver on the CAN bus, so TVS is needed to limit these voltage breakdowns and protect the CAN bus.

[0028] TVS usually has the characteristics of high-speed response, low leakage current, high allowable power and high reliability, and can effectively protect the CAN bus from electromagnetic interference and voltage fluctuations.

[0029] CAN1_TX_PC10 and CAN1_RX_PC11 are the communication interfaces between MCU and CAN chip; CAN1_STB_PA7 can control the CAN chip to enter low power mode.

[0030] Specifically, the bus transmitting end CAN_TX is connected to one end of the current limiting resistor R2, and the other end of the current limiting resistor R2 is connected to the transmitting end pin of the transceiver U1; the bus receiving end CAN_RX is respectively connected to one end of the pull-up resistor R1 and one end of the current limiting resistor R3, the other end of the pull-up resistor R1 is connected to the 5V power supply, and the other end of the current limiting resistor R3 is connected to the receiving end pin of the transceiver U1; the STB pin is connected to the STB pin of the transceiver U1;

[0031] The power pin of the transceiver U1 is connected to the 5V power supply and one end of the power port filter capacitor C2 respectively, and the other end of the power port filter capacitor C2 is grounded; the VIO pin of the transceiver U1 is connected to the 5V power supply and one end of the power port filter capacitor C1 respectively, and the other end of the power port filter capacitor C1 is connected to the ground pin of the transceiver U1 and the ground respectively; the CANH pin of the transceiver U1 is connected to the transmitting end pin of the inductor L1, and the CANL pin of the transceiver U1 is connected to the ground pin of the inductor L1;

[0032] Pin 4 of the inductor L1 is respectively connected to one end of the terminal resistor R5, pin 1 of the transient voltage suppressor D1, and one end of the ESD electrostatic capacitor C4; pin 3 of the inductor L1 is respectively connected to one end of the terminal resistor R4, pin 1 of the transient voltage suppressor D2, and one end of the ESD electrostatic capacitor C5; the other end of the terminal resistor R5 and the other end of the terminal resistor R4 are connected to one end of the RC filter circuit C3, and the other end of the RC filter circuit C3 is grounded; pin 2 of the transient voltage suppressor D1, pin 2 of the transient voltage suppressor D2, the other end of the ESD electrostatic capacitor C4, and the other end of the ESD electrostatic capacitor C5 are grounded.

[0033] However, in the above embodiment, adding two TVS on the CAN bus can effectively protect the circuit from the surge high voltage generated by electrostatic discharge and ensure the normal operation of the system. At the same time, adding terminal resistance on the CAN bus increases the communication reliability of the CAN bus. Common-mode inductors can filter out the common-mode electromagnetic interference of the signal line, attenuate the high-frequency part of the differential signal, and suppress the electromagnetic interference emitted by the CAN interface itself. However, the common-mode inductor will inevitably have parasitic inductance and DC resistance. Considering the number of bus nodes, communication distance and other factors, it will cause resonance and affect the quality of the bus. Therefore, it can be seen that this embodiment has a good improvement effect on electrostatic interference and conducted interference, but the use of common-mode inductors will also bring problems of resonance and transient voltage.

[0034] like Figure 2 , an embodiment of the present application is provided in which a peripheral circuit is added, which can overcome the above problems.

[0035] Circuit Design 1 A controllable 0.5VCC is connected to the CAN bus. The typical value in normal mode is 0.5VCC, and it is floating in standby mode. It can stabilize the common-mode output, and the auxiliary circuit stabilizes the invisible common-mode voltage, so that the bus implicit voltage is stabilized at 0.5VCC, reducing the resonance and other problems introduced by the use of common-mode inductors, improving the CAN differential waveform, and also improving the conducted emission interference of the CAN bus. One purpose of this design is to stabilize the common-mode output and improve the conducted emission interference of the CAN bus.

[0036] In this embodiment, compared with Figure 1 The terminal resistor R4 is added, and the other end of the terminal resistor R5 is connected to a peripheral circuit. Specifically,

[0037] The peripheral circuit specifically includes: the other ends of the terminal resistors R4 and R5 are respectively connected to the two branches of the current limiting resistors R6 and R7, wherein the other end of the current limiting resistor R6 is connected to the 3rd pin of the transistor Q1, the 2nd pin of the transistor Q1 is connected to the power supply, and the 1st pin of the transistor Q1 is connected to the resistor and the GPIO pin in sequence; the other end of the current limiting resistor R7 is connected to the 3rd pin of the transistor Q2, the 2nd pin of the transistor Q2 is grounded, and the 1st pin of the transistor Q1 is connected to the resistor and the power supply in sequence. A connecting branch is provided between the 1st pin and the 2nd pin of the transistor Q1, and a resistor is provided on the connecting branch; a connecting branch is provided between the 1st pin and the 2nd pin of the transistor Q2, and a resistor is provided on the connecting branch. The 1st pin of the transistor Q1 is the base, the 2nd pin is the emitter, and the 3rd pin is the collector; the 1st pin of the transistor Q2 is the base, the 2nd pin is the emitter, and the 3rd pin is the collector.

[0038] In this embodiment, it can be understood that the specific pins of each component in this circuit are based on Figure 1 The description is provided for the convenience of understanding by those skilled in the art. In actual situations, the specific pin settings may be different due to different hardware models. That is, the terms "pin 1", "pin 2", and "pin 3" in the specification and claims of the present invention and the above-mentioned drawings are intended to distinguish the objects referred to. This terminology does not distinguish the importance, positional relationship, etc.

[0039] In an optional embodiment of the present application, when the system does not have a strong requirement for EME, a 0 ohm resistor can be used instead of a common mode inductor; and the voltage value of the pull-up power supply can be changed according to the different power supply voltages of the MCU.

[0040] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0041] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A CAN bus interface circuit, characterized in that: The CAN bus interface circuit comprises: The bus transmitting end CAN_TX is connected to one end of the current limiting resistor R2, and the other end of the current limiting resistor R2 is connected to the transmitting end pin of the transceiver U1; the bus receiving end CAN_RX is respectively connected to one end of the pull-up resistor R1 and one end of the current limiting resistor R3, the other end of the pull-up resistor R1 is connected to the 5V power supply, and the other end of the current limiting resistor R3 is connected to the receiving end pin of the transceiver U1; the STB pin is connected to the STB pin of the transceiver U1; The power pin of the transceiver U1 is connected to the 5V power supply and one end of the power port filter capacitor C2 respectively, and the other end of the power port filter capacitor C2 is grounded; the VIO pin of the transceiver U1 is connected to the 5V power supply and one end of the power port filter capacitor C1 respectively, and the other end of the power port filter capacitor C1 is connected to the ground pin of the transceiver U1 and the ground respectively; the CANH pin of the transceiver U1 is connected to the transmitting end pin of the inductor L1, and the CANL pin of the transceiver U1 is connected to the ground pin of the inductor L1; Pin 4 of the inductor L1 is respectively connected to one end of the terminal resistor R5, pin 1 of the transient voltage suppressor D1, and one end of the ESD electrostatic capacitor C4; pin 3 of the inductor L1 is respectively connected to one end of the terminal resistor R4, pin 1 of the transient voltage suppressor D2, and one end of the ESD electrostatic capacitor C5; the other end of the terminal resistor R5 and the other end of the terminal resistor R4 are connected to one end of the RC filter circuit C3, and the other end of the RC filter circuit C3 is grounded; pin 2 of the transient voltage suppressor D1, pin 2 of the transient voltage suppressor D2, the other end of the ESD electrostatic capacitor C4, and the other end of the ESD electrostatic capacitor C5 are grounded.

2. The CAN bus interface circuit according to claim 1, characterized in that: The other ends of the terminal resistors R4 and R5 are connected to peripheral circuits.

3. The CAN bus interface circuit according to claim 2, characterized in that: The peripheral circuit specifically includes: The other ends of the terminal resistors R4 and R5 are connected to the two branches of the current limiting resistor R6 and the current limiting resistor R7 respectively, wherein the other end of the current limiting resistor R6 is connected to the 3rd pin of the transistor Q1, the 2nd pin of the transistor Q1 is connected to the power supply, and the 1st pin of the transistor Q1 is connected to the resistor and the GPIO pin in sequence; The other end of the current limiting resistor R7 is connected to the 3rd pin of the transistor Q2, the 2nd pin of the transistor Q2 is grounded, and the 1st pin of the transistor Q1 is connected to the resistor and the power supply in sequence.

4. The CAN bus interface circuit according to claim 3, characterized in that: A connecting branch is provided between pin 1 and pin 2 of the transistor Q1, and a resistor is provided on the connecting branch; a connecting branch is provided between pin 1 and pin 2 of the transistor Q2, and a resistor is provided on the connecting branch.

5. The CAN bus interface circuit according to claim 3, characterized in that: In transistor Q1, pin 1 is the base, pin 2 is the emitter, and pin 3 is the collector.

6. The CAN bus interface circuit according to claim 3, characterized in that: In transistor Q2, pin 1 is the base, pin 2 is the emitter, and pin 3 is the collector.

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