Semiconductor structure

Abstract

The utility model discloses a semiconductor structure, including a pad array. The pad array includes a plurality of first pads, a first pad boundary, a second pad boundary, a second pad and a third pad. The first pads are isolated from each other and arranged separately. The first pad boundary is arranged on one side of the pad array, including a plurality of first branch pads. The second pad boundary is arranged on the other side of the pad array opposite to the first pad boundary, including a plurality of second branch pads. The second pads are arranged separately from each other between the first branch pads. The third pads are arranged separately from each other between the second branch pads. The length of the second pad is smaller than the length of the third pad. Thereby, the pad array as a whole presents a left-right asymmetric layout arrangement, thereby improving the structural defects that may be derived from the semiconductor structure.

Description

Technical Field

[0001] The utility model relates to a semiconductor structure, in particular to a semiconductor structure comprising a pad. Background Art

[0002] As various electronic products develop towards miniaturization, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the DRAM cell with only a planar gate structure under the current mainstream development trend. Generally speaking, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage device to receive voltage signals from the bit line and word line. However, due to the limitations of process technology, the existing DRAM cell with a recessed gate structure still has many defects, and further improvements are needed to effectively improve the performance and reliability of related memory devices. Utility Model Content

[0003] One purpose of the present invention is to provide a semiconductor structure, which improves the structural defects of the semiconductor structure that may be derived from the continuous increase in storage unit density by arranging peripheral pads of different lengths on two opposite sides of a pad array.

[0004] In order to achieve the above-mentioned object, an embodiment of the utility model provides a semiconductor structure, including a pad array. The pad array includes a plurality of first pads, a first pad boundary, a second pad boundary, a second pad and a third pad. A plurality of first pads are arranged separately from each other along the first direction and the second direction. The first pad boundary is arranged on one side of the pad array, and the first pad boundary includes a plurality of first branch pads extending in a third direction. The second pad boundary is arranged on the other side of the pad array opposite to the first pad boundary, and the second pad boundary includes a plurality of second branch pads extending in the third direction. The second pads are arranged separately from each other between the first branch pads in the second direction. The third pads are arranged separately from each other between the second branch pads in the second direction. Wherein the length of the second pad in the third direction is less than the length of the third pad in the third direction.

[0005] In order to achieve the above-mentioned object, an embodiment of the utility model provides another semiconductor structure, including a pad array, wherein the pad array includes a plurality of first pads, the first pads are arranged into a plurality of rows extending in a first direction, and are arranged into a plurality of columns extending in a second direction. A first pad boundary is arranged on one side of the pad array, and the first pad boundary includes a plurality of first branch pads. A second pad boundary is arranged on the other side of the pad array opposite to the first pad boundary, and the second pad boundary includes a plurality of second branch pads. Wherein, the first pad closest to the first pad boundary in each of the rows has a first sawtooth profile, and the first pad closest to the second pad boundary in each of the rows has a second sawtooth profile different from the first sawtooth profile.

[0006] In general, the semiconductor structure and its manufacturing method respectively set peripheral pads of different lengths on two opposite sides of the pad array, so that the pad array as a whole presents an asymmetric layout to maintain the contact range between the pads in the storage area and their corresponding plugs, thereby enabling the semiconductor structure to have an optimized structure and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a deeper understanding of this embodiment and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 4 FIG. 1 is a schematic diagram of a semiconductor structure according to a preferred embodiment of the present invention, wherein:

[0009] Figure 1 is a schematic top view of a semiconductor structure;

[0010] Figure 2 for Figure 1 Schematic diagram of the cross section along the tangent line A-A' and the tangent line B-B';

[0011] Figure 3 is another schematic top view of a semiconductor structure; and

[0012] Figure 4 for Figure 3 The middle part is an enlarged schematic diagram;

[0013] Figures 5 to 9 The figure is a schematic diagram of a method for manufacturing a semiconductor structure according to a preferred embodiment of the present invention, wherein:

[0014] Figure 5A schematic flow chart of the steps of a method for manufacturing a semiconductor structure; and

[0015] Figure 6 A schematic diagram of a top view after forming a plug array, a preset storage pad array and a pad array;

[0016] Figure 7 A schematic cross-sectional view of a plug array, a preset storage pad array, and a pad array after formation;

[0017] Figure 8 A top view schematic diagram of the pad array after correction; and

[0018] Fig. 9 It is a cross-sectional schematic diagram after the pad array is corrected;

[0019] Fig.10 FIG. 1 is a top view schematic diagram of a modified pad array according to another embodiment of the present invention.

[0020] The reference numerals are described as follows:

[0021] 10Semiconductor structure

[0022] 100A storage area

[0023] 100B surrounding area

[0024] 102 insulation layer

[0025] 104 Isolation Structure

[0026] 110 plug array

[0027] 111, 111b, 111c plug

[0028] 120 character line

[0029] 122 Dielectric layer

[0030] 124 gate dielectric layer

[0031] 126 gates

[0032] 128 Covering layer

[0033] 130 pad array

[0034] Line 130a

[0035] Column 130b

[0036] 131 first pad

[0037] 133 First pad boundary

[0038] 135 first branch pad

[0039] 137 Second pad boundary

[0040] 139 Second branch pad

[0041] 141 Second pad

[0042] 143 Third pad

[0043] 145 Third pad boundary

[0044] 200 chips

[0045] 210 preset storage pad array

[0046] 211 preset storage land patterns

[0047] 211a preset pad center

[0048] 231, 231b, 231c pads

[0049] 230, 330, 430 pad arrays

[0050] A, B tangent

[0051] C1, C2, C3, C4, C5, C6 center of gravity

[0052] D1 first direction

[0053] D2 Second direction

[0054] D3 third direction

[0055] D4 Fourth direction

[0056] g1, g2, g3 distance

[0057] H1, H2 sawtooth height

[0058] O1, O2 opening

[0059] S1 first length

[0060] S2 second length

[0061] S3 third length

[0062] S4 fourth length

[0063] S5 fifth length

[0064] Angle between θ1 and θ2

[0065] Z1 first sawtooth profile

[0066] Z2 second sawtooth profile DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention, and with the accompanying drawings, describes in detail the composition and intended effects of the present invention. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0068] Please refer to Figures 1 to 4 , which is a schematic diagram of a semiconductor structure 10 in a preferred embodiment of the present invention. First, Figure 1 As shown, the semiconductor structure 10 includes a storage node pad (SN pad) array 130, which includes, for example, a metal material with low resistance such as aluminum (Al), titanium (Ti), copper (Cu) or tungsten (W), preferably tungsten, but not limited thereto. The pad array 130 includes a plurality of first pads 131, a first pad boundary 133, a second pad boundary 137, a plurality of second pads 141 and a plurality of third pads 143. The first pads 131 are isolated and separately arranged along a first direction D1 and a second direction D2 that are staggered and non-perpendicular to each other. The first pad boundary 133 and the second pad boundary 137 extend in the third direction D3, respectively, and are located at two opposite sides of the pad array 130, wherein the first pad boundary 133 located at one side of the pad array 130 further includes a plurality of first branch pads 135 extending in the first direction D1, and the second pad boundary 137 disposed at the other side further includes a plurality of second branch pads 139 extending in the first direction D1. In addition, the second pads 141 are disposed separately from each other between the first branch pads 135 in the third direction D3, and the third pads 143 are disposed separately from each other between the second branch pads 139 in the third direction D3.

[0069] It should be particularly noted that each first pad 131 has the same first length S1 in the first direction D1, and each second pad 141 and third pad 143 has a second length S2 and a third length S3 different from the first length S1 in the first direction D1, and the second length S2 of the second pad 141 is less than the third length S3 of the third pad 143. In this way, by arranging the second pad 141 and the third pad 143 with different lengths (the second length S2 and the third length S3, respectively) on two opposite sides of the pad array 130, the pad array 130 can be arranged as follows: Figure 1The top view as shown shows an overall left-right asymmetric layout arrangement, thereby improving the structural defects that may be derived from the continuous increase in the density of the memory cells in the semiconductor structure 10. In addition, in one embodiment, each of the first branch pads 135 and each of the second branch pads 139 disposed on two opposite sides of the pad array 130 also has a fourth length S4 and a fifth length S5 that are different from the first length S1 in the first direction D1, and the fourth length S4 of the first branch pad 135 is less than the fifth length S5 of the second branch pad 139, and also presents a left-right asymmetric layout arrangement.

[0070] For example Figure 1 As shown in FIG. 1 , no first pad 131 is sandwiched between the first branch pads 135 or the second pads 141 on one side of the pad array 130 in the third direction D3, while one first pad 131 is sandwiched between the third pads 143 on the other side of the pad array 130. Furthermore, the ends of each first branch pad 135 and each second pad 141 on one side of the pad array 130 are aligned with each other in the third direction D3, that is, the ends of the first branch pad 135 and the second pad 141 can all fall on the same tangent line A, as shown in FIG. Figure 1 On the other hand, the ends of each second branch pad 139 and each third pad 143 located on the other side of the pad array 130 are partially staggered in the third direction D3, so that the ends of the second branch pads 139 are aligned with each other and fall on the same tangent line B, but are not aligned with the ends of the third pads 143. In this embodiment, the first pad boundary 133 and the second pad boundary 137 are respectively arranged on the outside of all the first pads 131, all the second pads 141 and all the third pads 143 to achieve the effect of protecting the overall layout arrangement of the first pads 131. Those skilled in the art can easily understand that, in another embodiment, the semiconductor structure 10 may further include at least one third pad boundary 145 extending in the fourth direction D4, and the two ends of the third pad boundary 145 may be respectively connected to the first pad boundary 133 and the second pad boundary 137, so that the first pad boundary 133, the second pad boundary 137 and the third pad boundary 145 are arranged around the outside of all the first pads 131, all the second pads 141 and all the third pads 143, for example, the whole presents a rectangular frame shape or other suitable shapes, thereby achieving a more optimized protection effect.

[0071] like Figure 1 and Figure 2As shown, the semiconductor structure 10 also includes a substrate 100 and a plurality of word lines 120 disposed in the substrate 100. The aforementioned pad array 130 is, for example, disposed on the substrate 100, and the substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but is not limited thereto. Moreover, the first pad 131 of the pad array 130 is, in principle, disposed in a storage area (cell region) 100A with a relatively high component integration in the substrate 100, while the second pad 141, the first branch pad 135, the third pad 143 and the second branch pad 139 located on two opposite sides of the pad array 130 are, in principle, located in a peripheral region (periphery region) 100B with a relatively low component integration in the substrate 100. In one embodiment, the peripheral region 100B is, for example, disposed on at least one side of the storage region 100A, preferably, since Figure 1 or Figure 3 From the top view shown, the peripheral region 100B is, for example, disposed around the outside of the storage region 100A, but is not limited thereto. Each word line 120 is disposed in the substrate 100 in a spaced manner, and includes a dielectric layer 122, a gate dielectric layer 124, and a gate 126 stacked in sequence, and a cap layer 128 covering the gate 126, as shown in FIG. Figure 2 As shown. The surface of the cap layer 128 can be flush with the top surface of the substrate 100, so that each word line 120 serves as a buried word line (BWL) of the semiconductor device 10, and is isolated from components disposed on the substrate 100 by means of an insulating layer 102 disposed on the substrate 100. In one embodiment, the insulating layer 102 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure, but is not limited thereto.

[0072] For example Figure 1 and Figure 2 As shown, the semiconductor structure 10 further includes a plug array 110 which is also disposed on the substrate 100 and is disposed in a matrix arrangement along a third direction D3 and a fourth direction D4 which are perpendicular to each other and separated from each other. Figure 1As shown. The plug array 110 includes a plurality of plugs 111 and 113, which are respectively arranged in the storage area 100A and the peripheral area 100B. The plugs 111 and 113 are alternately arranged with the plurality of isolation structures 104 in the fourth direction D4, so as to electrically isolate the adjacent plugs 111 and 113 by means of the isolation structures 104. In one embodiment, the plug 111 includes, for example, epitaxial materials such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe) or germanium (Ge), or low-resistance metal materials such as aluminum, titanium, copper or tungsten, but is not limited thereto. It should be noted that, although the arrangement of the plug array 110 is different from that of the pad array 130, in the direction perpendicular to the substrate 100, each plug 111 is respectively disposed below each first pad 131 and physically contacts the corresponding first pad 131 above, and each plug 113 is disposed below each second branch pad 139 or each third pad 143 and physically contacts the corresponding second branch pad 139 or third pad 143 above. The bottom portion of the plug 111 disposed in the storage area 100A extends into the substrate 100 and is electrically connected to the transistor element (not shown) disposed in the substrate 100, while the top of the plug 111 is electrically connected to the first pad 131, so as to serve as a storage node contact (SNC) of the semiconductor device 10, so as to be further electrically connected to a storage node (SN) disposed subsequently. The bottom of each plug 113 disposed in the peripheral area 100B is located on the insulating layer 102, does not contact the substrate 100 and serves as a dummy plug. It should be noted that the first pad 131 closest to the second pad 141 or the first branch pad 135 in the first direction D1 and the plug 111 in contact with it have centroids C1 and C2 respectively, and the minimum distance g1 between the two centroids C1 and C2 is greater than the minimum distance g2 between the centroid C3 of the remaining first pad 131 and the centroid C4 of the plug 111 in contact with it. At the same time, the minimum distance g3 between the centroid C5 of the first pad 131 closest to the second branch pad 139 and the third pad 143 in the first direction D1 and the centroid C6 of the plug 111 in contact with it is also greater than the minimum distance g2, and preferably less than the minimum distance g1, but not limited thereto.

[0073] On the other hand, Figure 3 and Figure 4As shown, the first pads 131 are arranged into a plurality of rows 130a extending in the first direction D1, and a plurality of columns 130b extending in the second direction D2, and the whole presents another matrix layout arrangement. Among them, one of the first pads 131 closest to the second pad boundary 137 in each row 130a arranges a first sawtooth profile Z1 in the third direction D3, and one of the first pads 131 closest to the first pad boundary 133 in each column 130b arranges a second sawtooth profile Z2 different from the first sawtooth profile Z1 in the third direction D3. Among them, the opening O2 of the first sawtooth profile Z1 in the third direction D3 is larger than the opening O1 of the second sawtooth profile Z2 in the third direction D3, and the sawtooth height H2 of the first sawtooth profile Z1 in the fourth direction D4 perpendicular to the third direction D3 (i.e., the height difference between the highest point and the lowest point of the first sawtooth profile Z1) is also larger than the sawtooth height H2 of the second sawtooth profile Z2 in the fourth direction D4.

[0074] Under this configuration, the semiconductor structure 10 of the preferred embodiment of the utility model can maintain the minimum distances g1, g2, g3 between the center of gravity C1, C3, C5 of each first pad 131 in the storage area 100A and the center of gravity C2, C4, C6 of the corresponding plug 111 respectively by respectively configuring the surrounding pads with an asymmetric overall layout (for example, including the second pad 141, the first branch pad 135, the third pad 143 and the second branch pad 139) on the two opposite sides of the pad array 130. The minimum distance g1 and g3 between the center of gravity C1 and C5 of the first pad 131 and the center of gravity C2 and C6 of the corresponding plug 111 of the first pad 131 and the center of gravity C5 of the first pad 131 and the center of gravity C6 of the plug 111 are preferably set to prevent the center of gravity C1 and C5 of the first pad 131 and the center of gravity C2 and C6 of the plug 111 from being excessively offset, thereby causing the distance between them to be too large and seriously affecting the contact range between the first pad 131 and the corresponding plug 111. In this way, the semiconductor structure 10 of the present embodiment is provided with an optimized structure and performance. A person skilled in the art of the present invention should be able to easily understand that the semiconductor structure 10 of the present embodiment can also be provided with various components such as transistor components, word line components and / or bit line components in the storage area 100A according to actual device requirements. Furthermore, a plurality of capacitors (not shown) electrically connected to the first pads 131 may be further disposed above the pad array 130 to form a dynamic random access memory (DRAM) device and achieve good device performance, but the present invention is not limited thereto.

[0075] In order to enable a person skilled in the art to which the present invention belongs to easily understand the semiconductor structure 10 of the present invention, the manufacturing method of the semiconductor structure 10 of the present invention will be further described below.

[0076] Please refer to Figures 5 to 9 , which is a schematic diagram of a method for manufacturing a semiconductor structure 10 in a preferred embodiment of the present invention, wherein: Figure 5 is a schematic flow chart of the steps of a method for manufacturing a semiconductor structure, Figures 6 to 9 This is a schematic diagram of the semiconductor structure manufacturing process. First, please refer to Figure 5 and Figure 6 As shown, a chip 200 is provided, and a plug array 110 is formed on the chip 200 (step S1 ). The plug array 110 includes a plurality of plugs 111 , and a plug center 111 a is defined on each plug 111 .

[0077] Next, a mask layer (not shown) is formed on the chip 200, covering the plug array 110, and a preset storage pad array 210 is defined on the mask layer, including a plurality of preset storage pad patterns 211 (step S2). Each preset storage pad pattern 211 overlaps each plug 111 disposed below. Those skilled in the art should easily understand that in order to clearly present the relative relationship between the plug 111 and the preset storage pad pattern 211, Figure 6 Only part of the plugs 111 and part of the preset storage pad pattern 211 are shown. The specific arrangement of the plugs 111 is as follows. Figure 1 As shown, the storage pad patterns 211 are arranged in a matrix layout along the third direction D3 and the fourth direction D4 which are perpendicular to each other and separated from each other, and the specific arrangement of the preset storage pad patterns 211 is also as shown. Figure 1 As shown, the pads are arranged in a matrix layout along the first direction D1 and the second direction D2 which are interlaced and perpendicular to each other, but the present invention is not limited thereto. In addition, a preset pad center 211a is defined on each preset storage pad pattern 211 .

[0078] For example Figures 5 to 7 As shown, by presetting the storage pad array 210, a photolithography process is performed on the chip 200 to form a pad array 230 including a plurality of pads 231 (step S3) to overlap the plugs 111 below. It should be noted that the pads 231 are made, for example, by performing two self-aligned reverse patterning (SARP) processes, and pad boundaries 233, 237, a plurality of branch pads 235, 239 extending from the pad boundaries 233, 237 in the first direction D1, and surrounding pads 241, 243 arranged alternately with the branch pads 235, 239 in the third direction D3 are formed around the pad array 230 of the pads 231, as shown in FIG. Figure 6As shown, but not limited thereto. Due to the load effect of etching, at least part of the pads 231 are reduced in size after formation, or their positions deviate from the positions of the preset storage pad pattern 211, thereby affecting the overlap rate between each pad 231 and the corresponding plug 111. For example, the pad 231b adjacent to the branch pad 235 or the surrounding pad 241 is, for example, slightly offset toward the center of gravity 111b of the corresponding plug 111a in the first direction D1 or the second direction D2, while the pad 231c adjacent to the branch pad 239 or the surrounding pad 243 is, for example, away from the center of gravity 111b of the plug 111c in the first direction D1 or the second direction D2, so that the overlap relationship between the pads 231b, 231c and the corresponding plugs 111a, 111c is affected, but not limited thereto. Among them, although the formation positions of the pads 231b and 231c are obviously offset from the position of the preset storage pad pattern 211, the pad 231b and its corresponding plug 111b still maintain a certain degree of overlap, while the pad 231c and its corresponding plug 111c cannot maintain a certain degree of overlap. Figure 6 and Figure 7 shown.

[0079] Then, the pad 230 is processed by comparing the positional relationship between the plug center 111a, the preset pad center 211a and the pad center 231a (step S4). Specifically, since the pads 231b and 231c adjacent to the branch pads 235 and 239 or the surrounding pads 241 and 243 are prone to positional displacement or size deviation, the pad center 231a of the pads 231b and 231c, the plug center 111a of the corresponding plugs 111b and 111c and the preset pad center 211a of the preset storage pad pattern 211 can be jointly set to form an angle θ1 and θ2, such as Figure 6 As shown. Among them, the angle θ2 between the pad center 231a of the pad 231c located on one side, the plug center 111a of the plug 111c, and the preset pad center 211a of the preset storage pad pattern 211 is greater than the angle θ1 between the pad center 231a of the pad 231b located on the other side, the plug center 111a of the plug 111b, and the preset pad center 211a of the preset storage pad pattern 211. Therefore, the manufacturing method of the utility model can deduce the degree of deviation of the pad 231 by judging the angle between the pad center 231a of the pad 231, the plug center 111a of the plug 111, and the preset pad center 211a of the preset storage pad pattern 211 (step S41). For example, when the angle (eg, Figure 6When the included angle θ1) shown in FIG. 1 is less than 90 degrees (an acute angle), it means that the pad 231 still highly overlaps with its corresponding plug 111, and the degree of deviation is relatively slight. Figure 6 and Figure 7 On the other hand, when the angle between the pad center 231a of the pad 231, the plug center 111a of the plug 111, and the preset pad center 211a of the preset storage pad pattern 211 (for example, Figure 6 When the angle θ2 shown in FIG. 1 is greater than 90 degrees (an obtuse angle), it means that the pad 231 and its corresponding plug 111 do not overlap or overlap only in a small range, and the degree of deviation is relatively serious. In this operation, the overlap degree of each pad 231 and its corresponding plug 111 can be checked according to the angle between the pad center 231a of the pad 231, the plug center 111a of the plug 111, and the preset pad center 211a of the preset storage pad pattern 211, and further determine whether the pad 231 should be retained or corrected. That is to say, when the angle between the pad center 231a of the pad 231, the plug center 111a of the plug 111, and the preset pad center 211a of the preset storage pad pattern 211 is less than 90 degrees, it is judged that the pad 231 should be retained, and when the angle between the pad center 231a of the pad 231, the plug center 111a of the plug 111, and the preset pad center 211a of the preset storage pad pattern 211 is greater than 90 degrees, it is judged that the pad 231 should be corrected.

[0080] In one embodiment, modifying the pads 231 includes, for example, removing all pads 231 and re-forming a new pad array 330. Figure 8 As shown, the pad array 330 has Figure 6 In addition to the pads 231 shown in FIG. 1 , a plurality of pads 331 are additionally formed on one side of the pad 231c where the angle θ2 is greater than 90 degrees, wherein the pads 331 are aligned with each other in the third direction D3 and aligned in the third direction D3 as shown in FIG. Figure 6 The pad 231c shown, as Figure 8 Thus, the load effect derived from the etching defect is corrected by forming an additional pad 331, and the formation position of the pad 331 adjacent to the pad boundary 237 is corrected, so that all pads 231, 331 can maintain a certain degree of overlap with the corresponding plug 111 disposed below, as shown in FIG. Fig. 9As shown. In this operation, the formed semiconductor structure can have a more optimized structure, thereby improving its structural reliability. In addition, in another embodiment, the correction pad 231 includes, for example, when the angle between the pad center 231a of a pad 231, the plug center 111a of the plug 111, and the preset pad center 211a of the preset storage pad pattern 211 is greater than 90 degrees, removing the aforementioned pad 231, for example, as shown in Figure 6 The pads 231c shown in the figure, and other pads 231 aligned in the third direction D3. Those skilled in the art should easily understand that since the specific arrangement of the preset storage pad pattern 211 presents the matrix layout arrangement set along the first direction D1 and the second direction D2, the pads 231 of this embodiment also present a similar matrix layout arrangement accordingly. Therefore, when modifying the pads 231, it is preferred to remove the entire row of pads 231 that are also located on one side of the matrix layout arrangement presented by the pads 231, that is, remove all pads 231c adjacent to the branch pads 239 or the surrounding pads 243 to form a new pad array 430. Fig.10 As shown, the remaining pads 231 can all maintain a certain degree of overlap with the corresponding plugs 111 disposed therebelow, so that the formed semiconductor structure can have a more optimized structural reliability.

[0081] In this operation, by judging the angle between the pad center 231a of the pads 231b and 231c formed on two opposite sides and the plug center 111a of the plugs 111b and 111c corresponding thereto and the preset pad center 211a of the preset storage pad pattern 211, the degree of deviation of the pad 231 can be deduced, and the pad 231 can be retained or corrected. In addition, since the loading effect of etching causes the pad center 231a of the pad 231c on one side to be offset away from the center of gravity 111b of the plug 111c when forming the pad 231, the overlap rate between the pad 231c and the plug 111c is greatly affected. In this way, only the pad 231c on the aforementioned side needs to be corrected, thereby forming a pad array with an asymmetric overall layout, such as the following. Figure 1 The pad array 130 is shown. In this operation, the semiconductor structure 10 formed according to the manufacturing method of this embodiment can have an optimized structure and performance, and can further form a dynamic random access memory device and achieve good device performance.

[0082] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A semiconductor structure, characterized in that: include: A pad array, the pad array comprising: A plurality of first pads are arranged separately from each other along the first direction and the second direction; A first pad boundary is arranged at one side of the pad array, wherein the first pad boundary includes a plurality of first branch pads extending in the first direction; A second pad boundary is arranged at another side of the pad array opposite to the first pad boundary, the second pad boundary comprising a plurality of second branch pads extending in the first direction; A plurality of second pads are disposed between the first branch pads and separated from each other in a third direction; a plurality of third pads, arranged between the second branch pads and separated from each other in the third direction; The length of the second pad in the first direction is smaller than the length of the third pad in the first direction.

2. The semiconductor structure according to claim 1, characterized in that: In the third direction, the first pad is not sandwiched between the first branch pads or between the second pads, and the first pad is sandwiched between the second branch pads or the third pads.

3. The semiconductor structure according to claim 1, characterized in that: The first pad has a first length in the first direction, the second pad has a second length in the first direction, and the third pad has a third length in the first direction, wherein the first length, the second length, and the third length are all different.

4. The semiconductor structure according to claim 1, characterized in that: Ends of each of the second pads and each of the first branch pads are aligned with each other in the third direction, and ends of each of the third pads and the second branch pads are partially staggered in the third direction.

5. The semiconductor structure according to claim 1, characterized in that: Also includes: A plug array is arranged below the pad array, and the plug array comprises: A plurality of plugs are disposed below the first pad, the second pad and the third pad, and each of the first pad, each of the second pad and each of the third pads at least partially overlaps each of the plugs below.

6. The semiconductor structure according to claim 5, characterized in that: The distance between the center of gravity of the first pad closest to the second pad, the first branch pad, the third pad or the second branch pad in the first direction and the center of gravity of the corresponding plug is greater than the distance between the center of gravity of the remaining first pads and the center of gravity of the corresponding plug.

7. A semiconductor structure, characterized in that: include: A pad array, the pad array comprising: a plurality of first pads, the first pads being arranged in a plurality of rows extending in a first direction and in a plurality of columns extending in a second direction; A first pad boundary is arranged at one side of the pad array, wherein the first pad boundary includes a plurality of first branch pads; A second pad boundary is arranged at another side of the pad array opposite to the first pad boundary, wherein the second pad boundary includes a plurality of second branch pads; The first pad in each row that is closest to the first pad boundary has a first sawtooth profile, and the first pad in each row that is closest to the second pad boundary has a second sawtooth profile different from the first sawtooth profile.

8. The semiconductor structure according to claim 7, characterized in that: The opening of the first sawtooth profile is larger than the opening of the second sawtooth profile.

9. The semiconductor structure according to claim 7, characterized in that: A sawtooth height of the first sawtooth profile is greater than a sawtooth height of the second sawtooth profile.

10. The semiconductor structure according to claim 7, characterized in that: The pad array further comprises: second pads, disposed between the first branch pads and separated from each other in a third direction; and A third solder pad is arranged between the second branch solder pads and separated from each other in the third direction, wherein the first solder pad has a first length in the first direction, the second solder pad has a second length in the first direction, and the third solder pad has a third length in the first direction, and the first length, the second length and the third length are all different.

11. The semiconductor structure according to claim 10, characterized in that: In the third direction, the first pad is not sandwiched between the first branch pads or between the second pads, and the first pad is sandwiched between the second branch pads or the third pads.

12. The semiconductor structure according to claim 10, characterized in that: Also includes: A plug array, the plug array comprising: A plurality of plugs are disposed below the first pad, the second pad and the third pad, and each of the first pad, each of the second pad and each of the third pads at least partially overlaps each of the plugs below.

13. The semiconductor structure according to claim 12, characterized in that: The distance between the center of gravity of the first pad closest to the second pad, the first branch pad, the third pad or the second branch pad in the first direction and the center of gravity of the corresponding plug is smaller than the distance between the center of gravity of the remaining first pads and the center of gravity of the corresponding plug.

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