A silicon carbide diode chip structure

Abstract

A silicon carbide diode chip structure belongs to the technical field of semiconductor diode chips. It includes: an N-type silicon carbide substrate, an N-type epitaxial layer, a P-type field limiting ring region doping region, an oxygen-doped polysilicon protective layer, a borophosphosilicate glass protective layer, a silicon nitride protective layer, a polyimide protective layer, an N-type epitaxial layer P+ type doping region, an aluminum silicon compound alloy layer on the surface of the N-type epitaxial layer, an N electrode layer, and a P electrode layer. The composite passivation layer structure is sequentially: an oxygen-doped polysilicon passivation layer, a borophosphosilicate glass passivation layer, a silicon nitride passivation layer, and a polyimide passivation layer from the inner layer to the outer layer. An N-type epitaxial layer is formed on an N-type silicon carbide substrate, a P+ type doping region is formed in the middle region of the N-type epitaxial layer, and a P-type field limiting ring region doping region is formed in the peripheral region of the P+ type doping region. The problem that the field limiting ring region of the existing silicon carbide diode device is prone to ablation under high withstand voltage, resulting in device failure, is solved. It is widely used in the technical field of passivation layers of silicon carbide diodes and other high-voltage devices.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductor diode chips, and further relates to the technical field of silicon carbide diode chips, and specifically relates to a silicon carbide diode chip structure. Background Art

[0002] Since SiC (silicon carbide) has a bandgap width three times that of silicon, a breakdown field strength (0.8E16-3E16V / cm) ten times that of silicon, and a thermal conductivity (4.9W / cm K) 3.2 times that of silicon, silicon carbide is called a wide bandgap semiconductor material and is known as the third-generation semiconductor material in the industry. It can be used to make semiconductor devices that are resistant to high voltage, high temperature, and high frequency.

[0003] In the actual commercialization process of silicon carbide devices, silicon carbide diodes generally have typical voltage levels of 650V, 1200V, and 1700V. How to reasonably improve the device's voltage resistance level is a key issue of concern in the industry.

[0004] The existing silicon carbide diode chip structure mainly includes silicon carbide substrate, silicon carbide epitaxial layer, passivation layer, and metal electrode layer. The improvement of withstand voltage is generally determined by the P+ injection area of ​​the epitaxial layer. The field limiting ring outside the active area and the passivation layer on the field limiting ring both play a role in improving the withstand voltage, so how to optimize the passivation layer design is an important design task for preparing high-voltage silicon carbide diodes. Generally, SiN and PI glue are used as device passivation layers in designs, but it is not enough to rely solely on SiN and PI as passivation layers to reinforce the withstand voltage of the device. Under extreme working conditions, the device will be damaged. Through device failure analysis, it can be found that the field limiting ring area of ​​the device will be ablated.

[0005] In view of this, the present utility model is proposed. Summary of the invention

[0006] The technical problem to be solved by the utility model is to solve the problem that the field limiting ring region of the existing silicon carbide diode device is prone to ablation under high withstand voltage, resulting in device failure.

[0007] The inventive concept of the utility model is to use a composite passivation layer instead of a single SiN or PI passivation layer to reinforce the withstand voltage of the device, so as to improve the withstand voltage capability of the silicon carbide diode, thereby achieving the extreme working capability of the silicon carbide diode.

[0008] In the development of normal high-voltage devices, silicon dioxide and polyimide are generally selected as passivation layers. Silicon dioxide is generally prepared by thermal oxidation. Since the material needs to withstand high-temperature thermal stress for a long time, this process is not completely reliable. However, the use of PECVD to grow silicon dioxide greatly reduces the deposition rate, and the quality of the deposited silicon dioxide cannot be guaranteed. In addition, the passivation effect of silicon dioxide is not perfect. Defects and contamination in silicon dioxide, as well as the interface state of silicon-silicon dioxide, will destroy the stability of the device, and will also damage the electrical performance and reliability of the device. In actual products, this passivation layer combination is prone to device burnout under extreme working conditions, so we need to reinforce the device passivation layer.

[0009] Oxygen-doped polysilicon (SIPOS) is used as a passivation layer. Due to the electrical neutrality of SIPOS, the charges induced in the external environment do not accumulate on the silicon surface, but flow into the semi-insulating polysilicon and are captured by a large number of traps in the film, thereby forming a space charge region in the polysilicon that shields the external electric field, so that the energy band distribution on the surface of the silicon substrate is not affected by the external electric field. The semi-insulating property of the film allows current to flow through the film, thereby alleviating the surface electric field of the barrier region, thereby increasing the breakdown voltage of the junction. The SIPOS film contains oxygen atoms, which reduce the surface state density and the leakage current, solving the problems of creep, drift, and large reverse leakage current of the reverse characteristic curve of silicon devices. Therefore, the use of oxygen-doped polysilicon (SIPOS) can not only improve the reverse breakdown voltage of the device, but also greatly improve the reliability of the device.

[0010] Borophosphosilicate glass (BPSG) is generally used as an insulating layer before metal wiring. The role of doping with boron and phosphorus is to reduce the reflow temperature and reduce the thermal budget. The properties of borophosphosilicate glass are not stable enough and are often affected by the environment. The boron trioxide and phosphorus pentoxide in it easily react with water vapor in the air to generate boric acid and phosphoric acid, which then form defects and cause circuit short circuits. The longer the contact time with air, the more likely it is to occur, which ultimately leads to low product yield. The main purpose of adding boron and phosphorus is to reduce the reflow temperature and make the step (Step) after reflow smoother, so as to prevent the metal layer (Metal line) from being broken after sputtering.

[0011] Silicon nitride (SiN), silicon nitride film has excellent optoelectronic and mechanical properties such as dense structure, high dielectric constant, and large refractive index; silicon nitride film has low operating temperature, low cost and easy-to-control deposition conditions; silicon nitride film has high melting point, chemical inertness, high hardness and high electrical insulation performance; silicon nitride film has high resistivity and high breakdown field strength, good chemical stability and thermal stability, and excellent resistance to high-temperature oxidation. It can be used to make gate insulation layers of thin-film transistors, dielectric layers of microelectronic devices, and surface passivation layers; silicon nitride film has strong resistance to impurity diffusion and water vapor penetration, as well as strong radiation resistance. Therefore, using silicon nitride film as a passivation layer can effectively improve the working reliability of devices in extreme environments.

[0012] Polyimide (PI), polyimide is a polymer compound. The chemical properties of cured PI are very stable and it is resistant to all organic solvents and phosphoric acid, hydrochloric acid, hydrofluoric acid and other dilute acids. Studies have shown that in the PI / Si structure, the PI layer carries 1011cm-2 of negative charge, which can effectively weaken the adverse effects of the underlying positive charge on the device. The PI film is used for passivation, which can reduce the thermal stress and mechanical damage of the post-process, and can also reduce the electromigration of aluminum, reducing the probability of failure caused by open leads.

[0013] Therefore, using oxygen-doped polycrystalline silicon (SIPOS) + borophosphosilicate glass (BPSG) + silicon nitride (SiN) + polyimide (PI) as the passivation layer of the silicon carbide diode can greatly enhance the voltage resistance characteristics of the silicon carbide diode, enhance the adaptability of the device in later packaging, and greatly improve the reliability of the device, especially the device will not be damaged under extreme working conditions.

[0014] To this end, the utility model provides a silicon carbide diode chip structure, such as Figure 1-2 As shown. Includes:

[0015] N-type silicon carbide substrate 2, N-type epitaxial layer 3, P-type field limiting ring doping region 4, oxygen-doped polysilicon (SIPOS) protective layer 5, borophosphosilicate glass (BPSG) protective layer 6, silicon nitride (SiN) protective layer 7, polyimide (PI) protective layer 8, N-type epitaxial layer P+ type doping region 9, N-type epitaxial layer surface aluminum silicon compound alloy layer 10, N-electrode layer 1, P-electrode layer 11.

[0016] A P+ doped region 9 is formed in the middle region of the N-type epitaxial layer 3. The P+ doped region 9 consists of a peripheral annular region and an internal strip region, and there are at least two internal strip regions (determined by the specific parameters of the silicon carbide diode, usually hundreds to thousands of strips), and both ends of each internal strip region are respectively connected to the peripheral annular region to form a cell region.

[0017] A P-type field limiting ring doping region 4 is formed in the peripheral area of ​​the P+ type doping region 9 of the N-type epitaxial layer 3. The P-type field limiting ring doping region 4 surrounds the P+ type doping region 9, and the P-type field limiting ring doping region 4 has at least two field limiting rings (determined according to the specific parameters of the silicon carbide diode, usually tens to hundreds of field limiting rings), forming a field limiting ring region.

[0018] An oxygen-doped polysilicon (SIPOS) protection layer 5 is formed in the area where the P+ type doping region 9 is opened on the N type epitaxial layer 3 ; the oxygen-doped polysilicon (SIPOS) protection layer 5 covers a portion of the adjacent first P+ type doping region 9 .

[0019] A borophosphosilicate glass (BPSG) protective layer 6 is formed on the oxygen-doped polysilicon (SIPOS) protective layer 5 .

[0020] An aluminum-silicon compound alloy layer 10 is formed on the N-type epitaxial layer 3 in a region other than the surface oxygen-doped polysilicon (SIPOS) protection layer 5 .

[0021] A P-electrode layer 11 is formed at the opening of the aluminum-silicon compound alloy layer 10 ; the P-electrode layer 11 partially overlaps with the borophosphosilicate glass (BPSG) protection layer 6 .

[0022] A silicon nitride (SiN) protection layer 7 is formed on the borophosphosilicate glass (BPSG) protection layer 6 and a portion of the P-electrode layer 11 .

[0023] A polyimide (PI) protection layer 8 is formed on the silicon nitride (SiN) protection layer 7 and a portion of the P-electrode layer 11 .

[0024] An N-electrode layer 1 is formed on the bottom surface of the N-type silicon carbide substrate 2 .

[0025] The N-electrode layer 1 is a composite metal layer, which includes a titanium layer, a nickel layer, and a silver layer from the inside to the outside.

[0026] The thickness of the oxygen-doped polysilicon (SIPOS) protective layer 5 is 500 angstroms to 5000 angstroms, the thickness of the borophosphosilicate glass (BPSG) protective layer 6 is 2000 angstroms to 5000 angstroms, the thickness of the silicon nitride (SiN) protective layer 7 is 2000 angstroms to 30000 angstroms, and the thickness of the polyimide (PI) protective layer 8 is 20000 angstroms to 40000 angstroms.

[0027] The beneficial effects of the utility model are:

[0028] By utilizing a multi-layer composite passivation layer structure of oxygen-doped polysilicon (SIPOS) + borophosphosilicate glass (BPSG) + silicon nitride (SiN) + polyimide (PI), multiple protections for the device active area are achieved, and the device reliability capability has been qualitatively improved.

[0029] The technical solution of the utility model can be widely applied to the technical field of passivation layer of silicon carbide diodes and other high-voltage devices, and has certain guiding significance for device failure analysis and reliability improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the structure of a composite passivation layer silicon carbide diode.

[0031] Figure 2 It is a schematic diagram of the structure of the N-type epitaxial layer P+ type doped region and the P-type field limiting ring region.

[0032] In the figure: 1 is an N-electrode layer, 2 is an N-type silicon carbide substrate, 3 is an N-type epitaxial layer, 4 is a P-type field limiting ring doping region, 5 is an oxygen-doped polysilicon (SIPOS) protective layer, 6 is a borophosphosilicate glass (BPSG) protective layer, 7 is a silicon nitride (SiN) protective layer, 8 is a polyimide (PI) protective layer, 9 is an N-type epitaxial layer P+ doping region, 10 is an aluminum-silicon compound alloy layer on the surface of the N-type epitaxial layer, and 11 is a P-electrode layer. DETAILED DESCRIPTION

[0033] like Figure 1-2 As shown, the silicon carbide diode chip structure is specifically implemented as follows:

[0034] The P+ doped region 9 is a square ring-shaped region with arc-shaped corners at the outer ring-shaped region, and the inner strip-shaped region is a rectangular strip, and the number of the rectangular strips is 800.

[0035] The P-type field limiting ring doping region 4 is composed of 20 field limiting rings, and the shape of the field limiting ring is a square ring region with four circular arcs.

[0036] The material of the N-type silicon carbide substrate 2 is 4H SiC, the thickness is 330 μm±25 μm, and the resistivity is (0.012-0.025) ohm.cm.

[0037] The N-type epitaxial layer 3 formed on the N-type silicon carbide substrate 2 is an N-type epitaxial layer with a thickness of 18 μm and a doping concentration of 9E15 / cm 3 .

[0038] The P+ doped region 9 and the P-type field limiting ring doped region 4 are formed on the N-type epitaxial layer 3 by multiple high-temperature and high-energy aluminum ion implantations. The ion implantation temperature is 773K and the implantation is performed in multiple times. The multiple implantation doses are (9.5E14cm -2 、350KeV)、(6.8E14cm -2 、220KeV)、(3.6E14cm -2 、120KeV)、(2.7E14cm -2, 55KeV), the total doping concentration is 4.3e19cm -3 The junction depth is 0.6 μm to 0.7 μm. Then, the P+ doping region 9 and the P-type field limiting ring region doping region 4 are annealed and activated.

[0039] The thickness of the oxygen-doped polysilicon (SIPOS) protection layer 5 is 2000 angstroms.

[0040] The thickness of the borophosphosilicate glass (BPSG) protective layer 6 is 5000 angstroms.

[0041] The thickness of the silicon nitride (SiN) protection layer 7 is 20,000 angstroms.

[0042] The thickness of the polyimide (PI) protective layer 8 is 30,000 angstroms.

[0043] The thickness of the aluminum-silicon compound alloy layer 10 on the surface of the N-type epitaxial layer is 2000 angstroms.

[0044] The thickness of the P-electrode layer 11 is 40,000 angstroms.

[0045] The material of the N electrode layer 1 is a Ti / Ni / Ag composite layer, wherein Ti is an inner layer, Ni is a middle layer, and Ag is an outer layer. The thickness of each layer in the Ti / Ni / Ag composite layer is Ti / Ni / Ag=1000 angstroms / 2000 angstroms / 40000 angstroms.

[0046] Finally, it should be noted that the above embodiments are only examples for clear explanation. The present utility model includes but is not limited to the above embodiments. It is not necessary and impossible to list all implementation methods here. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. All implementation methods that meet the requirements of the present utility model belong to the protection scope of the present utility model.

Claims

1. A silicon carbide diode chip structure, characterized in that: include: N-type silicon carbide substrate (2), N-type epitaxial layer (3), P-type field limiting ring region doping region (4), oxygen-doped polysilicon (SIPOS) protective layer (5), borophosphosilicate glass (BPSG) protective layer (6), silicon nitride (SiN) protective layer (7), polyimide (PI) protective layer (8), N-type epitaxial layer P+ type doping region (9), N-type epitaxial layer surface aluminum silicon compound alloy layer (10), N-electrode layer (1), P-electrode layer (11); The front surface of the N-type silicon carbide substrate (2) is an N-type epitaxial layer (3); A P+ type doped region (9) is formed in the middle region of the N type epitaxial layer (3), wherein the P+ type doped region (9) is composed of a peripheral annular region and an internal strip region, wherein there are at least two internal strip regions, and both ends of each internal strip region are respectively connected to the peripheral annular region to form a cell region; A P-type field limiting ring doping region (4) is formed in the peripheral area of ​​the P+ type doping region (9) of the N-type epitaxial layer (3), wherein the P-type field limiting ring doping region (4) surrounds the P+ type doping region (9), and the P-type field limiting ring doping region (4) has at least two field limiting rings to form a field limiting ring region; An oxygen-doped polysilicon (SIPOS) protective layer (5) is formed above the opening area of ​​the P+ type doped region (9), and the oxygen-doped polysilicon (SIPOS) protective layer (5) covers a portion of the adjacent first P+ type doped region (9); The oxygen-doped polysilicon (SIPOS) protective layer (5) is provided with a borophosphosilicate glass (BPSG) protective layer (6); The area outside the oxygen-doped polycrystalline silicon (SIPOS) protective layer (5) is an aluminum-silicon compound alloy layer (10); The upper layer at the opening of the aluminum-silicon compound alloy layer (10) is a P-electrode layer (11), and the P-electrode layer (11) partially overlaps with a borophosphosilicate glass (BPSG) protective layer (6); The upper layer of the borophosphosilicate glass (BPSG) protective layer (6) and part of the P-electrode layer (11) is a silicon nitride (SiN) protective layer (7); The upper layer of the silicon nitride (SiN) protective layer (7) and part of the P electrode layer (11) is a polyimide (PI) protective layer (8); The lower layer of the bottom surface of the N-type silicon carbide substrate (2) is an N-electrode layer (1).

2. A silicon carbide diode chip structure as claimed in claim 1, characterized in that: The thickness of the oxygen-doped polysilicon (SIPOS) protective layer (5) is 500 angstroms to 5000 angstroms.

3. A silicon carbide diode chip structure as claimed in claim 1, characterized in that: The thickness of the borophosphosilicate glass (BPSG) protective layer (6) is 2000 angstroms to 5000 angstroms.

4. A silicon carbide diode chip structure as claimed in claim 1, characterized in that: The thickness of the silicon nitride (SiN) protective layer (7) is 2000 angstroms to 30000 angstroms.

5. The silicon carbide diode chip structure according to claim 1, characterized in that: The thickness of the polyimide (PI) protective layer (8) is 20,000 angstroms to 40,000 angstroms.

6. A silicon carbide diode chip structure as claimed in claim 1, characterized in that: The P+ type doped region (9) is composed of a square annular region with arc-shaped corners at the outer annular region, and the inner strip region is a rectangular strip, and the number of rectangular strips is 800; The P-type field limiting ring doping region (4) is composed of 20 field limiting rings, and the field limiting rings are in the shape of a square ring region with four circular arcs at the corners.

7. The silicon carbide diode chip structure according to claim 1, characterized in that: The N-electrode layer (1) is a composite metal layer.

8. A silicon carbide diode chip structure as claimed in claim 7, characterized in that: The composite metal layer is a titanium / nickel / silver composite metal layer, which comprises a titanium layer, a nickel layer and a silver layer from the inside to the outside.

9. A silicon carbide diode chip structure as claimed in claim 8, characterized in that: The thicknesses of the titanium layer, the nickel layer and the silver layer are 1000 angstroms, 2000 angstroms and 40000 angstroms respectively.

10. The silicon carbide diode chip structure according to claim 1, characterized in that: The thickness of the N-type epitaxial layer is 18 μm; The junction depth of the P+ doped region (9) and the P-type field limiting ring region doped region (4) is 0.6 μm to 0.7 μm; The thickness of the oxygen-doped polysilicon (SIPOS) protective layer (5) is 2000 angstroms; The thickness of the borophosphosilicate glass (BPSG) protective layer (6) is 5000 angstroms; The thickness of the silicon nitride (SiN) protective layer (7) is 20,000 angstroms; The thickness of the polyimide (PI) protective layer (8) is 30,000 angstroms; The thickness of the aluminum-silicon compound alloy layer (10) on the surface of the N-type epitaxial layer is 2000 angstroms; The thickness of the P electrode layer (11) is 40,000 angstroms.

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