Package structure
By designing a packaging structure that encapsulates chip-level packaging electronic components in a double-sided packaging structure and removing part of the thickness of the plastic seal layer, the need to reduce thickness in a double-sided packaging is solved, reducing costs and improving yield.
Patent Information
- Application Number
- CN202420747832.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-11
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2034-04-11
AI Technical Summary
In a double-sided packaging structure, in order to reduce thickness, it is necessary to convert the filter chip from a chip-level package to a smaller wafer-level package, but this increases costs and affects the yield of the product.
A packaging structure is designed in which a chip-level encapsulated electronic components are mounted on the front of the substrate, the first plastic sealing layer encapsulates the side walls of the electronic components, and by removing part of the thickness of the plastic sealing layer, the spacing between the substrate surface and the back surface of the electronic components is less than 50 μm or flush.
Using chip-level packaging electronic components in double-sided packaging while maintaining a smaller package thickness, reduces costs and avoids the molding problems caused by using wafer-level packaging, thereby improving product yield.
Smart Images
Figure CN222720409U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a packaging structure. Background Art
[0002] With the development of system-level packaging (SIP) technology and the increasingly urgent demand for miniaturization, double-sided packaging has gradually replaced single-sided packaging in power amplifier (PA) module products to meet the demand for miniaturization. In order to reduce the thickness of the double-sided packaging structure, the thickness requirements for the devices installed on the front of the substrate are becoming more and more stringent. Among them, in order to reduce the thickness of the packaging structure, the filter chip installed on the front of the substrate now needs to be transformed from chip scale package (CSP) to a smaller wafer level package (WLP). However, the conversion of filter chips to WLP increases costs on the one hand, and on the other hand, WLP type chips are not resistant to molding, which affects the yield of the product. Utility Model Content
[0003] The utility model provides a packaging structure, which can use chip-level packaged electronic components in double-sided packaging and can also maintain a small thickness, thereby being beneficial to reducing costs and improving yield.
[0004] In order to achieve the above-mentioned purpose, the utility model provides a packaging structure, which includes a substrate, a first front electronic component and a first plastic packaging layer; the substrate has a relative front and back side; the first front electronic component is installed on the front side of the substrate, the first front electronic component includes a chip body and a plastic packaging body that wraps the chip body, the front side of the first front electronic component faces the substrate and the back side of the first front electronic component faces away from the substrate; the first plastic packaging layer is formed on the front side of the substrate, wrapping the side wall of the first front electronic component; wherein the first plastic packaging layer covers the back side of the first front electronic component, and the distance between the surface of the first plastic packaging layer away from the substrate and the back side of the first front electronic component is less than 50μm; or, the surface of the first plastic packaging layer away from the substrate is flush with the back side of the first front electronic component.
[0005] Optionally, in the first front electronic component, the plastic packaging body covers the side walls of the chip body and the surface of the chip body away from the substrate; the surface of the plastic packaging body away from the substrate is flush with the surface of the first plastic packaging layer away from the substrate.
[0006] Optionally, in the first front electronic component, the plastic encapsulation body covers the side walls of the chip body and exposes the surface of the chip body away from the substrate; the surface of the first plastic encapsulation layer away from the substrate is flush with the surface of the first front electronic component chip body away from the substrate.
[0007] Optionally, the first front electronic component further includes a rewiring layer and a pad, wherein the rewiring layer is located on the front side of the chip body and is electrically connected to the chip body, and the pad is located on the rewiring layer.
[0008] Optionally, the first front electronic component is a filter chip in chip-scale packaging.
[0009] Optionally, a first front groove is provided on the front side of the substrate, and the first front electronic component is installed in the first front groove.
[0010] Optionally, a second front electronic component of a wire bonding type is installed on the front side of the substrate, a second front groove is provided on the front side of the substrate, and the second front electronic component is installed in the second front groove.
[0011] Optionally, the packaging structure further includes a back electronic component and a second plastic packaging layer, wherein the back electronic component is mounted on the back side of the substrate, and the second plastic packaging layer is located on the back side of the substrate and at least wraps the side wall of the back electronic component.
[0012] Optionally, a back side groove is provided on the back side of the substrate, and at least a portion of the back side electronic components are installed in the back side groove.
[0013] In the packaging structure of the utility model, a first front electronic component is installed on the front side of a substrate, the first front electronic component includes a chip body and a plastic packaging body that wraps the chip body, that is, the first front electronic component is a chip-level packaged device, the front side of the first front electronic component faces the substrate and the back side of the first front electronic component faces away from the substrate, the first plastic packaging layer on the front side of the substrate wraps the side wall of the first front electronic component, and by removing part of the thickness of the first plastic packaging layer, the distance between the surface of the first plastic packaging layer away from the substrate and the back side of the first front electronic component is less than 50 μm, or the surface of the first plastic packaging layer away from the substrate is flush with the back side of the first front electronic component, so that chip-level packaged electronic components can be used on the front side of the substrate in double-sided packaging and the packaging structure can also maintain a relatively small thickness, avoiding the method of using wafer-level packaged chips to reduce the thickness of the packaging structure, and reducing costs. In addition, the first front electronic component does not need to be ground in advance, and there is no need to worry about molding problems during the packaging of the first front electronic component, which is conducive to improving the yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1A schematic diagram of a packaging structure in which a first plastic packaging layer covers a first front electronic component provided by an embodiment of the utility model.
[0015] Figure 2 A schematic diagram of a packaging structure in which a first plastic packaging layer exposes a first front electronic component plastic packaging body provided by an embodiment of the utility model.
[0016] Figure 3 A schematic diagram of a packaging structure in which a first plastic packaging layer exposes a first front electronic component chip body provided by an embodiment of the utility model.
[0017] Figure 4 A schematic diagram of a packaging structure in which a first front electronic component is installed in a front groove of a substrate provided in an embodiment of the utility model.
[0018] Figure 5 A schematic diagram of a packaging structure in which a substrate has a plurality of front grooves on its front side provided by an embodiment of the utility model.
[0019] Figure 6 A schematic diagram of a packaging structure in which a first plastic packaging layer has an electromagnetic shielding layer on its surface provided by an embodiment of the utility model.
[0020] Figure 7 A flowchart of a method for manufacturing a packaging structure provided in one embodiment of the present application.
[0021] Figures 8 to 16 A schematic diagram of a packaging process of a packaging structure provided in one embodiment of the utility model.
[0022] Explanation of the reference numerals: 10-substrate; 101-conductive structure; 102-dielectric layer; 103-first front groove; 104-second front groove; 21-first front electronic component; 211-chip body; 212-plastic package; 213-rewiring layer; 214-solder pad; 22-second front electronic component; 23-third front electronic component; 24-fourth front electronic component; 30-first plastic package layer; 41-back electronic component; 42-solder ball; 50-second plastic package layer; 61-conductive column; 62-electromagnetic shielding layer. DETAILED DESCRIPTION
[0023] In order to use chip-scale packaged electronic components on the front side of a substrate in a double-sided package while maintaining a relatively small height of the package structure, thereby reducing costs and improving yield, the present application provides a package structure.
[0024] The packaging structure and its manufacturing method proposed in this application are further described in detail below in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the utility model will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.
[0025] refer to Figures 1 to 6 As shown, the packaging structure provided by the present application includes a substrate 10, a first front electronic component 21 and a first plastic encapsulation layer 30. The substrate 10 has a front and a back side opposite to each other. The first front electronic component 21 is mounted on the front side of the substrate 10, and the first front electronic component 21 includes a chip body 211 and a plastic encapsulation body 212 that encapsulates the chip body 211. The front side of the first front electronic component 21 faces the substrate 10 and the back side of the first front electronic component 10 faces away from the substrate 10. The first plastic encapsulation layer 30 is formed on the front side of the substrate 10, encapsulating the side wall of the first front electronic component 21; wherein the first plastic encapsulation layer 30 covers the back side of the first front electronic component 21 and the spacing between the surface of the first plastic encapsulation layer 30 away from the substrate 10 and the back side of the first front electronic component 21 is less than 50 μm, or the surface of the first plastic encapsulation layer 30 away from the substrate 10 is flush with the back side of the first front electronic component 21, so that the electronic components of chip-level packaging can be used on the front side of the substrate in the double-sided packaging and the packaging structure can also maintain a small height.
[0026] Specifically, the substrate 10 may be a printed circuit board, but is not limited thereto. Figure 1 As shown, the substrate 10 may include a conductive structure 101 and a dielectric layer 102 . The conductive structure 101 may include a plurality of interconnected circuit layers isolated by the dielectric layer 102 . The conductive structure 101 also includes a pad exposed from the dielectric layer 102 .
[0027] refer to Figures 1 to 6 As shown, the first front electronic component 21 is mounted on the front of the substrate 10, with the front of the first front electronic component 21 facing the substrate 10 and the back of the first front electronic component 21 facing away from the substrate 10. The first front electronic component 21 may be the thickest electronic component on the front of the substrate 10.
[0028] In some embodiments of the present application, the first front electronic component 21 is a filter chip of chip-scale packaging. In other embodiments, the first front electronic component 21 can be other devices of chip-scale packaging.
[0029] Exemplary, reference Figure 1 As shown, the first front electronic component 21 includes a chip body 211 and a plastic package 212 that wraps the chip body 211. The material of the plastic package 212 includes but is not limited to epoxy molding compound (EMC).
[0030] The first front electronic component 21 may further include a rewiring layer 213 and a pad 214, wherein the rewiring layer 213 is located on the front side of the chip body 211 and is electrically connected to the chip body 211, and a portion of the rewiring layer 213 may extend onto the plastic package 212, and the pad 214 is located on the rewiring layer 213. The pad 214 of the first front electronic component 21 may be soldered to the front side of the substrate 10.
[0031] refer to Figures 1 to 6 As shown, a first plastic encapsulation layer 30 is formed on the front side of the substrate 10, and the first plastic encapsulation layer 30 wraps the side wall of the first front electronic component 21. The material of the first plastic encapsulation layer 30 includes but is not limited to epoxy molding compound.
[0032] In one embodiment, reference Figure 1 As shown, the first plastic encapsulation layer 30 can cover the back side of the first front electronic component 21, and the spacing H between the surface of the first plastic encapsulation layer 30 away from the substrate 10 and the back side of the first front electronic component 21 can be less than 50 μm, so that the packaging structure of the double-sided package can maintain a small thickness while using chip-scale packaged electronic components. Exemplarily, the spacing H between the surface of the first plastic encapsulation layer 30 away from the substrate 10 and the back side of the first front electronic component can be less than or equal to 10 μm.
[0033] In one embodiment, if Figure 2 As shown, the plastic package 212 of the first front electronic component 21 covers the side wall of the chip body 211 and the surface of the chip body 211 away from the substrate 10. At this time, the surface of the plastic package 212 away from the substrate is the back of the first front electronic component 21. The surface of the plastic package 212 away from the substrate is flush with the surface of the first plastic package layer 30 away from the substrate. In this way, the thickness of the first plastic package layer 30 is small, thereby reducing the thickness of the packaging structure. It should be noted that in this application, "flush" can refer to the height difference between the two surfaces being within a very small range, for example, the very small range can be a range within which the process error can be controlled.
[0034] In one embodiment, if Figure 3 As shown, the plastic packaging body 212 of the first front electronic component 21 can cover the side wall of the chip body 211 and expose the surface of the chip body 211 away from the substrate. At this time, the back side of the first front electronic component 21 includes the surface of the chip body 211 away from the substrate and the surface of the plastic packaging body 212 away from the substrate. The surface of the first plastic packaging layer 30 away from the substrate is flush with the surface of the first front electronic component chip body 211 away from the substrate. In this way, the thickness of the first front electronic component 21 and the first plastic packaging layer 30 are both relatively small, which is beneficial to reducing the thickness of the packaging structure.
[0035] In one embodiment, if Figure 4As shown, the front side of the substrate 10 may be provided with a first front side groove 103, and the first front side electronic component 21 may be installed in the first front side groove 103, so that the height of the first front side electronic component 21 on the front side of the substrate can be reduced, and the thickness of the first plastic sealing layer 30 can be further reduced to further reduce the thickness of the packaging structure. It should be noted that when the first front side electronic component 21 is provided in the first front side groove 103, the first plastic sealing layer 30 may cover the first front side electronic component 21, or the surface of the first plastic sealing layer 30 away from the substrate may be flush with the back side of the first front side electronic component 21.
[0036] refer to Figures 1 to 6 As shown, a plurality of front electronic components may be mounted on the front of the substrate 10. Exemplarily, the plurality of front electronic components may include a first front electronic component 21, a second front electronic component 22, a third front electronic component 23, and a fourth front electronic component 24, wherein the first front electronic component 21 may be the front electronic component with the largest thickness, and the first plastic encapsulation layer 30 may cover the second front electronic component 22, the third front electronic component 23, and the fourth front electronic component 24. The second front electronic component 22 may be a wire-bonding type chip, the back of the second front electronic component 22 may be pasted on the front of the substrate 10, and the front may be electrically connected to the substrate 10 through a metal wire. The third front electronic component 23 may be a flip chip. The fourth front electronic component 24 may be a passive device, and the passive device includes but is not limited to a capacitor, an inductor, or a resistor.
[0037] Since the metal wires need to be at a certain height, in order to prevent the wire-bonded chip from affecting the overall thickness of the package structure, in one embodiment, Figure 5 As shown, the front side of the substrate 10 may be provided with a second front side groove 104, and the second front side electronic component 22 may be installed in the second front side groove 104, so that the second front side electronic component 22 with a larger thickness may be installed on the front side of the substrate 10 and the packaging structure may maintain a smaller thickness, without adding an additional packaging process, and the length of the metal wire may also be reduced.
[0038] like Figures 1 to 6 As shown, the packaging structure may further include a back electronic component 41, which may be mounted on the back of the substrate 10. A solder ball 42 may also be mounted on the back of the substrate 10, and the height of the solder ball 42 in the direction away from the back of the substrate is greater than the height of the back electronic component 41 in the direction away from the back of the substrate. The back electronic component 41 may be a chip or a passive device. The material of the solder ball 42 includes, but is not limited to, tin.
[0039] like Figures 1 to 6As shown, the packaging structure may further include a second plastic packaging layer 50, which is located on the back side of the substrate 10 and at least wraps the side wall of the back electronic component 41, and the solder ball 42 protrudes out of the second plastic packaging layer 50 away from the surface of the substrate.
[0040] In some embodiments, Figures 1 to 6 As shown, the second plastic encapsulation layer 50 covers the sidewalls of the back electronic component 41 and exposes the surface of the back electronic component 41 away from the substrate, so that the thickness of the second plastic encapsulation layer 50 can be reduced, and the overall thickness of the packaging structure can be reduced. In some embodiments, the second plastic encapsulation layer 50 can cover the sidewalls of the back electronic component 41 and the surface away from the substrate.
[0041] In some embodiments, a plurality of back electronic components 41 may be installed on the back side of the substrate 10. A back groove may be provided on the back side of the substrate 10, and at least a portion of the back electronic components 41 may be installed in the back groove. For example, if the back electronic components 41 with a larger thickness are installed in the back groove, the thickness of the second plastic encapsulation layer 50 may be further reduced, thereby reducing the overall thickness of the packaging structure.
[0042] In some embodiments, reference Figure 6 As shown, an electromagnetic shielding layer 62 can be set on the surface of the first plastic sealing layer 30, and the electromagnetic shielding layer 62 can cover the surface of the first plastic sealing layer 30 away from the substrate, the side wall of the first plastic sealing layer 30, the side wall of the substrate 10 and the side wall of the second plastic sealing layer 50. A plurality of conductive pillars 61 can be set on the front side of the substrate 10, and the plurality of conductive pillars 61 can be arranged in rows and columns on the front side of the substrate 10. One end of the conductive pillar 61 is electrically connected to the substrate 10, and the other end of the conductive pillar 61 is electrically connected to the electromagnetic shielding layer 62. In this way, the plurality of front electronic components on the front side of the substrate 10 can be shielded by cavity, thereby improving the performance of the packaging structure.
[0043] The packaging structure of the present application may be a system in package (SIP) structure. Exemplarily, the packaging structure may be a power amplifier module, but is not limited thereto.
[0044] The present application also provides a method for manufacturing a packaging structure, and the packaging structure mentioned above can be manufactured using the method for manufacturing a packaging structure. Figure 7 Flow chart of a method for manufacturing a packaging structure provided in one embodiment of the present application. Figure 7 As shown, the manufacturing method of the packaging structure includes:
[0045] Step S1, providing a substrate, wherein the substrate has a front side and a back side opposite to each other;
[0046] Step S2, mounting a first front electronic component on the front side of the substrate, wherein the first front electronic component comprises a chip body and a plastic package that wraps the chip body, wherein the front side of the first front electronic component faces the substrate and the back side of the first front electronic component faces away from the substrate;
[0047] Step S3, forming a first plastic encapsulation layer on the front surface of the substrate, wherein the first plastic encapsulation layer covers the first front electronic component; and
[0048] Step S4, removing part of the thickness of the first plastic encapsulation layer so that the distance between the surface of the first plastic encapsulation layer away from the substrate and the back side of the first front electronic component is less than 50 μm, or the surface of the first plastic encapsulation layer away from the substrate is flush with the back side of the first front electronic component.
[0049] Figures 8 to 16 The following is a schematic diagram of the packaging process of the packaging structure provided by an embodiment of the utility model. Figures 1 to 16 The method for manufacturing the packaging structure of the present application is described.
[0050] like Figure 8 As shown, a substrate 10 is provided, and the substrate 10 has opposite front and back surfaces.
[0051] The substrate 10 may be a printed circuit board, but is not limited thereto. Figure 8 As shown, the substrate 10 may include a conductive structure 101 and a dielectric layer 102 . The conductive structure 101 may include a plurality of interconnected circuit layers isolated by the dielectric layer 102 . The conductive structure 101 also includes a pad exposed from the dielectric layer 102 .
[0052] refer to Figure 8 As shown, the front side of the substrate 10 may be provided with a front groove, and the number of the front grooves may be single or multiple, for example, a first front groove 103 and a second front groove 104. The back side of the substrate 10 may also be provided with a back groove.
[0053] like Fig. 9 As shown, the first front electronic component 21 is mounted on the front of the substrate 10, the first front electronic component 21 includes a chip body 211 and a plastic package 212 that wraps the chip body 211, the front of the first front electronic component 21 faces the substrate 10 and the back of the first front electronic component 21 faces away from the substrate 10. In this step, the plastic package 212 can cover the surface of the chip body 211 away from the substrate, that is, there is no need to grind the plastic package 212 in the first electronic component 21 in advance.
[0054] The first front electronic component 21 may further include a rewiring layer 213 and a pad 214, wherein the rewiring layer 213 is located on the front side of the chip body 211 and is electrically connected to the chip body 211, and the pad 214 is located on the rewiring layer 213. The pad 214 of the first front electronic component 21 may be soldered to the front side of the substrate 10.
[0055] Exemplarily, the first front electronic component 21 may be a filter chip in a chip-scale package. In other embodiments, the first front electronic component 21 may be other devices in a chip-scale package.
[0056] refer to Fig. 9 As shown, the second front electronic component 22, the third front electronic component 23 and the fourth front electronic component 24 can also be mounted on the front side of the substrate 10. The first front electronic component 21 can be the front electronic component with the largest thickness; the second front electronic component 22 can be a wire-bonded chip, and the back side of the second front electronic component 22 can be pasted on the front side of the substrate 10. After the second front electronic component 22 is mounted, a wire bonding process is performed so that the front side of the second front electronic component 22 is electrically connected to the substrate 10 through a metal wire; the third front electronic component 23 can be a flip chip; the fourth front electronic component 24 can be a passive device, and the passive device includes but is not limited to a capacitor, an inductor or a resistor.
[0057] It should be noted that, in the case where the front side of the substrate 10 has a front side groove, the corresponding front side electronic components can be installed in the corresponding front side groove. Fig. 9 As shown, the first front electronic component 21 can be installed in the first front groove 103 , and the second front electronic component 22 can be installed in the second front groove 104 .
[0058] refer to Fig. 9 As shown, a conductive column 61 may be further provided on the front surface of the substrate 10, one end of the conductive column 61 being electrically connected to the substrate 10, and the height of the conductive column 61 may be greater than the height of the first front electronic component 21. The number of the conductive columns 61 may be multiple, and the multiple conductive columns 61 may be arranged in rows and columns on the front surface of the substrate 10.
[0059] refer to Fig.10 As shown, after the front electronic components are installed, a first plastic encapsulation layer 30 is formed on the front side of the substrate 10 , and the first plastic encapsulation layer 30 covers the first front electronic component 21 , the second front electronic component 22 , the third front electronic component 23 , the fourth front electronic component 24 and the conductive column 61 .
[0060] like Fig.11As shown, part of the thickness of the first plastic encapsulation layer 30 is removed, so that the distance between the surface of the first plastic encapsulation layer 30 away from the substrate 10 and the back of the first front electronic component 21 is less than 50 μm. Exemplarily, the distance between the surface of the first plastic encapsulation layer 30 away from the substrate 10 and the back of the first front electronic component 21 can be less than or equal to 10 μm.
[0061] For example, a portion of the thickness of the first plastic encapsulation layer 30 may be removed by a process such as grinding.
[0062] like Fig.12 and Fig.13 As shown, the first plastic encapsulation layer 30 may be further ground so that the surface of the first plastic encapsulation layer 30 away from the substrate is flush with the back surface of the first front electronic component 21 .
[0063] Specifically, in one embodiment, Fig.12 As shown, part of the first plastic packaging layer 30 may be removed until the plastic packaging body 212 of the first front electronic component 30 is exposed.
[0064] In one embodiment, after the plastic package 212 of the first front electronic component 30 is exposed, Fig.13 As shown, part of the first plastic packaging layer 30 and part of the plastic packaging body 212 may be further removed by grinding until the chip body 211 of the first front electronic component 21 is exposed.
[0065] In the process of grinding the first plastic encapsulation layer 30 until the chip body 211 of the first front electronic component 21 is exposed, rough grinding can be performed first and then fine grinding can be performed, so as to avoid damage to the chip body 211 during the grinding process. In other embodiments, grinding can also be performed once to the surface of the chip body 211 of the first front electronic component.
[0066] It should be noted that, in the process of grinding the first plastic packaging layer 30 , a portion of the height of the conductive pillar 61 can be simultaneously ground away.
[0067] refer to Fig.13 As shown, after the first plastic packaging layer 30 is ground to a set position, a back electronic component 41 can be installed on the back side of the substrate 10 , and a solder ball 42 can be set on the back side of the substrate 10 .
[0068] For example, there may be more than one back electronic component 41, and a back groove may be provided on the back of the substrate 10, and a thicker back electronic component may be provided in the back groove. The back electronic component 41 may be a chip or a passive device.
[0069] The solder balls 42 protrude from the rear electronic components 41 away from the surface of the substrate in a direction away from the rear surface of the substrate. The material of the solder balls 42 includes, but is not limited to, tin.
[0070] refer to Figures 14 to 16 As shown, a second plastic encapsulation layer 50 is formed on the back side of the substrate 10 , and the second plastic encapsulation layer 50 at least covers the side wall of the back electronic component 41 .
[0071] For example, Fig.14 As shown, the second plastic encapsulation layer 50 covers the rear electronic components 41 and the solder balls 42. The material of the second plastic encapsulation layer 50 may be epoxy molding compound, but is not limited thereto.
[0072] like Fig.15 As shown, a portion of the second plastic encapsulation layer 50 and a portion of the solder balls 42 are removed by grinding, so that the solder balls are exposed on the surface of the second plastic encapsulation layer 50 .
[0073] refer to Fig.15 and 16 As shown, a portion of the second plastic encapsulation layer 50 around the solder ball 42 may be removed by a laser ablation process to increase the exposed area of the solder ball 42 and facilitate the subsequent reshaping of the solder ball 42 .
[0074] Next, refer to Fig.16 As shown, a reflow process is performed to melt the solder ball 42 and reshape it into a spherical shape. It should be noted that in a direction perpendicular to the back side of the substrate and away from the back side of the substrate, the reshaped solder ball 42 still needs to protrude from the surface of the back electronic component 41 away from the back side of the substrate, so that the solder ball 42 can establish an electrical connection with other components.
[0075] refer to Figure 6 As shown, after the second plastic encapsulation layer 50 is formed, an electromagnetic shielding layer 62 can be formed on the surface of the first plastic encapsulation layer 30. The electromagnetic shielding layer 62 can cover the surface of the first plastic encapsulation layer 30 away from the substrate, the side walls of the first plastic encapsulation layer 30, the side walls of the substrate 10 and the side walls of the second plastic encapsulation layer 50, and the electromagnetic shielding layer 62 is electrically connected to the conductive column 61.
[0076] In the packaging structure and manufacturing method of the present application, a first front electronic component 21 is installed on the front side of the substrate 10, and the first front electronic component 21 includes a chip body 211 and a plastic package body 212 that wraps the chip body 211, that is, the first front electronic component 21 is a chip-level packaged device, the front side of the first front electronic component 21 faces the substrate 10 and the back side of the first front electronic component 21 faces away from the substrate 10, and the first plastic package layer 30 on the front side of the substrate wraps the side wall of the first front electronic component 21, and by removing part of the thickness of the first plastic package layer 30, the distance between the surface of the first plastic package layer 30 away from the substrate and the back side of the first front electronic component is less than 50μm, or the surface of the first plastic package layer 30 away from the substrate is flush with the back side of the first front electronic component 21, so that chip-level packaged electronic components can be used on the front side of the substrate in double-sided packaging and the packaging structure can also maintain a small thickness, avoiding the method of using wafer-level packaged chips to reduce the thickness of the packaging structure, reducing costs, in addition, the first front electronic component does not need to be ground in advance, and there is no need to worry about molding problems during the packaging of the first front electronic component, which is conducive to improving the yield.
[0077] It should be noted that this specification adopts a progressive description method, and the manufacturing method of the packaging structure described later focuses on the differences from the packaging structure described previously, and the same and similar parts between the various parts can be referred to each other.
[0078] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of rights of the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.
Claims
1. A packaging structure, characterized in that: include: a substrate having opposite front and back surfaces; A first front electronic component is mounted on the front side of the substrate, the first front electronic component comprises a chip body and a plastic package that wraps the chip body, the front side of the first front electronic component faces the substrate and the back side of the first front electronic component faces away from the substrate; as well as A first plastic packaging layer is formed on the front surface of the substrate and wraps the side wall of the first front electronic component; The first plastic encapsulation layer covers the back side of the first front electronic component, and the distance between the surface of the first plastic encapsulation layer away from the substrate and the back side of the first front electronic component is less than 50 μm; or, the surface of the first plastic encapsulation layer away from the substrate is flush with the back side of the first front electronic component.
2. The packaging structure according to claim 1, characterized in that: In the first front electronic component, the plastic packaging body covers the side walls of the chip body and the surface of the chip body away from the substrate; the surface of the plastic packaging body away from the substrate is flush with the surface of the first plastic packaging layer away from the substrate.
3. The packaging structure according to claim 1, characterized in that: In the first front electronic component, the plastic encapsulation body covers the side walls of the chip body and exposes the surface of the chip body away from the substrate; the surface of the first plastic encapsulation layer away from the substrate is flush with the surface of the first front electronic component chip body away from the substrate.
4. The packaging structure according to claim 1, characterized in that: The first front electronic component further includes a rewiring layer and a pad. The rewiring layer is located on the front side of the chip body and is electrically connected to the chip body. The pad is located on the rewiring layer.
5. The packaging structure according to claim 1, characterized in that: The first front electronic component is a filter chip in chip-scale packaging.
6. The packaging structure according to claim 1, characterized in that: A first front groove is arranged on the front side of the substrate, and the first front electronic component is installed in the first front groove.
7. The packaging structure according to claim 1, characterized in that: A second front electronic component of a wire bonding type is installed on the front side of the substrate, a second front groove is provided on the front side of the substrate, and the second front electronic component is installed in the second front groove.
8. The packaging structure according to claim 1, characterized in that: It also includes a back electronic component and a second plastic packaging layer. The back electronic component is mounted on the back side of the substrate. The second plastic packaging layer is located on the back side of the substrate and at least wraps the side wall of the back electronic component.
9. The packaging structure according to claim 8, characterized in that: A back groove is arranged on the back side of the substrate, and at least a part of the back electronic components are installed in the back groove.