Fan-out wafer-level packaging unit wire bonding module on electronic components

Abstract

The utility model discloses a module in which a fan-out type wafer-level packaging unit is wire-bonded on an electronic component, comprising a fan-out type wafer-level packaging unit, an electronic component, at least one first welding wire and at least two second welding wires. The fan-out type wafer-level packaging unit comprises a carrier, at least two bare crystals, a first dielectric layer, a second dielectric layer, a plurality of conducting lines, an outer protective layer and a plurality of welding pads; wherein each conducting line is formed by metal paste filled in a plurality of first grooves of the first dielectric layer and a plurality of second grooves of the second dielectric layer, and at least one welding pad is located around a chip area on the second surface of each bare crystal for external electrical connection, so as to solve the problem that the fan-out type packaging technology in the existing module with the fan-out type wafer-level packaging unit is easy to generate a higher manufacturing cost and is not conducive to environmental protection when making each conducting line.

Description

Technical Field

[0001] The utility model relates to a module, in particular to a module in which a fan-out type wafer-level packaging unit is wire-bonded on an electronic component. Background Art

[0002] Lightweight, thin, short, high-efficiency and high-reliability packaging technology is the development trend of the semiconductor industry, among which Fan-Out Wafer Level Packaging (FOWLP) is already an existing packaging technology.

[0003] In the advanced packaging FOWLP, the redistribution layer (RDL) is the most critical, because each conductive line in the RDL can make multiple pads on the die produce XY plane electrical extension and interconnection, so that multiple more dispersed pads can be formed around each die, which can effectively improve the design space and reliability of each conductive line. However, how to make each conductive line in the RDL maintain or achieve a certain degree of lightness, thinness and shortness while producing XY plane electrical extension and interconnection is the most critical. However, the forming method of each conductive line in the RDL technology used in the existing FOWLP packaging technology is to use chemical plating forming technology or electroplating forming technology to make it. In addition to the relatively high material cost and production cost, the process in the existing technology does not meet or is not conducive to environmental protection requirements. Moreover, when FOWLP is used to provide products with higher performance or more functions, at least two bare chips are generally set up in FOWLP and integrated through RDL to form a multi-chip fan-out wafer-level packaging unit. At this time, the demand for design space for each conductive line of the RDL in FOWLP will increase relatively, and the manufacturing technology of each conductive line in the RDL will also be relatively critical.

[0004] In addition, when FOWLP is used to produce module products, it is generally integrated into FOWLP through RDL to form a fan-out wafer-level packaging unit, and then the fan-out wafer-level packaging unit is combined with electronic components to form a module. At this time, the material cost and production cost of the product will increase relatively, and the production technology of each conductive line in RDL will also be relatively more critical. Utility Model Content

[0005] The main purpose of the utility model is to provide a module in which a fan-out wafer-level packaging unit is wire-bonded on an electronic component, comprising a fan-out wafer-level packaging unit, an electronic component, at least one first welding wire and at least two second welding wires, wherein the fan-out wafer-level packaging unit comprises a carrier, at least two bare crystals, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, an outer protective layer and a plurality of welding pads; wherein each conductive line is formed by metal paste filled in a plurality of first grooves of the first dielectric layer and a plurality of second grooves of the second dielectric layer, and at least one of the welding pads is located around a chip area on the second surface of each bare crystal for external electrical connection, thereby effectively solving the problem that the fan-out packaging technology in the existing module is prone to generate higher manufacturing costs and is not environmentally friendly when making each conductive line.

[0006] To achieve the above-mentioned purpose, the utility model provides a module in which a fan-out wafer-level packaging unit is wire-bonded on an electronic component, the module comprising a carrier, at least two bare dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, an outer protective layer, a plurality of solder pads, an electronic component, at least one first solder wire and at least two second solder wires; wherein the carrier has a first surface and an opposite second surface; wherein each of the bare dies is split from the same wafer or different wafers, and each of the bare dies is parallel and spaced apart and The die are arranged on the second surface of the carrier, each of the die has a first surface and an opposite second surface, the first surface of each of the die is fixed on the carrier, the second surface of each of the die has a plurality of crystal pads, and the vertical chip area of ​​the second surface is defined as a chip area; wherein the first dielectric layer is arranged on the second surface of the carrier and the second surface of each of the die, the first dielectric layer has a plurality of first grooves extending in a horizontal direction; wherein each of the crystal pads of each of the die is exposed to the outside by the plurality of the first grooves; wherein the second dielectric layer is arranged On the first dielectric layer, the second dielectric layer has a plurality of second grooves extending in a horizontal direction, and the plurality of second grooves are connected to the plurality of first grooves; wherein each of the conductive lines is formed by a metal paste filled in the plurality of first grooves and the plurality of second grooves, and each of the conductive lines is electrically connected to each of the die pads of each die; wherein the outer protective layer is disposed on the second dielectric layer, and the outer protective layer has a plurality of openings, and at least two of the openings are located around the chip area on the second surface of each die, wherein each of the conductive lines is electrically connected to each of the die pads of each die. The connection lines are exposed to the outside by the plurality of the openings; each of the bonding pads is a metal structure having a certain thickness formed in the plurality of the openings of the outer protective layer, and is electrically connected to each of the conductive lines, wherein each of the bare crystals can be electrically connected to the outside via the crystal pads, the conductive lines and the bonding pads around the chip area on the second surface of the bare crystal in sequence, thereby forming a fan-out type wafer-level packaging unit; wherein the electronic component has a first surface for the first surface of the carrier to be set on; wherein each of the first bonding wires is connected by a wire bonding (Wire A first bonding point and a second bonding point are formed on each bonding pad in each bare die respectively, so that each bare die of the fan-out wafer-level packaging unit is electrically connected; wherein each second bonding wire is formed on each bonding pad around the chip area and a fourth bonding point is formed on the first surface of the electronic component through the wire bonding operation, so that each bare die of the fan-out wafer-level packaging unit is electrically connected to the printed circuit board; wherein each first bonding wire and each second bonding wire are formed together through the wire bonding operation at the same time.

[0007] In a preferred embodiment of the present invention, the electronic component is a printed circuit board (PCB).

[0008] In a preferred embodiment of the present invention, the surface of each of the welding pads is flush with the surface of the outer protective layer.

[0009] In a preferred embodiment of the present invention, each of the bare dies is formed by being divided from the same wafer or different wafers.

[0010] In a preferred embodiment of the present invention, the horizontal heights of the second surfaces of each of the bare die on the carrier are the same.

[0011] In a preferred embodiment of the present invention, the carrier includes a silicon carrier, a glass carrier or a ceramic carrier.

[0012] In a preferred embodiment of the present invention, the metal paste includes silver paste, nano silver paste, copper paste or nano copper paste.

[0013] In a preferred embodiment of the present invention, the first surface of each of the bare chips is further disposed on the carrier by using a die attach film (DAF). BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a side cross-sectional schematic diagram of the module of the utility model.

[0015] Figure 2 It is a side cross-sectional schematic diagram of a bare die of the utility model being arranged on a carrier board.

[0016] Figure 3 It is a side cross-sectional schematic diagram of the utility model in which the first dielectric layer is arranged on the second surface of the carrier and the bare die.

[0017] Figure 4 It is a side cross-sectional schematic diagram of the second dielectric layer of the utility model arranged on the first dielectric layer.

[0018] Figure 5 It is a side cross-sectional schematic diagram of the first groove and the second groove of the utility model filled with metal paste.

[0019] Figure 6 yes Figure 5 A side cross-sectional schematic diagram of grinding the metal paste above the surface of the second dielectric layer.

[0020] Figure 7 It is a side view cross-sectional schematic diagram of the utility model in which a plurality of openings are formed on the outer protective layer.

[0021] Figure 8It is a side cross-sectional schematic diagram of the fan-out wafer-level packaging unit of the utility model.

[0022] Explanation of the reference numerals: 1-module; 1a-fan-out wafer-level packaging unit; 10-carrier; 10a-chip area; 11-first side; 12-second side; 20-bare crystal; 20a-first chip; 20b-second chip; 21-first side; 22-second side; 23-crystal pad; 30-first dielectric layer; 31-first groove; 40-second dielectric layer; 41-second groove; 50-conducting line; 50a-metal paste; 60-outer protective layer; 61-opening; 70-soldering pad; 80-electronic component; 81-first side; 90-first welding wire; 91-first welding point; 92-second welding point; 100-second welding wire; 101-third welding point; 102-fourth welding point; 110-chip bonding film. DETAILED DESCRIPTION

[0023] With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each element in each illustration is not drawn according to the actual scale and is not used to limit the present invention.

[0024] refer to Figure 1 The utility model provides a module 1 for wire bonding a fan-out wafer-level packaging unit on an electronic component. The module 1 includes a fan-out wafer-level packaging unit 1a, an electronic component 80, at least one first bonding wire 90 and at least two second bonding wires 100.

[0025] refer to Figure 8 The fan-out wafer-level packaging unit 1a includes a carrier 10, at least two bare chips (dies) 20, a first dielectric layer 30, a second dielectric layer 40, a plurality of conductive lines 50, an outer protective layer 60 and a plurality of pads 70.

[0026] The carrier board 10 has a first surface 11 and an opposite second surface 12. Figure 2 As shown, the carrier 10 includes a silicon (Si) carrier, a glass carrier or a ceramic carrier, but is not limited thereto, so as to facilitate diversified product development and application.

[0027] Each bare die 20 is separated from the same wafer or different wafers. Each bare die 20 is arranged parallel and spaced apart on the second surface 12 of the carrier 10. Figure 2 As shown, each bare die 20 has a first surface 21 and an opposite second surface 22. The first surface 21 of each bare die 20 is fixed on the carrier 10. The second surface 22 of each bare die has a plurality of pads 23, and the vertical chip area of ​​the second surface 22 is defined as a chip area 10a. Figure 2 As shown. Figure 2 The wafer pads 23 of each bare die 20 are described by taking two wafer pads 23 as an example, but the present invention is not limited thereto.

[0028] In addition, in order to illustrate the structural relationship and related functions of the utility model, Figures 1 to 8 In the illustrated embodiment, each bare die 20 on the carrier 10 further includes a first bare die 20 a and a second bare die 20 b , but this is not limiting. That is, two bare die 20 are used as an example for explanation, but this is not intended to limit the present invention.

[0029] The first dielectric layer 30 is disposed on the second surface 12 of the carrier 10 and the second surface 22 of each die 20 (the first die 20a and the second die 20b). The first dielectric layer 30 has a plurality of first grooves 31 extending in a horizontal direction. Figure 3 wherein each of the die pads 23 of each die 20 (the first die 20a and the second die 20b) is exposed to the outside by each first groove 31, such as Figure 3 shown.

[0030] The second dielectric layer 40 is disposed on the first dielectric layer 40. The second dielectric layer 40 has a plurality of second grooves 41 extending in a horizontal direction. Each second groove 41 is connected to each first groove 31. Figure 4 shown.

[0031] Each conductive circuit 50 is formed by a metal paste 50a filled in each first groove 31 and each second groove 41. Each conductive circuit 50 is electrically connected to each die pad 23 of each bare die 20 (the first bare die 20a and the second bare die 20b). Figure 6 As shown; wherein the metal paste 50a includes silver paste, nano silver paste, copper paste or nano copper paste, but is not limited. The nano silver paste material has the characteristics of low cost, high conductivity and low temperature sintering, but since the nano silver paste material is a common material, it is not described here.

[0032] The outer protective layer 60 is disposed on the second dielectric layer 40, and the outer protective layer 60 has a plurality of openings 61, and at least two of the openings 61 are located around the chip region 10a on the second surface 22 of each die 20 (the first die 20a and the second die 20b). Figure 7 wherein each conducting circuit 50 is exposed to the outside by each opening 61, such as Figure 7 As shown. Figure 7 The openings 61 of the outer protective layer 60 are described by taking four openings 61 as an example, but this is not intended to limit the present invention.

[0033] Each soldering pad 70 is a metal structure having a certain thickness formed in each opening 61 of the outer protective layer 60 and is electrically connected to each conductive circuit 50. Figure 8 As shown; wherein each bare die 20 (the first bare die 20a and the second bare die 20b) can be electrically connected to the outside via each die pad 23, each conductive circuit 50 and each pad 70 located around the chip area 10a on the second surface 22 of each bare die 20 (the first bare die 20a and the second bare die 20b) in sequence, so as to form the fan-out wafer-level packaging unit 1a, as shown Figure 8 shown.

[0034] The electronic component 80 has a first surface 81 on which the first surface 11 of the carrier 10 of the fan-out wafer-level packaging unit 1a is disposed. Figure 1 As shown; wherein the electronic component 80 is a printed circuit board (PCB, Printed circuitboard), but not limited.

[0035] Each first bonding wire 90 is subjected to a wire bonding operation to form a first solder joint 91 and a second solder joint 92 on each bonding pad 70 in each bare die 20 (the first bare die 20a and the second bare die 20b), so that each bare die 20 (the first bare die 20a and the second bare die 20b) of the fan-out wafer-level packaging unit 1a is electrically connected, such as Figure 1 shown.

[0036] In addition, in order to illustrate the structural relationship and related functions of the utility model, Figure 1 In the illustrated embodiment, the solder joint on the first bare crystal 20a is the first solder joint 91 but is not limited, and the solder joint on the second bare crystal 20b is the second solder joint 92 but is not limited, that is, each first solder wire 90 is illustrated by taking one as an example, but is not used to limit the present invention, and each first solder wire 90 is further wire-bonded on two adjacent solder pads 70 in each bare crystal 20 (the first bare crystal 20a and the second bare crystal 20b), but is not limited, so as to complete the electrical connection between the solder pads within the shortest distance between the bare crystals, in addition to saving the manufacturing cost, it can also avoid the cross-line state in the package. The cross-line state refers to that any solder wire spanning between any solder pad and its corresponding solder pad will span in the upper space on other solder pads, so that the signals between each solder pad and each solder wire interfere with each other, which is a common shortcoming in the existing package, so it will not be repeated here.

[0037] Each second bonding wire 100 is bonded to form a third bonding point 101 on each bonding pad 70 around the chip area 10a and a fourth bonding point 102 on the first surface 81 of the electronic component 80 through the bonding operation, so that each bare die 20 (the first bare die 20a and the second bare die 20b) of the fan-out wafer-level packaging unit 1a is electrically connected to the printed circuit board 70, such as Figure 1 shown.

[0038] In addition, in order to illustrate the structural relationship and related functions of the utility model, Figure 1 In the illustrated embodiment, the solder joints on each solder pad 70 around the chip region 10a of the first bare crystal 20a are the third solder joints 101 but are not limited, and the solder joints on each solder pad 70 around the chip region 10a of the second bare crystal 20b are the third solder joints 101 but are not limited, and the solder joints on the first surface 81 of the electronic component 80 adjacent to the chip region 10a of the first bare crystal 20a are the fourth solder joints 102 but are not limited, and the solder joints on the first surface 81 of the electronic component 80 adjacent to the chip region 10a of the second bare crystal 20b are the fourth solder joints 102 but are not limited, that is, each second solder wire 100 is illustrated by taking two as an example, but is not intended to limit the present invention.

[0039] refer to Figure 1 , each first welding wire 90 and each second welding wire 100 are formed together through the wire bonding operation at the same time, so as to simplify the process.

[0040] The manufacturing process of the module 1 may include the following steps, but is not limited thereto:

[0041] Step S1: Provide a carrier board 10, such as Figure 2 wherein the carrier 10 has a first surface 11 and an opposite second surface 12, such as Figure 2 shown.

[0042] Step S2: multiple dies 20 separated from the same wafer or different wafers are arranged parallely and spaced apart on the second surface 12 of the carrier 10, such as Figure 2 As shown; wherein each bare crystal 20 has a first surface 21 and an opposite second surface 22, the first surface 21 of each bare crystal 20 is disposed on the carrier 10, the second surface 22 of each bare crystal 20 has a plurality of crystal pads 23, and the vertical chip area of ​​the second surface 22 of each bare crystal 20 is defined as a chip area 10a, such as Figure 2 shown.

[0043] Step S3: Lay a first dielectric layer 30 on the carrier 10 and the second surface 22 of each bare die 20. Figure 3shown.

[0044] Step S4: forming a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, and allowing each die pad 23 of each bare die 20 to be exposed to the outside through each first groove 31. Figure 3 shown.

[0045] Step S5: Lay a second dielectric layer 40 on the first dielectric layer 30. Figure 4 shown.

[0046] Step S6: forming a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, and making each second groove 41 communicate with each first groove 31, such as Figure 4 shown.

[0047] Step S7: Filling a metal paste 50a into each of the first grooves 31 and each of the second grooves 41, and making the thickness of the metal paste 50a higher than the surface of the second dielectric layer 40, such as Figure 5 shown.

[0048] Step S8: Grind the metal paste 50a above the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of conductive circuits 50, such as Figure 6 shown.

[0049] Step S9: Lay an outer protective layer 60 on the second dielectric layer 40, such as Figure 7 shown.

[0050] Step S10: forming a plurality of openings 61 on the outer protective layer 60 and forming at least one of the openings 61 around the chip region 10a on the second surface 22 of each bare die 20, so that each conductive circuit 50 can be exposed to the outside through each opening 61. Figure 7 shown.

[0051] Step S11: forming a welding pad 70 in each opening 61 of the outer protective layer 60, such as Figure 8 As shown; wherein each pad 70 is a metal structure having a certain thickness, such as Figure 8 wherein each pad 70 is electrically connected to each conductive circuit 50, such as Figure 8 shown.

[0052] Step S12: Perform a segmentation operation to form a plurality of fan-out wafer-level packaging units 1a. Figure 8 As shown; wherein each fan-out wafer-level packaging unit 1a has at least two of the bare die 20, such as Figure 8 shown.

[0053] Step S13: providing an electronic component 80 having a first surface 81, and disposing the first surface 11 of the carrier 10 of the fan-out wafer-level packaging unit 1a on the first surface of the electronic component 80, such as Figure 1 shown.

[0054] Step S14: Perform a wire bonding operation to form a first solder joint 91 and a second solder joint 92 on each solder pad 70 in each bare die 20 of the fan-out wafer-level packaging unit 1a, and at least two second solder joints 100 form a third solder joint 101 on each solder pad 70 around the chip region 10a of the fan-out wafer-level packaging unit 1a, and a fourth solder joint 102 on the electronic component 80, respectively. Figure 1 wherein each bare die 20 within the fan-out wafer-level packaging unit 1a on the electronic component 80 is electrically connected through each first bonding wire 90, such as Figure 1 wherein each bare die 20 in the fan-out wafer-level packaging unit 1a on the electronic component 80 is electrically connected to the electronic component 80 through each second bonding wire 100 to form a module 1, such as Figure 1 shown.

[0055] In the manufacturing process of the module 1, the process corresponding to step S3 to step S10 can be regarded as the key step of making the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1a, wherein step S4 is to form a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, step S6 is to form a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, step S7 is to fill a metal paste 50a into each of the first grooves 31 and each of the second grooves 41, step S8 is to grind the metal paste 50a above the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of Since steps S4 to S8 are processes that are easy to implement accurately, the process is relatively simplified, which is sufficient to enable each conductive line 50 in the redistribution layer to generate XY plane electrical extension and interconnection, while also enabling the completed fan-out wafer-level packaging unit 1a to still maintain or achieve a certain degree of lightness, thinness and shortness, and when there are at least two bare chips 20 in the fan-out wafer-level packaging unit 1a, it still maintains or achieves a certain degree of lightness, thinness and shortness.

[0056] refer to Figure 1The surface of each welding pad 70 is flush with the surface of the outer protective layer 60 but is not restricted, so that the wire bonding operation can be easily performed on the surface of each welding pad 70 to enhance the reliability of the product. In addition, each welding pad 70 can withstand the positive pressure generated during the wire bonding operation or the formation of the welding point, so that the internal circuit will not be damaged by the positive pressure, and the internal circuit (such as each conductive circuit 50) can be allowed to pass through or be arranged under each welding pad 70.

[0057] refer to Figure 2 When each bare die 20 is formed by being divided from the same wafer, each bare die 20 has the same specification, performance or intended function but is not limited thereto.

[0058] refer to Figure 2 When each bare die 20 is formed by being divided from different wafers, it is beneficial to increase the diversified application of the product. Each bare die 20 can be a bare die with different specifications, performance or intended functions, but is not limited to it. Figure 2 The first bare die 20a is smaller in size than the second bare die 20b.

[0059] refer to Figure 2 The horizontal heights of the second surfaces 22 of the bare crystals 20 on the carrier 10 are the same, but not limited, so that the first grooves 31 of the first dielectric layer 30 and the second grooves 41 of the second dielectric layer 40 formed by the RDL technology can be extended and formed smoothly, which helps the subsequent structures stacked on the bare crystals 20 to maintain better structural flatness to increase the reliability of the product.

[0060] refer to Figure 2 The first surface 21 of each bare die 20 may be further disposed on the carrier 10 using a die attach film (DAF, Die Attach Film) 110, but this is not limited.

[0061] Compared with the existing module technology with fan-out wafer-level packaging units, the module 1 of the present invention has the following advantages:

[0062] (1) Compared with the related manufacturing technology of the fan-out wafer-level packaging unit in the existing module, the fan-out wafer-level packaging unit 1a manufactured by steps S3 to S10 in the process of manufacturing the module 1 of the present invention can maintain or achieve a certain degree of lightness, thinness and shortness by manufacturing each conductive line in the RDL so that each conductive line in the RDL can generate XY plane electrical extension and interconnection. These are simplified and easy to implement precisely, which is particularly beneficial to reducing the thickness of the packaging unit. Therefore, the manufacturing process of the present invention is not only relatively simple and cost-saving, but also can effectively improve the use efficiency and reliability of the module 1.

[0063] (2) In the molding process of each conductive line 50 of the fan-out wafer-level packaging unit 1a in the module 1 of the present invention, the metal paste 50a can be first filled into each first groove 31 and each second groove 41, and the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, such as Figure 5 As shown, the metal paste 50a which is higher than the surface of the second dielectric layer 40 is then ground so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form each conductive circuit 50, as shown in FIG. Figure 6 As shown, the manufacturing process of the utility model can effectively solve the problem that the existing fan-out packaging technology is prone to high manufacturing costs and is not environmentally friendly when making each conductive line. From the above, it can be seen that the fan-out wafer-level packaging unit 1a formed by the RDL of the present case is combined with the electronic component 80 to form the module 1, and the material cost and manufacturing cost requirements of the module 1 product will be relatively reduced.

[0064] (3) Each bare die 20 of the fan-out wafer-level packaging unit 1a in the module 1 of the present invention can be electrically connected to the outside via each die pad 23, each conductive line 50 (formed by RDL technology) and each pad 51 located around the chip area 1a on the second surface 22 of each bare die 20 in sequence. That is, each conductive line in the RDL can generate XY plane electrical extension and interconnection while also enabling the multi-chip fan-out wafer-level packaging unit to maintain or achieve a certain degree of light, thin and short integration effect, so as to provide a module product with higher performance (e.g., each bare die 20 is a bare die with the same specification, performance or intended function) or more functions (e.g., each bare die 20 is a bare die with different specifications, performance or intended function), thereby increasing the market competitiveness of the module product.

[0065] The above are only preferred embodiments of the present invention, which are only illustrative rather than restrictive of the present invention. Those skilled in the art will understand that many changes, modifications, and even equivalent changes may be made to the present invention within the spirit and scope defined by the claims of the present invention, but all of these will fall within the scope of protection of the present invention.

Claims

1. A module in which a fan-out wafer-level packaging unit is wire-bonded to an electronic component, characterized in that: Include: A carrier having a first surface and an opposite second surface; At least two bare die, each of which is split from the same wafer or different wafers, each of which is arranged parallel and spaced apart on the second surface of the carrier, each of which has a first surface and an opposite second surface, the first surface of each of which is fixed on the carrier, the second surface of each of which has a plurality of die pads, and a vertical chip area on the second surface is defined as a chip area; A first dielectric layer is disposed on the second surface of the carrier and the second surface of each of the bare crystals, the first dielectric layer having a plurality of first grooves extending in a horizontal direction; wherein each of the crystal pads of each of the bare crystals is exposed to the outside by the plurality of the first grooves; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer has a plurality of second grooves extending in a horizontal direction, and the plurality of second grooves are connected to the plurality of first grooves; A plurality of conducting circuits, each of which is formed by a metal paste filled in a plurality of the first grooves and a plurality of the second grooves, and each of the conducting circuits is electrically connected to each of the die pads of each of the bare die; An outer protective layer is disposed on the second dielectric layer, the outer protective layer has a plurality of openings and at least two of the openings are located around the chip region on the second surface of each die; Each of the conducting lines is exposed to the outside through each of the openings; A plurality of bonding pads, each of which is a metal structure having a certain thickness formed in the plurality of openings of the outer protective layer and electrically connected to each of the conductive lines; wherein each of the bare crystals can be electrically connected to the outside via the crystal pads, the conductive lines and the bonding pads around the chip area on the second surface of the bare crystal in sequence, thereby forming a fan-out wafer-level packaging unit; an electronic component having a first surface on which the first surface of the carrier is disposed; At least one first bonding wire, each of the first bonding wires is subjected to a wire bonding operation to form a first solder joint and a second solder joint on each of the bonding pads in each of the die, so that each of the die of the fan-out wafer-level packaging unit is electrically connected; and At least two second bonding wires, each of which is subjected to the wire bonding operation to form a third solder joint on each of the bonding pads around the chip area and a fourth solder joint on the first surface of the electronic component, so that each of the bare die of the fan-out wafer-level packaging unit is electrically connected to the printed circuit board; Each of the first welding wires and each of the second welding wires are formed simultaneously through the wire bonding operation.

2. The module according to claim 1, characterized in that The electronic component is a printed circuit board.

3. The module according to claim 1, characterized in that The surface of each welding pad is flush with the surface of the outer protective layer.

4. The module according to claim 1, characterized in that Each of the dies is formed by being separated from the same wafer or different wafers.

5. The module according to claim 1, characterized in that The level heights of the second surfaces of each of the bare die on the carrier are the same.

6. The module according to claim 1, characterized in that The carrier includes a silicon carrier, a glass carrier or a ceramic carrier.

7. The module according to claim 1, characterized in that The metal paste includes silver paste, nano silver paste, copper paste or nano copper paste.

8. The module according to claim 1, characterized in that The first surface of each bare die is disposed on the carrier using a chip bonding film.

Images