Integrated SIC-MOSFET structure containing ESD protection chip
By integrating ESD chips on SiC-MOSFETs, providing electrostatic discharge protection is solved, and the problem of SiC-MOSFET being affected by electrostatic discharge during use is improved, the stability and reliability of the device is simplified, and the design and manufacturing process is simplified.
Patent Information
- Application Number
- CN202421408326.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-20
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2034-06-20
AI Technical Summary
Existing SiC-MOSFETs are susceptible to electrostatic discharge during use, resulting in device failure or performance degradation, affecting the stability and reliability of the system.
An integrated SIC-MOSFET structure containing an ESD protection chip is designed. By integrating the ESD chip on the SiC-MOSFET, it provides electrostatic discharge protection, absorbs and disperses the electrostatic charge, and prevents the electrostatic discharge from causing damage to the device.
Effectively prevent the damage of electrostatic discharge to SiC-MOSFET, improve the stability and reliability of the device, reduce the demand for external components, simplify the design and manufacturing process, and reduce system costs.
Smart Images
Figure CN222720415U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of transistors, and in particular relates to an integrated SIC-MOSFET structure containing an ESD protection chip. Background Art
[0002] SiC-MOSFET refers to silicon carbide metal oxide semiconductor field effect transistor, which is a MOSFET device made of silicon carbide (SiC) material. Its structure is similar to that of traditional MOSFET, but silicon carbide is used as semiconductor material. SiC-MOSFET has a wide range of applications in high temperature, high frequency and high voltage fields, such as power electronics, electric vehicles, solar inverters and power transmission. However, there are still some problems in its use, one of which is electrostatic charge discharge. Electrostatic charge discharge is a common problem in the use of SiC-MOSFET. It may cause device failure or performance degradation, thus affecting the stability and reliability of the system. Electrostatic discharge may cause damage to the internal structure or key components of SiC-MOSFET, thereby reducing the performance of the device or causing it to fail completely. Even if no direct damage is caused, electrostatic discharge may cause the performance of SiC-MOSFET to degrade, such as increasing on-resistance, reducing switching speed, etc., thus affecting the stability and reliability of the device. Electrostatic discharge may not only affect the SiC-MOSFET itself, but also cause failure of the entire system, especially in critical application areas such as electric vehicles, medical equipment, etc.
[0003] In summary, the existing SiC-MOSFET has the problem of transient discharge affecting structural stability. Utility Model Content
[0004] In view of this, the utility model provides an integrated SIC-MOSFET structure containing an ESD protection chip, which can solve the problem that transient discharge of the existing SiC-MOSFET affects the structural stability.
[0005] The utility model is achieved in this way:
[0006] The utility model provides an integrated SIC-MOSFET structure containing an ESD protection chip, wherein the structure comprises a packaging layer and a substrate, wherein the packaging layer is sleeved on the outside of the substrate, the packaging layer is fixedly connected to the substrate, a source electrode and a drain electrode are arranged between the packaging layer and the substrate, the source electrode is fixedly connected to the packaging layer, the drain electrode is fixedly connected to the substrate, a channel is arranged between the source electrode and the drain electrode, the channel is fixedly connected to the source electrode and the drain electrode respectively, a gate electrode is arranged on the source electrode, an insulating layer is wrapped on the outside of the gate electrode, the packaging layer covers the gate electrode inside the source electrode, an ESD chip is arranged on the source electrode, the packaging layer covers the ESD chip inside the source electrode, the source electrode and the ESD chip are connected by metal wire welding, the source electrode is used to introduce current into the channel, the drain electrode is used to receive current flowing out of the channel, the channel is used to realize current conduction, the gate electrode is used to control the conductive performance of the channel, the ESD chip is used to provide electrostatic discharge protection, and the source electrode and the drain electrode are both electrically connected to external devices through leads.
[0007] The technical effects of an integrated SIC-MOSFET structure containing an ESD protection chip provided by the utility model are as follows: the encapsulation layer can protect the chip surface from physical damage, dust, moisture and chemical corrosion, and can provide mechanical support and structural strength for the chip, so that the SIC-MOSFET can remain stable during processing, transportation and use. The substrate provides mechanical support and can maintain the stability of the structure; at the same time, it prevents moisture and dust from entering the inside of the chip, thereby improving the reliability and stability of the device. The substrate is usually used as a ground plane or a power plane to provide power and ground distribution, while also reducing interconnection resistance and improving signal transmission performance. At the same time, the substrate can effectively diffuse and conduct the heat generated by the device, which helps to dissipate heat and keep the temperature of the device stable; it can also reduce crosstalk and mutual interference between devices, and improve the performance and reliability of the integrated circuit. By integrating the ESD chip on the SIC-MOSFET, it can provide fast and effective protection when the SIC-MOSFET is subjected to electrostatic discharge, and ensure that the SIC-MOSFET is not damaged by absorbing and dispersing electrostatic charges. The integration of the ESD protection function into the SiC-MOSFET chip can reduce the demand for external components, simplify the design and manufacturing process of the device, and thus reduce the overall cost of the system. Integrating ESD chips can optimize the performance of SiC-MOSFET, for example, by reducing the impact of external interference on device performance and improving the device's operating efficiency and stability.
[0008] On the basis of the above technical solution, the integrated SIC-MOSFET structure containing an ESD protection chip of the utility model can also be improved as follows:
[0009] Among them, the ESD chip includes a detection unit, a comparison unit, a protection unit and a trigger unit, and the detection unit, the comparison unit, the trigger unit and the protection unit are placed in sequence from top to bottom, the detection unit is fixedly connected to the comparison unit, the comparison unit is fixedly connected to the trigger unit, and the trigger unit is fixedly connected to the protection unit. The detection unit is used to detect whether the input signal exceeds a set threshold, the comparison unit is used to compare the input signal with the set threshold, the protection unit is used to perform voltage adjustment, and the trigger unit is used to trigger the operation of the protection unit.
[0010] The beneficial effect of adopting the above-mentioned improvement scheme is that the protection unit is used to adjust the voltage of the source and the drain when the input signal exceeds the set threshold value to prevent the device from being damaged.
[0011] Furthermore, the substrate is made of silicon material.
[0012] The beneficial effect of adopting the above-mentioned improvement scheme is that the silicon material has higher thermal conductivity and mechanical strength.
[0013] Furthermore, the protection unit is made of silicon carbide material.
[0014] The beneficial effects of adopting the above-mentioned improvement scheme are: silicon carbide material has a lower trigger threshold and a fast response speed. The trigger unit is used to trigger the protection unit to adjust the voltage of the source and drain when the detection unit detects that the input signal exceeds the set threshold;
[0015] Furthermore, the packaging layer is made of plastic.
[0016] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: plastic has good insulation performance and mechanical strength, can isolate the circuit inside the chip from the external environment, and reduce electrical interference.
[0017] Furthermore, the packaging layer is made of ceramic.
[0018] Furthermore, the insulating layer is made of silicon oxide.
[0019] The beneficial effect of adopting the above-mentioned improvement scheme is that silicon oxide has higher insulation performance.
[0020] Furthermore, the channel is made of silicon material.
[0021] Furthermore, the leads of the source and drain are made of polysilicon.
[0022] The beneficial effect of adopting the above-mentioned improvement scheme is that the polysilicon has a lower resistivity, thereby reducing signal transmission delay.
[0023] Furthermore, the channel is a Trapezoidal structure.
[0024] The beneficial effects of adopting the above-mentioned improvement scheme are: improving the electron flow characteristics in the channel, for example, reducing the non-uniformity of the drift velocity of electrons in the channel.
[0025] Compared with the prior art, the utility model provides an integrated SIC-MOSFET structure containing an ESD protection chip, which has the following beneficial effects: the encapsulation layer can protect the chip surface from physical damage, dust, moisture and chemical corrosion, and can provide mechanical support and structural strength for the chip, so that the SIC-MOSFET can remain stable during processing, transportation and use. The substrate provides mechanical support to maintain the stability of the structure; at the same time, it prevents moisture and dust from entering the inside of the chip, thereby improving the reliability and stability of the device. The substrate is usually used as a ground plane or a power plane to provide power and ground distribution, while also reducing interconnection resistance and improving signal transmission performance. At the same time, the substrate can effectively diffuse and conduct the heat generated by the device, which helps to dissipate heat and keep the temperature of the device stable; it can also reduce crosstalk and mutual interference between devices, and improve the performance and reliability of the integrated circuit. By integrating the ESD chip on the SIC-MOSFET, it can provide fast and effective protection when the SIC-MOSFET is subjected to electrostatic discharge, and ensure that the SIC-MOSFET is not damaged by absorbing and dispersing electrostatic charges. The integration of the ESD protection function into the SiC-MOSFET chip can reduce the demand for external components, simplify the design and manufacturing process of the device, and thus reduce the overall cost of the system. Integrating ESD chips can optimize the performance of SiC-MOSFET, for example, by reducing the impact of external interference on device performance and improving the device's operating efficiency and stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the description of the embodiments of the utility model will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0027] Figure 1 A schematic diagram of an integrated SIC-MOSFET structure containing an ESD protection chip;
[0028] Figure 2 A cross-sectional view of an ESD chip having an integrated SIC-MOSFET structure including an ESD protection chip;
[0029] In the accompanying drawings, the components represented by the reference numerals are listed as follows:
[0030] 10. Packaging layer; 11. Substrate; 12. Source; 13. Drain; 14. Gate; 15. ESD chip; 151. Detection unit; 152. Comparison unit; 153. Protection unit; 154. Trigger unit; 16. Insulation layer; 18. Channel. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solution and advantages of the implementation mode of the present invention clearer, the technical solution in the implementation mode of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the implementation mode of the present invention.
[0032] like Figure 1-2 As shown, an embodiment of an integrated SIC-MOSFET structure containing an ESD protection chip provided by the utility model, in this embodiment, includes a packaging layer 10 and a substrate 11, the packaging layer 10 is sleeved outside the substrate 11, the packaging layer 10 and the substrate 11 are fixedly connected, a source 12 and a drain 13 are arranged between the packaging layer 10 and the substrate 11, the source 12 is fixedly connected to the packaging layer 10, the drain 13 is fixedly connected to the substrate 11, a channel 18 is arranged between the source 12 and the drain 13, the channel 18 is fixedly connected to the source 12 and the drain 13 respectively, and a gate 18 is arranged on the source 12. 4, the outer side of the gate 14 is wrapped with an insulating layer 16, the encapsulation layer 10 covers the gate 14 inside, an ESD chip 15 is arranged on the source 12, the encapsulation layer 10 covers the ESD chip 15 inside, the source 12 and the ESD chip 15 are connected by metal wire welding, the source 12 is used to introduce current into the channel 18, the drain 13 is used to receive the current flowing out of the channel 18, the channel 18 is used to achieve current conduction, the gate 14 is used to control the conductive performance of the channel 18, the ESD chip 15 is used to provide electrostatic discharge protection, and the source 12 and the drain 13 are electrically connected to external devices through leads.
[0033] When in use, when the SIC-MOSFET is subjected to external electrostatic discharge, the detection unit 151 detects the presence of electrostatic discharge, the comparison unit 152 compares the electrostatic discharge signal with the set threshold, and when the electrostatic discharge signal exceeds the set threshold, the trigger unit 154 responds, and the trigger unit 154 triggers the protection unit 153 to work. Since the protection unit 153 is connected to the source 12, the protection unit 153 can adjust the voltage, and the ESD chip 15 establishes a low-impedance discharge path, so that the electrostatic voltage is discharged directly through the metal wire without passing through the source 12.
[0034] Among them, in the above technical scheme, the ESD chip 15 includes a detection unit 151, a comparison unit 152, a protection unit 153 and a trigger unit 154. The detection unit 151, the comparison unit 152, the trigger unit 154 and the protection unit 153 are placed in sequence from top to bottom. The detection unit 151 is fixedly connected to the comparison unit 152, the comparison unit 152 is fixedly connected to the trigger unit 154, and the trigger unit 154 is fixedly connected to the protection unit 153. The detection unit 151 is used to detect whether the input signal exceeds the set threshold, the comparison unit 152 is used to compare the input signal with the set threshold, the protection unit 153 is used to perform voltage adjustment, and the trigger unit 154 is used to trigger the operation of the protection unit 153.
[0035] Furthermore, in the above technical solution, the substrate 11 is made of silicon material.
[0036] Furthermore, in the above technical solution, the protection unit 153 is made of silicon carbide material.
[0037] Furthermore, in the above technical solution, the encapsulation layer 10 is made of plastic.
[0038] Furthermore, in the above technical solution, the packaging layer 10 is made of ceramic.
[0039] Furthermore, in the above technical solution, the insulating layer 16 is made of silicon oxide.
[0040] Furthermore, in the above technical solution, the channel 18 is made of silicon material.
[0041] Furthermore, in the above technical solution, the leads of the source 12 and the drain 13 are made of polysilicon.
[0042] Furthermore, in the above technical solution, the channel 18 is a Trapezoidal structure.
[0043] Specifically, the principle of the utility model is: when in use, when the SIC-MOSFET is subjected to external electrostatic discharge, the detection unit 151 detects the existence of electrostatic discharge, the comparison unit 152 compares the electrostatic discharge signal with the set threshold, and when the electrostatic discharge signal exceeds the set threshold, the trigger unit 154 responds, and the trigger unit 154 triggers the protection unit 153 to work. Since the protection unit 153 is connected to the source 12, the protection unit 153 can adjust the voltage, and the ESD chip 15 establishes a low-impedance discharge path, so that the electrostatic voltage is discharged directly through the metal wire without passing through the source 12.
Claims
1. An integrated SIC-MOSFET structure containing an ESD protection chip, characterized in that: The invention comprises an encapsulation layer (10) and a substrate (11), wherein the encapsulation layer (10) is sleeved on the outside of the substrate (11), the encapsulation layer (10) is fixedly connected to the substrate (11), a source electrode (12) and a drain electrode (13) are arranged between the encapsulation layer (10) and the substrate (11), the source electrode (12) is fixedly connected to the encapsulation layer (10), the drain electrode (13) is fixedly connected to the substrate (11), a channel (18) is arranged between the source electrode (12) and the drain electrode (13), the channel (18) is fixedly connected to the source electrode (12) and the drain electrode (13), respectively, a gate electrode (14) is arranged on the source electrode (12), the outer side of the gate electrode (14) is wrapped with an insulating layer (16), and the The encapsulation layer (10) covers the gate electrode (14) inside the encapsulation layer (10), an ESD chip (15) is arranged on the source electrode (12), the encapsulation layer (10) covers the ESD chip (15) inside the encapsulation layer (10), the source electrode (12) and the ESD chip (15) are connected by metal wire welding, the source electrode (12) is used to introduce current into the channel (18), the drain electrode (13) is used to receive current flowing out of the channel (18), the channel (18) is used to achieve current conduction, the gate electrode (14) is used to control the conductivity of the channel (18), the ESD chip (15) is used to provide electrostatic discharge protection, and the source electrode (12) and the drain electrode (13) are both electrically connected to external devices through leads.
2. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 1, characterized in that: The ESD chip (15) comprises a detection unit (151), a comparison unit (152), a protection unit (153) and a trigger unit (154); the detection unit (151), the comparison unit (152), the trigger unit (154) and the protection unit (153) are arranged in sequence from top to bottom; the detection unit (151) is fixedly connected to the comparison unit (152); the comparison unit (152) is fixedly connected to the trigger unit (154); the trigger unit (154) is fixedly connected to the protection unit (153); the detection unit (151) is used to detect whether an input signal exceeds a set threshold; the comparison unit (152) is used to compare the input signal with the set threshold; the protection unit (153) is used to adjust the voltage; and the trigger unit (154) is used to trigger the operation of the protection unit (153).
3. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 2, characterized in that: The substrate (11) is made of silicon material.
4. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 3, characterized in that: The protection unit (153) is made of silicon carbide material.
5. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 4, characterized in that: The packaging layer (10) is made of plastic.
6. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 5, characterized in that: The packaging layer (10) is made of ceramic.
7. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 6, characterized in that: The insulating layer (16) is made of silicon oxide.
8. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 7, characterized in that: The channel (18) is made of silicon material.
9. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 8, characterized in that: The leads of the source (12) and the drain (13) are made of polysilicon.
10. The integrated SIC-MOSFET structure containing an ESD protection chip according to claim 9, characterized in that: The channel (18) is a Trapezoidal structure.