Package structure

Abstract

A package structure includes a front oxide layer, a back oxide layer, a front nitride layer, a back nitride layer, an enhancement layer, and a circuit structure. The front oxide layer is disposed on the first substrate. The back oxide layer is disposed under the first substrate. The front nitride layer is disposed on the front oxide layer. The back nitride layer is disposed under the back oxide layer. The enhancement layer is disposed under the back nitride layer. The circuit structure is disposed on the front nitride layer.

Description

Technical Field

[0001] The present disclosure relates to a packaging structure. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as, for example, personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing various layers of insulating or dielectric materials, conductive materials, and semiconductive materials on a semiconductor substrate, and using lithography to pattern the various material layers to form circuit components and elements on the semiconductor substrate. Tens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. Individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then individually packaged in multi-chip modules or, for example, other types of packages.

[0003] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. In some applications, these smaller electronic components require smaller and more advanced packaging systems than in the past. In addition, as more and more metal layers are added to advanced back-end of line (BEOL) processing, the system on a chip (SOC) substrate warpage becomes higher and higher, which significantly reduces the system on integrated circuit (SoIC) substrate on chip process window and leads to low yield rate.

[0004] During the bonding and packaging process, semiconductor devices may be damaged by processing chemistry or stress. Utility Model Content

[0005] According to some embodiments of the present disclosure, the packaging structure includes a front oxide layer, a back oxide layer, a front nitride layer, a back nitride layer, an enhancement layer, and a circuit structure. The front oxide layer is disposed on the first substrate. The back oxide layer is disposed under the first substrate. The front nitride layer is disposed on the front oxide layer. The back nitride layer is disposed under the back oxide layer. The enhancement layer is disposed under the back nitride layer. The circuit structure is disposed on the front nitride layer.

[0006] According to some embodiments of the present disclosure, a packaging structure includes a first substrate, a back film stack, and a second substrate or a plurality of circuit connectors. The first substrate has a front side and a back side. The back film stack includes a back oxide layer disposed under the back side of the first substrate, a back nitride layer disposed under the back oxide layer, and a back enhancement layer disposed under the back nitride layer. The second substrate or a plurality of circuit connectors are disposed on the front side of the first substrate.

[0007] According to some embodiments of the present disclosure, a packaging structure includes a substrate, one or more integrated chips, a film stack, and a plurality of electrical connectors. The substrate has a through substrate via (TSV) formed therein, wherein the substrate through via protrudes above a first side of the substrate. One or more integrated chips are bonded to a second side of the substrate. The film stack is formed on the first side of the substrate. The film stack includes a first oxide layer, a first nitride layer, and a reinforcement layer. The first oxide layer is formed on the substrate and the substrate through via. The first nitride layer is formed on the first oxide layer. The reinforcement layer is formed on the first nitride layer. A plurality of electrical connectors are disposed in the film stack and contact the substrate through via. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of the present disclosure can be best understood from the following detailed description when read together with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figures 1A to 1H is a schematic cross-sectional view of manufacturing a semiconductor substrate according to an embodiment of the present disclosure;

[0010] Figure 2 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure;

[0011] FIG. 3A to FIG. 3H is a schematic cross-sectional view of manufacturing a semiconductor substrate according to an embodiment of the present disclosure;

[0012] Figure 4 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure;

[0013] FIG. 5A to FIG. 5E is a schematic cross-sectional view of manufacturing a semiconductor substrate according to an embodiment of the present disclosure;

[0014] Figure 6 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure;

[0015] Fig. 7A and Figure 7B is a schematic cross-sectional view of a bonding substrate with a backside film stack according to an embodiment of the present disclosure;

[0016] Fig. 8A A schematic side view of a substrate support tower for a batch processing chamber;

[0017] Figure 8B and Figure 8C is a schematic top view of a substrate support tower supporting substrates arranged at different positions;

[0018] Fig. 9A and Fig. 9B Schematically illustrates the warpage adjustment effect using a backside film stack according to an embodiment of the present disclosure;

[0019] FIG. 10A to FIG. 10K Schematically depicting warpage adjustment in a Chip-on-Wafer-on-Substrate (CoWoS) package according to an embodiment of the present disclosure;

[0020] Fig.11 The diagram schematically illustrates warpage adjustment in a system-on-integrated-chip (SoIC) packaging solution according to an embodiment of the present disclosure.

[0021]

Explanation of symbols

[0022] 10J: Region

[0023] 100:Device substrate

[0024] 101: Notch

[0025] 102: Wafer

[0026] 102B: Back

[0027] 102F: Front

[0028] 104B: Back oxide film

[0029] 104F: Front oxide film

[0030] 106B: Back transition layer

[0031] 106F: Front transition layer

[0032] 108: Etching stop layer

[0033] 110B: Back reinforcement layer

[0034] 110F: Front reinforcement layer

[0035] 112: Back film lamination

[0036] 114: Semiconductor element layer

[0037] 116: Interconnection structure

[0038] 118: Contact pad

[0039] 120: Circuit structure

[0040] 122: Polysilicon layer

[0041] 124: Dielectric layer

[0042] 150:Device substrate

[0043] 151: Wafer

[0044] 152:Sensor area

[0045] 154: Photosensitive area

[0046] 156: Area

[0047] 158: Transmission gate

[0048] 160: Interconnection structure

[0049] 162: Contact pad

[0050] 164: Color filter

[0051] 166: Microlens

[0052] 200: Method

[0053] 202: Operation

[0054] 204: Operation

[0055] 205: Operation

[0056] 206: Operation

[0057] 208: Operation

[0058] 210: Operation

[0059] 212: Operation

[0060] 214: Operation

[0061] 300:Device substrate

[0062] 300a: device substrate

[0063] 308B: Backside etching stop layer

[0064] 308B1: Etch stop layer

[0065] 308B2: Etch stop layer

[0066] 308B n : Etch stop layer

[0067] 308F: Front etch stop layer

[0068] 310B1: Back reinforcement layer

[0069] 310B2: Enhancement layer

[0070] 310B n : Enhancement Layer

[0071] 310F1: Front reinforcement layer

[0072] 312: Back film laminate

[0073] 312a: Back film laminate

[0074] 400: Method

[0075] 404: Operation

[0076] 405: Operation

[0077] 406: Operation

[0078] 408: Operation

[0079] 410: Operation

[0080] 500:Device substrate

[0081] 506B: implantation layer

[0082] 510B: Back reinforcement layer

[0083] 510F: Front reinforcement layer

[0084] 512: Back film laminate

[0085] 600: Method

[0086] 603: Operation

[0087] 605: Operation

[0088] 700:Semiconductor substrate

[0089] 700a: semiconductor substrate

[0090] 712: Back film laminate

[0091] 712a: Back film laminate

[0092] 800:Support Tower

[0093] 802: Support pin

[0094] 802a: Support pin

[0095] 802b: Support pin

[0096] 802c: Support pin

[0097] 804:Support rod

[0098] 902: Warp profile

[0099] 904: Warp Profile

[0100] 906: Warping trend

[0101] 908: Warping trend

[0102] 1000: Encapsulation

[0103] 1002:Intermediary substrate

[0104] 1003: cushion layer

[0105] 1004: Substrate through hole

[0106] 1006: Interconnection structure

[0107] 1008:Conductive connector

[0108] 1010: Integrated Circuit Chip

[0109] 1012: Bottom filler

[0110] 1014: Packaging glue

[0111] 1016: Molding material

[0112] 1018: Carrier substrate

[0113] 1020B: Oxide layer

[0114] 1020F: Oxide layer

[0115] 1022B: Enhanced layer

[0116] 1022F: Passivation film

[0117] 1024: contact opening

[0118] 1025: cushion layer

[0119] 1026:Electrical connector

[0120] 1028: Printed Circuit Board

[0121] 1030B: Back film laminate

[0122] 1030F: Front film laminate

[0123] 1100: Encapsulation

[0124] 1102: first substrate

[0125] 1102F: Front

[0126] 1102w: Curve

[0127] 1104: Second substrate

[0128] 1104B: Back

[0129] 1104F: Front

[0130] 1104w: Curve

[0131] 1106: Carrier substrate

[0132] 1108: Integrated chip

[0133] 1110: Interconnection structure

[0134] 1112: Back film lamination

[0135] 1114: Thin Film Stack

[0136] H: Height

[0137] T1: Thickness

[0138] T2: Thickness

[0139] T3:Thickness

[0140] T4:Thickness

[0141] T51:Thickness

[0142] T5 n :thickness

[0143] T61:Thickness

[0144] T6 n :thickness

[0145] T7:Thickness

[0146] T71:Thickness

[0147] T7 n :thickness

[0148] T8:Thickness

[0149] T9:Thickness DETAILED DESCRIPTION

[0150] The following disclosure provides many different embodiments or examples for implementing different features of the present application. Specific examples of components and configurations are described below to simplify the disclosure of the present application. Of course, these are only examples and are not intended to limit the present application. For example, the following description of forming a first feature on or above a second feature may include an embodiment in which a first and second feature are formed in direct contact, and may also include an embodiment in which other features are formed between the first and second features, so that the first and second features are not in direct contact. In addition, the present application may repeat component symbols and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, rather than governing the relationship between different embodiments and / or the architectures discussed.

[0151] Furthermore, this application may use spatially corresponding terms, such as "below," "below," "lower," "above," "higher," and similar terms, to describe the relationship of one element or feature to another element or feature in the drawings. Spatially corresponding terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be positioned (rotated 90 degrees or at other orientations) and the spatially corresponding descriptors used herein interpreted accordingly.

[0152] Embodiments of the present disclosure relate to methods for processing and bonding substrates to manufacture integrated circuit chips and devices for manufacturing the same. The substrate may include semiconductor devices formed thereon (e.g., on the front side of the substrate) and may be referred to as a device substrate. Specifically, embodiments of the present disclosure provide a method for depositing a back side dielectric film to protect devices on a substrate and / or adjust substrate warpage during bonding and packaging. In some embodiments, the back side dielectric film is deposited in a batch processing chamber, where both dielectric films are formed on the front and back sides of the substrate. The properties of the back side dielectric film, such as stress level and thickness, can be determined based on the bonding chemistry and packaging scheme.

[0153] Figures 1A to 1H is a schematic cross-sectional view of a device substrate 100 manufactured according to an embodiment of the present disclosure. In some embodiments, the device substrate 100 may be a logic device substrate configured to be bonded to an image sensor substrate to form a back-side image sensor wafer. Alternatively, the device substrate 100 may be any substrate to be stacked and bonded to another substrate, such as a logic substrate, a system substrate, a memory substrate, etc. Embodiments of the present disclosure provide a back-side film stack configured to improve back-side protection of a device in the device substrate 100 during a bonding process.

[0154] Figure 2 is a flow chart of a method 200 for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. In some embodiments, the method 200 may be used to process a device substrate 100. The device substrate 100 is made of a semiconductor wafer.

[0155] In operation 202, an oxide film 104 and a transition layer 106 are sequentially deposited on the front side 102F and the back side 102B of the wafer 102, such as Figure 1AAs shown. Wafer 102 is a bare substrate including elemental semiconductors, such as crystalline, polycrystalline or amorphous silicon or germanium; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.; combinations thereof, or other suitable materials. In some embodiments, wafer 102 includes multilayer semiconductors, semiconductor-on-insulator (SOI), such as silicon on insulator or germanium on insulator, etc.

[0156] like Figure 1A As shown, a front oxide film 104F and a back oxide film 104B (collectively referred to as oxide film 104) are formed on the front side 102F and the back side 102B of the wafer 102, respectively. The front oxide film 104F and the back oxide film 104B are formed simultaneously and have substantially the same properties, such as composition and thickness. The front oxide film 104F and the back oxide film 104B are formed simultaneously in a processing chamber, wherein both the front side 102F and the back side 102B of the wafer 102 are exposed to a processing environment. In some embodiments, the oxide film 104 may be formed by flowing an oxidizing precursor to the processing chamber. In some embodiments, one or more cleaning processes may be performed before the oxide film 104 is formed to remove native oxide and / or contaminants from the wafer 102.

[0157] The front oxide film 104F is sometimes referred to as a pad layer, which may provide isolation for subsequent layers to be formed on the wafer 102 .

[0158] The front oxide film 104F and the back oxide film 104B have the same thickness T1. In some embodiments, the thickness T1 is about to about In some embodiments, when the wafer 102 includes silicon, the oxide film 104 includes silicon oxide.

[0159] A front transition layer 106F and a back transition layer 106B (collectively referred to as transition layer 106) are formed on the front oxide film 104F and the back oxide film 104B, respectively. The front transition layer 106F and the back transition layer 106F are formed simultaneously and have substantially the same characteristics, such as composition and thickness. The front transition layer 106F and the back transition layer 106B are formed simultaneously in a processing chamber where both the front oxide film 104F and the back oxide film 104B are exposed to a processing environment. In some embodiments, the transition layer 106 and the oxide film 104 are deposited in the same processing chamber.

[0160] In some embodiments, the transition layer 106 may be a nitride of a semiconductor material, such as silicon nitride. The transition layer 106 may be formed by flowing a precursor including a nitrogen source and a semiconductor source.

[0161] The front transition layer 106F enables subsequent layers to be formed on the front oxide film 104F to adhere. For example, when polysilicon is subsequently deposited to form a semiconductor device therein, the transition layer 106 allows gradual crystallization between the wafer 102, the oxide film 104, and the subsequently formed polysilicon layer, so that the subsequently formed polysilicon layer adheres to the wafer 102.

[0162] The front transition layer 106F and the back transition layer 106B have the same thickness T2. In some embodiments, the thickness T2 is about About in the range between.

[0163] While the front oxide film 104F and the front transition layer 106F are formed to enable subsequent front-end production line processes, the back oxide film 104B and the back transition layer 106B remain on the wafer 102 during front-end production line processing and can provide protection for the wafer 102 during processing and bonding. However, during certain processes, such as wafer-level bonding processes, the back oxide film 104B and the back transition layer 106B formed simultaneously with the front oxide film 104F and the front transition layer 106F cannot provide sufficient protection for the wafer 102, resulting in damage to the wafer 102. Embodiments of the present disclosure provide an enhanced back film stack to prevent damage to the wafer 102 during the bonding process. Operations 204, 206, 208, and 210 may be performed to form an enhanced back film stack.

[0164] In operation 204, an etch stop layer 108 is deposited on the front transition layer 106F. Figure 1B As shown. The etch stop layer 108 is configured to serve as an etch stop layer during dry etching of a subsequent dielectric film on the etch stop layer 108 and can be selectively removed from the front transition layer 106F. The etch stop layer 108 can have a thickness T3. In some embodiments, the thickness T3 is about About in the range between.

[0165] In some embodiments, the etch stop layer 108 is an oxide film, such as silicon oxide. The etch stop layer 108 can be formed in a processing chamber, where the back side of the device substrate 100 is not exposed to the processing environment. In some embodiments, the etch stop layer 108 can be formed by any suitable process, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).

[0166] In operation 206, a reinforcement layer 110 is formed on the front and back sides of the device substrate 100, such as Figure 1C As shown. A front enhancement layer 110F and a back enhancement layer 110B (collectively referred to as enhancement layer 110) are formed on the etch stop layer 108 and the back transition layer 106B, respectively. The front enhancement layer 110F and the back enhancement layer 110B are formed simultaneously and have substantially the same characteristics, such as composition and thickness. The front enhancement layer 110F and the back enhancement layer 110B are formed simultaneously in a processing chamber, wherein both the etch stop layer 108 and the back transition layer 106B are exposed to a processing environment.

[0167] The enhancement layer 110 may be any film suitable for deposition on the back transition layer 106B, such that the back oxide film 104B, the back transition layer 106B, and the back enhancement layer 110B form a back film stack 112. During most processing steps, the back film stack 112 may remain on the wafer 102 to provide protection. In some embodiments, the back film stack 112 may also be used as a stress adjustment or warpage adjustment film to achieve a certain warpage in the device substrate 100.

[0168] The back reinforcement layer 110B has a thickness T4. In some embodiments, the thickness T4 is about About Less than Thickness less than 100mm may not provide adequate protection or stress accommodation / warpage adjustment. The thickness of T4 may generate too much stress and cause the back film stack 112 to peel off from the wafer 102. And (CIP1) needs to be increased to or Scope of Announcement ).

[0169] In some embodiments, the back enhancement layer 110B may include a suitable dielectric film, such as a semiconductor nitride or a semiconductor oxide. In some embodiments, the back enhancement layer 110B may include silicon nitride (Si3N4 or SiN), silicon oxynitride (SiON), Si-rich silicon nitride, N-rich silicon nitride, tetraethylorthosilicate (TEOS), silicon oxide, etc. In some embodiments, the back enhancement layer 110B may be a nitride of a semiconductor material, such as silicon nitride. The back enhancement layer 110 may be formed by flowing a precursor containing a nitrogen source and a semiconductor source.

[0170] In some embodiments, the back enhancement layer 110B and the back transition layer 106B may include the same material, such as silicon nitride. In some embodiments, the composition of the back enhancement layer 110B may be selected based on the desired stress level.

[0171] In some embodiments, method 200 includes an optional operation 205 performed before operation 206. In operation 205, after operation 204, device substrate 100 or wafer 102 is rotated relative to a substrate support by a certain angle so that the substrate support does not block both enhancement layer 110 and transition layer 106, especially when enhancement layer 110 and transition layer 106 are deposited in the same or similar processing chamber. For example, enhancement layer 110 and transition layer 106 can be deposited in the same or similar batch processing chamber, where the substrate support tower contacts a portion of the back side of the substrate being processed, such as Fig. 8A as shown in the example.

[0172] Fig. 8A is a schematic side view of a substrate support tower 800 for use in a batch processing chamber in which a plurality of device substrates 100 may be processed. Figure 8B 8 is a schematic top view of a substrate support tower 800 on which a device substrate 100 is disposed. FIG. 8A to FIG. 8BAs shown, the substrate support tower 800 includes support pins 802 configured to contact and support multiple substrates during processing. The support pins 802 can be evenly distributed along the support rods 804. In some embodiments, the substrate support tower 800 includes three support rods 804, so that each substrate is contacted by three support pins 802a, 802b, 802c. Fig. 8A As shown, the support pins 802 are in contact with the back surface of the device substrate 100. Therefore, the area on the back surface of the device substrate 100 that is in contact with the support pins 802 is blocked by the support pins 802 and film deposition is not performed.

[0173] exist Figure 8B 8, the device substrate 100 is disposed in a first position in relation to the support pins 802. The relative position between the substrate 100 and the support pins 802 can be controlled by marks or notches 101 formed on the edge of the device substrate 100. Figure 8C 8 is a schematic top view of a substrate support tower 800 having a device substrate 100 disposed at a second position thereon. The device substrate 100 is rotated from the first position to the second position at an angle α. In some embodiments, the enhancement layer 110 and the transition layer 106 are deposited in the same or similar batch processing chamber, wherein the device substrate 100 is located at different positions. For example, when the device substrate 100 is disposed on the support tower 800 at the first position, the transition layer 106 is deposited, and the device substrate 100 is rotated by an angle α and disposed on the support tower 800 at the second position to deposit the enhancement layer 110. In some embodiments, the angle α is in a range between about 20 degrees and 60 degrees.

[0174] In operation 208, the front reinforcement layer 110F is removed, while the back reinforcement layer 110B remains intact, as shown in FIG. Figure 1DAs shown. In some embodiments, the front enhancement layer 110F can be removed using a dry etching process. In some embodiments, the front enhancement layer 110F can be removed using a dry etching chemistry having a plasma source and an etchant gas. The plasma source can be inductively coupled plasma (ICR) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), etc. In some embodiments, the etchant gas can include tetrafluoromethane (CF4), difluoromethylene (CH2F2), hexafluoroethane (C2F6), and argon, optionally with the addition of oxygen and / or nitrogen to control the etching rate and etching selectivity. In some embodiments, the etchant gas has a high etching selectivity to the front enhancement layer 110F above the etch stop layer 108. The etch stop layer 108 allows the removal of the front enhancement layer 110F without damaging the front transition layer 106F.

[0175] In operation 210, the etch stop layer 108 is removed to expose the front transition layer 106F for subsequent processing, such as Figure 1E In some embodiments, the etch stop layer 108 may be removed by a wet etching process, such as a dilute HF immersion process. Alternatively, a plasma etching process may be performed using conventional dry etching chemicals such as HBr and Cl2 to minimize damage to the front transition layer 106F.

[0176] In operation 212, a process sequence is performed to fabricate a circuit structure 120 on the front transition layer 106F, such as Figure 1F The circuit structure 120 may include a semiconductor element layer 114 and an interconnect structure sequentially formed on the wafer 102. The circuit structure 120 may be a logic circuit, a memory circuit, a sensor circuit, etc. In some embodiments, the circuit structure 120 may be a control circuit for a sensor circuit.

[0177] The semiconductor device layer 114 may include one or more active devices (such as transistors, etc.) and one or more passive devices (such as resistors, capacitors, inductors, etc.) or a combination thereof. The semiconductor device layer 114 may be formed using front-end production line (FEOL) manufacturing technology. In some embodiments, FEOL includes at least several processes selected from isolation process, channel formation process, gate oxidation / gate formation process, doping process, spacer formation process and source / drain formation process. The semiconductor device layer 114 may include a contact structure formed using middle-end production line (MEOL) manufacturing technology. MEOL includes a contact metal formation process. The interconnect structure 116 may be formed using back-end production line (BEOL) manufacturing technology. BEOL includes the formation and patterning of dielectric layers and conductive metal layers. In some embodiments, BEOL and MEOL may be combined.

[0178] The interconnect structure 116 includes a plurality of interconnect layers embedded in a dielectric layer structure. The dielectric layer structure may include one or more of an oxide, an ultra-low-k dielectric material, a low-k dielectric material, etc., and the interconnect layer may include a conductive material, such as copper, aluminum, tungsten, a combination thereof, and / or the like. The interconnect layer may include a plurality of metal patterns (e.g., pads and lines) and metal vias alternately stacked in the dielectric layer structure. The interconnect structure 116 includes a contact structure connecting semiconductor elements from the semiconductor element layer 114. In some embodiments, the interconnect structure 116 includes a contact pad 118 located on a top surface of the interconnect structure 116. The contact pad 118 is configured to be bonded to a contact pad on another semiconductor substrate. The contact pad 118 may be formed of any suitable material. In some embodiments, the contact pad 118 is formed of a metal such as copper.

[0179] During FEOL fabrication, one or more polysilicon layers 122 may be formed on the back side of the wafer 102 over the back side film stack 112, such as Figure 1FIn some embodiments, the polysilicon layer 122 may be separated by a dielectric layer 124. The one or more polysilicon layers 122 and dielectric layers 124 are byproducts of a FEOL process in which a polysilicon layer is grown on the front side to form the semiconductor element layer 114. After bonding or packaging the device substrate 100, the polysilicon layer 122 and dielectric layer 124 are subsequently removed.

[0180] In operation 214, the device substrate 100 is bonded to a second semiconductor substrate 150, such as Figure 1G As shown. In some embodiments, the second semiconductor substrate 150 is a sensor wafer substrate having a sensor region 152 defined in a wafer 151. The sensor region 152 may include one or more photosensitive regions 154 corresponding to individual pixels. The photosensitive region 154 forms a photodiode with the doped region in the sensor region 152. The sensor region 152 also includes a drain region 156 for each individual pixel. A transmission gate 158 may span the gate region 156 and the photodiode to form a pixel. The transmission gate 158 may include an insulating layer and a gate contact.

[0181] The semiconductor substrate 150 also includes an interconnect structure 160 formed above the sensor region 152. The interconnect structure 160 may include one or more dielectric layers, wherein conductive lines and vias are disposed in dielectric materials connected to the pixels in the sensor region 152. Contact pads 162 may be formed in the uppermost dielectric layer and expose the top surface. The contact pads 162 are connected to the pixels in the sensor region 152 through conductive lines and vias in the interconnect structure 160. The contact pads 162 may be formed of any suitable material. In some embodiments, the contact pads 162 are formed of a metal such as copper.

[0182] The contact pads 162 in the semiconductor substrate 150 and the contact pads 118 in the device substrate 100 are designed to align with each other and form an electrical connection when the semiconductor substrate 150 and the device substrate 100 are bonded to each other.

[0183] Various bonding techniques may be employed to achieve bonding between the device substrate 100 and the semiconductor substrate 150. Suitable bonding techniques may include direct bonding, hybrid bonding, and the like.

[0184] Figure 1GA metal-to-metal bond is depicted, wherein the contact pad 118 and the corresponding contact pad 162 are compressed under heat to melt the metal and form a bond. In some embodiments, a thermal compression process can be performed on the device substrate 100, 150. The thermal compression process causes the metals to diffuse into each other. In some embodiments, the contact pads 118, 162 are copper, and the copper atoms at the contact surface can obtain enough energy to diffuse between the contact pads 118, 162. As a result, a uniform copper interface can be formed between the two contact pads 118, 162. This uniform copper interface helps the contact pads 118, 162 form uniform bonding features. In addition, the uniform bonding features also provide mechanical bonding to keep the device substrates 100, 150 together.

[0185] In some embodiments, the top surfaces of the contact pads 118, 162 may be approximately flush with the top surfaces of the corresponding semiconductor devices 100, 150. In other embodiments, the top surfaces of the contact pads 118, 162 may be elevated above the corresponding top surfaces of the substrates to ensure good metal-to-metal contact between the contact pads 118, 162. As a result, the contact pads 118, 162 may be fused through metal-to-metal contact and the device substrates 100, 150 may be spaced apart. In some embodiments, an underfill or adhesive may be deposited where such spacing occurs.

[0186] After bonding the device substrates 100 and 150, a color filter 164 and a microlens 166 may be formed on the semiconductor substrate 150. Figure 1H As shown. The wafer 151 is thinned on the back side until the wafer 151 reaches a predetermined thickness. This thinned wafer 151 allows light to pass through the wafer 151 and hit the photosensitive area 154 of the photodiode embedded in the wafer 151, so that the wafer 151 absorbs less. The thinning process can be achieved by using suitable techniques, such as grinding, polishing and / or chemical etching. In some embodiments, the thinning process can be implemented by using a chemical mechanical polishing (CMP) process. In the CMP process, a combination of etching material and grinding material contacts the back side of the wafer 151, and a grinding pad is used to grind away the back side of the wafer 151 until the desired thickness is reached. During the thinning process, the back film stack 112 protects the circuit structure 120 in the device substrate 100.

[0187] After thinning wafer 151, color filters 164 may be applied to the back side of wafer 151. Color filters 164 may be used to allow light of certain wavelengths to pass through while reflecting other wavelengths, thereby allowing the image sensor to determine the color of light received by photosensitive region 154. Color filters 164 may vary, such as red, green, and blue filters. Other combinations may also be used, such as cyan, yellow, and magenta, or white, transparent, or nearly transparent. The number of different colored color filters 164 may also vary.

[0188] In some embodiments, the color filter 164 may include a pigmented or dyed material, such as acrylic. For example, polymethyl-methacrylate (PMMA) or polyglycidylmethacrylate (PGMS) is a suitable material to which a pigment or dye may be added to form the color filter 164. However, other materials may be used. The color filter 164 may be formed by another suitable method known in the art.

[0189] Microlenses 166 may be formed above color filter 164. Microlenses 166 may be formed of any material that can be patterned and formed into a lens, such as a high-transmittance acrylic polymer. In some embodiments, the thickness of microlenses 166 is about 0.1 μm to about 2.5 μm. Microlenses 166 may be formed using liquid materials and spin coating techniques known in the art. In some embodiments, the spin coating layer is cut to form individual lenses and then reflowed to allow the cut portions of the spin coating layer to form curved surfaces of individual lenses. Other methods may also be used, such as deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.

[0190] The additional layers in the backside film stack 112 protect the circuit structures 120 in the device substrate 100 from being damaged by processing chemicals during bonding and subsequent processes, such as wet etching and cleaning processes.

[0191] Figures 3A to 3G 3 is a schematic cross-sectional view of a device substrate 300 manufactured according to an embodiment of the present disclosure. The device substrate 300 includes a backside film stack manufactured differently from the backside film stack 112 of the semiconductor substrate 100 . Figure 4 4 is a flow chart of a method 400 for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. The device substrate 300 may be manufactured according to the method 400 .

[0192] Similar to the device substrate 100, the device substrate 300 also includes a backside film stack to provide additional protection during the bonding process. However, the device substrate 300 includes a backside film stack 312 formed in a different manner than the backside film stack 112 of the device substrate 100. Specifically, the backside film stack 312 is formed by performing operations 404, 406, 408, 410 in the method 400. In some embodiments, the backside film stack 312 can be formed by repeating operations 404, 406, 408, 410 two or more times to achieve a desired thickness.

[0193] Method 400 includes operation 202, as described above and as Figure 3A The oxide film 104 and the transition layer 106 are sequentially deposited on the front side 102F and the back side 102B of the wafer 102 .

[0194] In operation 404, an etch stop layer 308 is deposited on both sides of the transition layer 106F. Figure 3A As shown. Front etch stop layer 308F and back etch stop layer 308B (collectively referred to as etch stop layer 308) are formed on front transition layer 106F and back transition layer 106B, respectively. Front etch stop layer 308F and back etch stop layer 308B are formed simultaneously and have substantially the same characteristics, such as composition and thickness. Etch stop layer 308 is configured to serve as an etch stop layer during dry etching of a subsequent dielectric film on etch stop layer 308 and can be selectively removed from front transition layer 106F. Etch stop layer 308 can have a thickness T61. In some embodiments, thickness T61 is about to about in the range between.

[0195] In some embodiments, etch stop layer 3081 is an oxide film, such as silicon oxide. Etch stop layer 3081 may be formed in the same process chamber as oxide film 104 and transition layer 106. Etch stop layer 3081 may be formed similarly to oxide film 104.

[0196] In operation 406, a reinforcement layer 3101 is formed on the front and back sides of the substrate 300, such as Figure 3B As shown. The front enhancement layer 310F1 and the back enhancement layer 310B1 (collectively referred to as enhancement layer 3101) are formed on the front etch stop layer 308F1 and the back etch stop layer 308B1, respectively. The front enhancement layer 310F1 and the back enhancement layer 310B1 are formed simultaneously and have substantially the same characteristics, such as composition and thickness. The front enhancement layer 310F1 and the back enhancement layer 310B1 are formed simultaneously in a processing chamber, wherein both the front etch stop layer 308F1 and the back etch stop layer 308B1 are exposed to a processing environment.

[0197] The enhancement layer 3101 may be any film suitable for deposition on the backside etch stop layer 308B1, such that the backside oxide film 104B, the backside transition layer 106B, the backside etch stop layer 308B1, and the backside enhancement layer 310B1 form a backside film stack 312. During most processing steps, the backside film stack 312 may remain on the wafer 102 to provide protection. In some embodiments, the backside film stack 312 may also be used as a stress adjustment or warpage adjustment film to achieve limited warpage in the device substrate 300.

[0198] The back reinforcement layer 310B1 has a thickness T51. In some embodiments, the thickness T51 is about to about In some embodiments, the back enhancement layer 310B1 may include a suitable dielectric film, such as a semiconductor nitride or a semiconductor oxide. In some embodiments, the back enhancement layer 310B may include silicon nitride (Si3N4 or SiN), silicon oxynitride (SiON), silicon-rich silicon nitride, nitrogen-rich silicon nitride, tetraethoxysilane (TEOS), silicon oxide, etc. In some embodiments, the back enhancement layer 310B1 may be a nitride of a semiconductor material, such as silicon nitride. The back enhancement layer 310B1 may be formed by flowing a precursor containing a nitrogen source and a semiconductor source.

[0199] In some embodiments, the enhancement layer 3101 and the transition layer 106 may include the same material, such as silicon nitride. In some embodiments, the composition of the back enhancement layer 310B1 may be selected based on the desired stress level. In some embodiments, the enhancement layer 310 and the transition layer 106 may be deposited in the same or similar processing chamber. For example, the enhancement layer 310 and the transition layer 106 may be deposited in the same or similar batch processing chamber.

[0200] Similar to operation 205 in method 200, optional operation 405 may be formed between operations 404 and 406. Figure 8B and Figure 8C As shown, when the substrate 300 is disposed on the support tower 800 at the first position, the transition layer 106 is deposited, and the substrate 300 is rotated by an angle α and disposed on the support tower 800 at the second position to deposit the enhancement layer 3101. In some embodiments, the angle α is in a range of about 20 degrees to 60 degrees.

[0201] In operation 408, the front reinforcement layer 310F1 is removed, while the back reinforcement layer 310B1 remains intact, as shown in FIG. Figure 3CIn some embodiments, the front enhancement layer 310F1 may be removed using a dry etching process. Suitable processes in operation 408 may be similar to the processes described in operation 208 in method 200. After operation 408, the front etch stop layer 308F1 is exposed, while the back etch stop layer 308B1 remains in the back film stack 312.

[0202] In operation 410, the front etch stop layer 308F1 is removed to expose the front transition layer 106F for subsequent processing, such as Figure 3D In some embodiments, the front etch stop layer 308F1 can be removed by a wet etching process, such as a dilute HF immersion process. Alternatively, a plasma etching process can be performed using conventional dry etching chemicals such as HBr and Cl2 to minimize damage to the front transition layer 106F.

[0203] At this stage, the processing sequence is performed to fabricate the circuit structure 120 on the front transition layer 106F. In some embodiments, operations 404, 406, 408, and 410 may be repeated one or more times to increase the thickness of the back film stack 312, such as Figure 3E As shown. With each cycle of operations 404, 406, 408 and 410, a pair of etch stop layers 310B n and reinforcement layer 310B n is added to the back film stack 312. Figure 3E As shown, the back film stack 312 may include n pairs of back etch stop layers 308B1-308B stacked together. n and back reinforcement layer 310B1-310B n , where n is equal to or greater than 1. Backside etch stop layer 308B1-308B n and back reinforcement layer 310B1-310B n Alternate arrangement. Etch stop layer 308B n and back reinforcement layer 310B n The number of pairs can be selected according to the process requirements.

[0204] Backside etching stop layer 308B n May have a thickness of T6 n In some embodiments, the backside etch stop layers 308B1-308B n The back reinforcement layer may have a thickness of T5. n In some embodiments, the back reinforcement layers 310B1-310B n can have substantially the same thickness, such as Figure 3E Alternatively, the back reinforcement layers 310B1-310B n Thickness T51-T5n In some embodiments, the back reinforcement layer 310B n Thickness T5 n It can increase with n, that is, T51<T5 n <…… <T5 n ,like Figure 3G shown.

[0205] Etch stop layer 308B n and back reinforcement layer 310B n The back etch stop layers 308B1-308B may be suitable dielectric materials that have etching selectivity to each other. n One or more dielectric materials may be included, such as silicon oxide, silicon oxynitride, silicon nitride, etc. Back enhancement layer 310B1-310B n The backside etch stop layers 308B1-308B may include one or more dielectric materials, such as silicon nitride, silicon oxynitride, silicon oxide, etc. In some embodiments, the backside etch stop layers 308B1-308B n Alternatively, the backside etch stop layers 308B1-308B n The back reinforcement layers 310B1-310B may be formed of different materials. n Alternatively, the back reinforcement layers 310B1-310B n Can be formed from different materials.

[0206] After the back film stack 312 reaches the target thickness, operation 212 may be performed to fabricate the circuit structure 120 on the front transition layer 106F, such as Figure 3F Then, operation 214 may be performed to bond the device substrate 300 to another semiconductor substrate (eg, semiconductor substrate 150), such as Figure 3G shown.

[0207] Figure 3H A device substrate 300a having a backside film stack 312a is schematically depicted. The backside film stack 312a includes n pairs of backside etch stop layers 308B. n and back reinforcement layer 310B n Back reinforcement layer 310B n Thickness T5 n Increased from T51 to T5 n .

[0208] like Figure 3E As shown, the back film stack 312 may include n pairs of back etch stop layers 308B1-308B stacked together. n and back reinforcement layer 310B1-310B n, where n is equal to or greater than 1.

[0209] FIG. 5A to FIG. 5E is a schematic cross-sectional view of a device substrate 500 manufactured according to an embodiment of the present disclosure. Figure 6 6 is a flow chart of a method 600 for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. Device substrate 500 may be manufactured according to method 600. Method 600 is similar to method 200, except that method 600 includes operation 603 after operation 202. Device substrate 500 is similar to device substrate 300, except that device substrate 500 includes a back transition layer having an implant.

[0210] Method 600 begins at operation 202, as described above and as Figure 5A The oxide film 104 and the transition layer 106 are sequentially deposited on the front side 102F and the back side 102B of the wafer 102 .

[0211] In operation 603 of method 600, an implantation is performed on the back transition layer 106B, such as Figure 5A In some embodiments, one or more impurities may be implanted into the back transition layer 106B to alter the crystal structure and produce an implanted layer 506B, such as Figure 5B In some embodiments, the implant layer 506B may have a thickness of about Peace The implanted layer 506B improves the adhesion between the wafer 102 and the subsequently deposited dielectric layer in the back film stack. In some embodiments, oxygen can be implanted into the back transition layer 106B. With the implanted oxygen, the implanted layer 506B provides better adhesion between the wafer 102 and the subsequently deposited layer.

[0212] After operation 603, operation 204 is performed to deposit an etch stop layer 108 on the front transition layer 106F. Figure 5C shown.

[0213] In operation 206, a reinforcement layer 510 is formed on the front and back sides of the substrate 500, such as Figure 5DAs shown. A front enhancement layer 510F and a back enhancement layer 510B (collectively referred to as enhancement layer 510) are formed on the etch stop layer 108 and the implant layer 506B, respectively. The front enhancement layer 510F and the back enhancement layer 510B are formed simultaneously and have substantially the same characteristics, such as composition and thickness. The front enhancement layer 510F and the back enhancement layer 510B are simultaneously formed in a processing chamber where both sides of the device substrate 500 are exposed to a processing environment. The enhancement layer 510 is similar to the enhancement layer 110, except that the enhancement layer 510 can be deposited at a greater thickness without being peeled off due to the implant layer 506B. The back enhancement layer 510B has a thickness T7. In some embodiments, the thickness T7 is about About A back film stack 512 is formed on the back side of the wafer 102. The back film stack 512 includes a back oxide film 104B, a back implant layer 506B, and a back enhancement layer 510B.

[0214] Operations 208 and 210 are then performed to remove the front side enhancement layer 510F and the etch stop layer 108 from the front side, while the back side film stack 512 remains intact.

[0215] Operations 212 and 214 may then be performed to form the circuit structure 120 and bond it to the second semiconductor substrate 150. Figure 5E shown.

[0216] Similarly, operation 603 may be added after operation 202 and before operation 404 in method 400. In operation 603, an implant layer 506B is formed from the back transition layer 106B.

[0217] Fig. 7A is a schematic cross-sectional view of a semiconductor substrate 700 having a backside film stack 712 according to an embodiment of the present disclosure. The backside film stack 712 is similar to the backside film stack 312, except that the backside film stack 712 includes an implanted layer 506B instead of the backside transition layer 106B.

[0218] Figure 7B is a schematic cross-sectional view of a semiconductor substrate 700a having a backside film stack 712a according to an embodiment of the present disclosure. The backside film stack 712a is similar to the backside film stack 312a, except that the backside film stack 712a includes an implanted layer 506B instead of the backside transition layer 106B. Unlike the backside film stack 712, the backside film stack 712a includes n pairs of backside etch stop layers 508B. n and back reinforcement layer 510B n , its thickness is T7 n Increased from T71 to T7 n .

[0219] Although the above examples illustrate bonding an image sensor wafer and a logic wafer at the wafer-to-wafer level, embodiments of the present disclosure may also facilitate wafer-to-wafer bonding between an image sensor wafer and a logic wafer or any suitable wafer.

[0220] The backside film stack according to the present disclosure may also be used to regulate stress and wafer warpage during various packaging schemes to improve bond adhesion and device performance.

[0221] Fig. 9A The warpage profiles of substrates with and without backside film stacks according to the present disclosure are included. Fig. 9A In Figure 1, the x-axis represents the position along the diameter of the substrate, and the y-axis represents the local warpage value. When the center area protrudes above the edge area, the substrate has positive warpage. When the center area is tilted from the edge area, the substrate has negative warpage. Fig. 9A A warp profile 902 of a conventional semiconductor substrate and a warp profile 904 of a semiconductor substrate having a backside film stack (e.g., backside film stacks 112, 312, 312a, 512, 512a, 712, 712a) are included. As shown in the warp profile 904, the conventional substrate has a significant negative warp near the center of the substrate. On the other hand, the warp profile 904 has a smaller positive warp. The warp profiles 902, 904 show that the backside film stack can adjust the warp. In some embodiments, the backside film stack according to the present disclosure can be used to induce positive warp in the substrate.

[0222] Fig. 9B The warping tendency along the processing steps of substrates with and without backside film stacks according to the present disclosure is included. Fig. 9B , the x-axis represents the processing step in the processing sequence, and the y-axis represents the average warpage of the substrate. Fig. 9B The warpage trend 906 of a conventional semiconductor substrate and the warpage trend 908 of a semiconductor substrate having a backside film stack such as backside film stacks 112, 312, 312a, 512, 512a, 712, 712a are included. Comparing the warpage trends 906 and 908, it is apparent that the backside film stack according to the present disclosure can reduce warpage during a process sequence.

[0223] FIG. 10A to FIG. 10J Warpage adjustment in a Chip-on-Wafer-on-Substrate (CoWoS) package 1000 according to the present disclosure is schematically depicted.

[0224] exist Fig. 10A In the embodiment, an interposer substrate 1002 is provided. The interposer substrate 1002 has a through substrate via (TSV) 1004 formed therein. An interconnect structure 1006 is formed on a front side of the interposer substrate 1002 .

[0225] exist Fig. 10B In the embodiment of the present invention, a plurality of pumps and conductive connectors 1008 are formed above the interconnect structure 1006. In some embodiments, the pumps and conductive connectors 1008 can be copper pillars.

[0226] exist Fig. 10C In the embodiment, front-scale wafer-to-wafer bonding is performed to bond a plurality of integrated circuit wafers 1010 via a pump and a conductive connector 1008. Before bonding the integrated circuit wafers 1010, an underfill 1012 may be applied over the interconnect structure 1006.

[0227] exist Fig. 10D In the embodiment of the present invention, a gap filling process is performed to encapsulate the integrated circuit wafer 1010 in the encapsulant 1014. After being formed, the encapsulant 1014 seals the integrated circuit wafer 1010 and the interconnect structure 1006. After the encapsulant 1014 is deposited, a planarization process is performed to make the back surface of the integrated circuit wafer 1010 flush with the top surface of the encapsulant 1014.

[0228] exist Fig. 10E In the process, an adhesive molding material 1016 is applied to the top surface of the integrated circuit die 1010 and the encapsulant 1014. A carrier substrate 1018 is then attached to the molding material 1016. The carrier substrate 1018 provides mechanical support for the interposer substrate 1002 and the integrated circuit die 1010 during intermediate operations of the manufacturing process. The package 1000 is then flipped over to allow processing from the back side of the interposer substrate 1002.

[0229] exist Fig.10F In some embodiments, the interposer substrate 1002 is thinned to expose the TSV 1004. The interposer substrate 1002 may be thinned by grinding, lapping, etching, polishing, or a combination of processes. In some embodiments, the interposer substrate 1002 may be recessed so that the TSV 1004 protrudes above the top surface of the interposer substrate 1002, such as Fig.10F In some embodiments, the recess process may be performed in a multi-step process, for example, by a CMP process, a wet etching process, and a subsequent dry etching process. The TSV 1004 may protrude a height H above the interposer substrate 1002. In some embodiments, the height H is in a range between about 5 microns and about 15 microns.

[0230] exist Figure 10GIn the embodiment, a front film stack 1030F is formed over the interposer substrate 1002 and the TSVs 1004, and a back film stack 1030B is formed on the carrier substrate 1018. The front film stack 1030F and the back film stack 1030B may be formed by any of the methods 200, 400, 600 described above.

[0231] The front film stack 1030F is configured to receive a connector, such as a microbump, connected to the TSV 1004. The front film stack 1030F may include a dielectric material suitable for accommodating the connector. In some embodiments, the front film stack 1030F may include an oxide layer 1020F and a passivation film 1022F over the oxide layer 1020F. In some embodiments, the oxide layer 1020F may be formed in a manner similar to the oxide film 104 according to operation 202 discussed above. The passivation film 1022F may include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, silicon oxide, etc. In some embodiments, the thickness T9 of the front film stack 1030F is in a range between about 75 microns and 200 microns, similar to the thickness T9 of the front film stack 1030F according to operation 202 discussed above. Figure 2 , Figure 4 , Figure 6 The backside film stack 112, 312, 312a, 512, 712 or 712a is manufactured by the method shown.

[0232] The back film stack 1030B is configured to provide stress adjustment to the package 1000. For example, the material and thickness of the back film stack 1030B are selected to adjust the warpage of the package 1000 so that the package 1000 has a positive warpage. The positive warpage extends the length of the contact surface on the front side of the package 1000, thereby improving the bonding between the TSV 1004 and the connector. The back film stack 1030B may include a dielectric material suitable for adjusting stress and warpage. In some embodiments, the back film stack 1030B may include an oxide layer 1020B and an enhancement layer 1022B above the oxide layer 1020B. In some embodiments, the oxide layer 1020B may be formed in a manner similar to the oxide film 104 according to operation 202 discussed above. The oxide layer 1020F and the oxide layer 1020B may be formed simultaneously in a processing chamber configured to process the front and back sides of one or more substrates. The enhancement layer 1022B may include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, silicon oxide, etc. In some embodiments, the thickness T8 of the back film stack 1030B is in a range between about 75 microns and 200 microns, similar to the thickness T8 of the back film stack 1030B. Figure 2 , Figure 4 , Figure 6 The backside film stack 112, 312, 312a, 512, 712 or 712a is manufactured by the method shown.

[0233] The front film stack 1030F and the back film stack 1030B may be formed by selectively performing the operations described in methods 200, 400, and 600. For example, appropriate combinations of operations 202, 204, 206, 208, 404, 406, 408, 410, and 603.

[0234] In some embodiments, the front film stack 1030F and the back film stack 1030B may have the same composition and thickness and may be formed during the same process by performing operation 202 one or more times, operations 404 and 406 one or more times, and so on, as described above.

[0235] In other embodiments, the front film stack 1030F and the back film stack 1030B may have different compositions and / or thicknesses. The various layers may be formed on both sides and then one or more film layers may be removed from the front side as described in operations 206, 208 or operations 408, 410.

[0236] exist Fig. 10H , contact opening 1024 passes through front film stack 1030F to expose TSV 1004. In some embodiments, contact opening 1024 is configured to receive a contact pump. As described above, back film stack 1030B can induce positive warpage in package 1000, thereby expanding the surface area in contact opening 1024 and improving bonding performance.

[0237] exist Fig.10I In the embodiment, a plurality of electrical connectors 1026 are formed in the contact openings 1024 to electrically contact the TSV 1004. The electrical connectors 1026 may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), etc. The electrical connectors 1026 may be formed by commonly used methods, such as evaporation, electroplating, printing, solder transfer, ball placement, etc.

[0238] Fig.10J yes Fig.10I10J in FIG. 10A is a schematic enlarged view of area 10J in FIG. 10B , showing details around electrical connector 1026 and TSV 1004. Fig.10J As shown, a liner layer 1003 may be formed around the TSV 1004 between the TSV 1004 and the interposer substrate 1002. The liner layer 1003 and the TSV 1004 protrude above the interposer substrate 1002 by about a height H. An electrical connector 1026 is disposed in the front film stack 1030F. A liner layer 1025 may be disposed between the electrical connector 1026 and the front film stack 1030F. The front film stack 1030F may have a thickness T9. The front film stack 1030F includes one or more dielectric materials. An exemplary composition of the front film stack 1030F may be similar to, but not limited to, the back film stacks 112, 312, 312a, 512, 712, 712a.

[0239] exist Figure 10K , the backside film stack 1030B is removed together with the carrier substrate 1018. The package 1000 may be attached to an additional package, such as a printed circuit board 1028, via electrical connectors 1026.

[0240] Film stacks according to the present disclosure may be used in any suitable packaging solution requiring warpage adjustment. Fig.11 Schematically depicts warpage adjustment in an integrated chip system (SoIC) package 1100 according to the present disclosure. The package 1100 may include a first substrate 1102 and a second substrate 1104 bonded together. When bonded, a front side 1102F of the first substrate 1102 and a front side 1104F of the second substrate 1104 are pressed against each other.

[0241] The first substrate 1102 may include a carrier substrate 1106 to which the interconnect structure 1110 is attached and one or more integrated wafer chips 1108. In some embodiments, a backside film stack 1112 is formed on the backside 1102B of the first substrate 1102. The backside film stack 1112 may be formed according to the present disclosure and used to generate positive warpage in the first substrate 1102. The backside film stack 1112 includes one or more dielectric materials. An exemplary composition of the backside film stack 1112 may be similar to, but not limited to, backside film stacks 112, 312, 312a, 512, 712, 712a. Curve 1102w schematically depicts a warpage profile of the first substrate 1102 after warpage adjustment by the backside film stack 1112. The positive warpage in the first substrate 1102 improves the bonding performance between the first substrate 1102 and the second substrate 1104.

[0242] Optionally, a thin film stack 1114 may be formed on the back side 1104B of the second substrate 1104. The thin film stack 1114 may be formed according to the present disclosure and used to generate positive warpage in the second substrate 1104. The film stack 1114 includes one or more dielectric materials. Exemplary compositions of the film stack 1114 may be similar to, but not limited to, the back side film stacks 112, 312, 312a, 512, 712, 712a. Curve 1104w schematically depicts the warpage profile of the second substrate 1104 after warpage adjustment by the thin film stack 1114. The positive warpage in the second substrate 1104 improves the bonding performance between the first substrate 1102 and the second substrate 1104. In some embodiments, the film stack 1114 generates compression warpage, which improves adhesion on the electrical connector 1026 or solder balls.

[0243] Various embodiments or examples described herein provide multiple advantages over the prior art. The film stack according to the present disclosure can reduce wet dip attack on the semiconductor substrate during bonding, such as bonding between an image sensor substrate and a logic device substrate. The film stack according to the present disclosure can be used to adjust stress and wafer warpage to improve bonding adhesion and device performance during various packaging schemes (such as CoWoS, SoIC, etc.). The film stack according to the present disclosure can be used to improve the bonding process and device performance in both wafer-to-wafer bonding and wafer-to-wafer bonding. The novel multilayer film back structure and process method according to the present disclosure can prevent contamination on CIS / ISP of wafer-to-wafer or wafer-to-wafer bonding. The multilayer film structure can provide warpage / stress adjustment during processing and bonding. For example, the new multilayer film structure can adjust stress and wafer warpage in CoWoS and SOIC packaging schemes, thereby improving bonding adhesion and device performance. It should be understood that not all advantages must be discussed herein, all embodiments or examples do not require specific advantages, and other embodiments or examples can provide different advantages.

[0244] Some embodiments of the present disclosure provide a method, comprising: forming a front oxide layer and a back oxide layer on a first substrate; depositing a front nitride layer on the front oxide layer, and depositing a back nitride layer on the back oxide layer; forming an enhancement layer on the back nitride layer; and executing a process sequence to manufacture a circuit structure on the front nitride layer.

[0245] In some embodiments, the method further comprises bonding a second substrate to the circuit structure, wherein the enhancement layer is exposed during the bonding process. In some embodiments, the second substrate comprises a plurality of image sensors thereon, and the circuit structure is configured to control the image sensors in the second substrate. In some embodiments, performing the process sequence comprises growing a polysilicon layer on the enhancement layer and removing the polysilicon layer. In some embodiments, forming the enhancement layer comprises: depositing an etch stop layer on the front nitride layer; depositing the enhancement layer on the back nitride layer and the etch stop layer; removing the enhancement layer from the etch stop layer; and removing the etch stop layer to expose the front nitride layer. In some embodiments, forming the enhancement layer comprises: depositing a first front etch stop layer on the front nitride layer and depositing a first back etch stop layer on the back nitride layer; depositing a first dielectric layer on the first back etch stop layer and the first front etch stop layer; removing the first dielectric layer from the first front etch stop layer; and removing the first front etch stop layer to expose the front nitride layer. In some embodiments, the method further comprises: depositing a second front etch stop layer on the front nitride layer and depositing a second back etch stop layer on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer and the second front etch stop layer; removing the second dielectric layer from the second front etch stop layer; and removing the second front etch stop layer to expose the front nitride layer. In some embodiments, the method further comprises: implanting a back nitride layer before forming the first back etch stop layer. In some embodiments, the method further comprises: implanting a back nitride layer before depositing the etch stop layer.

[0246] Some embodiments of the present disclosure provide a packaging structure, which includes a front oxide layer, a back oxide layer, a front nitride layer, a back nitride layer, an enhancement layer, and a circuit structure. The front oxide layer is disposed on a first substrate. The back oxide layer is disposed under the first substrate. The front nitride layer is disposed on the front oxide layer. The back nitride layer is disposed under the back oxide layer. The enhancement layer is disposed under the back nitride layer. The circuit structure is disposed on the front nitride layer.

[0247] In some embodiments, the package structure further includes a second substrate disposed on the circuit structure, wherein the reinforcement layer is exposed.

[0248] Some embodiments of the present disclosure provide a method for adjusting warpage, comprising: providing a first substrate, wherein the first substrate has a front side and a back side; depositing a back side film stack on the back side to produce a positive warpage profile in the first substrate; and bonding the front side of the first substrate to a second substrate or a plurality of circuit connectors.

[0249] In some embodiments, depositing a backside film stack includes: forming a front side oxide layer and a backside oxide layer on a first substrate; depositing a front side nitride layer on the front side oxide layer and depositing a backside nitride layer on the backside oxide layer; and forming a front side enhancement layer over the front side nitride layer and depositing the backside enhancement layer on the backside nitride layer. In some embodiments, the method further includes: removing the front side enhancement layer. In some embodiments, the method further includes: forming a plurality of contact openings through the front side enhancement layer, the front side nitride layer, and the front side oxide layer; and forming a plurality of electrical connectors in the contact openings. In some embodiments, providing a first substrate includes: providing an interposer substrate having a plurality of through substrate vias (TSVs) formed therein and an interconnect structure formed on a first side of the interposer substrate; bonding one or more integrated chips to the interconnect structure; and thinning a second side of the interposer substrate to expose the substrate through vias. In some embodiments, the backside film stack is formed on the first substrate, and the front side oxide layer and the front side nitride layer are formed on the second side of the interposer substrate and on the exposed portions of the substrate through vias. In some embodiments, providing a first substrate includes: providing a carrier substrate; and bonding one or more integrated chips to a first side of the carrier substrate, wherein the backside film stack is formed on a second side of the carrier substrate.

[0250] Some embodiments of the present disclosure provide a packaging structure, which includes a first substrate, a back film stack, and a second substrate or a plurality of circuit connectors. The first substrate has a front side and a back side. The back film stack includes a front oxide layer disposed on the first substrate, a back oxide layer disposed under the back side of the first substrate, a back nitride layer disposed under the back oxide layer, and a back enhancement layer disposed under the back nitride layer. The second substrate or a plurality of circuit connectors are disposed on the front side of the first substrate.

[0251] In some embodiments, the package structure further includes a front oxide layer disposed on the front side of the first substrate, a front nitride layer disposed on the front oxide layer, a plurality of contact openings passing through the front nitride layer and the front oxide layer, and a plurality of electrical connectors disposed in the contact openings. In some embodiments, the first substrate includes an interposer substrate having a plurality of substrate through holes extending from a first side of the interposer substrate to a second side of the interposer substrate, an interconnect structure disposed on the first side of the interposer substrate, one or more integrated chips disposed on the interconnect structure, and a carrier substrate disposed on the one or more integrated chips. In some embodiments, the first substrate includes a carrier substrate and one or more integrated chips disposed on the first side of the carrier substrate, wherein the back film stack is disposed on the second side of the carrier substrate.

[0252] Some embodiments of the present disclosure provide a packaging structure comprising: a through substrate via (TSV) formed in a substrate, wherein the through substrate via protrudes above a first side of the substrate; one or more integrated chips bonded to a second side of the substrate; a film stack formed on the first side of the substrate, wherein the film stack comprises a first oxide layer formed on the substrate and the through substrate via, a first nitride layer formed on the first oxide layer, and an enhancement layer formed on the first nitride layer; and a plurality of electrical connectors disposed in the film stack and contacting the through substrate via.

[0253] In some embodiments, the enhancement layer comprises a second oxide layer disposed on the first nitride layer and a second nitride layer disposed on the second oxide layer. In some embodiments, the second nitride layer is thicker than the first nitride layer. In some embodiments, the enhancement layer comprises a second nitride layer disposed on the first nitride layer, wherein the first nitride layer has implanted oxygen.

[0254] The foregoing summarizes the features of multiple embodiments or examples so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will recognize that they can easily use the present disclosure as a basis to design or modify other processes and structures that perform the same purpose and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, characterized in that: Include: A front oxide layer is disposed on a first substrate; A back oxide layer is disposed under the first substrate; a front nitride layer disposed on the front oxide layer; a back nitride layer disposed under the back oxide layer; an enhancement layer disposed below the back nitride layer; as well as A circuit structure is disposed on the front nitride layer.

2. The packaging structure according to claim 1, characterized in that: Also includes: A second substrate is disposed on the circuit structure, wherein the enhancement layer is exposed.

3. A packaging structure, characterized in that: Include: A first substrate having a front surface and a back surface; A back film laminate comprising: a back oxide layer disposed under the back surface of the first substrate; a back nitride layer disposed under the back oxide layer; and a backside enhancement layer disposed under the backside nitride layer; as well as A second substrate or a plurality of circuit connectors are disposed on the front surface of the first substrate.

4. The packaging structure according to claim 3, characterized in that: Also includes: A front oxide layer is disposed on the front surface of the first substrate; a front nitride layer disposed on the front oxide layer; a plurality of contact openings passing through the front nitride layer and the front oxide layer; as well as A plurality of electrical connectors are disposed in the plurality of contact openings.

5. The packaging structure according to claim 3 or claim 4, characterized in that: The first substrate comprises: An interposer substrate having a plurality of substrate through holes extending from a first side of the interposer substrate to a second side of the interposer substrate; an interconnect structure disposed on the first side of the interposer substrate; One or more integrated chips disposed on the interconnect structure; and A carrier substrate is disposed on the one or more integrated chips.

6. The packaging structure according to claim 3 or claim 4, characterized in that: The first substrate comprises: a carrier substrate; and One or more integrated chips are disposed on a first side of the carrier substrate, wherein the back film stack is disposed on a second side of the carrier substrate.

7. A packaging structure, characterized in that: Include: a substrate having a through-substrate hole formed therein, wherein the through-substrate hole protrudes above a first side of the substrate; One or more integrated chips bonded to a second side of the substrate; a film stack formed on the first side of the substrate, wherein the film stack comprises: a first oxide layer formed on the substrate and the substrate through-hole; a first nitride layer formed on the first oxide layer; and an enhancement layer formed on the first nitride layer; as well as A plurality of electrical connectors are disposed in the film stack and contact the substrate through-holes.

8. The packaging structure according to claim 7, characterized in that: The enhancement layer includes: a second oxide layer disposed on the first nitride layer; and A second nitride layer is disposed on the second oxide layer.

9. The packaging structure according to claim 8, characterized in that: The second nitride layer is thicker than the first nitride layer.

10. The packaging structure according to claim 7, characterized in that: The enhancement layer includes: A second nitride layer is disposed on the first nitride layer.

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