Compensation driving circuit and display panel

Abstract

The utility model discloses a compensation driving circuit and a display panel, the compensation driving circuit comprises a plurality of shift registers, the nth shift register comprises a pull-up module, a pull-down module and a voltage maintaining module, a voltage maintaining module is connected with at least one of a pull-up node and a pull-down node, an nth-level scanning driving line, an nth-level cascade line, a third potential line and a first potential line, so that the voltage maintaining module can maintain the high potential of the pull-up node and / or the high potential of the pull-down node; compared with the mode that a capacitor is adopted to maintain the high potential of the pull-up node and / or the high potential of the pull-down node, maintenance of the corresponding voltage can be achieved with a smaller frame space.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a compensation driving circuit and a display panel. Background Art

[0002] As people's tastes improve, higher requirements are placed on panel specifications, such as high refresh rate, high resolution, and long life. Compared with the use of flip film fixed gate driver chip (Gate COF), array substrate row driver (GOA) technology has great advantages in cost and functionality, so it has become the focus of panel development.

[0003] In a self-luminous display panel, a scanning driving signal and an initialization control signal provided by a scanning driving circuit and a compensation driving signal provided by a compensation driving circuit are usually required to jointly drive the pixel circuit. In some cases, the scanning driving circuit is also required to provide a corresponding luminescence control signal.

[0004] However, in the related art, the compensation driving circuit usually uses a capacitor to maintain or increase the corresponding potential. Since the capacitor occupies a large space, this will make the frame space occupied by the compensation driving circuit larger. Utility Model Content

[0005] The present application provides a compensation driving circuit and a display panel to alleviate the technical problem that the compensation driving circuit requires a large frame space.

[0006] In a first aspect, the present application provides a compensation driving circuit, which includes multiple shift registers, wherein the n-th level shift register includes a pull-up module, a pull-down module and a voltage maintaining module, the pull-up module is connected to the pull-up node, the first potential line and the n-th level compensation driving line; the pull-down module is connected to the pull-down node, the second potential line and the n-th level compensation driving line; the voltage maintaining module is connected to at least one of the pull-up node and the pull-down node, the n-th level scanning driving line, the n-th level cascade line, the third potential line and the first potential line, and the voltage maintaining module maintains the high potential of the pull-up node and / or the high potential of the pull-down node.

[0007] In some embodiments, the voltage maintaining module includes an upper voltage maintaining submodule and a lower voltage maintaining submodule, the upper voltage maintaining submodule is connected to the n-th level scan drive line, the n-th level cascade line, the pull-up node, the first potential line and the third potential line, and the upper voltage maintaining submodule maintains the high potential of the pull-up node; the lower voltage maintaining submodule is connected to the n-th level scan drive line, the n-th level cascade line, the pull-up node, the first potential line and the third potential line, and the lower voltage maintaining submodule maintains the high potential of the pull-down node.

[0008] In some embodiments, the upper voltage maintaining submodule includes a first transistor, a second transistor and a third transistor, the first electrode of the first transistor is connected to the n-th level scan drive line, the gate of the first transistor is connected to the n-th level cascade line, and the first transistor is an N-channel transistor; the gate of the second transistor is connected to the first electrode of the first transistor, the first electrode of the second transistor is connected to the first potential line, the second electrode of the second transistor is connected to the pull-up node, and the second transistor is a P-channel transistor; the first electrode of the third transistor is connected to the first electrode of the first transistor and the gate of the second transistor, the second electrode of the third transistor is connected to the third potential line, the gate of the third transistor is connected to the pull-up node and the second electrode of the second transistor, and the third transistor is an N-channel transistor.

[0009] In some embodiments, the lower voltage maintaining submodule includes a fourth transistor, a fifth transistor and a sixth transistor, the gate of the fourth transistor is connected to the second electrode of the first transistor, the first electrode of the fourth transistor is connected to the third potential line, and the fourth transistor is an N-channel transistor; the gate of the fifth transistor is connected to the second electrode of the fourth transistor, the first electrode of the fifth transistor is connected to the first potential line, the second electrode of the fifth transistor is connected to the second electrode of the first transistor and the gate of the fourth transistor, and the fifth transistor is a P-channel transistor; the gate of the sixth transistor is connected to the second electrode of the fourth transistor and the gate of the fifth transistor, the first electrode of the sixth transistor is connected to the first potential line, the second electrode of the sixth transistor is connected to the pull-down node, and the sixth transistor is a P-channel transistor.

[0010] In some embodiments, the voltage maintaining module includes an upper voltage maintaining submodule, which connects the nth level scan drive line, the nth level cascade line, the pull-up node, the first potential line and the third potential line, and the upper voltage maintaining submodule maintains the high potential of the pull-up node.

[0011] In some embodiments, the upper voltage maintaining submodule includes a first transistor, a second transistor and a third transistor, the first electrode of the first transistor is connected to the n-th level scan drive line, the gate of the first transistor is connected to the n-th level cascade line, and the first transistor is an N-channel transistor; the gate of the second transistor is connected to the first electrode of the first transistor, the first electrode of the second transistor is connected to the first potential line, the second electrode of the second transistor is connected to the pull-up node, and the second transistor is a P-channel transistor; the first electrode of the third transistor is connected to the first electrode of the first transistor and the gate of the second transistor, the second electrode of the third transistor is connected to the third potential line, the gate of the third transistor is connected to the pull-up node and the second electrode of the second transistor, and the third transistor is an N-channel transistor.

[0012] In some embodiments, the voltage maintaining module includes a lower voltage maintaining submodule, which connects the nth level scan drive line, the nth level cascade line, the pull-up node, the first potential line and the third potential line, and the lower voltage maintaining submodule maintains the high potential of the pull-down node.

[0013] In some embodiments, the lower voltage maintaining submodule includes a first transistor, a fourth transistor, a fifth transistor and a sixth transistor, the first electrode of the first transistor is connected to the n-th level scan drive line, the gate of the first transistor is connected to the n-th level cascade line, and the first transistor is an N-channel transistor; the gate of the fourth transistor is connected to the second electrode of the first transistor, the first electrode of the fourth transistor is connected to the third potential line, and the fourth transistor is an N-channel transistor; the gate of the fifth transistor is connected to the second electrode of the fourth transistor, the first electrode of the fifth transistor is connected to the first potential line, the second electrode of the fifth transistor is connected to the second electrode of the first transistor and the gate of the fourth transistor, and the fifth transistor is a P-channel transistor; the gate of the sixth transistor is connected to the second electrode of the fourth transistor and the gate of the fifth transistor, the first electrode of the sixth transistor is connected to the first potential line, the second electrode of the sixth transistor is connected to the pull-down node, and the sixth transistor is a P-channel transistor.

[0014] In some embodiments, the first potential line transmits a first potential signal, the second potential line transmits a second potential signal, and the third potential line transmits a third potential signal; the voltage of the first potential signal is higher than the voltage of the second potential signal, and the voltage of the second potential signal is higher than the voltage of the third potential signal.

[0015] In a second aspect, the present application provides a display panel, which includes the above-mentioned compensation driving circuit.

[0016] The compensation driving circuit and display panel provided in the present application connect at least one of the pull-up node and the pull-down node, the n-th level scanning driving line, the n-th level cascade line, the third potential line and the first potential line through a voltage maintaining module, so that the voltage maintaining module can maintain the high potential of the pull-up node and / or the high potential of the pull-down node. Compared with using a capacitor to maintain the high potential of the pull-up node and / or the high potential of the pull-down node, the corresponding voltage can be maintained with a smaller frame space.

[0017] Furthermore, compared to a compensation driving circuit having more components, the compensation driving circuit in each embodiment of the present application uses fewer components, which can further reduce the required frame space. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0019] Figure 1It is a structural schematic diagram of a compensation driving circuit in the related art.

[0020] Figure 2 for Figure 1 Schematic diagram of the waveform of the compensation driving signal output by the compensation driving circuit shown.

[0021] Figure 3 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0022] Figure 4 A first structural schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0023] Figure 5 A second structural schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0024] Figure 6 A schematic diagram of the cascade structure of the compensation drive circuit provided in an embodiment of the present application.

[0025] Figure 7 A schematic diagram of the structure of a compensation drive circuit provided in an embodiment of the present application.

[0026] Figure 8 for Figure 7 A structural diagram of a medium voltage maintenance module.

[0027] Fig. 9 for Figure 7 Another structural schematic diagram of the medium voltage maintenance module.

[0028] Fig.10 for Figure 7 The timing diagram of the compensation driving circuit shown. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. The features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present utility model, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0031] Figure 1The compensation driving circuit in the related art is a schematic diagram of the structure. The compensation driving circuit includes a shift register, the shift register includes a first pull-up transistor T11 and a second pull-up transistor T12, the first electrode of the first pull-up transistor T11 is connected to the first potential line, the second electrode of the first pull-up transistor T11 is connected to the first electrode of the second pull-up transistor T12, the second electrode of the second pull-up transistor T12 is connected to the pull-up node Q, and the n-th level initialization control line is connected to the gate of the first pull-up transistor T11 and the gate of the second pull-up transistor T12.

[0032] The shift register also includes a pull-up transistor T21 and a first capacitor C1, the first electrode of the pull-up transistor T21 is connected to the first potential line, the gate of the pull-up transistor T21 is connected to the pull-up node Q and one end of the first capacitor C1, and the second electrode of the pull-up transistor T21 is connected to the nth level compensation drive line and the other end of the first capacitor C1.

[0033] The shift register further includes a seventh transistor T55, a first electrode of the seventh transistor T55 is connected to the pull-down node QB, a second electrode of the seventh transistor T55 is connected to the third potential line, and a gate of the seventh transistor T55 is connected to the pull-up node Q.

[0034] The shift register further includes an eighth transistor T56, a first electrode of the eighth transistor T56 is connected to the pull-down node QB, a second electrode of the eighth transistor T56 is connected to the third potential line, and a gate of the eighth transistor T56 is connected to the nth stage initialization control line.

[0035] The shift register further includes a pull-down transistor T31, a first electrode of the pull-down transistor T31 is connected to the second potential line, a gate of the pull-down transistor T31 is connected to the pull-down node QB, and a second electrode of the pull-down transistor T31 is connected to the n-th level compensation driving line.

[0036] The shift register also includes a ninth transistor T69, a tenth transistor T41 and an eleventh transistor T42, the first electrode of the tenth transistor T41 is connected to the third potential line, the second electrode of the tenth transistor T41 is connected to the first electrode of the ninth transistor T69, the first electrode of the eleventh transistor T42 and the node N[n], the second electrode of the eleventh transistor T42 is connected to the pull-up node Q, the n-th level initialization control line is connected to the gate of the tenth transistor T41 and the gate of the eleventh transistor T42, the second electrode of the ninth transistor T69 is connected to the first potential line, and the gate of the ninth transistor T69 is connected to the pull-up node Q.

[0037] The shift register also includes a twelfth transistor T43 and a thirteenth transistor T44, the first electrode of the twelfth transistor T43 is connected to the pull-up node Q, the second electrode of the twelfth transistor T43 is connected to the first electrode of the thirteenth transistor T44 and the node N[n], the second electrode of the thirteenth transistor T44 is connected to the third potential line, and the pull-down node QB is connected to the gate of the twelfth transistor T43 and the gate of the thirteenth transistor T44.

[0038] The shift register also includes a fourteenth transistor T71, a fifteenth transistor T72, a sixteenth transistor T73, a seventeenth transistor T74 and a second capacitor C2, a first electrode of the fourteenth transistor T71 is connected to the n-th level scan drive line, a second electrode of the fourteenth transistor T71 is connected to the first electrode of the fifteenth transistor T72 and the first electrode of the sixteenth transistor T73, a second electrode of the fifteenth transistor T72 is connected to one end of the second capacitor C2, a gate of the sixteenth transistor T73 and a gate of the seventeenth transistor T74, a first potential line is connected to the second electrode of the sixteenth transistor T73, the other end of the second capacitor C2 and the first electrode of the seventeenth transistor T74, a second electrode of the seventeenth transistor T74 is connected to the pull-down node QB, and the n-th level cascade line is connected to the gate of the fourteenth transistor T71 and the gate of the fifteenth transistor T72.

[0039] Figure 2 The figure shows a waveform diagram of the compensation driving signal, wherein a high potential can turn on the corresponding transistor in the pixel circuit of the display panel to achieve compensation of the pixel circuit, and a low potential can turn off the transistor. Regardless of whether it is a high potential or a low potential, the first capacitor C1 and the second capacitor C2 are required to maintain the high potential of the pull-up node Q and the high potential of the pull-down node QB, respectively.

[0040] The sustaining capability is positively correlated with the capacity of the first capacitor C1 and the second capacitor C2. As the capacity increases, the occupied area of ​​the first capacitor C1 and the second capacitor C2 also increases, which requires a larger frame space.

[0041] Figure 3 The structure diagram of the display panel provided in the embodiment of the present application is as follows. The display panel includes a scan driving circuit 100, a compensation driving circuit 200, a timing controller 300, a data driver 400 and a pixel unit 500.

[0042] The pixel unit 500 includes a plurality of pixel circuits 510 distributed in an array. The timing controller 300 can generate a scan drive control signal SCS, a data drive control signal DCS and a source drive signal DS based on an externally provided synchronization signal. The data driver 400 can generate corresponding data signals D1, D2...Dm according to the source drive signal DS, and transmit them to the corresponding pixel circuit 510. The scan drive circuit 100 can generate corresponding scan drive signals Gn[1]...Gn[n] and initialization control signals INI[1]...INI[n] to the corresponding pixel circuit 510 based on the scan drive control signal SCS. The compensation drive circuit 200 can generate corresponding compensation drive signals REF[1]...REF[n] to the corresponding pixel circuit 510 based on the scan drive control signal SCS.

[0043] In some of the embodiments, the scan driving circuit 100 may also generate corresponding light emitting control signals EM[1] . . . EM[n] to the corresponding pixel circuits 510 according to the scan driving control signal SCS.

[0044] The pixel circuit 510 may be a 4T1C or 5T1C pixel circuit. Figure 4 As shown, the pixel circuit 510 includes a driving transistor T1, a writing transistor T2, a compensation transistor T3, an initialization transistor T4, a storage capacitor Cst and a light emitting device OLED.

[0045] The first electrode of the driving transistor T1 is connected to the first power signal VDD, the second electrode of the driving transistor T1 is connected to the anode of the light emitting device OLED, the first electrode of the initialization transistor T4 and one end of the storage capacitor Cst, the cathode of the light emitting device OLED is connected to the second power signal VSS, the second electrode of the initialization transistor T4 is connected to the initialization signal Vini, and the gate of the initialization transistor T4 is connected to the n-th level initialization control signal INI[n]. The other end of the storage capacitor Cst is connected to the gate of the driving transistor T1, the first electrode of the write transistor T2, and the first electrode of the compensation transistor T3, the second electrode of the write transistor T2 is connected to the data signal Vdata (one of D1, D2...Dm), and the gate of the write transistor T2 is connected to the n-th level scanning drive signal Gn[n]. The second electrode of the compensation transistor T3 is connected to the reference voltage signal Vref, and the gate of the compensation transistor T3 is connected to the n-th level compensation drive signal REF[n].

[0046] Another example Figure 5 As shown, the pixel circuit 510 is Figure 4A light-emitting control transistor T5 is added on the basis of the first power supply signal VDD, the second electrode of the light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1, and the gate of the light-emitting control transistor T5 is connected to the n-th level light-emitting control signal EM[n]. Figure 4 Be consistent.

[0047] It should be noted that, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode may be the drain; or, when the first electrode is the drain, the second electrode may be the source. Vg represents the gate potential of the driving transistor T1. Vs represents the source potential of the driving transistor T1.

[0048] Figure 6 Schematic diagram of the cascade structure of the compensation driving circuit 200 provided in an embodiment of the present application. Among them, the scanning driving circuit 100 can provide multiple cascade signals, such as the n-3rd level cascade signal Cout[n-3], the nth level cascade signal Cout[n], the n+3rd level cascade signal Cout[n+3], etc. The scanning driving circuit 100 can also provide multiple initialization control signals, such as the n-3rd level initialization control signal INI[n-3], the nth level initialization control signal INI[n], the n+3rd level initialization control signal INI[n+3], etc. The scanning driving circuit 100 can also provide multiple scanning driving signals, such as the n-3rd level scanning driving signal Gn[n-3], the nth level scanning driving signal Gn[n], the n+3rd level scanning driving signal Gn[n+3], etc.

[0049] The compensation drive circuit 200 may include multiple shift registers, such as an n-3th stage shift register 210 for outputting an n-3th stage compensation drive signal REF[n-3], an nth stage shift register 220 for outputting an nth stage compensation drive signal REF[n], an n+3th stage shift register 230 for outputting an n+3th stage compensation drive signal REF[n+3], and the like.

[0050] Exemplarily, the scan drive circuit 100 can provide the n-3rd-level initialization control signal INI[n-3], the n-3rd-level cascade signal Cout[n-3], and the n-3rd-level scan drive signal Gn[n-3] for the n-3rd-level shift register 210. The scan drive circuit 100 can also provide the nth-level initialization control signal INI[n], the nth-level cascade signal Cout[n], and the nth-level scan drive signal Gn[n] for the nth-level shift register 220. The scan drive circuit 100 can also provide the n+3rd-level initialization control signal INI[n+3], the n+3rd-level cascade signal Cout[n+3], and the n+3rd-level scan drive signal Gn[n+3] for the n+3rd-level shift register 230. By analogy, the scan drive circuit 100 can provide various required signals for the compensation drive circuit 200.

[0051] This embodiment provides a compensation driving circuit 200, which includes a plurality of shift registers. Figures 7 to 10 , wherein the n-th stage shift register 220 includes a pull-up module 10, a pull-down module 20 and a voltage maintaining module 30, the pull-up module 10 is connected to the pull-up node Q, the first potential line and the n-th stage compensation driving line; the pull-down module 20 is connected to the pull-down node QB, the second potential line and the n-th stage compensation driving line; the voltage maintaining module 30 is connected to at least one of the pull-up node Q and the pull-down node QB, the n-th stage scanning driving line, the n-th stage cascade line, the third potential line and the first potential line, and the voltage maintaining module 30 maintains the high potential of the pull-up node Q and / or the high potential of the pull-down node QB.

[0052] It can be understood that the compensation driving circuit 200 provided in this embodiment connects at least one of the pull-up node Q and the pull-down node QB, the n-th level scanning driving line, the n-th level cascade line, the third potential line and the first potential line through the voltage maintaining module 30, so that the voltage maintaining module 30 can maintain the high potential of the pull-up node Q and / or the high potential of the pull-down node QB. Compared with using a capacitor to maintain the high potential of the pull-up node Q and / or the high potential of the pull-down node QB, the corresponding voltage can be maintained with a smaller border space.

[0053] Furthermore, compared to the compensation driving circuit 200 with more components, the compensation driving circuit 200 in each embodiment of the present application uses fewer components, which can further reduce the required frame space.

[0054] It should be noted that, in the present application, a high potential is a potential that can turn on an N-channel transistor or turn off a P-channel transistor, and a low potential is a potential that can turn on a P-channel transistor or turn off an N-channel transistor.

[0055] Among them, the first potential line transmits the first potential signal VGH, the second potential line transmits the second potential signal VGL3, and the third potential line transmits the third potential signal VGL2; the voltage of the first potential signal VGH is higher than the voltage of the second potential signal VGL3, and the voltage of the second potential signal VGL3 is higher than the voltage of the third potential signal VGL2.

[0056] The n-th level compensation driving line transmits the n-th level compensation driving signal REF[n], the n-th level scanning driving line transmits the n-th level scanning driving signal Gn[n], and the n-th level cascade line transmits the n-th level cascade signal Cout[n].

[0057] In one embodiment, if Figure 7 As shown, the voltage maintenance module 30 includes an upper voltage maintenance submodule 301 and a lower voltage maintenance submodule 302. The upper voltage maintenance submodule 301 is connected to the n-th level scan drive line, the n-th level cascade line, the pull-up node Q, the first potential line and the third potential line. The lower voltage maintenance submodule 302 is connected to the n-th level scan drive line, the n-th level cascade line, the pull-up node Q, the first potential line and the third potential line.

[0058] It should be noted that the upper voltage maintenance submodule 301 is used to maintain the high potential of the pull-up node Q, that is, when the pull-up node Q is at a high potential, the upper voltage maintenance submodule 301 can maintain the high potential of the pull-up node Q for a longer time. The lower voltage maintenance submodule 302 is used to maintain the high potential of the pull-down node QB, that is, when the pull-down node QB is at a low potential, the lower voltage maintenance submodule 302 can maintain the high potential of the pull-down node QB for a longer time.

[0059] In some other embodiments, such as Figure 8 As shown, the voltage maintaining module 30 may only include an upper voltage maintaining submodule 301, which is connected to the n-th level scan drive line, the n-th level cascade line, the pull-up node Q, the first potential line and the third potential line, and the upper voltage maintaining submodule 301 maintains the high potential of the pull-up node Q.

[0060] In some other embodiments, such as Fig. 9 As shown, the voltage maintaining module 30 may also only include a lower voltage maintaining sub-module 302, which is connected to the n-th level scan drive line, the n-th level cascade line, the pull-up node Q, the first potential line and the third potential line, and the lower voltage maintaining sub-module 302 maintains the high potential of the pull-down node QB.

[0061] In one embodiment, if Figure 7 , Figure 8As shown, the upper voltage maintaining submodule 301 includes a first transistor T51, a second transistor T53 and a third transistor T61, the first electrode of the first transistor T51 is connected to the n-th level scan driving line, the gate of the first transistor T51 is connected to the n-th level cascade line, and the first transistor T51 is an N-channel transistor; the gate of the second transistor T53 is connected to the first electrode of the first transistor T51, the first electrode of the second transistor T53 is connected to the first potential line, the second electrode of the second transistor T53 is connected to the pull-up node Q, and the second transistor T53 is a P-channel transistor; the first electrode of the third transistor T61 is connected to the first electrode of the first transistor T51 and the gate of the second transistor T53, the second electrode of the third transistor T61 is connected to the third potential line, the gate of the third transistor T61 is connected to the pull-up node Q and the second electrode of the second transistor T53, and the third transistor T61 is an N-channel transistor.

[0062] It should be noted that, in the present application, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or, when the first electrode is the drain, the second electrode is the source.

[0063] Among them, when the cascade signal is at a high potential, the first transistor T51 is turned on; at this time, since the n-th level scan drive signal Gn[n] is at a low potential, the second transistor T53 is turned on, so that the pull-up node Q is at a high potential, and the high potential can turn on the third transistor T61, so that the gate of the second transistor T53 is always at the low potential of the third potential signal VGL2, thereby maintaining the high potential of the pull-up node Q.

[0064] In one embodiment, if Figure 7 As shown, the lower voltage maintaining submodule 302 includes a fourth transistor T52, a fifth transistor T54 and a sixth transistor T62, the gate of the fourth transistor T52 is connected to the second electrode of the first transistor T51, the first electrode of the fourth transistor T52 is connected to the third potential line, and the fourth transistor T52 is an N-channel transistor; the gate of the fifth transistor T54 is connected to the second electrode of the fourth transistor T52, the first electrode of the fifth transistor T54 is connected to the first potential line, the second electrode of the fifth transistor T54 is connected to the second electrode of the first transistor T51 and the gate of the fourth transistor T52, and the fifth transistor T54 is a P-channel transistor; the gate of the sixth transistor T62 is connected to the second electrode of the fourth transistor T52 and the gate of the fifth transistor T54, the first electrode of the sixth transistor T62 is connected to the first potential line, the second electrode of the sixth transistor T62 is connected to the pull-down node QB, and the sixth transistor T62 is a P-channel transistor.

[0065] In another embodiment, Fig. 9As shown, the lower voltage maintaining submodule 302 may also include a first transistor T51, a fourth transistor T52, a fifth transistor T54 and a sixth transistor T62, wherein the first electrode of the first transistor T51 is connected to the n-th level scan driving line, the gate of the first transistor T51 is connected to the n-th level cascade line, and the first transistor T51 is an N-channel transistor; the gate of the fourth transistor T52 is connected to the second electrode of the first transistor T51, the first electrode of the fourth transistor T52 is connected to the third potential line, and the fourth transistor T52 is an N-channel transistor; the gate of the fifth transistor T54 is connected to the second electrode of the fourth transistor T52, the first electrode of the fifth transistor T54 is connected to the first potential line, the second electrode of the fifth transistor T54 is connected to the second electrode of the first transistor T51 and the gate of the fourth transistor T52, and the fifth transistor T54 is a P-channel transistor; the gate of the sixth transistor T62 is connected to the second electrode of the fourth transistor T52 and the gate of the fifth transistor T54, the first electrode of the sixth transistor T62 is connected to the first potential line, the second electrode of the sixth transistor T62 is connected to the pull-down node QB, and the sixth transistor T62 is a P-channel transistor.

[0066] It should be noted that, regardless of Figure 7 still Fig. 9 In the lower voltage maintaining submodule 302 shown in the figure, when the nth level scan drive signal Gn[n] and the cascade signal are both at a high potential, the first transistor T51 is turned on, and the fourth transistor T52 is turned on, so that the gate of the fifth transistor T54 and the gate of the sixth transistor T62 are at a low potential of the third potential signal VGL2, so that the fifth transistor T54 and the sixth transistor T62 are both turned on. Since the opening of the fifth transistor T54 can keep the gate of the fourth transistor T52 at a high potential, the sixth transistor T62 can be continuously turned on, so that the high potential of the pull-down node QB can be maintained.

[0067] In one embodiment, if Figure 7 As shown, the pull-up module 10 includes a pull-up transistor T21, a first electrode of the pull-up transistor T21 is connected to the first potential line, a gate of the pull-up transistor T21 is connected to the pull-up node Q, and a second electrode of the pull-up transistor T21 is connected to the nth level compensation driving line.

[0068] It should be noted that the first potential signal VGH transmitted in the first potential line may be a high potential in some implementations, and may be a low potential in other embodiments.

[0069] The pull-up transistor T21 may be an N-channel thin film transistor in some embodiments, and may be a P-channel thin film transistor in other embodiments.

[0070] In one embodiment, if Figure 7As shown, the pull-down module 20 includes a pull-down transistor T31, a first electrode of the pull-down transistor T31 is connected to the second potential line, a gate of the pull-down transistor T31 is connected to the pull-down node QB, and a second electrode of the pull-down transistor T31 is connected to the nth level compensation driving line.

[0071] It should be noted that the second potential signal VGL3 transmitted in the second potential line may be a high potential in some implementations, and may be a low potential in other embodiments.

[0072] The pull-down transistor T31 may be an N-channel thin film transistor in some embodiments, and may be a P-channel thin film transistor in other embodiments.

[0073] In one embodiment, if Figure 7 As shown, the n-th stage shift register 220 also includes a first pull-up transistor T11 and a second pull-up transistor T12, the first electrode of the first pull-up transistor T11 is connected to the first potential line, the second electrode of the first pull-up transistor T11 is connected to the first electrode of the second pull-up transistor T12, the second electrode of the second pull-up transistor T12 is connected to the pull-up node Q, and the n-th stage initialization control line is connected to the gate of the first pull-up transistor T11 and the gate of the second pull-up transistor T12.

[0074] It should be noted that the n-th stage initialization control line is used to transmit the n-th stage initialization control signal INI[n]. The channel type of the first pull-up transistor T11 is the same as the channel type of the second pull-up transistor T12, and illustratively, both may be N-channel types.

[0075] In one embodiment, if Figure 7 As shown, the nth stage shift register 220 further includes a seventh transistor T55, a first electrode of the seventh transistor T55 is connected to the pull-down node QB, a second electrode of the seventh transistor T55 is connected to the third potential line, and a gate of the seventh transistor T55 is connected to the pull-up node Q.

[0076] It should be noted that the potential of the third potential signal VGL2 transmitted in the third potential line may be a low potential. The seventh transistors T55 may be N-channel thin film transistors by way of example.

[0077] In one embodiment, if Figure 7 As shown, the nth stage shift register 220 further includes an eighth transistor T56, a first electrode of the eighth transistor T56 is connected to the pull-down node QB, a second electrode of the eighth transistor T56 is connected to the third potential line, and a gate of the eighth transistor T56 is connected to the nth stage initialization control line.

[0078] It should be noted that the eighth transistors T56 may be N-channel thin film transistors by way of example.

[0079] In one embodiment, if Figure 7 As shown, the n-th stage shift register 220 also includes a ninth transistor T69, a tenth transistor T41 and an eleventh transistor T42, the first electrode of the tenth transistor T41 is connected to the third potential line, the second electrode of the tenth transistor T41 is connected to the first electrode of the ninth transistor T69, the first electrode of the eleventh transistor T42 and the node N[n], the second electrode of the eleventh transistor T42 is connected to the pull-up node Q, the n-th stage initialization control line is connected to the gate of the tenth transistor T41 and the gate of the eleventh transistor T42, the second electrode of the ninth transistor T69 is connected to the first potential line, and the gate of the ninth transistor T69 is connected to the pull-up node Q.

[0080] It should be noted that the tenth transistor T41 and the eleventh transistor T42 can both be N-channel thin film transistors, which can pull down the potential of the pull-up node Q to the potential of the third potential signal VGL2 when the n-th level initialization control signal INI[n] is at a high potential. The ninth transistor T69 can also be an N-channel thin film transistor, which can pull up the potential of the node N[n] to the potential of the first potential signal VGH when the pull-up node Q is at a high potential, thereby preventing the pull-up node Q from leaking through at least one of the tenth transistor T41 and the eleventh transistor T42.

[0081] In one embodiment, if Figure 7 As shown, the n-th stage shift register 220 also includes a twelfth transistor T43 and a thirteenth transistor T44, the first electrode of the twelfth transistor T43 is connected to the pull-up node Q, the second electrode of the twelfth transistor T43 is connected to the first electrode of the thirteenth transistor T44 and the node N[n], the second electrode of the thirteenth transistor T44 is connected to the third potential line, and the pull-down node QB is connected to the gate of the twelfth transistor T43 and the gate of the thirteenth transistor T44.

[0082] It should be noted that the twelfth transistor T43 and the thirteenth transistor T44 can both be N-channel thin film transistors, which can pull down the potential of the pull-up node Q to the potential of the third potential signal VGL2 when the pull-down node QB is at a high potential. The node N[n] can prevent the pull-up node Q from leaking through at least one of the twelfth transistor T43 and the thirteenth transistor T44.

[0083] It should be noted that the second transistor T53, the fifth transistor T54 and the sixth transistor T62 can be low-temperature polysilicon thin film transistors with higher mobility, which can achieve fast output while reducing the channel width of these transistors. Figure 7 The other transistors shown in the figure may be low-temperature polysilicon thin film transistors in some embodiments or indium gallium zinc oxide thin film transistors in other embodiments.

[0084] exist Fig.10 In the case where the n-th level initialization control signal INI[n] is at a high potential, the first pull-up transistor T11 and the second pull-up transistor T12 are both turned on, and the pull-up node Q outputs a high potential, thereby turning on the pull-up transistor T21, so that the n-th level compensation drive signal REF[n] is also at a high potential; at the same time, the n-th level scan drive signal Gn[n] is at a low potential, the cascade signal is at a high potential, and the upper voltage maintenance submodule 301 in the voltage maintenance module 30 can maintain the high potential of the pull-up node Q. In this way, the pull-up transistor T21 can be continuously turned on, and the first potential signal VGH that continuously outputs a high potential is the n-th level compensation drive signal REF[n]. In this case, the upper voltage maintenance submodule 301 can play the same role as Figure 1 The first capacitor C1 shown in FIG.

[0085] When the n-th level scanning driving signal Gn[n] and the cascade signal are both at high potential, the tenth transistor T41 and the eleventh transistor T42 are both turned on, and the pull-up node Q is at a low potential; at the same time, the first transistor T51 is turned on, so that the gate of the fourth transistor T52 is at a high potential, so that the fourth transistor T52 is turned on, so that the gate of the fifth transistor T54 and the gate of the sixth transistor T62 are connected to the low potential third potential signal VGL2, the fifth transistor T54 and the sixth transistor T62 are both turned on, the opening of the fifth transistor T54 can keep the gate of the fourth transistor T52 at a high potential, and the opening of the sixth transistor T62 can keep the pull-down node QB at a high potential, so that the pull-down transistor T31 is continuously turned on to output the low potential second potential signal VGL3 as the n-th level compensation driving signal REF[n]. In this case, the lower voltage maintenance submodule 302 can play the same role as Figure 1 The second capacitor C2 shown in FIG.

[0086] In summary, compared with Figure 1 Two large-area first capacitors C1 and second capacitors C2 are used. Figure 7 Although two transistors with a smaller footprint are added, the layout can still be implemented with a smaller border space while maintaining the same high stability.

[0087] In one embodiment, the present embodiment provides a display panel, and the display panel includes the compensation driving circuit 200 mentioned above.

[0088] It can be understood that since the display panel provided in this embodiment includes the above-mentioned compensation driving circuit 200, it can also connect at least one of the pull-up node Q and the pull-down node QB, the n-th level scanning driving line, the n-th level cascade line, the third potential line and the first potential line through the voltage maintaining module 30, so that the voltage maintaining module 30 can maintain the high potential of the pull-up node Q and / or the high potential of the pull-down node QB. Compared with using a capacitor to maintain the high potential of the pull-up node Q and / or the high potential of the pull-down node QB, the corresponding voltage can be maintained with a smaller border space.

[0089] Furthermore, compared to the compensation driving circuit 200 with more components, the compensation driving circuit 200 in each embodiment of the present application uses fewer components, which can further reduce the required frame space.

[0090] Among them, the display panel can be a self-luminous display panel, and the self-luminous display panel can be exemplarily an organic light emitting diode display panel, a micro light emitting diode display panel, a mini light emitting diode display panel or a quantum dot light emitting diode display panel.

[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0092] The compensation driving circuit 200 and the display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A compensation driving circuit, characterized in that: The compensation driving circuit includes a plurality of shift registers, wherein the n-th stage shift register includes: A pull-up module, the pull-up module is connected to the pull-up node, the first potential line and the nth level compensation driving line; A pull-down module, the pull-down module is connected to the pull-down node, the second potential line and the n-th level compensation driving line; A voltage maintaining module, wherein the voltage maintaining module is connected to at least one of the pull-up node and the pull-down node, the n-th level scan drive line, the n-th level cascade line, the third potential line and the first potential line, and the voltage maintaining module maintains a high potential of the pull-up node and / or a high potential of the pull-down node.

2. The compensation driving circuit according to claim 1, characterized in that: The voltage maintenance module comprises: an upper voltage maintaining submodule, the upper voltage maintaining submodule being connected to the n-th level scan driving line, the n-th level cascade line, the pull-up node, the first potential line and the third potential line, the upper voltage maintaining submodule maintaining a high potential of the pull-up node; A lower voltage maintaining submodule is connected to the n-th level scan drive line, the n-th level cascade line, the pull-up node, the first potential line and the third potential line, and the lower voltage maintaining submodule maintains a high potential of the pull-down node.

3. The compensation driving circuit according to claim 2, characterized in that: The upper voltage maintaining submodule comprises: a first transistor, wherein a first electrode of the first transistor is connected to the n-th level scanning driving line, a gate of the first transistor is connected to the n-th level cascade line, and the first transistor is an N-channel transistor; a second transistor, wherein a gate of the second transistor is connected to a first electrode of the first transistor, a first electrode of the second transistor is connected to the first potential line, a second electrode of the second transistor is connected to the pull-up node, and the second transistor is a P-channel transistor; A third transistor, wherein the first electrode of the third transistor is connected to the first electrode of the first transistor and the gate of the second transistor, the second electrode of the third transistor is connected to the third potential line, the gate of the third transistor is connected to the pull-up node and the second electrode of the second transistor, and the third transistor is an N-channel transistor.

4. The compensation driving circuit according to claim 3, characterized in that: The lower voltage maintaining submodule comprises: a fourth transistor, wherein a gate of the fourth transistor is connected to the second electrode of the first transistor, a first electrode of the fourth transistor is connected to the third potential line, and the fourth transistor is an N-channel transistor; a fifth transistor, wherein a gate of the fifth transistor is connected to the second electrode of the fourth transistor, a first electrode of the fifth transistor is connected to the first potential line, a second electrode of the fifth transistor is connected to the second electrode of the first transistor and the gate of the fourth transistor, and the fifth transistor is a P-channel transistor; A sixth transistor, wherein the gate of the sixth transistor is connected to the second electrode of the fourth transistor and the gate of the fifth transistor, the first electrode of the sixth transistor is connected to the first potential line, the second electrode of the sixth transistor is connected to the pull-down node, and the sixth transistor is a P-channel transistor.

5. The compensation driving circuit according to claim 1, characterized in that: The voltage maintaining module includes an upper voltage maintaining submodule, which connects the n-th level scan drive line, the n-th level cascade line, the pull-up node, the first potential line and the third potential line, and maintains the high potential of the pull-up node.

6. The compensation driving circuit according to claim 5, characterized in that: The upper voltage maintaining submodule comprises: a first transistor, wherein a first electrode of the first transistor is connected to the n-th level scanning driving line, a gate of the first transistor is connected to the n-th level cascade line, and the first transistor is an N-channel transistor; a second transistor, wherein a gate of the second transistor is connected to a first electrode of the first transistor, a first electrode of the second transistor is connected to the first potential line, a second electrode of the second transistor is connected to the pull-up node, and the second transistor is a P-channel transistor; A third transistor, wherein the first electrode of the third transistor is connected to the first electrode of the first transistor and the gate of the second transistor, the second electrode of the third transistor is connected to the third potential line, the gate of the third transistor is connected to the pull-up node and the second electrode of the second transistor, and the third transistor is an N-channel transistor.

7. The compensation driving circuit according to claim 1, characterized in that: The voltage maintaining module includes a lower voltage maintaining submodule, which is connected to the n-th level scan drive line, the n-th level cascade line, the pull-up node, the first potential line and the third potential line, and the lower voltage maintaining submodule maintains the high potential of the pull-down node.

8. The compensation driving circuit according to claim 7, characterized in that: The lower voltage maintaining submodule comprises: a first transistor, wherein a first electrode of the first transistor is connected to the n-th level scanning driving line, a gate of the first transistor is connected to the n-th level cascade line, and the first transistor is an N-channel transistor; a fourth transistor, wherein a gate of the fourth transistor is connected to the second electrode of the first transistor, a first electrode of the fourth transistor is connected to the third potential line, and the fourth transistor is an N-channel transistor; a fifth transistor, wherein a gate of the fifth transistor is connected to the second electrode of the fourth transistor, a first electrode of the fifth transistor is connected to the first potential line, a second electrode of the fifth transistor is connected to the second electrode of the first transistor and the gate of the fourth transistor, and the fifth transistor is a P-channel transistor; A sixth transistor, wherein the gate of the sixth transistor is connected to the second electrode of the fourth transistor and the gate of the fifth transistor, the first electrode of the sixth transistor is connected to the first potential line, the second electrode of the sixth transistor is connected to the pull-down node, and the sixth transistor is a P-channel transistor.

9. The compensation driving circuit according to any one of claims 1 to 8, characterized in that: The first potential line transmits a first potential signal, the second potential line transmits a second potential signal, and the third potential line transmits a third potential signal; The voltage of the first potential signal is higher than the voltage of the second potential signal, and the voltage of the second potential signal is higher than the voltage of the third potential signal.

10. A display panel, characterized in that: The display panel comprises the compensation driving circuit as claimed in any one of claims 1 to 9.

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