Shift register, gate drive circuit and display device

Abstract

The utility model provides a shift register, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register comprises a first input sub-circuit, an output sub-circuit, a first pull-down control sub-circuit, a second pull-down control sub-circuit, a first pull-down sub-circuit and a second pull-down sub-circuit, a connection node of the first input sub-circuit and the output sub-circuit is a pull-up node, a connection node of the first pull-down control sub-circuit and the first pull-down sub-circuit is a first pull-down node, and a connection node of the second pull-down control sub-circuit and the second pull-down sub-circuit is a second pull-down node; the shift register further comprises a first auxiliary sub-circuit and a second auxiliary sub-circuit. The first auxiliary sub-circuit is configured to pull down the potential of a first pull-down node to a non-working level signal when the second power supply voltage is a working level signal; and the second auxiliary sub-circuit is configured to pull down the potential of a second pull-down node to a non-working level signal when the first power supply voltage is a working level signal.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register, a gate driving circuit and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the very important technologies is the mass production of GOA (Gate Driver on Array, array substrate row drive) technology. The TFT (Thin Film Transistor) gate switch circuit is integrated on the array substrate of the display panel using GOA technology to form a scan drive for the display panel, thereby eliminating the gate drive integrated circuit part. It can not only reduce product costs in terms of material cost and manufacturing process, but also the display panel can achieve a beautiful design with symmetry on both sides and narrow borders. At the same time, since the process of bonding in the gate direction can be omitted, it is also beneficial to improve production capacity and yield. This gate switch circuit integrated on the array substrate using GOA technology is also called a GOA circuit or a shift register circuit. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a gate drive circuit and a display device.

[0004] The embodiment of the present disclosure provides a shift register, which includes: a first input subcircuit, an output subcircuit, a first pull-down control subcircuit, a second pull-down control subcircuit, a first pull-down subcircuit, and a second pull-down subcircuit;

[0005] The first input subcircuit is configured to precharge the pull-up node by a first scan signal in response to a first input signal;

[0006] The output subcircuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node;

[0007] The first pull-down control subcircuit is configured to respond to a first power supply voltage and control the potential of the first pull-down node through the first power supply voltage;

[0008] The second pull-down control subcircuit is configured to respond to a second power supply voltage and control the potential of the second pull-down node by the second power supply voltage;

[0009] a first pull-down sub-circuit, responsive to the potential of the pull-up node, pulling down the first pull-down node;

[0010] The second pull-down sub-circuit pulls down the second pull-down node in response to the potential of the pull-up node; wherein,

[0011] The shift register further includes: a first auxiliary subcircuit and a second auxiliary subcircuit;

[0012] The first auxiliary subcircuit is configured to pull down the potential of the first pull-down node to a non-operating level signal when the second power supply voltage is an operating level signal;

[0013] The second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node to a non-operating level signal when the first power supply voltage is an operating level signal.

[0014] The shift register further includes a global reset subcircuit configured to globally reset the output of the pull-up node and the signal output terminal through a non-working level signal in response to a global reset signal.

[0015] Wherein, the first auxiliary subcircuit is specifically configured to respond to the global reset signal and, when the second power supply voltage is a working level signal, convert the non-working level signal through the first power supply voltage;

[0016] The second auxiliary subcircuit is specifically configured to, in response to the global reset signal, pull down the potential of the second pull-down node to a non-operating level signal through the second power supply voltage when the first power supply voltage is an operating level signal.

[0017] Wherein, the first auxiliary sub-circuit and the second auxiliary sub-circuit both include a seventeenth transistor;

[0018] A first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first power supply voltage terminal, a second electrode is connected to the first pull-down node, and a control electrode is connected to the global reset signal terminal;

[0019] A first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second power supply voltage terminal, a second electrode is connected to the second pull-down node, and a control electrode is connected to the global reset signal terminal.

[0020] Wherein, the global reset subcircuit includes a fourth transistor and a seventh transistor;

[0021] The first electrode of the fourth transistor is connected to the pull-up node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the global reset signal terminal;

[0022] The first electrode of the seventh transistor is connected to the signal output terminal, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the global reset signal terminal.

[0023] Wherein, the first auxiliary subcircuit is specifically configured to pull down the first pull-down node to a non-operating voltage through the first power supply voltage in response to a frame start signal when the second power supply voltage is an operating level signal;

[0024] The second auxiliary sub-circuit is specifically configured to pull down the second pull-down node to a non-operating voltage through the second power supply voltage in response to a frame start signal when the first power supply voltage is an operating level signal.

[0025] Wherein, the first auxiliary sub-circuit and the second auxiliary sub-circuit both include a seventeenth transistor;

[0026] The first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first power supply voltage terminal, the second electrode is connected to the first pull-down node, and the control electrode is connected to the frame start signal terminal;

[0027] A first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second power supply voltage terminal, a second electrode is connected to the second pull-down node, and a control electrode is connected to the frame start signal terminal.

[0028] Wherein, the first auxiliary subcircuit is specifically configured to pull down the first pull-down node through a non-working level signal in response to the second power supply voltage when the second power supply voltage is a working level signal;

[0029] The second auxiliary sub-circuit is specifically configured to pull down the second pull-down node through a non-operating level signal in response to the first power supply voltage when the first power supply voltage is an operating level signal.

[0030] Wherein, the first auxiliary sub-circuit and the second auxiliary sub-circuit both include a seventeenth transistor;

[0031] The first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the second power supply voltage terminal;

[0032] The first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the first power supply voltage terminal.

[0033] Wherein, the first auxiliary subcircuit is specifically configured to, in response to the potential of the second pull-down node, pull down the potential of the first pull-down node through a non-working level signal when the second power supply voltage is a working level signal;

[0034] The second auxiliary sub-circuit is specifically configured to, when the first power supply voltage is a working level signal, respond to the potential of the first pull-down node and pull down the potential of the second pull-down node through a non-working level signal.

[0035] Wherein, the first auxiliary sub-circuit and the second auxiliary sub-circuit both include a seventeenth transistor;

[0036] A first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first pull-down node, a second electrode is connected to the non-working level signal terminal, and a control electrode is connected to the second pull-down node;

[0037] The first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the first pull-down node.

[0038] The shift register further includes a pull-up reset subcircuit configured to reset the output of the pull-up node through a non-working level signal in response to a pull-up reset signal.

[0039] The pull-up reset subcircuit comprises a second transistor, a first electrode of the second transistor is connected to the pull-up node, a second electrode is connected to a non-working level signal terminal, and a control electrode is connected to a pull-up reset signal terminal.

[0040] Wherein, the first input signal is multiplexed into the first scanning signal; the first input sub-circuit includes a first transistor;

[0041] The first electrode and the control electrode of the first transistor are connected to the first input signal terminal, and the second electrode is connected to the pull-up node.

[0042] The shift register further includes a second input subcircuit configured to precharge the pull-up node through a second scan signal in response to a second input signal.

[0043] Wherein, the second input subcircuit comprises a second transistor;

[0044] The first electrode of the second transistor is connected to the pull-up node, the second electrode is connected to the second scan signal terminal, and the control electrode is connected to the second input signal terminal.

[0045] Wherein, the first input subcircuit comprises a first transistor;

[0046] The first electrode of the first transistor is connected to the first scan signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the first input signal terminal.

[0047] Wherein, the shift register further includes two first noise reduction sub-circuits and two second noise reduction sub-circuits;

[0048] One of the two first noise reduction sub-circuits is configured to reduce the noise of the output of the pull-up node through a non-working level signal in response to the potential of the first pull-down node, and the other is configured to reduce the noise of the output of the pull-up node through a non-working level signal in response to the potential of the second pull-down node;

[0049] One of the two second noise reduction sub-circuits is configured to respond to the potential of the first pull-down node and to reduce the noise of the output of the signal output end through a non-working level signal, and the other is configured to respond to the potential of the second pull-down node and to reduce the noise of the output of the signal output end through a non-working level signal.

[0050] Wherein, the two first noise reduction sub-circuits each include a tenth transistor;

[0051] The first electrode of the tenth transistor in one of the first noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage end, and the control electrode is connected to the first pull-down node; the first electrode of the tenth transistor in another of the first noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage end, and the control electrode is connected to the second pull-down node.

[0052] Wherein, the two second noise reduction sub-circuits each include an eleventh transistor;

[0053] The first electrode of the eleventh transistor in one of the second noise reduction sub-circuits is connected to the signal output terminal, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the first pull-down node; the first electrode of the eleventh transistor in another of the second noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the signal output terminal.

[0054] The shift register further includes a cascade subcircuit configured to output a clock signal through a cascade signal terminal in response to the potential of the pull-up node.

[0055] Wherein, the cascade sub-circuit includes a thirteenth transistor;

[0056] The first electrode of the thirteenth transistor is connected to the clock signal terminal, the second electrode is connected to the cascade signal terminal, and the control electrode is connected to the pull-up node.

[0057] Wherein, the shift register further includes two third noise reduction sub-circuits;

[0058] One of the two third noise reduction sub-circuits is configured to perform noise reduction on the output of the cascade signal terminal through a non-working level signal in response to the control of the first pull-down node; the other is configured to perform noise reduction on the output of the cascade signal terminal through a non-working level signal in response to the control of the second pull-down node.

[0059] Wherein, the first pull-down control subcircuit and the second pull-down control subcircuit both include a fifth transistor and a ninth transistor;

[0060] For the first pull-down control sub-circuit, the first electrode of the fifth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor and the first power supply voltage terminal, and the second electrode is connected to the first pull-down node;

[0061] For the second pull-down control sub-circuit, the first electrode of the fifth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor and the second power supply voltage terminal, and the second electrode is connected to the second pull-down node.

[0062] Wherein, the first pull-down sub-circuit and the second pull-down sub-circuit both include a sixth transistor and an eighth transistor;

[0063] For the first pull-down sub-circuit, the first electrode of the sixth transistor is connected to the first pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node; the first electrode of the eighth transistor is connected to the control electrode of the fifth transistor and the first electrode of the ninth transistor, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node;

[0064] For the second pull-down sub-circuit, the first electrode of the sixth transistor is connected to the second pull-down node, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the pull-up node; the first electrode of the eighth transistor is connected to the control electrode of the fifth transistor and the first electrode of the ninth transistor, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the pull-up node.

[0065] Wherein, the first pull-down control subcircuit and the second pull-down control subcircuit both include a fifth transistor;

[0066] For the first pull-down control sub-circuit, the first electrode and the control electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the first pull-down node;

[0067] For the first pull-down control sub-circuit, the first electrode and the control electrode of the fifth transistor are connected to the second power supply voltage terminal, and the second electrode is connected to the second pull-down node.

[0068] Wherein, the first pull-down sub-circuit and the second pull-down sub-circuit both include a sixth transistor;

[0069] The first electrode of the sixth transistor is connected to the first pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node;

[0070] The first electrode of the sixth transistor is connected to the second pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node.

[0071] An embodiment of the present disclosure provides a gate driving circuit, which includes a plurality of cascaded shift registers, wherein the shift register is any one of the shift registers described above.

[0072] An embodiment of the present disclosure provides a display device, which includes the above-mentioned gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 is a circuit diagram of an exemplary shift register.

[0074] Figure 2 for Figure 1 The working timing diagram of the shift register is shown.

[0075] Figure 3 4 is a circuit diagram of a first exemplary shift register according to an embodiment of the present disclosure.

[0076] Figure 4 This is a circuit diagram of a second exemplary shift register according to an embodiment of the present disclosure.

[0077] Figure 5 4 is a circuit diagram of a third exemplary shift register according to an embodiment of the present disclosure.

[0078] Figure 6 This is a circuit diagram of a fourth exemplary shift register according to an embodiment of the present disclosure.

[0079] Figure 7 This is a circuit diagram of a fifth exemplary shift register according to an embodiment of the present disclosure.

[0080] Figure 8 This is a circuit diagram of a sixth exemplary shift register according to an embodiment of the present disclosure.

[0081] Fig. 9 4 is a circuit diagram of a seventh exemplary shift register according to an embodiment of the present disclosure.

[0082] Fig.10 This is a circuit diagram of an eighth exemplary shift register according to an embodiment of the present disclosure.

[0083] Fig.11 4 is a circuit diagram of a ninth exemplary shift register according to an embodiment of the present disclosure.

[0084] Fig.12 This is a circuit diagram of a tenth exemplary shift register according to an embodiment of the present disclosure.

[0085] Fig.13This is a circuit diagram of an eleventh exemplary shift register according to an embodiment of the present disclosure.

[0086] Fig.14 This is a circuit diagram of a twelfth exemplary shift register according to an embodiment of the present disclosure.

[0087] Fig.15 This is a circuit diagram of the thirteenth exemplary shift register of the embodiment of the present disclosure.

[0088] Fig.16 This is a circuit diagram of the fourteenth exemplary shift register of the embodiment of the present disclosure.

[0089] Fig.17 This is a circuit diagram of a fifteenth exemplary shift register according to an embodiment of the present disclosure.

[0090] Fig.18 This is a circuit diagram of a sixteenth exemplary shift register according to an embodiment of the present disclosure.

[0091] Fig.19 This is a circuit diagram of a seventeenth exemplary shift register according to an embodiment of the present disclosure.

[0092] Fig. 20 This is a circuit diagram of an eighteenth exemplary shift register according to an embodiment of the present disclosure.

[0093] Fig.21 This is a circuit diagram of a nineteenth exemplary shift register according to an embodiment of the present disclosure.

[0094] Fig. 22 This is a circuit diagram of the twentieth exemplary shift register of the embodiment of the present disclosure.

[0095] Fig.23 This is a circuit diagram of the twenty-first exemplary shift register of the embodiment of the present disclosure.

[0096] Fig.24 This is a circuit diagram of a twenty-second exemplary shift register of an embodiment of the present disclosure.

[0097] Fig.25 This is a circuit diagram of a twenty-third exemplary shift register of an embodiment of the present disclosure.

[0098] Fig.26 This is a circuit diagram of a twenty-fourth exemplary shift register of an embodiment of the present disclosure.

[0099] Fig. 27 This is a circuit diagram of the twenty-fifth exemplary shift register of the embodiment of the present disclosure.

[0100] Fig.28This is a circuit diagram of the twenty-sixth exemplary shift register of the embodiment of the present disclosure.

[0101] Fig.29 This is a circuit diagram of the twenty-seventh exemplary shift register of the embodiment of the present disclosure.

[0102] Fig.30 This is a circuit diagram of a twenty-eighth exemplary shift register of an embodiment of the present disclosure.

[0103] Fig.31 This is a circuit diagram of a twenty-ninth exemplary shift register of an embodiment of the present disclosure.

[0104] Fig.32 This is a circuit diagram of the thirtieth exemplary shift register of the embodiment of the present disclosure.

[0105] Fig.33 This is a circuit diagram of the thirty-first exemplary shift register of the embodiment of the present disclosure.

[0106] Fig.34 This is a circuit diagram of a thirty-second exemplary shift register of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0107] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0108] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0109] It should be noted that the transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present invention, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first electrode is the source of the N-type transistor, and the second electrode is the drain of the N-type transistor. When a high-level signal is input to the gate, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative labor, and therefore it is also within the scope of protection of the embodiments of the present invention.

[0110] Among them, since the transistor used in the embodiment of the present invention is an N-type transistor, the working level signal in the embodiment of the present invention refers to a high level signal, and the non-working level signal is a low level signal; the corresponding working level signal terminal is a high level signal terminal, and the non-working level signal terminal is a low level signal terminal VGL.

[0111] Usually, the display panel includes a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are cross-arranged to define a plurality of pixel areas, and each pixel area is provided with a pixel unit. The structure of the display panel is described by taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example. When the display panel is driven to display, a gate scanning signal can be written to the gate line row by row according to the picture to be displayed, and a data voltage signal can be written to each data line at the same time, so that the pixel units in the display panel are lit up row by row.

[0112] Among them, the gate scanning signal is provided by the gate driving circuit, and the data voltage signal is provided by the source driving circuit; in the related technology, the gate driving circuit can be integrated into the gate driving chip, and the source driving circuit can be integrated into the source driving chip; and currently, in order to reduce the number of chips and realize narrow frame or no frame, a technology of integrating the gate driving circuit on the array substrate (Gate On Array; GOA) is provided; wherein the gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate, each shift register is connected to the gate line one by one, and is used to provide a gate scanning signal for the gate line connected thereto.

[0113] In order to make it clearer how the shift register implements the output of the gate scanning signal, a specific example of the shift register unit is used for explanation below.

[0114] Figure 1 is a circuit diagram of an exemplary shift register; Figure 1As shown, the shift register includes an input subcircuit 1, an output subcircuit 3, a pull-up reset subcircuit 2, a global reset subcircuit 6, two pull-down control subcircuits 41 / 42, two pull-down subcircuits 51 / 52, two first noise reduction subcircuits 71 / 72, and two second noise reduction subcircuits 81 / 82. For the convenience of description, the two pull-down control subcircuits 41 / 42 are respectively referred to as the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42, and the two pull-down subcircuits 51 / 52 are respectively referred to as the first pull-down subcircuit 51 and the second pull-down subcircuit 52. The first pull-down control subcircuit 41 is connected to the first pull-down subcircuit 51, and the connection node between the two is called the first pull-down node PD1; the second pull-down control subcircuit 42 is connected to the second pull-down subcircuit 52, and the connection node between the two is called the second pull-down node PD2.

[0115] Continue to refer to Figure 1 , the input subcircuit 1 is configured to respond to the input signal and precharge the pull-up node PU through the input signal. The output subcircuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal G(N). The pull-up reset subcircuit 2 is configured to reset the pull-up node PU through a low-level signal under the control of the pull-up reset signal. The global reset subcircuit 6 is configured to respond to the global reset signal and reset the pull-up node PU and the signal output terminal G(N) through a low-level signal. The output subcircuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal G(N). The first pull-down control subcircuit 41 is configured to respond to the first power supply voltage signal and control the potential of the first pull-down node PD1 through the first power supply voltage signal. The second pull-down control subcircuit 42 is configured to respond to the second power supply voltage signal and control the potential of the second pull-down node PD2 through the second power supply voltage signal. The first pull-down subcircuit 51 is configured to pull down the potential of the first pull-down node PD1 through a low-level signal in response to the potential of the pull-up node PU. The second pull-down subcircuit 52 is configured to pull down the potential of the second pull-down node PD2 through a low-level signal in response to the potential of the pull-up node PU. One of the two first noise reduction subcircuits 71 performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the first pull-down node PD1, and the other 72 performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the second pull-down node PD2. One of the two second noise reduction subcircuits 81 performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the first pull-down node PD1, and the other 82 performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the second pull-down node PD2.

[0116] Specifically, continuing to refer to 1, the input subcircuit 1 includes a first transistor M1, the pull-up reset subcircuit 2 includes a second transistor M2, the output subcircuit 3 includes a third transistor M3 and a storage capacitor C1, the global reset subcircuit 6 includes a fourth transistor M4 and a seventh transistor M7, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 both include a fifth transistor and a ninth transistor, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor and an eighth transistor, each first noise reduction subcircuit includes a tenth transistor, and each second noise reduction subcircuit includes an eleventh transistor. Among them, for the convenience of description, the fifth transistor and the ninth transistor in the first pull-down control sub-circuit 41 are represented by M5A and M9A, respectively, and the fifth transistor and the ninth transistor in the second pull-down sub-circuit 52 are represented by M5B and M9B, respectively; the sixth transistor and the eighth transistor in the first pull-down sub-circuit 51 are represented by M6A and M8A, respectively, and the sixth transistor and the eighth transistor in the second pull-down sub-circuit 52 are represented by M6B and M8B, respectively; the tenth transistor in the two first noise reduction sub-circuits are represented by M10A and M10B, respectively; and the eleventh transistor in the two second noise reduction sub-circuits are represented by M11A and M11B, respectively.

[0117] Among them, the source and gate of M1 are connected to the signal input terminal, and the drain of M1 is connected to the pull-up node PU. The source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal. The source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU. The first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N). The source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low-level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0118] It should be noted that in the embodiment of the present disclosure, only the input subcircuit 1 responds to the input signal and pre-charges the pull-up node PU through the input signal. In actual applications, the input subcircuit 1 can also respond to the input signal and pre-charge the pull-up node PU through an independent first signal. Correspondingly, the source of M1 in the input subcircuit 1 may not be connected to its gate. For example, the source of M1 is connected to the first signal terminal, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the signal input terminal. At this time, a high-level signal is written to the signal input terminal, M1 is turned on, and the high-level signal written to the first signal terminal pre-charges the pull-up node PU. In the embodiment of the present disclosure, only the example of the source and gate of M1 being connected together is used for illustration, but it should be understood that this does not constitute a limitation on the protection scope of the embodiment of the present disclosure.

[0119] When the shift register in the embodiment of the present disclosure is applied to the gate drive circuit, except for the first stage shift register, the signal input terminal of the Nth stage shift register is connected to the signal output terminal G(N-1) of the N-1th stage shift register; except for the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the signal output terminal G(N+1) of the N+1th stage shift register. N≥2, and N is an integer.

[0120] Figure 2 for Figure 1 The working timing diagram of the shift register shown in FIG. Figure 2As shown, when the gate drive circuit is working, when G(N-1) is a high level signal, G(N+1) and the signal input to the global reset signal terminal are low level signals, M1 is turned on, M2 is turned off, and the pull-up node PU starts charging. When the pull-up node PU is a high level signal, M6A / M6B / M8A / M8B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level signal, ensuring that the pull-up node PU remains a high level signal and outputs normally. However, during the Blanking time between T1 and T3, at the moment T2 when the first power supply voltage terminal VDDO and the second power supply voltage terminal VDDE switch between high and low level signals, the first power supply voltage of the first power supply voltage terminal VDDO switches from a low level signal to a high level signal, and the second power supply voltage of the second power supply voltage terminal VDDE switches from a high level signal to a low level signal, M5A / M9A opens, the first pull-down node PD1 rises to a high potential, M5A / M9A closes, and the second pull-down node PD2 floats; or when the first power supply voltage of the first power supply voltage terminal VDDO switches from a high level signal to a low level signal, and the second power supply voltage of the second power supply voltage terminal VDDE switches from a low level signal to a high level signal, M5B / M9B opens, the second pull-down node PD2 rises to a high potential, M5A / M9A closes, and the first pull-down node PD1 floats. During the time period T2 to T4, one of the first pull-down node PD1 and the second pull-down node PD2 is a high-level signal, and the other is in a floating state. The pull-down node signal voltage in the floating state cannot be pulled down quickly, and the voltage is still high. The first pull-down node PD1 and the second pull-down node PD2 are both at a high potential and work simultaneously, and the pull-up node PU is continuously discharged through M10, and the pull-up node PU is continuously pulled down, and the gate drive circuit of this row has no output, resulting in black lines or flickering screen.

[0121] In view of the above problems, the embodiment of the present disclosure adds a first auxiliary subcircuit and a second auxiliary subcircuit on the basis of the above shift register. The first auxiliary subcircuit is configured to pull down the potential of the first pull-down node to a low-level signal when the second power supply voltage is a high-level signal; the second auxiliary subcircuit is configured to pull down the potential of the second pull-down node to a low-level signal when the first power supply voltage is a high-level signal.

[0122] Since the second power supply voltage is a high-level signal, the second pull-down node is a high-level signal. At this time, the first auxiliary sub-circuit pulls down the first pull-down sub-circuit to a low-level signal. In this way, before the pull-up node is charged, it can be ensured that the first pull-down node and the second pull-down node are not at a high-level signal at the same time, which helps to improve the charging capacity of the pull-up node.

[0123] Next, the technical solution of the embodiment of the present disclosure is described in detail with reference to specific examples.

[0124] First example: Figure 3 is a circuit diagram of a shift register according to a first example of an embodiment of the present disclosure; Figure 3 As shown, the shift register includes a first input subcircuit 11, a pull-up reset subcircuit 2, an output subcircuit 3, a global reset subcircuit 6, a first pull-down control subcircuit 41, a second pull-down control subcircuit 42, a first pull-down subcircuit 51, a second pull-down subcircuit 52, a first auxiliary subcircuit 91 and a second auxiliary subcircuit 92. Among them, the first input subcircuit 11 is configured to respond to the first input signal and precharge the pull-up node PU through the first input signal. The output subcircuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal G (N). The pull-up reset subcircuit 2 is configured to respond to the pull-up reset signal and reset the output of the pull-up node through a low-level signal. The global reset subcircuit 6 is configured to respond to the global reset signal and globally reset the output of the pull-up node PU and the signal output terminal G (N) through a low-level signal. The first pull-down control subcircuit 41 is configured to respond to the first power supply voltage and control the potential of the first pull-down node PD1 through the first power supply voltage. The second pull-down control subcircuit 42 is configured to respond to the second power supply voltage and control the potential of the second pull-down node PD2 through the second power supply voltage. The first pull-down subcircuit 51 is configured to respond to the potential of the pull-up node and pull down the potential of the first pull-down node PD1 through a low-level signal. The second pull-down subcircuit 52 is configured to respond to the potential of the pull-up node and pull down the potential of the second pull-down node PD2 through a low-level signal. The first auxiliary subcircuit 91 is configured to respond to the global reset signal and pull down the potential of the first pull-down node PD1 through the first power supply voltage when the second power supply voltage is a high-level signal. The second auxiliary subcircuit 92 is configured to respond to the global reset signal and pull down the potential of the second pull-down node PD2 through the second power supply voltage when the first power supply voltage is a high-level signal.

[0125] In this example, by adding the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, when the second pull-down control sub-circuit 42 is working, that is, the second power supply voltage is converted from a low-level signal to a high-level signal, and the first power supply voltage is converted from a high-level signal to a low-level signal, before the pull-up node is charged, the first auxiliary sub-circuit 91 is controlled to work by the global reset signal, and the first pull-down node PD1 is pulled down by a low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time, and only the second pull-down node PD2 competes with the potential of the pull-up node, which helps to improve the charging capacity of the pull-up node. Similarly, when the first pull-down control subcircuit 41 is working, that is, the first power supply voltage is converted from a low-level signal to a high-level signal, and the second power supply voltage is converted from a high-level signal to a low-level signal, before the pull-up node is charged, the second auxiliary subcircuit 92 is controlled to work by the global reset signal, and the second pull-down node PD2 is pulled down by the low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time, and only the potential of the first pull-down node PD1 competes with the potential of the pull-up node, which helps to improve the charging capacity of the pull-up node. In addition, in this example, the first auxiliary subcircuit 91 and the second auxiliary subcircuit 92 are controlled by the global reset signal, that is, for the entire shift register, no control signal is added due to the addition of the first auxiliary subcircuit 91 and the second auxiliary subcircuit 92, so the control of the shift register is relatively simple.

[0126] Continue to refer to Figure 3 When the shift register in the embodiment of the present disclosure is applied to the gate driving circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the signal output terminal G(N-1) of the N-1th shift register; except for the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the signal output terminal G(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0127] In some examples, continue to refer to Figure 3 , the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 both include a seventeenth transistor. For ease of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is represented by M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is represented by M17B. Among them, the source of M17A is connected to the first power supply voltage terminal VDDO, the drain of M17A is connected to the first pull-down node PD1, and the gate of M17A is connected to the global reset signal terminal STV0. The source of M17B is connected to the second power supply voltage terminal VDDE, the drain of M17B is connected to the second pull-down node PD2, and the gate of M17B is connected to the global reset signal terminal STV0.

[0128] Specifically, the global reset signal terminal STV0 is used to introduce a global reset signal, the first power supply voltage terminal VDDO is used to introduce a first power supply voltage, and the second power supply voltage terminal VDDE is used to introduce a second power supply voltage. When the second power supply voltage of the second power supply voltage terminal VDDE is converted from a low level to a high level, the first power supply voltage of the first power supply voltage terminal VDDO is converted from a high level to a low level, and the global reset signal written by the global reset signal terminal STV0 is a high level signal, M17A is turned on, and at this time the first power supply voltage is a low level to pull down the potential of the first pull-down node PD1. Similarly, when the first power supply voltage of the first power supply voltage terminal VDDO is converted from a low level to a high level, the second power supply voltage of the second power supply voltage terminal VDDE is converted from a high level to a low level, and the global reset signal written by the global reset signal terminal STV0 is a high level signal, M17B is turned on, and at this time the second power supply voltage is a low level to pull down the potential of the second pull-down node PD2. This example can effectively avoid the competition relationship between the pull-up node and the first pull-down node PD1 / the second pull-down node PD2.

[0129] In some examples, continue to refer to Figure 3 The global reset subcircuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal STV0. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal STV0.

[0130] Specifically, in the global reset stage, the global reset signal written into the global reset signal terminal STV0 is a high-level signal, and the fourth transistor M4 and the seventh transistor M7 are both turned on. At this time, the low-level signal written into the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4, and resets the signal output terminal G(N) through the seventh transistor M7.

[0131] In some examples, continue to refer to Figure 3 , the shift register further includes two first noise reduction sub-circuits 71 / 72 and two second noise reduction sub-circuits 81 / 82. One (71) of the two first noise reduction sub-circuits 71 / 72 performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the first pull-down node PD1, and the other (72) performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the second pull-down node PD2. One (81) of the two second noise reduction sub-circuits 81 / 82 performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the first pull-down node PD1, and the other (82) performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the second pull-down node PD2.

[0132] Wherein, the two first noise reduction sub-circuits 71 / 72 each include a tenth transistor, and the two second noise reduction sub-circuits 81 / 82 each include an eleventh transistor. The tenth transistor in the two first noise reduction sub-circuits 71 / 72 is represented by M10A and M10B respectively; the eleventh transistor in the two second noise reduction sub-circuits 81 / 82 is represented by M11A and M11B respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0133] Specifically, in the output noise reduction stage, when the potential of the first pull-down node PD1 is at a high level, M10A and M11A are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) are pulled down by the low-level signal written by the low-level signal terminal VGL. When the potential of the second pull-down node PD2 is at a high level, M10B and M11B are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) are pulled down by the low-level signal written by the low-level signal terminal VGL.

[0134] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source and gate of M1 are connected to the first input signal terminal G(N-1), the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal G(N+1).

[0135] Specifically, in the input stage, the first input signal written into the first input signal terminal G(N-1) is a high-level signal, M1 is turned on, and the pull-up node PU is precharged by the high-level signal. In the pull-up reset stage, the pull-up reset signal written into the pull-up reset signal terminal G(N+1) is a high-level signal, M2 is turned on, and the pull-up node PU is discharged by a low-level signal, thereby resetting the pull-up node PU.

[0136] In some examples, the output subcircuit 3 includes a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0137] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the signal output terminal G(N) outputs a high-level signal.

[0138] In some examples, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 both include a fifth transistor and a ninth transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control subcircuit 41 are represented by M5A and M9A, respectively, and the fifth transistor and the ninth transistor in the second pull-down subcircuit 52 are represented by M5B and M9B, respectively. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE.

[0139] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A and M9A are both turned on, and the potential of the first pull-down node PD1 is pulled up to the first power supply voltage, that is, at a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, MB5 and M9B are both turned on, and the potential of the second pull-down node PD2 is pulled up to the second power supply voltage, that is, at a high potential. It should be noted that the first power supply voltage and the second power supply voltage can be the same power supply voltage. In the embodiment disclosed herein, only the first power supply voltage and the second power supply voltage are described as the same power supply voltage.

[0140] In some examples, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor and an eighth transistor; for ease of description, the sixth transistor and the eighth transistor in the first pull-down subcircuit 51 are represented by M6A and M8A, respectively, and the sixth transistor and the eighth transistor in the second pull-down subcircuit 52 are represented by M6B and M8B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0141] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B / M8A / M8B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0142] Second example: Figure 4 is a circuit diagram of a shift register according to a second example of an embodiment of the present disclosure; Figure 4 As shown, the structure of the shift register of this example is substantially the same as that of the first example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the first example.

[0143] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0144] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0145] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0146] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0147] The other structures of the shift register in this example may be the same as those in the first example, and thus will not be repeated here.

[0148] The third example: Figure 5 is a circuit diagram of a shift register according to a third example of an embodiment of the present disclosure; Figure 5 As shown, the structure of the shift register in this example is substantially the same as that in the first example, with the only difference being that a cascade subcircuit 111 is added to the shift register in the first example, and the cascade output subcircuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0149] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13 , a source of M13 connected to the clock signal terminal CLK, a drain of M13 connected to the cascade signal terminal output_C(N), and a gate of M13 connected to the pull-up node PU.

[0150] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0151] When the shift register in the embodiment of the present disclosure is applied to the gate drive circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the N-1th shift register; except for the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0152] In some examples, continue to refer to Figure 5 The shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to respond to the potential of the first pull-down node PD1 and pull down the output of the cascade signal terminal through a low-level signal; the other third noise reduction sub-circuit is configured to respond to the potential of the second pull-down node PD2 and pull down the output of the cascade signal terminal through a low-level signal.

[0153] Among them, continue to refer to Figure 5 , the two third noise reduction sub-circuits can each include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0154] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0155] Continue to refer to Figure 5 The shift register in this example may further include a first discharge subcircuit 101 and a second discharge subcircuit 102; the first discharge subcircuit 101 is configured to discharge the first pull-down node PD1 through a low-level signal in response to the first input signal. The second discharge subcircuit 102 is configured to discharge the second pull-down node PD2 through a low-level signal in response to the first input signal.

[0156] Specifically, when the first input signal is written as a high-level signal, the first input sub-circuit 11 operates to pre-charge the pull-up node PU. At this time, the first pull-down node PD1 is discharged through the first discharge sub-circuit 101, and the second pull-down node PD2 is discharged through the second discharge sub-circuit 102, thereby avoiding competition between the potential of the first pull-down node PD1 and the second pull-down node PD2 and the pull-up node PU.

[0157] Wherein, the first discharge subcircuit 101 and the second discharge subcircuit 102 may both include a sixteenth transistor. For ease of description, the sixteenth transistor in the first discharge subcircuit 101 is represented by M16A, and the sixteenth transistor in the second discharge subcircuit 102 is represented by M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0158] In the input stage, the first input signal written into the first input signal terminal is a high level signal, M16A and M16B are both turned on, and the low level signal written into the low level signal terminal VGL pulls down the potentials of the first pull-down node PD1 and the second pull-down node PD2.

[0159] The other structures of the shift register in this example may be the same as those in the first example, and thus will not be repeated here.

[0160] Fourth example: Figure 6 is a circuit diagram of a shift register according to a fourth example of an embodiment of the present disclosure; Figure 6 As shown, the structure of the shift register of this example is substantially the same as that of the third example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the third example.

[0161] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0162] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0163] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0164] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0165] The other structures of the shift register in this example may be the same as those in the first example, and thus will not be repeated here.

[0166] The fifth example: Figure 7 is a circuit diagram of a shift register according to a fifth example of an embodiment of the present disclosure; Figure 7 As shown, the structure of the shift register of this example is roughly the same as that of the first example, and the only difference is that the shift register can realize bidirectional scanning, and the first input subcircuit 11 and the pull-up reset subcircuit 2 are different from those in the first example. In this example, since the shift register can realize bidirectional scanning, during forward scanning, the first input subcircuit 11 is used for precharging the pull-up node PU, and the pull-up reset subcircuit 2 is used for resetting the pull-up node PU; during reverse scanning, the first input subcircuit 11 is used for resetting the pull-up node PU, and the pull-up reset subcircuit 2 is used for precharging the pull-up node PU. Therefore, in order to facilitate understanding, the first input subcircuit 11 in the above example is still referred to as the first input subcircuit 11, and the pull-up reset subcircuit 2 is referred to as the second input subcircuit 12. Since the first input subcircuit 11 and the second input subcircuit 12 are the main components used to support the shift register to realize bidirectional scanning, the connection relationship between the first input subcircuit 11 and the second input subcircuit 12 and the above-mentioned first input subcircuit 11 and the pull-up reset subcircuit 2 is different.

[0167] Continue to refer to Figure 7 Specifically, the first input subcircuit 11 is configured to precharge the pull-up node PU through the first scan signal in response to the first input signal. The second input subcircuit 12 is configured to precharge the pull-up node PU through the second scan signal in response to the second input signal.

[0168] In some examples, the first input subcircuit 11 includes a first transistor M1; the second input subcircuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0169] Specifically, during forward scanning, in the input stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written into the first scan signal terminal VDS is a high-level signal, and the pull-up node PU is precharged by the first scan signal. In the pull-up reset stage, the second input signal written into the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written into the second scan signal terminal VSD is a low-level signal, and the pull-up node PU is discharged by the second scan signal, thereby resetting the pull-up node PU.

[0170] When scanning in reverse, in the input stage, the second input signal written into the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written into the second scan signal terminal VSD is a high-level signal. At this time, the pull-up node PU is precharged by the second scan signal. In the pull-up reset stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written into the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is discharged by the first scan signal, thereby resetting the pull-up node PU.

[0171] The other structures of the shift register in this example may be the same as those in the first example, and thus will not be repeated here.

[0172] The sixth example: Figure 8 is a circuit diagram of a shift register according to a sixth example of an embodiment of the present disclosure; Figure 8 As shown, the structure of the shift register of this example is substantially the same as that of the fifth example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the fifth example.

[0173] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0174] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0175] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0176] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0177] The other structures of the shift register in this example may be the same as those in the fifth example, and thus will not be repeated here.

[0178] The seventh example: Fig. 9 is a circuit diagram of a shift register according to a seventh example of an embodiment of the present disclosure; Fig. 9 As shown, the structure of the shift register of this example is substantially the same as that of the fifth example, with the only difference being that this shift register adds a cascade subcircuit 111 on the basis of the shift register of the first example, and the cascade output subcircuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0179] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13 , a source of M13 connected to the clock signal terminal CLK, a drain of M13 connected to the cascade signal terminal output_C(N), and a gate of M13 connected to the pull-up node PU.

[0180] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0181] When the shift register in the embodiment of the present disclosure is applied to the gate driving circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the N-1th shift register; except for the last stage shift register, the second input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0182] In some examples, the shift register not only includes the above-mentioned structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the first pull-down node PD1; and the other third noise reduction sub-circuit is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the second pull-down node PD2.

[0183] Among them, continue to refer to Figure 5 , the two third noise reduction sub-circuits can each include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0184] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0185] The other structures of the shift register in this example may be the same as those in the fifth example, and thus will not be repeated here.

[0186] The eighth example: Fig.10 is a circuit diagram of a shift register according to an eighth example of an embodiment of the present disclosure; Fig.10 As shown, the structure of the shift register of this example is substantially the same as that of the seventh example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the seventh example.

[0187] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0188] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0189] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0190] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0191] The other structures of the shift register in this example may be the same as those in the seventh example, and thus will not be repeated here.

[0192] Ninth example: Fig.11 is a circuit diagram of a shift register according to a ninth example of an embodiment of the present disclosure; Fig.11As shown, the shift register includes a first input subcircuit 11, a pull-up reset subcircuit 2, an output subcircuit 3, a first pull-down control subcircuit 41, a second pull-down control subcircuit 42, a first pull-down subcircuit 51, a second pull-down subcircuit 52, a first auxiliary subcircuit 91 and a second auxiliary subcircuit 92. Among them, the first input subcircuit 11 is configured to respond to the first input signal and precharge the pull-up node PU through the first input signal. The output subcircuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal. The pull-up reset subcircuit 2 is configured to respond to the pull-up reset signal and reset the output of the pull-up node PU through a low-level signal. The first pull-down control subcircuit 41 is configured to respond to the first power supply voltage and control the potential of the first pull-down node PD1 through the first power supply voltage. The second pull-down control subcircuit 42 is configured to respond to the second power supply voltage and control the potential of the second pull-down node PD2 through the second power supply voltage. The first pull-down subcircuit 51 is configured to pull down the potential of the first pull-down node PD1 through a low-level signal in response to the potential of the pull-up node PU. The second pull-down subcircuit 52 is configured to pull down the potential of the second pull-down node PD2 through a low-level signal in response to the potential of the pull-up node PU. The first auxiliary subcircuit 91 is configured to pull down the potential of the first pull-down node PD1 through the first power supply voltage when the second power supply voltage is a high-level signal in response to the frame start signal. The second auxiliary subcircuit 92 is configured to pull down the potential of the second pull-down node PD2 through the second power supply voltage in response to the frame start signal when the first power supply voltage is a high-level signal.

[0193] In this example, by adding a first auxiliary sub-circuit 91 and a second auxiliary sub-circuit 92, when the second pull-down control sub-circuit 42 is working, that is, the second power supply voltage is converted from a low-level signal to a high-level signal, and the first power supply voltage is converted from a high-level signal to a low-level signal, before the pull-up node PU is charged (except for the first-stage shift register), the first auxiliary sub-circuit 91 is controlled to work by a frame start signal, and the first pull-down node PD1 is pulled down by a low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time, and only the second pull-down node PD2 competes with the potential of the pull-up node PU, which helps to improve the charging capacity of the pull-up node PU. Similarly, when the first pull-down control subcircuit 41 is working, that is, the first power supply voltage is converted from a low-level signal to a high-level signal, and the second power supply voltage is converted from a high-level signal to a low-level signal, before the pull-up node PU is charged, the second auxiliary subcircuit 92 is controlled to work by the frame start signal, and the second pull-down node PD2 is pulled down by a low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time, and only the potentials of the first pull-down node PD1 and the pull-up node PU compete with each other, which helps to improve the charging capacity of the pull-up node PU.

[0194] Continue to refer to Fig.11 When the shift register in the embodiment of the present disclosure is applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the N-stage shift register is connected to the signal output terminal G(N-1) of the N-1-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the N-stage shift register is connected to the signal output terminal G(N+1) of the N+1-stage shift register. N≥2, and N is an integer. The first input signal terminal of the first-stage shift register and the second input signal terminal of the last-stage shift register are connected to the frame start signal. In this example, the first auxiliary subcircuit 91 and the second auxiliary subcircuit 92 are controlled by the frame start signal, that is, for the gate drive circuit, the control signal is not increased due to the addition of the first auxiliary subcircuit 91 and the second auxiliary subcircuit 92, so the control of the shift register is relatively simple.

[0195] In some examples, continue to refer to Fig.11, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 both include a seventeenth transistor. For ease of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is represented by M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is represented by M17B. Among them, the source of M17A is connected to the first power supply voltage terminal VDDO, the drain of M17A is connected to the first pull-down node PD1, and the gate of M17A is connected to the frame start signal terminal STV. The source of M17B is connected to the second power supply voltage terminal VDDE, the drain of M17B is connected to the second pull-down node, and the gate of M17B is connected to the frame start signal terminal STV.

[0196] Specifically, the frame start signal terminal STV is used to introduce a frame start signal, the first power supply voltage terminal VDDO is used to introduce a first power supply voltage, and the second power supply voltage terminal VDDE is used to introduce a second power supply voltage. When the second power supply voltage of the second power supply voltage terminal VDDE is converted from a low level to a high level, the first power supply voltage of the first power supply voltage terminal VDDO is converted from a high level to a low level, and the frame start signal written by the frame start signal terminal STV is a high level signal, M17A is turned on, and at this time the first power supply voltage is a low level to pull down the potential of the first pull-down node PD1. Similarly, when the first power supply voltage of the first power supply voltage terminal VDDO is converted from a low level to a high level, the second power supply voltage of the second power supply voltage terminal VDDE is converted from a high level to a low level, and the frame start signal written by the frame start signal terminal STV is a high level signal, M17B is turned on, and at this time the second power supply voltage is a low level to pull down the potential of the second pull-down node PD2. This example can effectively avoid the competition relationship between the pull-up node PU and the first pull-down node PD1 / the second pull-down node PD2.

[0197] In some examples, continue to refer to Fig.11 The shift register of the embodiment of the present disclosure further includes a global reset subcircuit 6, which is configured to globally reset the output of the pull-up node and the signal output terminal through a low-level signal in response to a global reset signal.

[0198] The global reset subcircuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal STV0. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal STV0.

[0199] Specifically, in the global reset stage, the global reset signal written into the global reset signal terminal STV0 is a high-level signal, and the fourth transistor M4 and the seventh transistor M7 are both turned on. At this time, the low-level signal written into the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4, and resets the signal output terminal G(N) through the seventh transistor M7.

[0200] In some examples, continue to refer to Fig.11 , the shift register further includes two first noise reduction sub-circuits 71 / 72 and two second noise reduction sub-circuits 81 / 82. One (71) of the two first noise reduction sub-circuits 71 / 72 performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the first pull-down node PD1, and the other (72) performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the second pull-down node PD2. One (81) of the two second noise reduction sub-circuits 81 / 82 performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the first pull-down node PD1, and the other (82) performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the second pull-down node PD2.

[0201] Among them, the two first noise reduction sub-circuits 71 / 72 each include a tenth transistor, and the two second noise reduction sub-circuits 81 / 82 each include an eleventh transistor. The tenth transistor in the two first noise reduction sub-circuits is represented by M10A and M10B respectively; the eleventh transistor in the two second noise reduction sub-circuits is represented by M11A and M11B respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0202] Specifically, in the output noise reduction stage, when the potential of the first pull-down node PD1 is at a high level, M10A and M11A are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) are pulled down by the low-level signal written by the low-level signal terminal VGL. When the potential of the second pull-down node PD2 is at a high level, M10B and M11B are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) are pulled down by the low-level signal written by the low-level signal terminal VGL.

[0203] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source and gate of M1 are connected to the first input signal terminal, the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal.

[0204] Specifically, in the input stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the pull-up node PU is precharged by the high-level signal. In the pull-up reset stage, the pull-up reset signal written into the pull-up reset signal terminal is a high-level signal, M2 is turned on, and the pull-up node PU is discharged by a low-level signal, thereby resetting the pull-up node PU.

[0205] In some examples, the output subcircuit 3 includes a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0206] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the signal output terminal G(N) outputs a high-level signal.

[0207] In some examples, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 both include a fifth transistor and a ninth transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control subcircuit 41 are represented by M5A and M9A, respectively, and the fifth transistor and the ninth transistor in the second pull-down subcircuit 52 are represented by M5B and M9B, respectively. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE.

[0208] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A and M9A are both turned on, and the potential of the first pull-down node PD1 is pulled up to the first power supply voltage, that is, at a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, MB5 and M9B are both turned on, and the potential of the second pull-down node PD2 is pulled up to the second power supply voltage, that is, at a high potential. It should be noted that the first power supply voltage and the second power supply voltage can be the same power supply voltage. In the embodiment disclosed herein, only the first power supply voltage and the second power supply voltage are described as the same power supply voltage.

[0209] In some examples, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor and an eighth transistor; for ease of description, the sixth transistor and the eighth transistor in the first pull-down subcircuit 51 are represented by M6A and M8A, respectively, and the sixth transistor and the eighth transistor in the second pull-down subcircuit 52 are represented by M6B and M8B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0210] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B / M8A / M8B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0211] The tenth example: Fig.12 is a circuit diagram of a shift register according to a tenth example of an embodiment of the present disclosure; Fig.12 As shown, the structure of the shift register of this example is substantially the same as that of the ninth example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the ninth example.

[0212] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0213] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0214] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0215] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0216] The other structures of the shift register in this example may be the same as those in the ninth example, so they will not be repeated here.

[0217] Eleventh example: Fig.13 1 is a circuit diagram of a shift register according to an eleventh example of an embodiment of the present disclosure; Fig.13 As shown, the structure of the shift register in this example is substantially the same as that in the ninth example, with the only difference being that a cascade subcircuit 111 is added to the shift register in the ninth example, and the cascade output subcircuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0218] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13 , a source of M13 connected to the clock signal terminal CLK, a drain of M13 connected to the cascade signal terminal output_C(N), and a gate of M13 connected to the pull-up node PU.

[0219] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0220] When the shift register in the embodiment of the present disclosure is applied to the gate drive circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the N-1th shift register; except for the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0221] In some examples, continue to refer to Fig.13 The shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to respond to the potential of the first pull-down node PD1 and pull down the output of the cascade signal terminal through a low-level signal; the other third noise reduction sub-circuit is configured to respond to the potential of the second pull-down node PD2 and pull down the output of the cascade signal terminal through a low-level signal.

[0222] Among them, continue to refer to Fig.13 , the two third noise reduction sub-circuits can each include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0223] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0224] Continue to refer to Fig.13The shift register in this example may further include a first discharge subcircuit 101 and a second discharge subcircuit 102; the first discharge subcircuit 101 is configured to discharge the first pull-down node PD1 through a low-level signal in response to the first input signal. The second discharge subcircuit 102 is configured to discharge the second pull-down node PD2 through a low-level signal in response to the first input signal.

[0225] Specifically, when the first input signal is written as a high-level signal, the first input sub-circuit 11 operates to pre-charge the pull-up node PU. At this time, the first pull-down node PD1 is discharged through the first discharge sub-circuit 101, and the second pull-down node PD2 is discharged through the second discharge sub-circuit 102, thereby avoiding competition between the potential of the first pull-down node PD1 and the second pull-down node PD2 and the pull-up node PU.

[0226] Wherein, the first discharge subcircuit 101 and the second discharge subcircuit 102 may both include a sixteenth transistor. For ease of description, the sixteenth transistor in the first discharge subcircuit 101 is represented by M16A, and the sixteenth transistor in the second discharge subcircuit 102 is represented by M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0227] In the input stage, the first input signal written into the first input signal terminal is a high level signal, M16A and M16B are both turned on, and the low level signal written into the low level signal terminal VGL pulls down the potentials of the first pull-down node PD1 and the second pull-down node PD2.

[0228] The other structures of the shift register in this example may be the same as those in the ninth example, so they will not be repeated here.

[0229] Example 12: Fig.14 is a circuit diagram of a shift register according to a twelfth example of an embodiment of the present disclosure; Fig.14 As shown, the structure of the shift register of this example is substantially the same as that of the eleventh example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51, and the second pull-down subcircuit 52 are different from those of the eleventh example.

[0230] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0231] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0232] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0233] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0234] The other structures of the shift register in this example may be the same as those in the eleventh example, and thus will not be repeated here.

[0235] Thirteenth example: Fig.15 13 is a circuit diagram of a shift register according to a thirteenth example of an embodiment of the present disclosure; Fig.15As shown, the structure of the shift register of this example is roughly the same as that of the ninth example, and the only difference is that the shift register can realize bidirectional scanning, and the first input subcircuit 11 and the pull-up reset subcircuit 2 are different from those in the ninth example. In this example, since the shift register can realize bidirectional scanning, during forward scanning, the first input subcircuit 11 is used for precharging the pull-up node PU, and the pull-up reset subcircuit 2 is used for resetting the pull-up node PU; during reverse scanning, the first input subcircuit 11 is used for resetting the pull-up node PU, and the pull-up reset subcircuit 2 is used for precharging the pull-up node PU. Therefore, in order to facilitate understanding, the first input subcircuit 11 in the above example is still referred to as the first input subcircuit 11, and the pull-up reset subcircuit 2 is referred to as the second input subcircuit 12. Since the first input subcircuit 11 and the second input subcircuit 12 are the main components used to support the shift register to realize bidirectional scanning, the connection relationship between the first input subcircuit 11 and the second input subcircuit 12 and the above-mentioned first input subcircuit 11 and the pull-up reset subcircuit 2 is different.

[0236] Continue to refer to Fig.15 Specifically, the first input subcircuit 11 is configured to precharge the pull-up node PU through the first scan signal in response to the first input signal. The second input subcircuit 12 is configured to precharge the pull-up node PU through the second scan signal in response to the second input signal.

[0237] In some examples, the first input subcircuit 11 includes a first transistor M1; the second input subcircuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0238] Specifically, during forward scanning, in the input stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written into the first scan signal terminal VDS is a high-level signal, and the pull-up node PU is precharged by the first scan signal. In the pull-up reset stage, the second input signal written into the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written into the second scan signal terminal VSD is a low-level signal, and the pull-up node PU is discharged by the second scan signal, thereby resetting the pull-up node PU.

[0239] When scanning in reverse, in the input stage, the second input signal written into the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written into the second scan signal terminal VSD is a high-level signal. At this time, the pull-up node PU is precharged by the second scan signal. In the pull-up reset stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written into the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is discharged by the first scan signal, thereby resetting the pull-up node PU.

[0240] The other structures of the shift register in this example may be the same as those in the ninth example, so they will not be repeated here.

[0241] Fourteenth example: Fig.16 14 is a circuit diagram of a shift register according to an embodiment of the present disclosure; Fig.16 As shown, the structure of the shift register of this example is substantially the same as that of the thirteenth example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the thirteenth example.

[0242] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0243] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0244] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0245] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0246] The other structures of the shift register in this example may be the same as those in the thirteenth example, so they will not be repeated here.

[0247] Example 15: Fig.17 1 is a circuit diagram of a shift register according to a fifteenth example of an embodiment of the present disclosure; Fig.17 As shown, the structure of the shift register of this example is substantially the same as that of the fourteenth example, with the only difference being that a cascade subcircuit 111 is added to the shift register of the fourteenth example, and the cascade output subcircuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0248] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13 , a source of M13 connected to the clock signal terminal CLK, a drain of M13 connected to the cascade signal terminal output_C(N), and a gate of M13 connected to the pull-up node PU.

[0249] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0250] When the shift register in the embodiment of the present disclosure is applied to the gate driving circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the N-1th shift register; except for the last stage shift register, the second input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0251] In some examples, the shift register not only includes the above-mentioned structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the first pull-down node PD1; and the other third noise reduction sub-circuit is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the second pull-down node PD2.

[0252] Among them, continue to refer to Fig.17, the two third noise reduction sub-circuits can each include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0253] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0254] The other structures of the shift register in this example may be the same as those in the fourteenth example, so they will not be repeated here.

[0255] Example 16: Fig.18 16 is a circuit diagram of a shift register according to an embodiment of the present disclosure; Fig.18 As shown, the structure of the shift register of this example is substantially the same as that of the fifteenth example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the fifteenth example.

[0256] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0257] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0258] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0259] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0260] The other structures of the shift register in this example may be the same as those in the fifteenth example, and thus will not be repeated here.

[0261] Example 17: Fig.19 17 is a circuit diagram of a shift register according to an embodiment of the present disclosure; Fig.19 As shown, the shift register includes a first input subcircuit 11, a pull-up reset subcircuit 2, an output subcircuit 3, a first pull-down control subcircuit 41, a second pull-down control subcircuit 42, a first pull-down subcircuit 51, a second pull-down subcircuit 52, a first auxiliary subcircuit 91 and a second auxiliary subcircuit 92. Among them, the first input subcircuit 11 is configured to respond to the first input signal and precharge the pull-up node PU through the first input signal. The output subcircuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal. The pull-up reset subcircuit 2 is configured to respond to the pull-up reset signal and reset the output of the pull-up node PU through a low-level signal. The first pull-down control subcircuit 41 is configured to respond to the first power supply voltage and control the potential of the first pull-down node PD1 through the first power supply voltage. The second pull-down control subcircuit 42 is configured to respond to the second power supply voltage and control the potential of the second pull-down node PD2 through the second power supply voltage. The first pull-down subcircuit 51 is configured to pull down the potential of the first pull-down node PD1 through a low-level signal in response to the potential of the pull-up node PU. The second pull-down subcircuit 52 is configured to pull down the potential of the second pull-down node PD2 through a low-level signal in response to the potential of the pull-up node PU. The first auxiliary subcircuit 91 is configured to pull down the potential of the first pull-down node PD1 through a low-level signal in response to the second power supply voltage when the second power supply voltage is a high-level signal. The second auxiliary subcircuit 92 is configured to pull down the potential of the second pull-down node PD2 through a low-level signal in response to the first power supply voltage when the first power supply voltage is a high-level signal.

[0262] In this example, by adding a first auxiliary sub-circuit 91 and a second auxiliary sub-circuit 92, when the second pull-down control sub-circuit 42 is working, that is, the second power supply voltage is converted from a low-level signal to a high-level signal, and the first power supply voltage is converted from a high-level signal to a low-level signal, before the pull-up node PU is charged (except for the first-stage shift register), the first auxiliary sub-circuit 91 is controlled to work by the second power supply voltage, and the first pull-down node PD1 is pulled down by a low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time, and only the second pull-down node PD2 competes with the potential of the pull-up node PU, which helps to improve the charging capacity of the pull-up node PU. Similarly, when the first pull-down control subcircuit 41 is working, that is, the first power supply voltage is converted from a low-level signal to a high-level signal, and the second power supply voltage is converted from a high-level signal to a low-level signal. Before the pull-up node PU is charged, the second auxiliary subcircuit 92 is controlled to work by the first power supply voltage, and the second pull-down node PD2 is pulled down by a low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time, and only the potentials of the first pull-down node PD1 and the pull-up node PU compete with each other, which helps to improve the charging capacity of the pull-up node PU. In this example, the first auxiliary subcircuit 91 is controlled by the second power supply voltage, and the second auxiliary subcircuit 92 is controlled by the first power supply voltage, that is, for the entire shift register, no control signal is added due to the addition of the first auxiliary subcircuit 91 and the second auxiliary subcircuit 92, so the control of the shift register is relatively simple.

[0263] Continue to refer to Fig.19 When the shift register in the embodiment of the present disclosure is applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the N-stage shift register is connected to the signal output terminal G(N-1) of the N-1-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the N-stage shift register is connected to the signal output terminal G(N+1) of the N+1-stage shift register. N≥2, and N is an integer. The first input signal terminal of the first-stage shift register and the second input signal terminal of the last-stage shift register are connected to the frame start signal.

[0264] In some examples, continue to refer to Fig.19, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 both include a seventeenth transistor. For ease of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is represented by M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is represented by M17B. Among them, the source of M17A is connected to the first pull-down node PD1, the drain of M17A is connected to the low-level signal terminal VGL, and the gate of M17A is connected to the second power supply voltage terminal VDDE. The source of M17B is connected to the second pull-down node PD2, the drain of M17B is connected to the low-level signal terminal, and the gate of M17B is connected to the first power supply voltage terminal VDDO.

[0265] Specifically, the first power supply voltage terminal VDDO is used to introduce the first power supply voltage, and the second power supply voltage terminal VDDE is used to introduce the second power supply voltage. When the second power supply voltage of the second power supply voltage terminal VDDE is converted from a low level to a high level, and the first power supply voltage of the first power supply voltage terminal VDDO is converted from a high level to a low level, M17A is turned on, and the low level signal written by the low level signal terminal VGL at this time pulls down the potential of the first pull-down node PD1. Similarly, when the first power supply voltage of the first power supply voltage terminal VDDO is converted from a low level to a high level, and the second power supply voltage of the second power supply voltage terminal VDDE is converted from a high level to a low level, M17B is turned on, and the low level signal written by the low level signal terminal VGL at this time pulls down the potential of the second pull-down node PD2. This example can effectively avoid the competition between the pull-up node PU and the first pull-down node PD1 / the second pull-down node PD2.

[0266] In some examples, continue to refer to Fig.19 The shift register of the embodiment of the present disclosure further includes a global reset subcircuit 6, which is configured to globally reset the output of the pull-up node PU and the signal output terminal through a low-level signal in response to a global reset signal.

[0267] The global reset subcircuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal STV0. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal STV0.

[0268] Specifically, in the global reset stage, the global reset signal written into the global reset signal terminal STV0 is a high-level signal, and the fourth transistor M4 and the seventh transistor M7 are both turned on. At this time, the low-level signal written into the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4, and resets the signal output terminal G(N) through the seventh transistor M7.

[0269] In some examples, continue to refer to Fig.19 , the shift register also includes two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the first pull-down node PD1, and the other performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the second pull-down node PD2. One of the two second noise reduction sub-circuits performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the first pull-down node PD1, and the other performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the second pull-down node PD2.

[0270] Wherein, each first noise reduction sub-circuit includes a tenth transistor, and each second noise reduction sub-circuit includes an eleventh transistor. The tenth transistors in the two first noise reduction sub-circuits are represented by M10A and M10B respectively; the eleventh transistors in the two second noise reduction sub-circuits are represented by M11A and M11B respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0271] Specifically, in the output noise reduction stage, when the potential of the first pull-down node PD1 is at a high level, M10A and M11A are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) are pulled down by the low-level signal written by the low-level signal terminal VGL. When the potential of the second pull-down node PD2 is at a high level, M10B and M11B are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) are pulled down by the low-level signal written by the low-level signal terminal VGL.

[0272] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source and gate of M1 are connected to the first input signal terminal, the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal.

[0273] Specifically, in the input stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the pull-up node PU is precharged by the high-level signal. In the pull-up reset stage, the pull-up reset signal written into the pull-up reset signal terminal is a high-level signal, M2 is turned on, and the pull-up node PU is discharged by a low-level signal, thereby resetting the pull-up node PU.

[0274] In some examples, the output subcircuit 3 includes a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0275] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the signal output terminal G(N) outputs a high-level signal.

[0276] In some examples, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 both include a fifth transistor and a ninth transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control subcircuit 41 are represented by M5A and M9A, respectively, and the fifth transistor and the ninth transistor in the second pull-down subcircuit 52 are represented by M5B and M9B, respectively. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE.

[0277] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A and M9A are both turned on, and the potential of the first pull-down node PD1 is pulled up to the first power supply voltage, that is, at a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, MB5 and M9B are both turned on, and the potential of the second pull-down node PD2 is pulled up to the second power supply voltage, that is, at a high potential. It should be noted that the first power supply voltage and the second power supply voltage can be the same power supply voltage. In the embodiment disclosed herein, only the first power supply voltage and the second power supply voltage are described as the same power supply voltage.

[0278] In some examples, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor and an eighth transistor; for ease of description, the sixth transistor and the eighth transistor in the first pull-down subcircuit 51 are represented by M6A and M8A, respectively, and the sixth transistor and the eighth transistor in the second pull-down subcircuit 52 are represented by M6B and M8B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0279] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B / M8A / M8B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0280] Example 18: Fig. 20 18 is a circuit diagram of a shift register according to an eighteenth example of an embodiment of the present disclosure; Fig. 20 As shown, the structure of the shift register of this example is substantially the same as that of the seventeenth example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the seventeenth example.

[0281] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0282] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0283] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0284] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0285] The other structures of the shift register in this example may be the same as those in the seventeenth example, and thus will not be repeated here.

[0286] Nineteenth example: Fig.21 19 is a circuit diagram of a shift register according to a nineteenth example of an embodiment of the present disclosure; Fig.21 As shown, the structure of the shift register in this example is substantially the same as that in the seventeenth example, with the only difference being that a cascade subcircuit 111 is added to the shift register in the seventeenth example, and the cascade output subcircuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0287] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13 , a source of M13 connected to the clock signal terminal CLK, a drain of M13 connected to the cascade signal terminal output_C(N), and a gate of M13 connected to the pull-up node PU.

[0288] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0289] When the shift register in the embodiment of the present disclosure is applied to the gate drive circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the N-1th shift register; except for the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0290] In some examples, continue to refer to Fig.21 The shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to respond to the potential of the first pull-down node PD1 and pull down the output of the cascade signal terminal through a low-level signal; the other third noise reduction sub-circuit is configured to respond to the potential of the second pull-down node PD2 and pull down the output of the cascade signal terminal through a low-level signal.

[0291] Among them, continue to refer to Fig.21 , the two third noise reduction sub-circuits can each include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0292] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0293] Continue to refer to Fig.21 The shift register in this example may further include a first discharge subcircuit 101 and a second discharge subcircuit 102; the first discharge subcircuit 101 is configured to discharge the first pull-down node PD1 through a low-level signal in response to the first input signal. The second discharge subcircuit 102 is configured to discharge the second pull-down node PD2 through a low-level signal in response to the first input signal.

[0294] Specifically, when the first input signal is written as a high-level signal, the first input sub-circuit 11 operates to pre-charge the pull-up node PU. At this time, the first pull-down node PD1 is discharged through the first discharge sub-circuit 101, and the second pull-down node PD2 is discharged through the second discharge sub-circuit 102, thereby avoiding competition between the potential of the first pull-down node PD1 and the second pull-down node PD2 and the pull-up node PU.

[0295] Wherein, the first discharge subcircuit 101 and the second discharge subcircuit 102 may both include a sixteenth transistor. For ease of description, the sixteenth transistor in the first discharge subcircuit 101 is represented by M16A, and the sixteenth transistor in the second discharge subcircuit 102 is represented by M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0296] In the input stage, the first input signal written into the first input signal terminal is a high level signal, M16A and M16B are both turned on, and the low level signal written into the low level signal terminal VGL pulls down the potentials of the first pull-down node PD1 and the second pull-down node PD2.

[0297] The other structures of the shift register in this example may be the same as those in the seventeenth example, and thus will not be repeated here.

[0298] The twentieth example: Fig. 22 2 is a circuit diagram of a shift register according to the twentieth example of an embodiment of the present disclosure; Fig. 22 As shown, the structure of the shift register of this example is substantially the same as that of the nineteenth example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the nineteenth example.

[0299] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0300] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0301] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0302] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0303] The other structures of the shift register in this example may be the same as those in the nineteenth example, and thus will not be repeated here.

[0304] Example 21: Fig.23 21 is a circuit diagram of a shift register according to the twenty-first example of an embodiment of the present disclosure; Fig.23 As shown, the structure of the shift register of this example is roughly the same as that of the seventeenth example, and the only difference is that the shift register can realize bidirectional scanning, and the first input subcircuit 11 and the pull-up reset subcircuit 2 are different from those in the seventeenth example. In this example, since the shift register can realize bidirectional scanning, during forward scanning, the first input subcircuit 11 is used for precharging the pull-up node PU, and the pull-up reset subcircuit 2 is used for resetting the pull-up node PU; during reverse scanning, the first input subcircuit 11 is used for resetting the pull-up node PU, and the pull-up reset subcircuit 2 is used for precharging the pull-up node PU. Therefore, in order to facilitate understanding, the first input subcircuit 11 in the above example is still referred to as the first input subcircuit 11, and the pull-up reset subcircuit 2 is referred to as the second input subcircuit 12. Since the first input subcircuit 11 and the second input subcircuit 12 are the main components used to support the shift register to realize bidirectional scanning, the connection relationship between the first input subcircuit 11 and the second input subcircuit 12 and the above-mentioned first input subcircuit 11 and the pull-up reset subcircuit 2 is different.

[0305] Continue to refer to Fig.23 Specifically, the first input subcircuit 11 is configured to precharge the pull-up node PU through the first scan signal in response to the first input signal. The second input subcircuit 12 is configured to precharge the pull-up node PU through the second scan signal in response to the second input signal.

[0306] In some examples, the first input subcircuit 11 includes a first transistor M1; the second input subcircuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0307] Specifically, during forward scanning, in the input stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written into the first scan signal terminal VDS is a high-level signal, and the pull-up node PU is precharged by the first scan signal. In the pull-up reset stage, the second input signal written into the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written into the second scan signal terminal VSD is a low-level signal, and the pull-up node PU is discharged by the second scan signal, thereby resetting the pull-up node PU.

[0308] When scanning in reverse, in the input stage, the second input signal written into the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written into the second scan signal terminal VSD is a high-level signal. At this time, the pull-up node PU is precharged by the second scan signal. In the pull-up reset stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written into the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is discharged by the first scan signal, thereby resetting the pull-up node PU.

[0309] The other structures of the shift register in this example may be the same as those in the seventeenth example, and thus will not be repeated here.

[0310] Example 22: Fig.24 22 is a circuit diagram of a shift register according to a twenty-second example of an embodiment of the present disclosure; Fig.24 As shown, the structure of the shift register of this example is substantially the same as that of the twenty-first example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51, and the second pull-down subcircuit 52 are different from those of the twenty-first example.

[0311] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0312] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0313] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0314] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0315] The other structures of the shift register in this example may be the same as those in the twenty-first example, so they will not be repeated here.

[0316] Example 23: Fig.25 23 is a circuit diagram of a shift register according to a twenty-third example of an embodiment of the present disclosure; Fig.25 As shown, the structure of the shift register of this example is substantially the same as that of the fourteenth example, with the only difference being that a cascade subcircuit 111 is added to the shift register of the twenty-second example, and the cascade output subcircuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0317] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13 , a source of M13 connected to the clock signal terminal CLK, a drain of M13 connected to the cascade signal terminal output_C(N), and a gate of M13 connected to the pull-up node PU.

[0318] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0319] When the shift register in the embodiment of the present disclosure is applied to the gate driving circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the N-1th shift register; except for the last stage shift register, the second input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0320] In some examples, the shift register not only includes the above-mentioned structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the first pull-down node PD1; and the other third noise reduction sub-circuit is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the second pull-down node PD2.

[0321] Among them, continue to refer to Fig.25 , the two third noise reduction sub-circuits can each include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0322] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0323] The other structures of the shift register in this example may be the same as those in the twenty-second example, so they will not be repeated here.

[0324] Example 24: Fig.26 24 is a circuit diagram of a shift register according to an embodiment of the present disclosure; Fig.26 As shown, the structure of the shift register of this example is substantially the same as that of the twenty-third example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51, and the second pull-down subcircuit 52 are different from those of the twenty-third example.

[0325] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0326] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0327] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0328] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0329] The other structures of the shift register in this example may be the same as those in the twenty-third example, so they will not be repeated here.

[0330] Example 25: Fig. 27 25 is a circuit diagram of a shift register according to an embodiment of the present disclosure; Fig. 27As shown, the shift register includes a first input subcircuit 11, a pull-up reset subcircuit 2, an output subcircuit 3, a first pull-down control subcircuit 41, a second pull-down control subcircuit 42, a first pull-down subcircuit 51, a second pull-down subcircuit 52, a first auxiliary subcircuit 91 and a second auxiliary subcircuit 92. Among them, the first input subcircuit 11 is configured to respond to the first input signal and precharge the pull-up node PU through the first input signal. The output subcircuit 3 is configured to respond to the potential of the pull-up node PU and output the clock signal through the signal output terminal. The pull-up reset subcircuit 2 is configured to respond to the pull-up reset signal and reset the output of the pull-up node PU through a low-level signal. The first pull-down control subcircuit 41 is configured to respond to the first power supply voltage and control the potential of the first pull-down node PD1 through the first power supply voltage. The second pull-down control subcircuit 42 is configured to respond to the second power supply voltage and control the potential of the second pull-down node PD2 through the second power supply voltage. The first pull-down subcircuit 51 is configured to pull down the potential of the first pull-down node PD1 through a low-level signal in response to the potential of the pull-up node PU. The second pull-down subcircuit 52 is configured to pull down the potential of the second pull-down node PD2 through a low-level signal in response to the potential of the pull-up node PU. The first auxiliary subcircuit 91 is configured to pull down the potential of the first pull-down node PD1 through a low-level signal in response to the potential of the second node when the second power supply voltage is a high-level signal. The second auxiliary subcircuit 92 is configured to pull down the potential of the second pull-down node PD2 through a low-level signal in response to the potential of the first node when the first power supply voltage is a high-level signal.

[0331] In this example, by adding a first auxiliary sub-circuit 91 and a second auxiliary sub-circuit 92, when the second pull-down control sub-circuit is working, that is, the second power supply voltage is converted from a low-level signal to a high-level signal, and the first power supply voltage is converted from a high-level signal to a low-level signal, the second pull-down node PD2 is pulled up to the high potential of the second power supply voltage, and before the pull-up node PU is charged (except for the first-stage shift register), the first auxiliary sub-circuit 91 is controlled to work through the high potential of the second node, and the first pull-down node PD1 is pulled down through a low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time, and only the second pull-down node PD2 competes with the potential of the pull-up node PU, which helps to improve the charging capacity of the pull-up node PU. Similarly, when the first pull-down control subcircuit is working, that is, the first power supply voltage is converted from a low-level signal to a high-level signal, and the second power supply voltage is converted from a high-level signal to a low-level signal, the first pull-down node PD1 is pulled up to the high potential of the first power supply voltage, and before the pull-up node PU is charged, the second auxiliary subcircuit 92 is controlled to work by the high potential of the first pull-down node PD1, and the second pull-down node PD2 is pulled down by the low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time, and only the potentials of the first pull-down node PD1 and the pull-up node PU compete with each other, which helps to improve the charging capacity of the pull-up node PU. In this example, the first auxiliary subcircuit 91 is controlled by the potential of the second pull-down node PD2, and the second auxiliary subcircuit 92 is controlled by the voltage of the first pull-down node PD1, that is, for the entire shift register, no control signal is added due to the addition of the first auxiliary subcircuit 91 and the second auxiliary subcircuit 92, so the control of the shift register is relatively simple.

[0332] Continue to refer to Fig. 27 When the shift register in the embodiment of the present disclosure is applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the N-stage shift register is connected to the signal output terminal G(N-1) of the N-1-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the N-stage shift register is connected to the signal output terminal G(N+1) of the N+1-stage shift register. N≥2, and N is an integer. The first input signal terminal of the first-stage shift register and the second input signal terminal of the last-stage shift register are connected to the frame start signal.

[0333] In some examples, continue to refer to Fig. 27, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 both include a seventeenth transistor. For ease of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is represented by M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is represented by M17B. Among them, the source of M17A is connected to the first pull-down node PD1, the drain of M17A is connected to the low-level signal terminal VGL, and the gate of M17A is connected to the second pull-down node PD2. The source of M17B is connected to the second pull-down node PD2, the drain of M17B is connected to the low-level signal terminal, and the gate of M17B is connected to the first pull-down node PD1.

[0334] Specifically, the first power supply voltage terminal VDDO is used to introduce the first power supply voltage, and the second power supply voltage terminal VDDE is used to introduce the second power supply voltage. When the second power supply voltage of the second power supply voltage terminal VDDE is converted from a low level to a high level, and the first power supply voltage of the first power supply voltage terminal VDDO is converted from a high level to a low level, M17A is turned on, and the low level signal written by the low level signal terminal VGL at this time pulls down the potential of the first pull-down node PD1. Similarly, when the first power supply voltage of the first power supply voltage terminal VDDO is converted from a low level to a high level, and the second power supply voltage of the second power supply voltage terminal VDDE is converted from a high level to a low level, M17B is turned on, and the low level signal written by the low level signal terminal VGL at this time pulls down the potential of the second pull-down node PD2. This example can effectively avoid the competition between the pull-up node PU and the first pull-down node PD1 / the second pull-down node PD2.

[0335] In some examples, continue to refer to Fig. 27 The shift register of the embodiment of the present disclosure further includes a global reset subcircuit 6, which is configured to respond to a global reset signal and globally reset the output of the pull-up node PU and the signal output terminal G(N) through a low-level signal.

[0336] The global reset subcircuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal STV0. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal STV0.

[0337] Specifically, in the global reset stage, the global reset signal written into the global reset signal terminal STV0 is a high-level signal, and the fourth transistor M4 and the seventh transistor M7 are both turned on. At this time, the low-level signal written into the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4, and resets the signal output terminal G(N) through the seventh transistor M7.

[0338] In some examples, continue to refer to Fig.19 , the shift register also includes two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the first pull-down node PD1, and the other performs noise reduction on the output of the pull-up node PU through a low-level signal in response to the potential of the second pull-down node PD2. One of the two second noise reduction sub-circuits performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the first pull-down node PD1, and the other performs noise reduction on the output of the signal output terminal G(N) through a low-level signal in response to the potential of the second pull-down node PD2.

[0339] Wherein, each first noise reduction sub-circuit includes a tenth transistor, and each second noise reduction sub-circuit includes an eleventh transistor. The tenth transistors in the two first noise reduction sub-circuits are represented by M10A and M10B respectively; the eleventh transistors in the two second noise reduction sub-circuits are represented by M11A and M11B respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0340] Specifically, in the output noise reduction stage, when the potential of the first pull-down node PD1 is at a high level, M10A and M11A are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) are pulled down by the low-level signal written by the low-level signal terminal VGL. When the potential of the second pull-down node PD2 is at a high level, M10B and M11B are turned on, and the potential of the pull-up node PU and the signal output terminal G(N) are pulled down by the low-level signal written by the low-level signal terminal VGL.

[0341] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source and gate of M1 are connected to the first input signal terminal, the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal.

[0342] Specifically, in the input stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the pull-up node PU is precharged by the high-level signal. In the pull-up reset stage, the pull-up reset signal written into the pull-up reset signal terminal is a high-level signal, M2 is turned on, and the pull-up node PU is discharged by a low-level signal, thereby resetting the pull-up node PU.

[0343] In some examples, the output subcircuit 3 includes a third transistor M3 and a storage capacitor C1; wherein the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0344] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the signal output terminal G(N) outputs a high-level signal.

[0345] In some examples, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 both include a fifth transistor and a ninth transistor. For ease of description, the fifth transistor and the ninth transistor in the first pull-down control subcircuit 41 are represented by M5A and M9A, respectively, and the fifth transistor and the ninth transistor in the second pull-down subcircuit 52 are represented by M5B and M9B, respectively. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE.

[0346] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A and M9A are both turned on, and the potential of the first pull-down node PD1 is pulled up to the first power supply voltage, that is, at a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, MB5 and M9B are both turned on, and the potential of the second pull-down node PD2 is pulled up to the second power supply voltage, that is, at a high potential. It should be noted that the first power supply voltage and the second power supply voltage can be the same power supply voltage. In the embodiment disclosed herein, only the first power supply voltage and the second power supply voltage are described as the same power supply voltage.

[0347] In some examples, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor and an eighth transistor; for ease of description, the sixth transistor and the eighth transistor in the first pull-down subcircuit 51 are represented by M6A and M8A, respectively, and the sixth transistor and the eighth transistor in the second pull-down subcircuit 52 are represented by M6B and M8B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B, the drain of M8B is connected to the low level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0348] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B / M8A / M8B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0349] Example 26: Fig.28 26 is a circuit diagram of a shift register according to an embodiment of the present disclosure; Fig.28 As shown, the structure of the shift register of this example is substantially the same as that of the twenty-fifth example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51, and the second pull-down subcircuit 52 are different from those of the twenty-fifth example.

[0350] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0351] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0352] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0353] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0354] The other structures of the shift register in this example may be the same as those in the twenty-fifth example, so they will not be repeated here.

[0355] Example 27: Fig.29 27 is a circuit diagram of a shift register according to an embodiment of the present disclosure; Fig.21 As shown, the structure of the shift register in this example is substantially the same as that in the twenty-fifth example, with the only difference being that a cascade sub-circuit 111 is added to the shift register in the twenty-fifth example, and the cascade output sub-circuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0356] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13 , a source of M13 connected to the clock signal terminal CLK, a drain of M13 connected to the cascade signal terminal output_C(N), and a gate of M13 connected to the pull-up node PU.

[0357] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0358] When the shift register in the embodiment of the present disclosure is applied to the gate drive circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the N-1th shift register; except for the last stage shift register, the pull-up reset signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0359] In some examples, continue to refer to Fig.21 The shift register not only includes the above structure, but also includes two third noise reduction sub-circuits, one of which is configured to respond to the potential of the first pull-down node PD1 and pull down the output of the cascade signal terminal through a low-level signal; the other third noise reduction sub-circuit is configured to respond to the potential of the second pull-down node PD2 and pull down the output of the cascade signal terminal through a low-level signal.

[0360] Among them, continue to refer to Fig.21 , the two third noise reduction sub-circuits can each include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0361] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0362] Continue to refer to Fig.29 The shift register in this example may further include a first discharge subcircuit 101 and a second discharge subcircuit 102; the first discharge subcircuit 101 is configured to discharge the first pull-down node PD1 through a low-level signal in response to the first input signal. The second discharge subcircuit 102 is configured to discharge the second pull-down node PD2 through a low-level signal in response to the first input signal.

[0363] Specifically, when the first input signal is written as a high-level signal, the first input sub-circuit 11 operates to pre-charge the pull-up node PU. At this time, the first pull-down node PD1 is discharged through the first discharge sub-circuit 101, and the second pull-down node PD2 is discharged through the second discharge sub-circuit 102, thereby avoiding competition between the potential of the first pull-down node PD1 and the second pull-down node PD2 and the pull-up node PU.

[0364] Wherein, the first discharge subcircuit 101 and the second discharge subcircuit 102 may both include a sixteenth transistor. For ease of description, the sixteenth transistor in the first discharge subcircuit 101 is represented by M16A, and the sixteenth transistor in the second discharge subcircuit 102 is represented by M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0365] In the input stage, the first input signal written into the first input signal terminal is a high level signal, M16A and M16B are both turned on, and the low level signal written into the low level signal terminal VGL pulls down the potentials of the first pull-down node PD1 and the second pull-down node PD2.

[0366] The other structures of the shift register in this example may be the same as those in the twenty-fifth example, so they will not be repeated here.

[0367] Example 28: Fig.30 28 is a circuit diagram of a shift register according to a twenty-eighth example of an embodiment of the present disclosure; Fig.30 As shown, the structure of the shift register of this example is substantially the same as that of the twenty-seventh example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51, and the second pull-down subcircuit 52 are different from those of the twenty-seventh example.

[0368] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0369] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0370] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0371] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0372] The other structures of the shift register in this example may be the same as those in the twenty-seventh example, so they will not be repeated here.

[0373] Example 29: Fig.31 29 is a circuit diagram of a shift register according to a twenty-ninth example of an embodiment of the present disclosure; Fig.31 As shown, the structure of the shift register of this example is roughly the same as that of the twenty-fifth example, and the only difference is that the shift register can realize bidirectional scanning, and the first input subcircuit 11 and the pull-up reset subcircuit 2 are different from those in the seventeenth example. In this example, since the shift register can realize bidirectional scanning, during forward scanning, the first input subcircuit 11 is used for precharging the pull-up node PU, and the pull-up reset subcircuit 2 is used for resetting the pull-up node PU; during reverse scanning, the first input subcircuit 11 is used for resetting the pull-up node PU, and the pull-up reset subcircuit 2 is used for precharging the pull-up node PU. Therefore, in order to facilitate understanding, the first input subcircuit 11 in the above example is still referred to as the first input subcircuit 11, and the pull-up reset subcircuit 2 is referred to as the second input subcircuit 12. Since the first input subcircuit 11 and the second input subcircuit 12 are the main components used to support the shift register to realize bidirectional scanning, the connection relationship between the first input subcircuit 11 and the second input subcircuit 12 and the above-mentioned first input subcircuit 11 and the pull-up reset subcircuit 2 is different.

[0374] Continue to refer to Fig.31 Specifically, the first input subcircuit 11 is configured to precharge the pull-up node PU through the first scan signal in response to the first input signal. The second input subcircuit 12 is configured to precharge the pull-up node PU through the second scan signal in response to the second input signal.

[0375] In some examples, the first input subcircuit 11 includes a first transistor M1; the second input subcircuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0376] Specifically, during forward scanning, in the input stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written into the first scan signal terminal VDS is a high-level signal, and the pull-up node PU is precharged by the first scan signal. In the pull-up reset stage, the second input signal written into the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written into the second scan signal terminal VSD is a low-level signal, and the pull-up node PU is discharged by the second scan signal, thereby resetting the pull-up node PU.

[0377] When scanning in reverse, in the input stage, the second input signal written into the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written into the second scan signal terminal VSD is a high-level signal. At this time, the pull-up node PU is precharged by the second scan signal. In the pull-up reset stage, the first input signal written into the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written into the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is discharged by the first scan signal, thereby resetting the pull-up node PU.

[0378] The other structures of the shift register in this example may be the same as those in the twenty-fifth example, so they will not be repeated here.

[0379] The 30th example: Fig.32 is a circuit diagram of a shift register according to the thirtieth example of an embodiment of the present disclosure; Fig.32 As shown, the structure of the shift register of this example is substantially the same as that of the thirtieth example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the twenty-ninth example.

[0380] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0381] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0382] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0383] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0384] The other structures of the shift register in this example may be the same as those in the twenty-ninth example, so they will not be repeated here.

[0385] Example 31: Fig.33 is a circuit diagram of a shift register according to a thirty-first example of an embodiment of the present disclosure; Fig.33 As shown, the structure of the shift register of this example is substantially the same as that of the fourteenth example, with the only difference being that the shift register adds a cascade subcircuit 111 on the basis of the shift register of the thirtieth example, and the cascade output subcircuit 3 is configured to output the clock signal through the cascade signal terminal in response to the potential of the pull-up node PU.

[0386] In some examples, the cascade sub-circuit 111 includes a thirteenth transistor M13 , a source of M13 connected to the clock signal terminal CLK, a drain of M13 connected to the cascade signal terminal output_C(N), and a gate of M13 connected to the pull-up node PU.

[0387] Specifically, in the output stage, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully opened, and the clock signal written by the clock signal terminal CLK is a high-level signal in this stage. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0388] When the shift register in the embodiment of the present disclosure is applied to the gate driving circuit, except for the first stage shift register, the first input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N-1) of the N-1th shift register; except for the last stage shift register, the second input signal terminal of the Nth stage shift register is connected to the cascade signal terminal output_C(N+1) of the N+1th shift register. N≥2, and N is an integer.

[0389] In some examples, the shift register not only includes the above-mentioned structure, but also includes two third noise reduction sub-circuits, one of which is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the first pull-down node PD1; and the other third noise reduction sub-circuit is configured to pull down the output of the cascade signal terminal through a low-level signal in response to the potential of the second pull-down node PD2.

[0390] Among them, continue to refer to Fig.33 , the two third noise reduction sub-circuits can each include a twelfth transistor, represented by M12A and M12B respectively; the source of M12A is connected to the cascade signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascade signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0391] Specifically, in the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written by the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0392] The other structures of the shift register in this example may be the same as those in the thirtieth example, so they will not be repeated here.

[0393] Example 32: Fig.34 32 is a circuit diagram of a shift register according to a thirty-second example of an embodiment of the present disclosure; Fig.34 As shown, the structure of the shift register of this example is substantially the same as that of the thirty-first example, with the only difference being that the specific structures of the first pull-down control subcircuit 41, the second pull-down control subcircuit 42, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are different from those of the thirty-first example.

[0394] Specifically, in this example, the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0395] When the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0396] In this example, the first pull-down subcircuit 51 and the second pull-down subcircuit 52 both include a sixth transistor. For ease of description, the sixth transistors in the first pull-down subcircuit 51 and the second pull-down subcircuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0397] Specifically, when the potential of the pull-up node PU is at a high level, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to a low level, ensuring that the pull-up node PU remains at a high level and outputs normally.

[0398] The other structures of the shift register in this example may be the same as those in the thirty-first example, so they will not be repeated here.

[0399] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, comprising: a first input subcircuit, an output subcircuit, a first pull-down control subcircuit, a second pull-down control subcircuit, a first pull-down subcircuit, and a second pull-down subcircuit; The first input subcircuit is configured to precharge the pull-up node by a first scan signal in response to a first input signal; The output subcircuit is configured to output the clock signal through the signal output terminal in response to the potential of the pull-up node; The first pull-down control subcircuit is configured to respond to a first power supply voltage and control the potential of the first pull-down node through the first power supply voltage; The second pull-down control subcircuit is configured to respond to a second power supply voltage and control the potential of the second pull-down node by the second power supply voltage; a first pull-down sub-circuit, responsive to the potential of the pull-up node, pulling down the first pull-down node; The second pull-down sub-circuit pulls down the second pull-down node in response to the potential of the pull-up node; wherein, The shift register further includes: a first auxiliary subcircuit and a second auxiliary subcircuit; The first auxiliary subcircuit is configured to pull down the potential of the first pull-down node to a non-operating level signal when the second power supply voltage is an operating level signal; The second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node to a non-operating level signal when the first power supply voltage is an operating level signal.

2. The shift register according to claim 1, wherein: The invention also includes a global reset subcircuit configured to globally reset the output of the pull-up node and the signal output terminal through a non-working level signal in response to a global reset signal.

3. The shift register according to claim 2, wherein: The first auxiliary subcircuit is specifically configured to respond to the global reset signal and, when the second power supply voltage is a working level signal, convert the non-working level signal through the first power supply voltage; The second auxiliary subcircuit is specifically configured to, in response to the global reset signal, pull down the potential of the second pull-down node to a non-operating level signal through the second power supply voltage when the first power supply voltage is an operating level signal.

4. The shift register according to claim 3, wherein: The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a seventeenth transistor; A first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first power supply voltage terminal, a second electrode is connected to the first pull-down node, and a control electrode is connected to the global reset signal terminal; A first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second power supply voltage terminal, a second electrode is connected to the second pull-down node, and a control electrode is connected to the global reset signal terminal.

5. The shift register according to claim 2, wherein: The global reset subcircuit includes a fourth transistor and a seventh transistor; The first electrode of the fourth transistor is connected to the pull-up node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the global reset signal terminal; The first electrode of the seventh transistor is connected to the signal output terminal, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the global reset signal terminal.

6. The shift register according to claim 1, wherein: The first auxiliary subcircuit is specifically configured to pull down the first pull-down node to a non-operating voltage through the first power supply voltage in response to a frame start signal when the second power supply voltage is an operating level signal; The second auxiliary sub-circuit is specifically configured to pull down the second pull-down node to a non-operating voltage through the second power supply voltage in response to a frame start signal when the first power supply voltage is an operating level signal.

7. The shift register according to claim 6, wherein: The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a seventeenth transistor; The first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first power supply voltage terminal, the second electrode is connected to the first pull-down node, and the control electrode is connected to the frame start signal terminal; A first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second power supply voltage terminal, a second electrode is connected to the second pull-down node, and a control electrode is connected to the frame start signal terminal.

8. The shift register according to claim 1, wherein: The first auxiliary subcircuit is specifically configured to pull down the first pull-down node through a non-working level signal in response to the second power supply voltage when the second power supply voltage is a working level signal; The second auxiliary sub-circuit is specifically configured to pull down the second pull-down node through a non-operating level signal in response to the first power supply voltage when the first power supply voltage is an operating level signal.

9. The shift register according to claim 8, wherein: The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a seventeenth transistor; The first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the second power supply voltage terminal; The first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the first power supply voltage terminal.

10. The shift register according to claim 1, wherein: The first auxiliary subcircuit is specifically configured to pull down the potential of the first pull-down node through a non-working level signal in response to the potential of the second pull-down node when the second power supply voltage is a working level signal; The second auxiliary sub-circuit is specifically configured to, when the first power supply voltage is a working level signal, respond to the potential of the first pull-down node and pull down the potential of the second pull-down node through a non-working level signal.

11. The shift register according to claim 10, wherein: The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a seventeenth transistor; A first electrode of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first pull-down node, a second electrode is connected to the non-working level signal terminal, and a control electrode is connected to the second pull-down node; The first electrode of the seventeenth transistor in the second auxiliary sub-circuit is connected to the second pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the first pull-down node.

12. The shift register according to any one of claims 1 to 11, wherein: The invention also includes a pull-up reset subcircuit configured to reset the output of the pull-up node through a non-working level signal in response to the pull-up reset signal.

13. The shift register according to claim 12, wherein: The pull-up reset subcircuit comprises a second transistor, a first electrode of the second transistor is connected to the pull-up node, a second electrode is connected to a non-working level signal terminal, and a control electrode is connected to a pull-up reset signal terminal.

14. The shift register according to claim 12, wherein: The first input signal is multiplexed into the first scanning signal; the first input sub-circuit includes a first transistor; The first electrode and the control electrode of the first transistor are connected to the first input signal terminal, and the second electrode is connected to the pull-up node.

15. The shift register according to any one of claims 1 to 11, wherein: The method further includes a second input sub-circuit configured to precharge the pull-up node through a second scan signal in response to a second input signal.

16. The shift register according to claim 15, wherein: The second input subcircuit includes a second transistor; The first electrode of the second transistor is connected to the pull-up node, the second electrode is connected to the second scan signal terminal, and the control electrode is connected to the second input signal terminal.

17. The shift register according to claim 15, wherein: The first input subcircuit includes a first transistor; The first electrode of the first transistor is connected to the first scan signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the first input signal terminal.

18. The shift register according to any one of claims 1 to 11, wherein: Also includes two first noise reduction sub-circuits and two second noise reduction sub-circuits; One of the two first noise reduction sub-circuits is configured to reduce the noise of the output of the pull-up node through a non-working level signal in response to the potential of the first pull-down node, and the other is configured to reduce the noise of the output of the pull-up node through a non-working level signal in response to the potential of the second pull-down node; One of the two second noise reduction sub-circuits is configured to respond to the potential of the first pull-down node and to reduce the noise of the output of the signal output end through a non-working level signal, and the other is configured to respond to the potential of the second pull-down node and to reduce the noise of the output of the signal output end through a non-working level signal.

19. The shift register according to claim 18, wherein: The two first noise reduction sub-circuits each include a tenth transistor; The first electrode of the tenth transistor in one of the first noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage end, and the control electrode is connected to the first pull-down node; the first electrode of the tenth transistor in another of the first noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage end, and the control electrode is connected to the second pull-down node.

20. The shift register according to claim 18, wherein: The two second noise reduction sub-circuits each include an eleventh transistor; The first electrode of the eleventh transistor in one of the second noise reduction sub-circuits is connected to the signal output terminal, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the first pull-down node; the first electrode of the eleventh transistor in another of the second noise reduction sub-circuits is connected to the pull-up node, the second electrode is connected to the non-working voltage terminal, and the control electrode is connected to the signal output terminal.

21. The shift register according to any one of claims 1 to 11, wherein: It also includes a cascade sub-circuit configured to output a clock signal through a cascade signal terminal in response to the potential of the pull-up node.

22. The shift register according to claim 21, wherein: The cascade sub-circuit includes a thirteenth transistor; The first electrode of the thirteenth transistor is connected to the clock signal terminal, the second electrode is connected to the cascade signal terminal, and the control electrode is connected to the pull-up node.

23. The shift register according to claim 21, wherein: Also included are two third noise reduction sub-circuits; One of the two third noise reduction sub-circuits is configured to perform noise reduction on the output of the cascade signal terminal through a non-working level signal in response to the control of the first pull-down node; The other is configured to reduce noise on the output of the cascade signal terminal through a non-working level signal in response to the control of the second pull-down node.

24. The shift register according to any one of claims 1 to 11, wherein: The first pull-down control subcircuit and the second pull-down control subcircuit each include a fifth transistor and a ninth transistor; For the first pull-down control sub-circuit, the first electrode of the fifth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor and the first power supply voltage terminal, and the second electrode is connected to the first pull-down node; For the second pull-down control sub-circuit, the first electrode of the fifth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor and the second power supply voltage terminal, and the second electrode is connected to the second pull-down node.

25. The shift register according to claim 24, wherein: The first pull-down sub-circuit and the second pull-down sub-circuit each include a sixth transistor and an eighth transistor; For the first pull-down sub-circuit, the first electrode of the sixth transistor is connected to the first pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node; the first electrode of the eighth transistor is connected to the control electrode of the fifth transistor and the first electrode of the ninth transistor, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node; For the second pull-down sub-circuit, the first electrode of the sixth transistor is connected to the second pull-down node, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the pull-up node; the first electrode of the eighth transistor is connected to the control electrode of the fifth transistor and the first electrode of the ninth transistor, the second electrode is connected to the non-working level signal end, and the control electrode is connected to the pull-up node.

26. The shift register according to any one of claims 1 to 11, wherein: The first pull-down control subcircuit and the second pull-down control subcircuit each include a fifth transistor; For the first pull-down control sub-circuit, the first electrode and the control electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the first pull-down node; For the first pull-down control sub-circuit, the first electrode and the control electrode of the fifth transistor are connected to the second power supply voltage terminal, and the second electrode is connected to the second pull-down node.

27. The shift register according to any one of claims 1 to 11, wherein: The first pull-down sub-circuit and the second pull-down sub-circuit each include a sixth transistor; The first electrode of the sixth transistor is connected to the first pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node; The first electrode of the sixth transistor is connected to the second pull-down node, the second electrode is connected to the non-working level signal terminal, and the control electrode is connected to the pull-up node.

28. A gate drive circuit, characterized in that: It comprises a plurality of cascaded shift registers, wherein the shift register is the shift register described in any one of claims 1 to 27.

29. A display device, characterized in that: Includes the gate drive circuit as described in claim 28.

Images