Core board of HDMI (High Definition Multimedia Interface) input interface

Abstract

The utility model discloses a core board of an HDMI input interface, and belongs to the field of chip boards. The onboard device comprises a board body, a golden finger used for being connected with an external substrate in an inserted mode is arranged on one side of the board body, and a plurality of pins corresponding to the data interfaces are defined on the golden finger. And the data interface comprises an HDMI (High Definition Multimedia Interface), an MIPI0 interface, an MIPI1 interface and an AUDIO interface. The beneficial effects are that HDMI-to-MIPI signal conversion is carried out through the bypass chip, and the signal is fed back to the SOC for screen projection, so that the video output delay can be reduced, and a clearer and smoother video can be obtained.

Description

Technical Field

[0001] The utility model relates to a core board of a HDMI input interface, belonging to the field of chip boards. Background Art

[0002] Currently, all development boards of the LT6911C chip do not have an HDMI in interface. If you use HDMI to USB to transmit images, the delay will be very high. Therefore, adding HDMI to MIPI CSI on the basis of this chip can reduce the delay. Utility Model Content

[0003] The purpose of the utility model is to provide a core board of an HDMI input interface, which can effectively solve the above-mentioned problems.

[0004] In order to solve the above technical problems, the utility model is achieved through the following technical solutions:

[0005] The onboard device includes a board body, and a gold finger for plugging with an external substrate is arranged on one side of the board body, and a plurality of pins corresponding to the data interface are defined on the gold finger;

[0006] The data interface includes an HDMI interface, a MIPI0 interface, a MIPI1 interface, and an AUDIO interface.

[0007] Further: the pin definition of the gold finger is that the 2nd, 3rd, 5th, 6th, 8th, 9th, 11th, 12th, 15th, 16th, 23rd, and 61st are HDMI interfaces for transmitting video data; the 26th, 27th, 28th, 29th, and 31st are AUDIO interfaces for transmitting audio data; the 40th, 39th, 36th, 35th, 38th, 37th, 42th, 41st, 44th, and 43rd are MIPI1 interfaces for transmitting video data to the display screen; the 54th, 53rd, 50th, 49th, 52nd, 51st, 56th, 55th, 58th, and 57th are MIPI0 interfaces for processing image data from the camera.

[0008] The beneficial effects are:

[0009] By converting HDMI to MIPI signals through the bypass chip and feeding them back to the SOC for screen projection, the delay of video output can be reduced, and clearer and smoother video can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For ease of explanation, the present invention is described in detail by the following specific implementations and drawings.

[0011] Figure 1 This is a schematic diagram of the chip board pins of the utility model. DETAILED DESCRIPTION

[0012] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to be used to explain the present invention, but cannot be understood as limiting the present invention.

[0013] It should be noted that, in the description of the present invention, unless otherwise specified, "plurality" means two or more; the terms "upper", "lower", "left", "right", "inside", "outside", "front end", "rear end", "head", "tail", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0014] Furthermore, the terms “first,” “second,” “third,” etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

[0015] At the same time, in the description of the present invention, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0016] See also Figure 1 This is an embodiment of a core board of an HDMI input interface of the utility model.

[0017] The onboard device includes a board body, and a gold finger for plugging with an external substrate is arranged on one side of the board body, and a plurality of pins corresponding to the data interface are defined on the gold finger;

[0018] The data interfaces include HDMI interface, MIPI0 interface, MIPI1 interface, and AUDIO interface.

[0019] Further: the pin definition of the gold finger is, the 2nd, 3rd, 5th, 6th, 8th, 9th, 11th, 12th, 15th, 16th, 23rd, and 61st are HDMI interfaces for transmitting video data; the 26th, 27th, 28th, 29th, and 31st are AUDIO interfaces for transmitting audio data; the 40th, 39th, 36th, 35th, 38th, 37th, 42th, 41st, 44th, and 43rd are MIPI1 interfaces for transmitting video data to the display screen; the 54th, 53rd, 50th, 49th, 52nd, 51st, 56th, 55th, 58th, and 57th are MIPI0 interfaces for processing image data from the camera.

[0020] The maximum clock rate of the RX Clock Channel Negative Input pin 2 is 340MHz. The maximum frequency of the negative input signal of the receiving clock channel of this chip is 340MHz.

[0021] Pin 3, RX Clock Channel Positive Input, has a maximum clock rate of 340MHz. The maximum frequency of the positive input signal of the receiving clock channel of this chip is 340MHz.

[0022] The maximum data rate of the RX Data Channel Lane-0 Negative Input of pins 5 and 6 is 3.4Gbps. This indicates that the maximum data rate of the negative input signal of the receiving data channel 0 of this product is 3.4Gbps.

[0023] The maximum data rate of the RX Data Channel Lane-1 Positive Input of pins 8 and 9 is 3.4Gbps. This indicates that the maximum data rate of the positive input signal of the receiving data channel 1 of this product is 3.4Gbps.

[0024] The maximum data rate of the RX Data Channel Lane-2 Positive Input of pins 11 and 12 is 3.4Gbps. This indicates that the maximum data rate of the positive input signal of the receiving end data channel 2 of this product is 3.4Gbps.

[0025] Pin 15 is used to transfer data between the master device and the slave device. The SDA signal is bidirectional and can be output by the master device or the slave device.

[0026] Pin 16 is used to control the rhythm of data transmission. The SCL signal is unidirectional and is sent from the master device to the slave device.

[0027] Although both SCL and SDA signals are key components in I2C communication, they differ in function, direction, and purpose. SCL is primarily responsible for controlling the clock for data transmission, while SDA is responsible for the actual transmission of data, and together they ensure effective and synchronous communication on the I2C bus.

[0028] Pin 23, in the DisplayPort (DP) receiver (RX) configuration, has the HPD (hot plug detection) signal, which is generated by the DP receiver (i.e., monitor or other display device) to tell the DP source device (such as a computer or video output device); and the signal is driven using a 3.3 volt TTL (transistor-transistor logic) signal level;

[0029] The standard value for the pin 61 surface mount chip resistor is 7.68 kilo-ohms.

[0030] Pin 26, GPIO is a general-purpose input and output port that can be configured as input or output and is used to connect external devices or sensors to achieve data interaction.

[0031] Pin 27, used to connect to the secure, manageable, modular, and extensible platform provided by the Web Server (IIS) role in Windows Server 2012;

[0032] Pin 28, SCLK (Serial Clock) is a key signal line in the IIS bus and is used to synchronize data transmission.

[0033] Pin 29, the master clock signal of the I2S interface, also known as the system clock or master clock. This clock signal is used to synchronize the internal operation of the audio codec (such as CS42436).

[0034] Pin 31 is mainly used to transmit digital audio signals.

[0035] Pin 40, MIPI TX Port3 / Clock Channel Negative Output, maximum frequency is 750MHz12;

[0036] LVDS TX Port3 / Lane2 Channel Negative Output, maximum data rate is 1.2Gbps;

[0037] Pin 39, MIPI TX Port3 / Clock Channel Positive Output, maximum frequency is 750MHz;

[0038] LVDS TX Port3 / Lane2 Channel Positive Output, maximum data rate 1.2Gbps;

[0039] Pin 36, MIPI TX Port3 / Lane0 Channel Negative Output, maximum data rate is 1.5Gbps.

[0040] LVDS TX Port3 / Lane3 Channel Negative Output, maximum data rate is 1.2Gbps.

[0041] Pin 35, MIPI TX Port3 / Lane0 Channel Positive Output, maximum data rate is 1.5Gbps;

[0042] LVDS TX Port3 / Lane3 Channel Positive Output, maximum data rate is 1.2Gbps.

[0043] Pin 38, MIPI TX Port3 / Lane1 Channel Negative Output, maximum data rate is 1.5Gbps;

[0044] LVDS TX Port3 / Clock Channel Negative Output, maximum frequency is 171MHz.

[0045] Pin 37, MIPI TX Port3 / Lane1 Channel Positive Output, maximum data rate is 1.5Gbps.

[0046] LVDS TX Port3 / Clock Channel Positive Output, maximum frequency is 171MHz.

[0047] Pin 42, MIPI TX Port3 / Lane2 Channel Negative Output, maximum data rate is 1.5Gbps.

[0048] LVDS TX Port3 / Lane1 Channel Negative Output, maximum data rate is 1.2Gbps.

[0049] Pin 41, MIPI TX Port3 / Lane2 Channel Positive Output, maximum data rate is 1.5Gbps;

[0050] LVDS TX Port3 / Lane1 Channel Positive Output, maximum data rate is 1.2Gbps.

[0051] Pin 44, MIPI TX Port3 / Lane3 Channel Negative Output, maximum data rate is 1.5Gbps.

[0052] LVDS TX Port3 / Lane0 Channel Negative Output, maximum data rate is 1.2Gbps.

[0053] Pin 43, MIPI TX Port3 / Lane3 Channel Positive Output, maximum data rate is 1.5Gbps.

[0054] LVDS TX Port3 / Lane0 Channel Positive Output, maximum data rate is 1.2Gbps. 54, 53, 50, 49, 52, 51, 56, 55, 58, 57

[0056] Pin 54, MIPI TX Port1 / Clock Channel Negative Output, maximum frequency is 750MHz.

[0057] LVDS TX Port1 / Lane2 Channel Negative Output, maximum data rate is 1.2Gbps.

[0058] Pin 53, MIPI TX Port1 / Clock Channel Positive Output, maximum frequency is 750MHz.

[0059] LVDS TX Port1 / Lane2 Channel Positive Output, maximum data rate is 1.2Gbps.

[0060] Pin 50, MIPI TX Port1 / Lane0 Channel Negative Output, maximum data rate is 1.5Gbps.

[0061] LVDS TX Port1 / Lane3 Channel Negative Output, maximum data rate is 1.2Gbps.

[0062] Pin 49, MIPI TX Port1 / Lane0 Channel Positive Output, maximum data rate is 1.5Gbps.

[0063] LVDS TX Port1 / Lane3 Channel Positive Output, maximum data rate is 1.2Gbps.

[0064] Pin 52, MIPI TX Port1 / Lane1 Channel Negative Output, maximum data rate is 1.5Gbps.

[0065] LVDS TX Port1 / Clock Channel Negative Output, maximum frequency is 171MHz.

[0066] Pin 51, MIPI TX Port1 / Lane1 Channel Positive Output, maximum data rate is 1.5Gbps.

[0067] LVDS TX Port1 / Clock Channel Positive Output, maximum frequency is 171MHz.

[0068] Pin 56, MIPI TX Port1 / Lane2 Channel Negative Output, maximum data rate is 1.5Gbps.

[0069] LVDS TX Port1 / Lane1 Channel Negative Output, maximum data rate is 1.2Gbps.

[0070] Pin 55, MIPI TX Port1 / Lane2 Channel Positive Output, maximum data rate is 1.5Gbps.

[0071] LVDS TX Port1 / Lane1 Channel Positive Output, maximum data rate is 1.2Gbps.

[0072] Pin 58, MIPI TX Port1 / Lane3 Channel Negative Output, maximum data rate is 1.5Gbps.

[0073] LVDS TX Port1 / Lane0 Channel Negative Output, maximum data rate is 1.2Gbps.

[0074] Pin 57, MIPI TX Port1 / Lane3 Channel Positive Output, maximum data rate is 1.5Gbps.

[0075] For LVDS TX Port1 / Lane0 Channel Positive Output, the maximum data rate is 1.2Gbps.

[0076] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention of the utility model.

Claims

1. A core board of an HDMI input interface, characterized in that: The onboard device includes a board body, and a gold finger for plugging with an external substrate is arranged on one side of the board body, and a plurality of pins corresponding to the data interface are defined on the gold finger; the data interface includes an HDMI interface, a MIPI0 interface, a MIPI1 interface, and an AUDIO interface.

2. The core board of the HDMI input interface according to claim 1, characterized in that: The pin definition of the gold finger is: the 2nd, 3rd, 5th, 6th, 8th, 9th, 11th, 12th, 15th, 16th, 23rd, and 61st are HDMI interfaces for transmitting video data; the 26th, 27th, 28th, 29th, and 31st are AUDIO interfaces for transmitting audio data; the 40th, 39th, 36th, 35th, 38th, 37th, 42th, 41st, 44th, and 43rd are MIPI1 interfaces for transmitting video data to the display screen; the 54th, 53rd, 50th, 49th, 52th, 51st, 56th, 55th, 58th, and 57th are MIPI0 interfaces for processing image data from the camera.

Images