Display device

Abstract

The utility model relates to a display device. The tiled display device comprises a display device. The display device includes: a substrate; a plurality of transistors on one surface of the substrate; a plurality of light emitting elements on the plurality of transistors; a plurality of bottom wirings on the back surface of the substrate; and a first selective reflective film between the substrate and the plurality of bottom wirings. The first selective reflective film includes M pairs of first and second layers, where M is an integer greater than or equal to 2. The refractive index of the first layer is higher than that of the second layer.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to a display device and a spliced ​​display device including the display device. Background Art

[0002] With the development of an information-oriented society, there is an increasing demand for display devices for displaying images in various ways. For example, a spliced ​​display device including a plurality of display devices is released as a product, and each of the plurality of display devices may be a flat panel display device such as a liquid crystal display, an electroluminescent display, and a light-emitting display. The light-emitting display device may include an organic light-emitting display panel or a light-emitting diode display panel, the organic light-emitting display panel including an organic light-emitting diode (OLED) element as a light-emitting element, and the light-emitting diode display panel including an inorganic light-emitting diode element such as a light-emitting diode (LED) as a light-emitting element.

[0003] A display device includes a display area in which pixels for displaying an image are arranged and a non-display area (or border area) arranged around the display area and in which wiring for driving the pixels is arranged. Recently, borderless display devices have been released to increase or maximize the area of ​​the display area. Therefore, there is an increasing demand for display devices that can reduce the area of ​​the non-display area or remove the non-display area by forming wiring on the side surface of the substrate.

[0004] Bottom wirings such as data lines and power lines may be disposed on the rear surface of the display device to reduce or minimize the non-display area of ​​the display device. However, in the process of patterning the bottom wirings, the characteristics of the thin film transistor (TFT) may be changed by plasma, and therefore, the bottom wirings may be identified in the inspection process of the thin film transistor (TFT) for inspecting the pixel. Utility Model Content

[0005] Aspects and features of embodiments of the present disclosure provide a display device and a tiled display device capable of preventing recognition of a bottom wiring during an inspection process for inspecting a thin film transistor of a pixel.

[0006] However, the embodiments of the present disclosure are not limited to those described herein. The above and other embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] According to one or more embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate; a plurality of transistors on one surface of the substrate; a plurality of light-emitting elements on the plurality of transistors; a plurality of bottom wirings on the rear surface of the substrate; and a first selective reflection film between the substrate and the plurality of bottom wirings. The first selective reflection film comprises M pairs of a first layer and a second layer, wherein M is an integer greater than or equal to 2. The refractive index of the first layer is higher than the refractive index of the second layer.

[0008] The target reflection wavelength of the first selective reflection film may be 310 nm or less.

[0009] A difference between a refractive index of the first layer and a refractive index of the second layer may be 0.55 or more.

[0010] The first layer can be TiO 2 , and the second layer may include SiO 2 or HfO 2 .

[0011] The first layer can be Si 3 N 4 , and the second layer includes SiO 2 .

[0012] The thickness of the first layer may be smaller than the thickness of the second layer.

[0013] The display device may further include a second selective reflection film between the substrate and the plurality of transistors. The second selective reflection film may include N pairs of third and fourth layers, where N is an integer greater than or equal to 2. The refractive index of the third layer may be higher than that of the fourth layer.

[0014] The target reflection wavelength of the second selective reflection film may be 310 nm or less.

[0015] The target reflection wavelength of the first selective reflection film may be substantially the same as the target reflection wavelength of the second selective reflection film.

[0016] The target reflection wavelength of the second selective reflection film may be smaller than the target reflection wavelength of the first selective reflection film.

[0017] The thickness of the second selective reflection film may be smaller than the thickness of the first selective reflection film.

[0018] The display device may further include a second selective reflection film between the substrate and the plurality of transistors. The second selective reflection film may include N pairs of third and fourth layers, where N is an integer greater than or equal to 2. The refractive index of the third layer may be higher than that of the fourth layer.

[0019] The target reflection wavelength of the second selective reflection film may be greater than the target reflection wavelength of the first selective reflection film.

[0020] The thickness of the second selective reflection film may be greater than the thickness of the first selective reflection film.

[0021] The thickness of the third layer may be greater than the thickness of the first layer, and the thickness of the fourth layer may be greater than the thickness of the third layer.

[0022] The display device may also include: data lines on one surface of the substrate; power lines on one surface of the substrate; and side wirings on the side surface of the substrate, connected to one or more of the bottom wirings and the data lines, and connected to one or more of the bottom wirings and the power lines.

[0023] The display device may further include a device identifier on a rear surface of the substrate and separated from the bottom wiring.

[0024] According to one or more embodiments of the present disclosure, a display device is provided, the display device including a substrate, a plurality of first transistors of a first sub-pixel and a plurality of second transistors of a second sub-pixel on a surface of the substrate, a first light-emitting element on the plurality of first transistors of the first sub-pixel and a second light-emitting element on the plurality of second transistors of the second sub-pixel, a plurality of bottom wirings on the rear surface of the substrate, and a first selective reflection film between the substrate and the plurality of bottom wirings. The first selective reflection film includes a first reflection film overlapping with the plurality of first transistors of the first sub-pixel in the thickness direction of the substrate and a second reflection film overlapping with the plurality of second transistors of the second sub-pixel in the thickness direction of the substrate. The first reflection film and the second reflection film are spaced apart from each other.

[0025] Each of the first reflective film and the second reflective film may include M pairs of first and second layers, where M may be an integer greater than or equal to 2. The refractive index of the first layer may be higher than that of the second layer.

[0026] According to one or more embodiments of the present disclosure, a spliced ​​display device is provided, the spliced ​​display device comprising a plurality of display devices and a connecting member between the plurality of display devices. One of the plurality of display devices comprises: a substrate; a plurality of transistors on one surface of the substrate; a plurality of light-emitting elements on the plurality of transistors; a plurality of bottom wirings on the rear surface of the substrate; and a first selective reflection film between the substrate and the plurality of bottom wirings. The first selective reflection film comprises M pairs of a first layer and a second layer, wherein M is an integer greater than or equal to 2. The refractive index of the first layer is higher than the refractive index of the second layer.

[0027] According to the above and other embodiments of the present disclosure, when the display panel includes a first selective reflection film that reflects short-wavelength light of 310 nm or less, the short-wavelength light can be prevented or reduced from being incident on the first channel to the nineteenth channel of the first transistor to the nineteenth transistor of each of the sub-pixels. Therefore, the threshold voltage of the first transistor to the nineteenth transistor can be prevented or reduced from being positively offset due to the short-wavelength light. Therefore, the difference in characteristics between the transistor that is positively offset by the influence of the short-wavelength light and the transistor that is not positively offset by the influence of the short-wavelength light can be minimized. Therefore, the visibility of the bottom wiring and the device identification in the current value image calculated in the inspection process can be reduced.

[0028] According to the above and other embodiments of the present disclosure, since the second selective reflection film has the same target reflection wavelength as the first selective reflection film, the light of the first wavelength that has passed through the first selective reflection film without being reflected by the first selective reflection film can be reflected by the second selective reflection film. Therefore, the short wavelength light of 310 nm or less can be further prevented from being incident on the first channel to the nineteenth channel of the first transistor to the nineteenth transistor of each of the sub-pixels.

[0029] According to the above and other embodiments of the present disclosure, since the second selective reflection film has a target reflection wavelength different from the target reflection wavelength of the first selective reflection film, the light of the second wavelength that has passed through the first selective reflection film without being reflected by the first selective reflection film can be reflected by the second selective reflection film. Therefore, short-wavelength light of 310 nm or less can be further prevented from being incident on the first to nineteenth channels of the first to nineteenth transistors of each of the sub-pixels.

[0030] According to the above and other embodiments of the present disclosure, because the second selective reflection film has a target reflection wavelength corresponding to the main peak wavelength of light emitted from the light emitting element, light emitted from the light emitting element that travels to the lower part can be reflected to the upper part and emitted, thereby improving the luminous efficiency of the light emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 and Figure 2 is a perspective view showing a display device according to one or more embodiments;

[0033] Figure 3 is a layout diagram showing first to third sub-pixels of a pixel of a display device according to one or more embodiments;

[0034] Figure 4 is a block diagram showing a display device according to one or more embodiments;

[0035] Figure 5 is an equivalent circuit diagram showing a first sub-pixel according to one or more embodiments;

[0036] Figure 6 is an equivalent circuit diagram showing a current path flowing through a first sub-pixel in an inspection process according to one or more embodiments;

[0037] Figure 7 is a cross-sectional view showing one example of first to fourth transistors and a light emitting element of a first subpixel according to one or more embodiments;

[0038] Figure 8 It is shown in detail Figure 7 an enlarged cross-sectional view of an example of a first selective reflection film;

[0039] Fig. 9 is shown by the patterning used Figure 2 Table of plasma wavelengths produced by different plasma gases of the bottom wiring shown in FIG.

[0040] Fig.10 The first reflective metal layer and the second reflective metal layer are shown. Figure 8 a table of the thickness of the first reflective metal layer and the thickness of the second reflective metal layer calculated for the first target wavelength shown in FIG.

[0041] Fig.11 and Fig.12 is a current value image showing current values ​​calculated by the inspection process when the first selective reflection film is present and absent;

[0042] Fig.13 is a cross-sectional view showing an example of first to fourth transistors of a first subpixel according to one or more embodiments;

[0043] Fig.14 It is shown in detail Fig.13 an enlarged cross-sectional view of an example of a second selective reflection film;

[0044] Fig.15 is a cross-sectional view showing one example of first to fourth transistors of a first subpixel according to one or more embodiments;

[0045] Fig.16 The third reflective metal layer and the fourth reflective metal layer are shown as follows Fig.14 a table of the thickness of the third reflective metal layer and the thickness of the fourth reflective metal layer calculated according to the second target wavelength shown in FIG.

[0046] Fig.17 is a cross-sectional view showing an example of first to fourth transistors of a first subpixel according to one or more embodiments;

[0047] Fig.18 It is shown Fig.17 an enlarged cross-sectional view of an example of a second selective reflection film;

[0048] Fig.19 The third reflective metal layer and the fourth reflective metal layer are shown as follows Fig.17 a table of the thickness of the third reflective metal layer and the thickness of the fourth reflective metal layer calculated according to the third target wavelength shown in FIG.

[0049] Fig. 20 is a cross-sectional view showing one example of a first transistor and a second transistor of a first sub-pixel and a first transistor and a second transistor of a second sub-pixel according to one or more embodiments;

[0050] Fig.21 is a perspective view showing a spliced ​​display device including a plurality of display devices according to one or more embodiments;

[0051] Fig. 22 It is shown in detail Fig.21 an enlarged layout diagram of area W; and

[0052] Fig.23 It is shown along Fig. 22 A cross-sectional view of an example of a spliced ​​display device taken along line N-N'. DETAILED DESCRIPTION

[0053] By referring to the detailed description and the accompanying drawings of the embodiments, the aspects and features of the embodiments of the present disclosure and the methods for realizing the same can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0054] Unless otherwise specified, the same reference numerals, numbers or combinations thereof denote the same elements throughout the drawings and written descriptions, and therefore, descriptions thereof will not be repeated. In addition, parts not related to the description of one or more embodiments may not be shown to make the description clear.

[0055] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. In addition, cross-hatching and / or shading used in the drawings are generally provided to clarify boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise stated.

[0056] Various embodiments are described herein with reference to cross-sectional views that are schematic diagrams of embodiments and / or intermediate structures. As such, variations in the shapes illustrated, such as due to manufacturing techniques and / or tolerances, are contemplated. In addition, specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the present disclosure. Therefore, the embodiments disclosed herein should not be construed as being limited to the specifically illustrated regional shapes, but rather should include deviations in shapes, such as due to manufacturing.

[0057] For example, an implant region shown as a rectangle may have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from an implant region to a non-implant region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to be limiting. Therefore, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways without departing from the spirit or scope of the present disclosure.

[0058] In the detailed description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of various embodiments. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments.

[0059] For ease of explanation, spatial relative terms such as "below", "below", "down", "below", "above", "on", etc. can be used in this article to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "below" or "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device can be oriented in addition (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged at the upper or lower side of the second part, without being limited to the upper side of the second part based on the direction of gravity.

[0060] Furthermore, in this specification, the phrase “on a plane” or “in a plan view” means observing a target portion from the top, and the phrase “in cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0061] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, such that one or more intervening elements, layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to, or there may be intervening layers, regions, or components. However, "directly connected / directly coupled" refers to one component being directly connected or directly coupled to another component without an intermediate component. Meanwhile, other expressions describing the relationship between components (such as "between," "directly between," or "adjacent to" and "directly adjacent to") can be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0062] For the purposes of the present disclosure, expressions such as "at least one of," "one of," and "selected from," when following an element of a list, modify the elements of the entire list without modifying the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XYY, XZ, YZ, and ZZ), or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0063] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as the second element, second component, second region, second layer or second part.

[0064] In the example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0065] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the presence of the features, wholes, steps, operations, elements and / or components set forth, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0066] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms rather than as terms of degree, and are intended to allow for inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within an acceptable range of deviations of the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, "may" used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure."

[0067] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in the reverse order of the described order.

[0068] In addition, any numerical range disclosed and / or listed herein is intended to include all sub-ranges of the same numerical precision contained in the range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 and the maximum value 10.0 (and including 1.0 and 10.0), that is, a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly describe any sub-range contained in the scope explicitly described herein. All such ranges are intended to be inherently described in this specification so that modifications for explicitly describing any such sub-ranges will meet the requirements of patent law or patent law.

[0069] The electronic device or electrical device and / or any other related device or component according to one or more embodiments of the present disclosure described herein can be implemented using any appropriate hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0070] In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using a standard storage device, such as, for example, a random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as, for example, a CD-ROM, a flash drive, etc. In addition, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed to one or more other computing devices without departing from the spirit and scope of the present disclosure.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0072] Figure 1 and Figure 2 is a perspective view showing a display device according to one or more embodiments.

[0073] refer to Figure 1 and Figure 2 The display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (tablet PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs).

[0074] The display device 10 according to one or more embodiments may include a display panel 100 , a first circuit board 200 , a source driving circuit 300 , a second circuit board 400 , and a power supply circuit 500 .

[0075] The display panel 100 includes a substrate SUB, a bottom wiring BTL, a plurality of pixels PX, a plurality of first side wirings SIL1, a plurality of second side wirings SIL2, and a plurality of device identifiers DID. The bottom wiring BTL includes a first bottom fan-out wiring BFL1 and a second bottom fan-out wiring BFL2.

[0076] The substrate SUB includes a first surface FS, a second surface BS, a plurality of chamfered surfaces CS1 to CS8 , and a plurality of side surfaces SS1 to SS4 .

[0077] The first surface FS may be a front surface of the substrate SUB The first surface FS may have a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2.

[0078] The second surface BS may be a surface opposite to the first surface FS. The second surface BS may be a rear surface of the substrate SUB. The second surface BS may have a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2. The second surface BS may be a surface opposite to the first surface FS.

[0079] The plurality of chamfered surfaces CS1 to CS8 refer to inclined cutting surfaces disposed between the first surface FS and the plurality of side surfaces SS1 to SS4 and between the second surface BS and the plurality of side surfaces SS1 to SS4 to prevent chipping defects from occurring in the plurality of first side wirings SIL1 and the plurality of second side wirings SIL2. Since each of the plurality of first side wirings SIL1 and the plurality of second side wirings SIL2 may have a gentle bending angle due to the plurality of chamfered surfaces CS1 to CS8, chipping or cracking of the plurality of first side wirings SIL1 and the plurality of second side wirings SIL2 may be prevented.

[0080] The first chamfered surface CS1 may extend from a first side (e.g., lower side) of the first surface FS. The second chamfered surface CS2 may extend from a second side (e.g., left side) of the first surface FS. The third chamfered surface CS3 may extend from a third side (e.g., upper side) of the first surface FS. The fourth chamfered surface CS4 may extend from a fourth side (e.g., right side) of the first surface FS. The inner angle formed by the first surface FS and the first chamfered surface CS1, the inner angle formed by the first surface FS and the second chamfered surface CS2, the inner angle formed by the first surface FS and the third chamfered surface CS3, and the inner angle formed by the first surface FS and the fourth chamfered surface CS4 may be greater than 90 degrees.

[0081] The fifth chamfered surface CS5 may extend from a first side (e.g., lower side) of the second surface BS. The sixth chamfered surface CS6 may extend from a second side (e.g., left side) of the second surface BS. The seventh chamfered surface CS7 may extend from a third side (e.g., upper side) of the second surface BS. The eighth chamfered surface CS8 may extend from a fourth side (e.g., right side) of the second surface BS. The inner angle formed by the second surface BS and the fifth chamfered surface CS5, the inner angle formed by the second surface BS and the sixth chamfered surface CS6, the inner angle formed by the second surface BS and the seventh chamfered surface CS7, and the inner angle formed by the second surface BS and the eighth chamfered surface CS8 may be greater than 90 degrees.

[0082] The first side surface SS1 may extend from the first chamfered surface CS1. The first chamfered surface CS1 may be disposed between the first surface FS and the first side surface SS1. The first side surface SS1 may be a lower surface of the substrate SUB.

[0083] The second side surface SS2 may extend from the second chamfered surface CS2. The second chamfered surface CS2 may be disposed between the first surface FS and the second side surface SS2. The second side surface SS2 may be a left side of the substrate SUB.

[0084] The third side surface SS3 may extend from the third chamfered surface CS3. The third chamfered surface CS3 may be disposed between the first surface FS and the third side surface SS3. The third side surface SS3 may be an upper surface of the substrate SUB.

[0085] The fourth side surface SS4 may extend from the fourth chamfered surface CS4. The fourth chamfered surface CS4 may be disposed between the first surface FS and the fourth side surface SS4. The fourth side surface SS4 may be a right side of the substrate SUB.

[0086] A plurality of pixels PX may be disposed on the first surface FS of the substrate SUB to display an image. The plurality of pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix along the first direction DR1 and the second direction DR2. Figure 3 A description is given of a plurality of pixels PX.

[0087] The plurality of first side wirings SIL1 may be disposed on the first surface FS, the second surface BS, and at least two chamfered surfaces of the plurality of chamfered surfaces CS1 to CS8, and may be disposed on at least one of the plurality of side surfaces SS1 to SS4. For example, the plurality of first side wirings SIL1 may be disposed on the first surface FS, the second surface BS, the first chamfered surface CS1, the fifth chamfered surface CS5, and the first side surface SS1 to connect the first pad disposed on the first side of the first surface FS and the first bottom fan-out wiring BFL1 of the second surface BS.

[0088] The plurality of second side wirings SIL2 may be disposed on the first surface FS, the second surface BS, and at least two of the plurality of chamfered surfaces CS1 to CS8, and may be disposed on at least one of the plurality of side surfaces SS1 to SS4. For example, the plurality of second side wirings SIL2 may be disposed on the first surface FS, the second surface BS, the third chamfered surface CS3, the seventh chamfered surface CS7, and the third side surface SS3 to connect a second pad disposed on a second side of the first surface FS opposite to the first side and a second bottom fan-out wiring BFL2 of the second surface BS.

[0089] Each of the plurality of first side wirings SIL1 connects a first pad disposed on the first surface FS and a first bottom fan-out wiring BFL1 disposed on the second surface BS. Each of the plurality of second side wirings SIL2 connects a second pad disposed on the first surface FS and a second bottom fan-out wiring BFL2 disposed on the second surface BS. The first pad and the second pad may correspond to a front pad. The first pad may be connected to a data line connected to a pixel PX of a substrate SUB. Some of the second pads may be connected to a first power line disposed on the first surface FS of the substrate SUB, and another portion may be connected to a global power line disposed on the first surface FS of the substrate SUB.

[0090] Each of the multiple device identifiers DID may be an identification, such as an identification number assigned to each display device 10 to distinguish the display device 10. The multiple device identifiers DID may be disposed on the second surface BS of the substrate SUB. When viewed on a plane, the multiple device identifiers DID may be disposed to be separated (e.g., separated) from the first bottom fan-out wiring BFL1, the second bottom fan-out wiring BFL2, the multiple first side wirings SIL1, and the multiple second side wirings SIL2. In addition, when viewed on a plane, the multiple device identifiers DID may be disposed to be separated (e.g., separated) from the multiple first circuit boards 200 and the second circuit boards 400. That is, the multiple device identifiers DID may be in an electrically floating state.

[0091] Some of the plurality of device identifiers DID may be disposed adjacent to the sixth chamfered surface CS6, and others may be disposed adjacent to the eighth chamfered surface CS8. Some of the plurality of device identifiers DID may be disposed closer to the fifth chamfered surface CS5 than others. Furthermore, some of the plurality of device identifiers DID may be disposed adjacent to the seventh chamfered surface CS7 compared to some of the above.

[0092] The plurality of device identifiers DID may be a back metal layer formed of the same material as the first bottom fan-out wiring BFL1 and the second bottom fan-out wiring BFL2 by the same process. For example, the back metal layer may be formed as a single layer or multiple layers made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or an alloy thereof.

[0093] A plurality of first circuit boards 200 may be disposed on the second surface BS of the substrate SUB. Each of the plurality of first circuit boards 200 may be connected to a first bottom fan-out wiring BFL1 disposed on the second surface BS of the substrate SUB by using a conductive adhesive member such as an anisotropic conductive film. The plurality of first circuit boards 200 may be electrically connected to the plurality of first side wirings SIL1 through the first bottom fan-out wiring BFL1. The plurality of first circuit boards 200 may be a flexible printed circuit board, a printed circuit board, and / or a flexible film.

[0094] The second circuit board 400 may be disposed on the second surface BS of the substrate SUB. The second circuit board 400 may be connected to the second bottom fan-out wiring BFL2 disposed on the second surface BS of the substrate SUB by using a conductive adhesive member. The second circuit board 400 may be electrically connected to the plurality of second side wirings SIL2 through the second bottom fan-out wiring BFL2. The second circuit board 400 may be a flexible printed circuit board, a printed circuit board, or a flexible film.

[0095] Each of the source driver circuits 300 may generate a data voltage and provide the generated data voltage to the data line through the first circuit board 200, the first bottom fan-out wiring BFL1, and the plurality of first side wirings SIL1. Each of the source driver circuits 300 may be formed as an integrated circuit (IC) and attached to the corresponding first circuit board 200. Alternatively, the source driver circuits 300 may be directly attached to the second surface BS of the substrate SUB using a chip on glass (COG) method.

[0096] The power circuit 500 can generate a suitable voltage (e.g., a predetermined voltage) and provide it to a suitable voltage line (e.g., a predetermined voltage line) through the second circuit board 400, the second bottom fan-out wiring BFL2, and the plurality of second side wirings SIL2. For example, the power circuit 500 can generate a first power supply voltage and provide it to a first power supply line through the second circuit board 400, the second bottom fan-out wiring BFL2, and the plurality of second side wirings SIL2. In addition, the power circuit 500 can generate a global power supply voltage GV and provide it to a global power supply line through the second circuit board 400, the second bottom fan-out wiring BFL2, and the plurality of second side wirings SIL2. The power circuit 500 can be formed as an integrated circuit (IC) and attached to the second circuit board 400. Alternatively, the power circuit 500 can be directly attached to the second surface BS of the substrate SUB using a chip on glass (COG) method.

[0097] like Figure 1 and Figure 2 As shown in , the flexible film bent along the side surface of the substrate SUB can be removed by using the plurality of first side wirings SIL1 and the plurality of second side wirings SIL2. Therefore, a borderless display device can be realized.

[0098] Figure 3 is a layout diagram showing first to third sub-pixels of a pixel of a display device according to one or more embodiments.

[0099] refer to Figure 3 , each of the pixels PX may include a plurality of sub-pixels SP1, SP2, and SP3. Figure 3 , it is shown that each of the pixels PX includes three sub-pixels SP1, SP2, and SP3, that is, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, but the present disclosure is not limited thereto. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be connected to a PWM data line DL (see Figure 4 ), at least one of the first data line RDL (see Figure 4 ), the second data line GDL (see Figure 4 ) and the third data line BDL (see Figure 4 ) and at least one of the scanning lines GWL, GIL, GCL, SWPL, PAEL, PWEL (see Figure 4 ) at least one of ).

[0100] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have a rectangular, square, or diamond plane shape. For example, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have a rectangular plane shape having a short side in the first direction DR1 and a long side in the second direction DR2. Alternatively, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have a square or diamond plane shape having sides having the same length.

[0101] like Figure 3 As shown in , the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged along the first direction DR1. Alternatively, one of the second sub-pixel SP2 and the third sub-pixel SP3 and the first sub-pixel SP1 may be arranged along the first direction DR1, and the other of the second sub-pixel SP2 and the third sub-pixel SP3 and the first sub-pixel SP1 may be arranged along the second direction DR2. For example, the first sub-pixel SP1 and the second sub-pixel SP2 may be arranged along the first direction DR1, and the first sub-pixel SP1 and the third sub-pixel SP3 may be arranged along the second direction DR2. Alternatively, one of the first sub-pixel SP1 and the third sub-pixel SP3 and the second sub-pixel SP2 may be arranged along the first direction DR1, and the other of the first sub-pixel SP1 and the third sub-pixel SP3 and the third sub-pixel SP3 may be arranged along the second direction DR2.

[0102] The first subpixel SP1 may emit a first light, the second subpixel SP2 may emit a second light, and the third subpixel SP3 may emit a third light. Here, the first light may be light of a red wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a blue wavelength band. The red wavelength band may be a wavelength band of about 600nm to 750nm, the green wavelength band may be a wavelength band of about 480nm to 560nm, and the blue wavelength band may be a wavelength band of about 370nm to 460nm, but the present disclosure is not limited thereto.

[0103] Each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may include an inorganic light emitting element having an inorganic semiconductor as a light emitting element that emits light. For example, the inorganic light emitting element may be a flip chip type micro light emitting diode (LED), but the present disclosure is not limited thereto.

[0104] like Figure 3As shown in , the area of ​​the first sub-pixel SP1, the area of ​​the second sub-pixel SP2, and the area of ​​the third sub-pixel SP3 may be substantially the same, but the present disclosure is not limited thereto. At least one of the area of ​​the first sub-pixel SP1, the area of ​​the second sub-pixel SP2, and the area of ​​the third sub-pixel SP3 may be different from the areas of the other sub-pixels. Alternatively, any two of the area of ​​the first sub-pixel SP1, the area of ​​the second sub-pixel SP2, and the area of ​​the third sub-pixel SP3 may be substantially the same, and the area of ​​another sub-pixel may be different from the areas of the above two sub-pixels. Alternatively, the area of ​​the first sub-pixel SP1, the area of ​​the second sub-pixel SP2, and the area of ​​the third sub-pixel SP3 may be different from each other.

[0105] Figure 4 is a block diagram illustrating a display device according to one or more embodiments.

[0106] refer to Figure 4 The display device 10 includes a display panel 100 , a scan driving circuit 110 , a data driving circuit 300G, a timing control circuit 600 and a power supply circuit 500 .

[0107] The display area DA of the display panel 100 may include sub-pixels SP1, SP2 and SP3 that display images, a scan write line GWL connected to the sub-pixels SP1, SP2 and SP3, a scan initialization line GIL, a scan control line GCL, a scan signal line SWPL, a PWM emission line PWEL, a PAM emission line PAEL, a PWM data line DL, a first data line RDL, a second data line GDL and a third data line BDL.

[0108] The scan write line GWL, the scan initialization line GIL, the scan control line GCL, the scan signal line SWPL, the PWM light emitting line PWEL, and the PAM light emitting line PAEL may extend in a first direction DR1 (X-axis direction), and may be arranged along a second direction DR2 (Y-axis direction) crossing the first direction DR1 (X-axis direction). The PWM data line DL, the first data line RDL, the second data line GDL, and the third data line BDL may extend in a second direction DR2 (Y-axis direction), and may be arranged along the first direction DR1 (X-axis direction). The first data lines RDL may be electrically connected to each other, the second data lines GDL may be electrically connected to each other, and the third data lines BDL may be electrically connected to each other.

[0109] The sub-pixels SP1, SP2, and SP3 may include a first sub-pixel SP1 emitting a first light, a second sub-pixel SP2 emitting a second light, and a third sub-pixel SP3 emitting a third light. The first light represents light of a red wavelength band, the second light represents light of a green wavelength band, and the third light represents light of a blue wavelength band. For example, the main peak wavelength of the first light may be within a range of about 600 nm to about 750 nm, the main peak wavelength of the second light may be within a range of about 480 nm to about 560 nm, and the main peak wavelength of the third light may be within a range of about 370 nm to about 460 nm.

[0110] Each of the sub-pixels SP1, SP2, and SP3 may be connected to one of the scan write lines GWL, one of the scan initialization lines GIL, one of the scan control lines GCL, one of the scan signal lines SWPL, one of the PWM light emission lines PWEL, and one of the PAM light emission lines PAEL. In addition, each of the first sub-pixels SP1 may be connected to one of the PWM data lines DL and one of the first data lines RDL. In addition, each of the second sub-pixels SP2 may be connected to one of the PWM data lines DL and one of the second data lines GDL. In addition, each of the third sub-pixels SP3 may be connected to one of the PWM data lines DL and one of the third data lines BDL.

[0111] The non-display area NDA of the display panel 100 may include a scan driving circuit 110 , a first demultiplexer DMX1 , and a second demultiplexer DMX2 .

[0112] The scan driving circuit 110 may be disposed on the display panel 100 to apply signals to the scan write lines GWL, the scan initialization lines GIL, the scan control lines GCL, the scan signal lines SWPL, the PWM emission lines PWEL, and the PAM emission lines PAEL. Figure 4 It is shown that the scan driving circuit 110 is disposed at one edge of the display panel 100 , but is not limited thereto. The scan driving circuit 110 may be disposed on both edges of the display panel 100 .

[0113] The scan driving circuit 110 may include a first scan signal driving circuit 111 , a second scan signal driving circuit 112 , a frequency scanning signal driving circuit 113 and a light emitting signal driving circuit 114 .

[0114] The first scan signal driving circuit 111 may receive a first scan driving control signal GDCS1 from the timing control circuit 600. The first scan signal driving circuit 111 may output a scan initialization signal to the scan initialization line GIL and a scan write signal to the scan write line GWL according to the first scan driving control signal GDCS1. That is, the first scan signal driving circuit 111 may output two scan signals together, namely, a scan initialization signal and a scan write signal.

[0115] The second scan signal driving circuit 112 may receive a second scan driving control signal GDCS2 from the timing control circuit 600. The second scan signal driving circuit 112 may output a scan control signal to the scan control line GCL according to the second scan driving control signal GDCS2.

[0116] The sweep signal driving circuit 113 may receive the first light emission control signal ECS1 and the sweep control signal SWCS from the timing control circuit 600. The sweep signal driving circuit 113 may output a PWM light emission signal to the PWM light emission line PWEL and output a sweep signal to the sweep signal line SWPL according to the first light emission control signal ECS1. In other words, the sweep signal driving circuit 113 may output the PWM light emission signal and the sweep signal together.

[0117] The light emitting signal driving circuit 114 may receive the second light emitting control signal ECS2 from the timing control circuit 600. The light emitting signal driving circuit 114 may output a PAM light emitting signal to the PAM light emitting line PAEL according to the second light emitting control signal ECS2.

[0118] The first demultiplexer DMX1 switches the connection between each PWM data line DL and the global power line GVL. In addition, the first demultiplexer DMX1 switches the connection between each first data line RDL and the first data voltage line RPL, switches the connection between each second data line GDL and the second data voltage line GPL, and switches the connection between each third data line BDL and the third data voltage line BPL.

[0119] The second demultiplexer DMX2 may be disposed between the fan-out wiring FL and the PWM data lines DL. The second demultiplexer DMX2 may distribute the PWM data voltage applied to each fan-out wiring FL to Q (Q is an integer greater than or equal to 2) PWM data lines DL or Q first data lines RDL, second data lines GDL, and third data lines BDL.

[0120] The first signal separator DMX1 may be disposed adjacent to the second pad, and the second signal separator DMX2 may be disposed adjacent to the first pad. That is, the first signal separator DMX1 may be disposed adjacent to one side of the display panel 100 (e.g., the lower side of the display panel 100). The second signal separator DMX2 may be disposed adjacent to the other side of the display panel 100 (e.g., the upper side of the display panel 100).

[0121] The timing control circuit 600 receives the digital video data DATA and the timing signal TSS. The timing control circuit 600 can generate the first scan drive control signal GDCS1, the second scan drive control signal GDCS2, the first light emission control signal ECS1, the second light emission control signal ECS2 and the sweep control signal SWCS for controlling the operation timing of the scan drive circuit 110 according to the timing signal TSS. In addition, the timing control circuit 600 can generate the source control signal DCS for controlling the operation timing of the data drive circuit 300G.

[0122] The timing control circuit 600 outputs the first scanning driving control signal GDCS1, the second scanning driving control signal GDCS2, the first emission control signal ECS1, the second emission control signal ECS2 and the sweep control signal SWCS to the scanning driving circuit 110. The timing control circuit 600 outputs the digital video data DATA and the source control signal DCS to the data driving circuit 300G.

[0123] The data driving circuit 300G may include a plurality of source driving circuits 300. The data driving circuit 300G converts digital video data DATA into an analog PWM data voltage and outputs it to the fan-out wiring FL.

[0124] The power supply circuit 500 may generate a first data voltage and output it to a first data voltage line RPL, may generate a second data voltage and output it to a second data voltage line GPL, and may generate a third data voltage and output it to a third data voltage line BPL. The power supply circuit 500 may generate a global power supply voltage GV and output it to a global power supply line GVL.

[0125] In addition, the power supply circuit 500 may generate a plurality of power supply voltages and output them to the display panel 100. For example, the power supply circuit 500 may output a first power supply voltage VDD1, a second power supply voltage VDD2, a third power supply voltage VSS, an initialization voltage VINT, a gate-on voltage VGL, and a gate-off voltage VGH to the display panel 100. The first power supply voltage VDD1 and the second power supply voltage VDD2 may be high potential driving voltages for driving the light emitting element of each of the sub-pixels SP1, SP2, and SP3. The third power supply voltage VSS may be a low potential driving voltage for driving the light emitting element of each of the sub-pixels SP1, SP2, and SP3. The initialization voltage VINT and the gate-off voltage VGH are applied to each of the sub-pixels SP1, SP2, and SP3, and the gate-on voltage VGL and the gate-off voltage VGH may be applied to the scan driving circuit 110.

[0126] Figure 5 is an equivalent circuit diagram illustrating a first subpixel according to one or more embodiments.

[0127] refer to Figure 5 , the first sub-pixel SP1 according to one or more embodiments may be connected to the k-th scan write line GWLk, the k-th scan initialization line GILk, the k-th scan control line GCLk, the k-th scan signal line SWPLk, the k-th PWM light-emitting line PWELk, and the k-th PAM light-emitting line PAELk. In addition, the first sub-pixel SP1 may be connected to the j-th PWM data line DLj and the first data line RDL. In addition, the first sub-pixel SP1 may be connected to the first power line VDL1 to which the first power voltage VDD1 is applied, the second power line VDL2 to which the second power voltage VDD2 is applied, the third power line VSL to which the third power voltage VSS is applied, the initialization voltage line VIL to which the initialization voltage VINT is applied, and the gate-off voltage line VGHL to which the gate-off voltage VGH is applied. Meanwhile, the j-th PWM data line DLj may be referred to as the first data line, and for ease of description, the first data line RDL may be referred to as the second data line.

[0128] The first sub-pixel SP1 may include a light emitting element EL, a first pixel driving unit PDU1 , a second pixel driving unit PDU2 , and a third pixel driving unit PDU3 .

[0129] The light emitting element EL emits light according to the driving current generated by the second pixel driving unit PDU2. The light emitting element EL may be disposed between the seventeenth transistor T17 and the third power line VSL. The first electrode of the light emitting element EL may be connected to the second electrode of the seventeenth transistor T17, and the second electrode may be connected to the third power line VSL. The first electrode of the light emitting element EL may be an anode electrode, and the second electrode may be a cathode electrode. The light emitting element EL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light emitting element EL may be a micro light emitting diode formed of an inorganic semiconductor, but is not limited thereto.

[0130] The first pixel driving unit PDU1 generates a control current according to the jth PWM data voltage of the jth PWM data line DLj to control the voltage of the third node N3 of the third pixel driving unit PDU3. Since the pulse width of the first driving current flowing through the light emitting element EL can be adjusted by the control current of the first pixel driving unit PDU1, the first pixel driving unit PDU1 can be a pulse width modulation PWM unit for performing pulse width modulation on the first driving current flowing through the light emitting element EL.

[0131] The first pixel driving unit PDU1 may include first to seventh transistors T1 to T7 and a first capacitor C1 .

[0132] The first transistor T1 controls a control current flowing between a first electrode and a second electrode of the first transistor T1 according to a PWM data voltage applied to a gate electrode.

[0133] The second transistor T2 is turned on by the kth scan write signal of the kth scan write line GWLk to provide the PWM data voltage of the jth PWM data line DLj to the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the kth scan write line GWLk, the first electrode may be connected to the jth PWM data line DLj, and the second electrode may be connected to the first electrode of the first transistor T1.

[0134] The third transistor T3 is turned on by the k-th scanning initialization signal of the k-th scanning initialization line GILk to connect the initialization voltage line VIL to the gate electrode of the first transistor T1. In this case, the gate-on voltage VGL of the k-th scanning initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. Specifically, because the voltage difference between the gate-on voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the third transistor T3, the third transistor T3 may be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the initialization voltage VINT may be stably applied to the gate electrode of the first transistor T1, regardless of the threshold voltage of the third transistor T3.

[0135] The third transistor T3 may include a plurality of transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. Therefore, the voltage of the gate electrode of the first transistor T1 may be prevented from leaking through the third transistor T3. The gate electrode of the first sub-transistor T31 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the gate electrode of the first transistor T1, and the second electrode may be connected to the first electrode of the second sub-transistor T32. The gate electrode of the second sub-transistor T32 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the second electrode of the first sub-transistor T31, and the second electrode may be connected to the initialization voltage line VIL.

[0136] The fourth transistor T4 is turned on by the kth scan write signal of the kth scan write line GWLk to connect the gate electrode of the first transistor T1 to the second electrode. Therefore, the first transistor T1 can operate as a diode while the fourth transistor T4 is turned on (eg, the first transistor T1 can be diode-connected).

[0137] The fourth transistor T4 may include a plurality of transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. Therefore, the voltage of the gate electrode of the first transistor T1 may be prevented from leaking through the fourth transistor T4. The gate electrode of the third sub-transistor T41 may be connected to the kth scan write line GWLk, the first electrode may be connected to the second electrode of the first transistor T1, and the second electrode may be connected to the first electrode of the fourth sub-transistor T42. The gate electrode of the fourth sub-transistor T42 may be connected to the kth scan write line GWLk, the first electrode may be connected to the second electrode of the third sub-transistor T41, and the second electrode may be connected to the gate electrode of the first transistor T1.

[0138] The fifth transistor T5 is turned on by the kth PWM light emitting signal of the kth PWM light emitting line PWELk to connect the first electrode of the first transistor T1 to the first power line VDL1. The gate electrode of the fifth transistor T5 may be connected to the kth PWM light emitting line PWELk, the first electrode may be connected to the first power line VDL1, and the second electrode may be connected to the first electrode of the first transistor T1.

[0139] The sixth transistor T6 is turned on by the kth PWM light emitting signal of the kth PWM light emitting line PWELk to connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driving unit PDU3. The gate electrode of the sixth transistor T6 may be connected to the kth PWM light emitting line PWELk, the first electrode may be connected to the second electrode of the first transistor T1, and the second electrode may be connected to the third node N3 of the third pixel driving unit PDU3.

[0140] The seventh transistor T7 is turned on by the kth scan control signal of the kth scan control line GCLk to provide the gate-off voltage VGH of the gate-off voltage line VGHL to the first node N1 connected to the kth sweep signal line SWPLk. Therefore, during the period in which the initialization voltage VINT is applied to the gate electrode of the first transistor T1 and the period in which the PWM data voltage of the jth PWM data line DLj and the threshold voltage of the first transistor T1 are programmed, the voltage change of the gate electrode of the first transistor T1 can be prevented from being reflected to the kth scan signal of the kth sweep signal line SWPLk through the first capacitor C1. The gate electrode of the seventh transistor T7 can be connected to the kth scan control line GCLk, the first electrode can be connected to the gate-off voltage line VGHL, and the second electrode can be connected to the first node N1.

[0141] The first capacitor C1 may be disposed between the gate electrode of the first transistor T1 and the first node N1. One electrode of the first capacitor C1 may be connected to the gate electrode of the first transistor T1, and the other electrode may be connected to the first node N1.

[0142] The first node N1 may be a contact point of the kth sweep signal line SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor C1.

[0143] The second pixel driving unit PDU2 generates a driving current applied to the light emitting element EL according to the first PWM data voltage of the first data line RDL. The second pixel driving unit PDU2 may be a pulse amplitude modulation unit (PAM unit) that performs pulse amplitude modulation. The second pixel driving unit PDU2 may be a constant current generator that generates a constant driving current according to the first PWM data voltage.

[0144] In addition, the second pixel driving unit PDU2 of each of the first sub-pixels SP1 can receive the same first PWM data voltage and generate the same driving current regardless of the brightness of the first sub-pixel SP1. Similarly, the second pixel driving unit PDU2 of each of the second sub-pixels SP2 can receive the same second PWM data voltage and generate the same driving current regardless of the brightness of the second sub-pixel SP2. The second pixel driving unit PDU2 of each of the third sub-pixels SP3 can receive the same third PWM data voltage and generate the same driving current regardless of the brightness of the third sub-pixel SP3.

[0145] The second pixel driving unit PDU2 may include eighth to fourteenth transistors T8 to T14 and a second capacitor C2 .

[0146] The eighth transistor T8 controls a driving current flowing to the light emitting element EL according to a voltage applied to a gate electrode of the eighth transistor T8.

[0147] The ninth transistor T9 is turned on by the kth scan write signal of the kth scan write line GWLk to provide the first PWM data voltage of the first data line RDL to the first electrode of the eighth transistor T8. The gate electrode of the ninth transistor T9 can be connected to the kth scan write line GWLk, the first electrode can be connected to the first data line RDL, and the second electrode can be connected to the first electrode of the eighth transistor T8.

[0148] The tenth transistor T10 is turned on by the k-th scanning initialization signal of the k-th scanning initialization line GILk to connect the initialization voltage line VIL to the gate electrode of the eighth transistor T8. Therefore, during the conduction period of the tenth transistor T10, the gate electrode of the eighth transistor T8 can be discharged to the initialization voltage VINT of the initialization voltage line VIL. In this case, the gate-on voltage VGL of the k-th scanning initialization signal can be different from the initialization voltage VINT of the initialization voltage line VIL. In particular, since the voltage difference between the gate-on voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the tenth transistor T10, the tenth transistor T10 can be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the eighth transistor T8. Therefore, when the tenth transistor T10 is turned on, the initialization voltage VINT can be stably applied to the gate electrode of the eighth transistor T8, regardless of the threshold voltage of the tenth transistor T10.

[0149] The tenth transistor T10 may include a plurality of transistors connected in series. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. Therefore, the voltage of the gate electrode of the eighth transistor T8 may be prevented from leaking through the tenth transistor T10. The gate electrode of the fifth sub-transistor T101 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the gate electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the sixth sub-transistor T102. The gate electrode of the sixth sub-transistor T102 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the second electrode of the fifth sub-transistor T101, and the second electrode may be connected to the initialization voltage line VIL.

[0150] The eleventh transistor T11 is turned on by the kth scan write signal of the kth scan write line GWLk and connects the gate electrode of the eighth transistor T8 to the second electrode. Therefore, the eighth transistor T8 can operate as a diode while the eleventh transistor T11 is turned on (eg, the eighth transistor T8 is diode-connected).

[0151] The eleventh transistor T11 may include a plurality of transistors connected in series. For example, the eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112. Therefore, the voltage of the gate electrode of the eighth transistor T8 may be prevented from leaking through the eleventh transistor T11. The gate electrode of the seventh sub-transistor T111 may be connected to the kth scan write line GWLk, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the eighth sub-transistor T112. The gate electrode of the eighth sub-transistor T112 may be connected to the kth scan write line GWLk, the first electrode may be connected to the second electrode of the seventh sub-transistor T111, and the second electrode may be connected to the gate electrode of the eighth transistor T8.

[0152] The twelfth transistor T12 is turned on by the kth PWM light emitting signal of the kth PWM light emitting line PWELk to connect the first electrode of the eighth transistor T8 to the second power line VDL2. The gate electrode of the twelfth transistor T12 may be connected to the kth PWM light emitting line PWELk, the first electrode may be connected to the second power line VDL2, and the second electrode may be connected to the first electrode of the eighth transistor T8.

[0153] The twelfth transistor T12 may include a plurality of transistors connected in parallel. For example, the twelfth transistor T12 may include a ninth sub-transistor T121 and a tenth sub-transistor T122. The gate electrodes of the ninth sub-transistor T121 and the tenth sub-transistor T122 may be connected to the kth PWM light emitting line PWELk, the first electrodes may be connected to the second power line VDL2, and the second electrodes may be connected to the first electrode of the eighth transistor T8.

[0154] The thirteenth transistor T13 is turned on by the kth scan control signal of the kth scan control line GCLk and connects the first power line VDL1 to the second node N2. A gate electrode of the thirteenth transistor T13 may be connected to the kth scan control line GCLk, a first electrode may be connected to the first power line VDL1, and a second electrode may be connected to the second node N2.

[0155] The fourteenth transistor T14 is turned on by the kth PWM light emitting signal of the kth PWM light emitting line PWELk, and connects the second power line VDL2 to the second node N2. Therefore, when the fourteenth transistor T14 is turned on, the second power supply voltage VDD2 of the second power line VDL2 can be provided to the second node N2. The gate electrode of the fourteenth transistor T14 can be connected to the kth PWM light emitting line PWELk, the first electrode can be connected to the second power line VDL2, and the second electrode can be connected to the second node N2.

[0156] The second capacitor C2 may be provided between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor C2 may be connected to the gate electrode of the eighth transistor T8, and the other electrode thereof may be connected to the second node N2.

[0157] The second node N2 may be a contact point of the second electrode of the thirteenth transistor T13 , the second electrode of the fourteenth transistor T14 , and the other electrode of the second capacitor C2 .

[0158] The third pixel driving unit PDU3 adjusts a period of applying a driving current to the light emitting element EL according to the voltage of the third node N3.

[0159] The third pixel driving unit PDU3 may include fifteenth to nineteenth transistors T15 to T19 and a third capacitor C3 .

[0160] The fifteenth transistor T15 is turned on or off according to the voltage of the third node N3. When the fifteenth transistor T15 is turned on, the driving current of the eighth transistor T8 can be provided to the light emitting element EL. In addition, when the fifteenth transistor T15 is turned off, the driving current of the eighth transistor T8 may not be provided to the light emitting element EL. Therefore, the conduction period of the fifteenth transistor T15 may be substantially the same as the emission period of the light emitting element EL. The gate electrode of the fifteenth transistor T15 may be connected to the third node N3, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the seventeenth transistor T17.

[0161] The sixteenth transistor T16 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the third node N3. Therefore, during the turn-on period of the sixteenth transistor T16, the third node N3 may be discharged to the initialization voltage VINT of the initialization voltage line VIL.

[0162] The sixteenth transistor T16 may include a plurality of transistors connected in series. For example, the sixteenth transistor T16 may include an eleventh sub-transistor T161 and a twelfth sub-transistor T162. Therefore, the voltage of the third node N3 may be prevented from leaking through the sixteenth transistor T16. The gate electrode of the eleventh sub-transistor T161 may be connected to the kth scan control line GCLk, the first electrode may be connected to the third node N3, and the second electrode may be connected to the first electrode of the twelfth sub-transistor T162. The gate electrode of the twelfth sub-transistor T162 may be connected to the kth scan control line GCLk, the first electrode may be connected to the second electrode of the eleventh sub-transistor T161, and the second electrode may be connected to the initialization voltage line VIL.

[0163] The seventeenth transistor T17 is turned on by the kth PAM emission signal of the kth PAM light emitting line PAELk to connect the second electrode of the fifteenth transistor T15 to the first electrode of the light emitting element EL. The gate electrode of the seventeenth transistor T17 may be connected to the kth PAM light emitting line PAELk, the first electrode may be connected to the second electrode of the fifteenth transistor T15, and the second electrode may be connected to the first electrode of the light emitting element EL.

[0164] The eighteenth transistor T18 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the first electrode of the light emitting element EL. Therefore, during the turn-on period of the eighteenth transistor T18, the first electrode of the light emitting element EL can be discharged to the initialization voltage VINT of the initialization voltage line VIL. The gate electrode of the eighteenth transistor T18 can be connected to the kth scan control line GCLk, the first electrode can be connected to the first electrode of the light emitting element EL, and the second electrode can be connected to the initialization voltage line VIL.

[0165] The nineteenth transistor T19 is turned on by the test signal of the test signal line TSTL to connect the first electrode of the light emitting element EL to the third power line VSL. The gate electrode of the nineteenth transistor T19 may be connected to the test signal line TSTL, the first electrode may be connected to the first electrode of the light emitting element EL, and the second electrode may be connected to the third power line VSL. The nineteenth transistor T19 may include a plurality of sub-transistors T191 and T192 connected in series. The gate electrodes of the sub-transistors T191 and T192 may be connected to the test signal line TSTL. The first electrode of the sub-transistor T191 may be connected to the first electrode of the light emitting element EL, and the second electrode of the sub-transistor T191 may be connected to the first electrode of the sub-transistor T192. The first electrode of the sub-transistor T192 may be connected to the second electrode of the sub-transistor T191, and the second electrode of the sub-transistor T192 may be connected to the third power line VSL.

[0166] The third capacitor C3 may be disposed between the third node N3 and the initialization voltage line VIL. One electrode of the third capacitor C3 may be connected to the third node N3, and the other electrode thereof may be connected to the initialization voltage line VIL.

[0167] The third node N3 may be a contact point of the second electrode of the sixth transistor T6, the gate electrode of the fifteenth transistor T15, the first electrode of the eleventh sub-transistor T161, and one electrode of the third capacitor C3.

[0168] One of the first electrode and the second electrode of each of the first to nineteenth transistors T1 to T19 may be a source electrode, and the other may be a drain electrode. The active layer of each of the first to nineteenth transistors T1 to T19 may be formed of one of polycrystalline silicon, amorphous silicon, and an oxide semiconductor. When the active layer of each of the first to nineteenth transistors T1 to T19 is polycrystalline silicon, it may be formed by a low temperature polycrystalline silicon (LTPS) process.

[0169] In addition, Figure 5In the above description, it is mainly described that each of the first to nineteenth transistors T1 to T19 is formed of a P-type MOSFET, but the present disclosure is not limited thereto. For example, each of the first to nineteenth transistors T1 to T19 may be formed of an N-type MOSFET.

[0170] Alternatively, the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 in the first sub-pixel SP1, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed by N-type MOSFETs to increase the ability of the light-emitting element EL to express black by blocking leakage current. In this case, the gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the gate electrode of the fourth sub-transistor T42 and the gate electrode of the seventh sub-transistor T111 and the gate electrode of the eighth sub-transistor T112 of the eleventh transistor T11 may be connected to the kth control line (not shown) to which the kth control signal is applied. The kth scan initialization signal GILk and the kth control signal may have a pulse generated as the gate-off voltage VGH. In addition, active layers of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 are formed of oxide semiconductor, and the remaining transistors may be formed of polycrystalline silicon.

[0171] Alternatively, one of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the active layer of the transistor formed of the N-type MOSFET in the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 may be formed of an oxide semiconductor, and the active layer of the transistor formed of the P-type MOSFET may be formed of polysilicon.

[0172] Alternatively, one of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 may be formed by an N-type MOSFET, and the other may be formed by a P-type MOSFET. In this case, the active layer of the transistor formed by the N-type MOSFET in the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 may be formed by an oxide semiconductor, and the active layer of the transistor formed by the P-type MOSFET may be formed by polysilicon.

[0173] Alternatively, one of the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the active layer of the transistor formed of the N-type MOSFET in the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 may be formed of an oxide semiconductor, and the active layer of the transistor formed of the P-type MOSFET may be formed of polysilicon.

[0174] Alternatively, one of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the active layer of the transistor formed of the N-type MOSFET in the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an oxide semiconductor, and the active layer of the transistor formed of the P-type MOSFET may be formed of polysilicon.

[0175] In one or more embodiments, the second sub-pixel SP2 and the third sub-pixel SP3 according to one or more embodiments may be combined with Figure 5 The described first subpixel SP1 is substantially the same. Therefore, the description of the second subpixel SP2 and the third subpixel SP3 according to one or more embodiments may not be repeated.

[0176] Figure 6 is an equivalent circuit diagram illustrating a current path flowing through a first sub-pixel in an inspection process according to one or more embodiments.

[0177] refer to Figure 6 , in the inspection process, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 may be turned on, and the fifth transistor T5 and the sixth transistor T6 of the first pixel driving unit PDU1 may be turned off. Due to the turn-on of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 in the inspection process, current may flow from the jth PWM data line DLj to the initialization voltage line VIL through the second transistor T2, the first transistor T1, the fourth transistor T4 and the third transistor T3 in the first pixel driving unit PDU1. Therefore, the current values ​​of the sub-pixels SP1, SP2 and SP3 of all pixels PX may be calculated by sensing the current passing through the jth PWM data line DLj. Therefore, as Fig.11 and Fig.12 As shown in , a current value image showing current values ​​can be calculated by mapping the current values ​​to the sub-pixels SP1 , SP2 , and SP3 of the pixel PX, respectively.

[0178] Figure 7 is a cross-sectional view illustrating one example of first to fourth transistors and a light emitting element of a first subpixel according to one or more embodiments.

[0179] refer to Figure 7 , the substrate SUB may be made of an insulating material such as glass and / or a polymer resin. For example, when the substrate SUB is made of a polymer resin, it may include polyimide. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc.

[0180] The buffer film BF may be disposed on the first surface of the substrate SUB. The buffer film BF may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer film BF may be formed as a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0181] The active layer may be disposed on the buffer film BF. The active layer includes Figure 5 The first channel to the nineteenth channel, the first source electrode to the nineteenth source electrode, and the first drain electrode to the nineteenth drain electrode of the first transistor T1 to the nineteenth transistor T19 shown in FIG. The active layer may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon and / or an oxide semiconductor. The first source electrode to the nineteenth source electrode and the first drain electrode to the nineteenth drain electrode may be a region having conductivity by doping a silicon semiconductor and / or an oxide semiconductor with ions or impurities.

[0182] exist Figure 7 , as an active layer, a first channel CH1, a first source electrode S1, and a first drain electrode D1 of a first transistor T1, a second channel CH2, a second source electrode S2, and a second drain electrode D2 of a second transistor T2, a first sub-channel CH31, a first sub-source electrode S31, and a first sub-drain electrode D31 of a first sub-transistor T31 of a third transistor T3, a second sub-channel CH32, a second sub-source electrode S32, and a second sub-drain electrode D32 of a second sub-transistor T32 of the third transistor T3, a third sub-channel CH41, a third sub-source electrode S41, and a third sub-drain electrode D41 of a third sub-transistor T41 of a fourth transistor T4, a fourth sub-channel CH42, a fourth sub-source electrode S42, and a fourth sub-drain electrode D42 of a fourth sub-transistor T42 of a fourth transistor T4.

[0183] The gate insulating film 130 may be disposed on the active layer. The gate insulating film 130 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0184] The first gate metal layer may be disposed on the gate insulating film 130. The first gate metal layer includes Figure 5The first gate electrode to the nineteenth gate electrode and the first gate connection electrode to the third gate connection electrode of the first transistor T1 to the nineteenth transistor T19 shown in . The first gate metal layer may be formed as a single layer or a multilayer made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) and / or an alloy thereof.

[0185] exist Figure 7 In the figure, the first gate electrode G1 of the first transistor T1, the second gate electrode G2 of the second transistor T2, the first sub-gate electrode G31 of the first sub-transistor T31 of the third transistor T3, the second sub-gate electrode G32 of the second sub-transistor T32 of the third transistor T3, the third sub-gate electrode G41 of the third sub-transistor T41 of the fourth transistor T4, and the fourth sub-gate electrode G42 of the fourth sub-transistor T42 of the fourth transistor T4 are shown as the first gate metal layer.

[0186] The first channel CH1 of the first transistor T1 overlaps with the first gate electrode G1 in the third direction DR3 (for example, the thickness direction of the substrate SUB), but does not overlap with the first source electrode S1 and the first drain electrode D1. The second channel CH2 of the second transistor T2 overlaps with the second gate electrode G2 in the third direction DR3, but does not overlap with the second source electrode S2 and the second drain electrode D2. The first sub-channel CH31 of the first sub-transistor T31 overlaps with the first sub-gate electrode G31 in the third direction DR3, but does not overlap with the first sub-source electrode S31 and the first sub-drain electrode D31. The second sub-channel CH32 of the second sub-transistor T32 overlaps with the second sub-gate electrode G32 in the third direction DR3, but does not overlap with the second sub-source electrode S32 and the second sub-drain electrode D32. The third sub-channel CH41 of the third sub-transistor T41 overlaps with the third sub-gate electrode G41 in the third direction DR3, but does not overlap with the third sub-source electrode S41 and the third sub-drain electrode D41. The fourth sub-channel CH42 of the fourth sub-transistor T42 overlaps the fourth sub-gate electrode G42 in the third direction DR3 , but does not overlap the fourth sub-source electrode S42 and the fourth sub-drain electrode D42 .

[0187] The first interlayer insulating film 141 may be disposed on the first gate metal layer. The first interlayer insulating film 141 may be formed of an inorganic layer such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0188] The second gate metal layer may be disposed on the first interlayer insulating film 141. The second gate metal layer includes Figure 5One electrode of the first capacitor C1, one electrode of the second capacitor C2, and one electrode of the third capacitor C3 shown in FIG. The second gate metal layer may be formed as a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0189] The second interlayer insulating film 142 may be disposed on the second gate metal layer. The second interlayer insulating film 142 may be formed of an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0190] The first source metal layer may be disposed on the second interlayer insulating film 142. The first source metal layer includes a first source connection electrode ACE1, a second source connection electrode ACE2, and an initialization voltage line VIL. The first source metal layer may be formed as a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or an alloy thereof.

[0191] The first source connection electrode ACE1 may be connected to the second source electrode S2 of the second transistor T2 through the first active contact hole ACH1 passing through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The second source connection electrode ACE2 may be connected to the first gate electrode G1 of the first transistor T1 through the gate contact hole GCH passing through the first interlayer insulating film 141 and the second interlayer insulating film 142. In addition, the second source connection electrode ACE2 may be connected to the first sub-source electrode S31 of the first sub-transistor T31 and the fourth sub-drain electrode D42 of the fourth sub-transistor T42 through the second active contact hole ACH2 passing through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The initialization voltage line VIL may be connected to the second sub-drain electrode D32 of the second sub-transistor T32 through the third active contact hole ACH3 passing through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0192] The first planarization film 160 may be disposed on the first source metal layer. The first planarization film 160 may be formed of an organic film such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0193] The first inorganic insulating film 161 may be disposed on the first planarization film 160. The first inorganic insulating film 161 may be formed of an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0194] The second source metal layer may be disposed on the first inorganic insulating film 161. The second source metal layer includes a j-th PWM data line DLj. The second source metal layer may be formed as a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or an alloy thereof. The j-th PWM data line DLj may be connected to the first source connection electrode ACE1 through a contact hole DCH passing through the first planarization film 160 and the first inorganic insulating film 161.

[0195] The second planarization film 180 may be disposed on the second source metal layer. The second planarization film 180 may be formed of an organic film such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0196] The second inorganic insulating film 181 may be disposed on the second planarization film 180. The second inorganic insulating film 181 may be formed of an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0197] The third source metal layer may be disposed on the second inorganic insulating film 181. The third source metal layer includes Figure 5 The third source metal layer may be formed as a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) and / or alloys thereof.

[0198] The third planarization film 190 may be disposed on the third source metal layer. The third planarization film 190 may be formed of an organic film such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0199] The third inorganic insulating film 191 may be disposed on the third planarization film 190. The third inorganic insulating film 191 may be formed of an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0200] The fourth source metal layer may be disposed on the third inorganic insulating film 191. The fourth source metal layer includes Figure 5 The fourth source metal layer may be formed as a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) and / or alloys thereof.

[0201] The third power line VSL, the anode pad electrode APD, and the cathode pad electrode CPD may be disposed to be separated (eg, spaced apart) from each other. That is, the third power line VSL, the anode pad electrode APD, and the cathode pad electrode CPD may be electrically separated.

[0202] The transparent metal layer TCO may be disposed on the anode pad electrode APD and the cathode pad electrode CPD. The transparent metal layer TCO may be a layer that increases adhesion with the first contact electrode CTE1 and the second contact electrode CTE2 of the light emitting element EL. The transparent metal layer TCO may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0203] The protective film PVX may be disposed on the third power line VSL, the anode pad electrode APD, the cathode pad electrode CPD, and the transparent metal layer TCO. The protective film PVX may be disposed to cover the edges of the third power line VSL, the anode pad electrode APD, the cathode pad electrode CPD, and the transparent metal layer TCO. The protective film PVX may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0204] The light emitting element EL is a flip chip type micro LED, in which the first contact electrode CTE1 and the second contact electrode CTE2 are arranged to face the anode pad electrode APD and the cathode pad electrode CPD. The light emitting element EL may be an inorganic light emitting element made of an inorganic material such as gallium nitride (GaN). The light emitting element EL may have a length of several micrometers to several hundred micrometers in the first direction DR1, the second direction DR2, and the third direction DR3. For example, each of the lengths of the light emitting element EL in the first direction DR1, the second direction DR2, and the third direction DR3 may be about 100 μm or less.

[0205] The light emitting element EL may be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the light emitting elements EL may be directly transferred from the silicon wafer to the anode pad electrode APD and the cathode pad electrode CPD of the substrate SUB. Alternatively, each of the light emitting elements EL may be transferred to the anode pad electrode APD and the cathode pad electrode CPD of the substrate SUB by an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material (such as PDMS or silicon) as a transfer substrate.

[0206] Each of the light emitting elements EL may be a light emitting structure including a base substrate SPUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE2.

[0207] The base substrate SPUB may be a sapphire substrate, but the present disclosure is not limited thereto.

[0208] The n-type semiconductor NSEM may be disposed on one surface of the base substrate SPUB. For example, the n-type semiconductor NSEM may be disposed on the lower surface of the base substrate SPUB. The n-type semiconductor NSEM may be made of GaN doped with an n-type conductive dopant such as Si, Ge, Se, and / or Sn.

[0209] The active layer MQW may be disposed on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, and may include other III- to V-group semiconductor materials according to the wavelength band of the emitted light.

[0210] The p-type semiconductor PSEM may be disposed on one surface of the active layer MQW. The p-type semiconductor PSEM may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, and / or Ba.

[0211] The first contact electrode CTE1 may be disposed on the p-type semiconductor PSEM, and the second contact electrode CTE2 may be disposed on another portion of one surface of the n-type semiconductor NSEM. Another portion of one surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is disposed may be disposed to be separated (e.g., spaced apart) from a portion of one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

[0212] The first contact electrode CTE1 and the anode pad electrode APD may be adhered to each other by a conductive adhesive such as an anisotropic conductive film or an anisotropic conductive paste. Alternatively, the first contact electrode CTE1 and the anode pad electrode APD may be bonded to each other by a welding process.

[0213] The first selective reflection film RFL1 may be disposed on a second surface of the substrate SUB opposite to the first surface. The first surface of the substrate SUB may be a front surface of the substrate SUB, and the second surface of the substrate SUB may be a rear surface of the substrate SUB. The first selective reflection film RFL1 may be designed to mainly reflect light λ1 of a first wavelength incident on the second surface of the substrate SUB. The light λ1 of the first wavelength may be light having a wavelength of 310 nm or less. Figures 8 to 12 A detailed description is given of the first selective reflection film RFL1.

[0214] The fifth source metal layer may be disposed on the first selective reflection film RFL1. The fifth source metal layer includes a bottom wiring BTL. The bottom wiring BTL may include Figure 2 The fifth source metal layer may be formed as a single layer or multiple layers of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) and / or alloys thereof.

[0215] Figure 8 It is shown in detail Figure 7 FIG. 1 is an enlarged cross-sectional view of an example of a first selective reflection film. Fig. 9 is shown by the patterning used Figure 2 Table of plasma wavelengths produced by different plasma gases shown in the bottom wiring. Fig.10 The first reflective metal layer and the second reflective metal layer are shown. Figure 8 The thickness of the first reflective metal layer and the thickness of the second reflective metal layer calculated for the first target wavelength are shown in the table. Figure 8 It is shown Figure 7 An enlarged cross-sectional view of region Z.

[0216] like Figure 8 As shown in , the first selective reflection film RFL1 may be used as a distributed Bragg reflector. That is, the first selective reflection film RFL1 may reflect light of a first wavelength and transmit light of other wavelengths. The first wavelength may be a target reflection wavelength to be reflected by the first selective reflection film RFL1.

[0217] The first selective reflection film RFL1 includes M pairs (M is an integer greater than or equal to 2) of first layers LL1 and second layers LL2 to serve as a distributed Bragg reflector. The M first layers LL1 and the M second layers LL2 may be alternately arranged. In each of the M pairs, the second layer LL2 may be arranged closer to the substrate SUB than the first layer LL1. For example, three pairs of the first layer LL1 and the second layer LL2 of the first selective reflection film RFL1 may be arranged in the third direction DR3 in the order of the bottom wiring BTL, the first layer LL1, the second layer LL2, the first layer LL1, the second layer LL2, the first layer LL1, the second layer LL2, and the substrate SUB.

[0218] like Fig. 9 As shown in FIG. 1 , in the process of forming the bottom wiring BTL, chlorine (Cl 2 ) gas, oxygen (O 2 ) gas, carbon tetrafluoride (CF 4 ) and oxygen (O 2) gas as a material for etching the bottom wiring BTL. For example, chlorine (Cl 2 ) gas may be a material directly involved in etching of the bottom wiring BTL, and oxygen (O 2 ) gas, carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) Gas can be a post-processing material for process optimization.

[0219] At this time, from chlorine (Cl 2 ) gas, the wavelength of short-wavelength light with high energy can be 260nm and 310nm. In addition, the wavelength of short-wavelength light emitted by oxygen (O 2 ) gas and carbon tetrafluoride (CF 4 ) can have a wavelength of 290nm, 300nm and 310nm. 2 )The wavelength of the high-energy short-wavelength light emitted by the gas can be 310nm.

[0220] When high-energy short-wavelength light is incident on the channels of the first to nineteenth transistors T1 to T19, the characteristics of the first to nineteenth transistors T1 to T19 may be changed due to the influence of the short-wavelength light. For example, the threshold voltages of the first to nineteenth transistors T1 to T19 may be positively shifted.

[0221] However, in the first to nineteenth channels of the first to nineteenth transistors T1 to T19, short-wavelength light may not be incident on the channel overlapping with the bottom wiring BTL in the third direction DR3. Therefore, a characteristic difference may occur between a transistor that is positively offset due to being affected by short-wavelength light and a transistor that is not positively offset without being affected by short-wavelength light.

[0222] The target reflection wavelength to be reflected by the first selective reflection film RFL1 may be 310 nm or less. For example, the target reflection wavelength of the first selective reflection film RFL1 may be 310 nm, which is the wavelength of chlorine (Cl 2 ) gas, oxygen (O 2 ) gas, carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) gas. Alternatively, the target reflection wavelength of the first selective reflection film RFL1 may be 290 nm or 300 nm, which is the wavelength of all emitted light from oxygen (O 2 ) gas and carbon tetrafluoride (CF 4 ) is the wavelength of light emitted. Alternatively, the target reflection wavelength of the first selective reflection film RFL1 may be 260 nm, which is the wavelength of light emitted from chlorine (Cl 2 )The wavelength of light emitted by the gas.

[0223] like Fig.10 As shown in FIG. 1 , the refractive index of the first layer LL1 may be greater than the refractive index of the second layer LL2. The first layer LL1 may be Si 3 N 4 or TiO 2 , and the second layer LL2 may be SiO 2 or HfO 2 For example, the first layer LL1 may be TiO 2 , and the second layer LL2 may be SiO 2 or HfO 2 Alternatively, the first layer LL1 may be Si 3 N 4 , and the second layer LL2 may be SiO 2 .

[0224] When the first layer LL1 is TiO 2 When the first layer LL1 is Si, the refractive index of the first layer LL1 may be 2.77. 3 N 4 When , the refractive index of the first layer LL1 may be 2.01.

[0225] When the second layer LL2 is HfO 2 When the second layer LL2 is SiO 2 When , the refractive index of the second layer LL2 can be 1.46.

[0226] The thickness of the first layer LL1 and the thickness of the second layer LL2 may be calculated as in Equation 1.

[0227] Equation 1

[0228]

[0229] In Equation 1, t represents the thickness of the first layer LL1 or the second layer LL2 of the first selective reflection film RFL1, λ represents the target reflection wavelength of the first selective reflection film RFL1, and n represents the refractive index of the first layer LL1 or the second layer LL2.

[0230] When the first layer LL1 is TiO 2 And the second layer LL2 is HfO 2When the first selective reflection film RFL1 includes three pairs of the first layer LL1 and the second layer LL2, the total thickness of the first selective reflection film RFL1 may be about 205.5 nm.

[0231] Alternatively, when the first layer LL1 is TiO 2 The second layer LL2 is SiO 2 When the first selective reflection film RFL1 includes three pairs of the first layer LL1 and the second layer LL2, the total thickness of the first selective reflection film RFL1 may be about 243 nm.

[0232] Alternatively, when the first layer LL1 is Si 3 N 4 The second layer LL2 is SiO 2 When the first selective reflection film RFL1 includes three pairs of the first layer LL1 and the second layer LL2, the total thickness of the first selective reflection film RFL1 may be about 274.5 nm.

[0233] Fig.11 and Fig.12 is a current value image showing current values ​​calculated by the inspection process when the first selective reflection film is present and absent.

[0234] When the display panel 100 does not include the first selective reflection film RFL1, in the manufacturing process of forming the bottom wiring BTL, short-wavelength light of 310nm or less may be incident on the first channel to the nineteenth channel of the first transistor T1 to the nineteenth transistor T19 of each of the sub-pixels SP1, SP2 and SP3. In this case, the characteristics of the first transistor T1 to the nineteenth transistor T19 may be changed due to the influence of the short-wavelength light. For example, the threshold voltage of the first transistor T1 to the nineteenth transistor T19 may be positively shifted. However, in the first channel to the nineteenth channel of the first transistor T1 to the nineteenth transistor T19, the short-wavelength light may not be incident on the channel overlapping with the bottom wiring BTL in the third direction DR3.

[0235] That is, when the display panel 100 does not include the first selective reflection film RFL1, a characteristic difference may occur between a transistor that is positively shifted due to being affected by short-wavelength light and a transistor that is not positively shifted without being affected by short-wavelength light. Fig.11 As shown in , since whether it is affected by short-wavelength light is determined by whether the channel of the transistor overlaps with the bottom wiring BTL, the bottom wiring pattern BTLP corresponding to the bottom wiring BTL and the device identifier pattern DIDP corresponding to the device identifier DID can be formed in the circuit composed of Figure 6 The current value calculated by the inspection process is identified in the image.

[0236] like Figures 8 to 10 As shown in , when the display panel 100 includes a first selective reflection film RFL1 that reflects short-wavelength light of 310 nm or less, the short-wavelength light can be prevented or reduced from being incident on the first channel to the nineteenth channel of the first transistor T1 to the nineteenth transistor T19 of each of the sub-pixels SP1, SP2, and SP3. Therefore, the threshold voltage of the first transistor T1 to the nineteenth transistor T19 due to the short-wavelength light can be prevented or reduced. Therefore, the characteristic difference between the transistor that is positively offset by the influence of the short-wavelength light and the transistor that is not positively offset without being affected by the short-wavelength light can be reduced or minimized. As shown in FIG. Fig.12 As shown in Figure 6 The visibility of the bottom wiring pattern BTLP and the device identifier pattern DIDP in the current value image of the inspection process calculation is checked.

[0237] Fig.13 is a cross-sectional view illustrating an example of first to fourth transistors of a first subpixel according to one or more embodiments.

[0238] Fig.13 The implementation method and Figure 7 The difference between the embodiments is that a second selective reflection film RFL2 is provided instead of the buffer film BF. Fig.13 In the implementation mode of Figure 7 The description of the implementation method is repeated.

[0239] refer to Fig.13 , the second selective reflection film RFL2 may be disposed on the first surface of the substrate SUB. The first surface of the substrate SUB may be the front surface of the substrate SUB, and the second surface of the substrate SUB may be the rear surface of the substrate SUB.

[0240] Active layer ACT (see Fig.14 ) may be disposed on the second selective reflection film RFL2. The second selective reflection film RFL2 may be designed to mainly reflect the light λ1 of the first wavelength incident on the second surface of the substrate SUB. Fig.14 A detailed description is given of the second selective reflection film RFL2.

[0241] Fig.14 It is shown in detail Fig.13 FIG. 1 is an enlarged cross-sectional view of an example of a second selective reflection film. Fig.14 It is shown Fig.13 An enlarged cross-sectional view of region Y.

[0242] refer to Fig.14 , the second selective reflection film RFL2 can be used as a distributed Bragg reflector. That is, the second selective reflection film RFL2 can be used as a selective reflection film that reflects light of a first wavelength and transmits light of another wavelength. To this end, the second selective reflection film RFL2 includes N pairs (N is an integer greater than or equal to 2) of third layers LL3 and fourth layers LL4. N third layers LL3 and N fourth layers LL4 can be alternately arranged. In each of the N pairs, the third layer LL3 can be arranged closer to the substrate SUB than the fourth layer LL4. For example, three pairs of third layers LL3 and fourth layers LL4 of the second selective reflection film RFL2 can be arranged in the third direction DR3 in the order of substrate SUB, third layer LL3, fourth layer LL4, third layer LL3, fourth layer LL4, third layer LL3, fourth layer LL4 and active layer ACT.

[0243] The target reflection wavelength to be reflected by the second selective reflection film RFL2 may be substantially the same as the target reflection wavelength of the first selective reflection film RFL1. That is, the target reflection wavelength to be reflected by the second selective reflection film RFL2 may be 310 nm or less. In this case, the material, refractive index, and thickness of the third layer LL3 may be substantially the same as the material, refractive index, and thickness of the first layer LL1. In addition, the material, refractive index, and thickness of the fourth layer LL4 may be substantially the same as the material, refractive index, and thickness of the second layer LL2. That is, the material, refractive index, and thickness of the third layer LL3, the material, refractive index, and thickness of the fourth layer LL4, and the thickness of the second selective reflection film RFL2 may be substantially the same as the material, refractive index, and thickness of the first layer LL1, the material, refractive index, and thickness of the second layer LL2, and the thickness of the first selective reflection film RFL1.

[0244] like Fig.13 and Fig.14 As shown in , because the second selective reflection film RFL2 has the same target reflection wavelength as the first selective reflection film RFL1, the first wavelength light λ1 that passes through the first selective reflection film RFL1 without being reflected by the first selective reflection film RFL1 can be reflected by the second selective reflection film RFL2. Therefore, short wavelength light of 310 nm or less can be further prevented from being incident on the first to nineteenth channels of the first to nineteenth transistors T1 to T19 of each of the sub-pixels SP1, SP2, and SP3.

[0245] Fig.15 is a cross-sectional view illustrating one example of first to fourth transistors of a first subpixel according to one or more embodiments.

[0246] Fig.15 The implementation method and Figure 7 The difference of the embodiment is that a second selective reflection film RFL2_1 is provided instead of the buffer film BF. Fig.15 In the implementation mode of Figure 7 The description of the implementation method is repeated.

[0247] refer to Fig.15 , the second selective reflection film RFL2_1 may be disposed on a first surface of the substrate SUB. The first surface of the substrate SUB may be a front surface of the substrate SUB, and the second surface of the substrate SUB may be a rear surface of the substrate SUB.

[0248] The active layer may be disposed on the second selective reflection film RFL2_1. The second selective reflection film RFL2_1 may be designed to mainly reflect light λ2 of a second wavelength incident on the second surface of the substrate SUB. That is, the target reflection wavelength to be reflected by the second selective reflection film RFL2_1 is 310 nm or less, but the target reflection wavelength to be reflected by the second selective reflection film RFL2_1 may be different from the target reflection wavelength of the first selective reflection film RFL1.

[0249] For example, when the target reflection wavelength of the first selective reflection film RFL1 is 310 nm (which is from chlorine (Cl 2 ) gas, oxygen (O 2 ) gas and carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) When the wavelength of light emitted by the gas is 290 nm, the target reflection wavelength of the second selective reflection film RFL2_1 may be 290 nm or 300 nm, which is the wavelength of light emitted by the oxygen (O 2 ) gas and carbon tetrafluoride (CF 4 Alternatively, the target reflection wavelength of the second selective reflection film RFL2_1 may be 260 nm, which is the wavelength of light emitted from chlorine (Cl 2 )The wavelength of light emitted by the gas.

[0250] like Fig.15 As shown in , because the second selective reflection film RFL2 has a target reflection wavelength different from the target reflection wavelength of the first selective reflection film RFL1, the second wavelength light λ2 that passes through the first selective reflection film RFL1 without being reflected by the first selective reflection film RFL1 can be reflected by the second selective reflection film RFL2. Therefore, short wavelength light of 310 nm or less can be further prevented from being incident on the first to nineteenth channels of the first to nineteenth transistors T1 to T19 of each of the sub-pixels SP1, SP2, and SP3.

[0251] Fig.16 The third reflective metal layer and the fourth reflective metal layer are shown as follows Fig.14 The thickness of the third reflective metal layer and the thickness of the fourth reflective metal layer calculated for the second target wavelength are shown in the table.

[0252] refer to Fig.16 , the second selective reflection film RFL2_1 may have a combination with Fig.14 Essentially the same structure as described.

[0253] When the third layer LL3 is TiO 2 And the fourth layer LL4 is HfO 2When the third layer LL3 has a refractive index of 2.77 and the fourth layer LL4 has a refractive index of 1.9, the difference between the refractive index of the third layer LL3 and the refractive index of the fourth layer LL4 may be about 0.87. When the target reflection wavelength of the second selective reflection film RFL2_1 is 260nm, the thickness of the third layer LL3 may be about 23.5nm, and the thickness of the fourth layer LL4 may be about 34.2nm. In this case, when the second selective reflection film RFL2_1 includes three pairs of the third layer LL3 and the fourth layer LL4, the total thickness of the second selective reflection film RFL2_1 may be about 173.1nm.

[0254] Alternatively, when the third layer LL3 is TiO 2 And the fourth layer LL4 is SiO 2 When the second selective reflection film RFL2_1 includes three pairs of the third layer LL3 and the fourth layer LL4, the total thickness of the second selective reflection film RFL2_1 may be about 204 nm.

[0255] Alternatively, when the third layer LL3 is Si 3 N 4 And the fourth layer LL4 is SiO 2 When the third layer LL3 has a refractive index of 2.01, the fourth layer LL4 has a refractive index of 1.46. The difference between the refractive index of the third layer LL3 and the refractive index of the fourth layer LL4 may be about 0.55. When the target reflection wavelength of the second selective reflection film RFL2_1 is 260nm, the thickness of the third layer LL3 may be about 32.3nm, and the thickness of the fourth layer LL4 may be about 44.5nm. In this case, when the second selective reflection film RFL2_1 includes three pairs of the third layer LL3 and the fourth layer LL4, the total thickness of the second selective reflection film RFL2_1 may be about 230.4nm.

[0256] Fig.17 is a cross-sectional view illustrating an example of first to fourth transistors of a first subpixel according to one or more embodiments.

[0257] refer to Fig.17, the second selective reflection film RFL2_2 may be disposed on the first surface of the substrate SUB. The first surface of the substrate SUB may be the front surface of the substrate SUB, and the second surface of the substrate SUB may be the rear surface of the substrate SUB.

[0258] The active layer may be disposed on the second selective reflection film RFL2_2. The second selective reflection film RFL2_2 may be designed to mainly reflect the light λ3 of the third wavelength emitted from the light emitting element EL.

[0259] The target reflection wavelength of the second selective reflection film RFL2_2 may be different from the target reflection wavelength of the first selective reflection film RFL 1. Specifically, the target reflection wavelength of the second selective reflection film RFL2_2 may be greater than the target reflection wavelength of the first selective reflection film RFL 1.

[0260] The target reflection wavelength reflected by the second selective reflection film RFL2_2 may be the main peak wavelength of light emitted from the light emitting element EL having the lowest light emitting efficiency. For example, the target reflection wavelength of the second selective reflection film RFL2_2 may be about 650 nm, which is the main peak wavelength of light of the red wavelength band emitted by the light emitting element EL of the first sub-pixel SP1. Alternatively, the target reflection wavelength of the second selective reflection film RFL2_2 may be about 520 nm, which is the main peak wavelength of light of the green wavelength band emitted by the light emitting element EL of the second sub-pixel SP2. Alternatively, the target reflection wavelength of the second selective reflection film RFL2_2 may be about 420 nm, which is the main peak wavelength of light of the blue wavelength band emitted by the light emitting element EL of the second sub-pixel SP2.

[0261] Fig.18 It is shown Fig.17 FIG. 1 is an enlarged cross-sectional view of an example of a second selective reflection film. Fig.19 The third reflective metal layer and the fourth reflective metal layer are shown as follows Fig.17 The thickness of the third reflective metal layer and the thickness of the fourth reflective metal layer calculated according to the third target wavelength are shown in the table. Fig.18 It is shown Fig.17 An enlarged cross-sectional view of region X.

[0262] refer to Fig.18, the second selective reflection film RFL2_2 can be used as a distributed Bragg reflector. That is, the second selective reflection film RFL2_2 can be used as a selective reflection film that reflects light of a third wavelength and transmits light of other wavelengths. To this end, the second selective reflection film RFL2_2 includes N pairs (N is an integer greater than or equal to 2) of third layers LL3 and fourth layers LL4. N third layers LL3 and N fourth layers LL4 can be alternately arranged. In each of the N pairs, the third layer LL3 can be arranged farther away from the substrate SUB than the fourth layer LL4. For example, three pairs of third layers LL3 and fourth layers LL4 of the second selective reflection film RFL2_2 can be arranged in the third direction DR3 in the order of substrate SUB, fourth layer LL4, third layer LL3, fourth layer LL4, third layer LL3, fourth layer LL4, third layer LL3 and active layer ACT.

[0263] refer to Fig.19 , when the third layer LL3 is TiO 2 And the fourth layer LL4 is HfO 2 When the second selective reflection film RFL2_2 includes three pairs of the third layer LL3 and the fourth layer LL4, the total thickness of the second selective reflection film RFL2_2 may be approximately 432.6 nm.

[0264] Alternatively, when the third layer LL3 is TiO 2 And the fourth layer LL4 is SiO 2 When the second selective reflection film RFL2_2 includes three pairs of the third layer LL3 and the fourth layer LL4, the total thickness of the second selective reflection film RFL2_2 may be about 510 nm.

[0265] Alternatively, when the third layer LL3 is Si 3 N 4 And the second layer LL2 is SiO 2When the third layer LL3 has a refractive index of 2.01, the fourth layer LL4 has a refractive index of 1.46. The difference between the refractive index of the third layer LL3 and the refractive index of the fourth layer LL4 may be about 0.55. When the target reflection wavelength of the second selective reflection film RFL2_2 is 650nm, the thickness of the third layer LL3 may be about 80.9nm, and the thickness of the fourth layer LL4 may be about 111.3nm. In this case, when the second selective reflection film RFL2_2 includes three pairs of the third layer LL3 and the fourth layer LL4, the total thickness of the second selective reflection film RFL2_2 may be about 576.6nm.

[0266] like Figures 17 to 19 As shown in , the second selective reflection film RFL2 has a target reflection wavelength corresponding to the main peak wavelength of light emitted from the light emitting element EL. Therefore, since light traveling downward from the light emitting element EL can be reflected and emitted upward, the light emitting efficiency of the light emitting element EL can be improved.

[0267] Fig. 20 is a cross-sectional view illustrating one example of first and second transistors of a first subpixel and first and second transistors of a second subpixel according to one or more embodiments.

[0268] refer to Fig. 20 The first selective reflection film RFL1 includes a plurality of reflection films SRFL1 and SRFL2 disposed to be separated (eg, spaced apart) from each other. Each of the plurality of reflection films SRFL1 and SRFL2 may overlap the first to nineteenth transistors T1 to T19 of each of the sub-pixels SP1, SP2, and SP3.

[0269] For example, the first selective reflection film RFL1 may include a first reflection film SRFL1 and a second reflection film SRFL2. The first reflection film SRFL1 may overlap the first to nineteenth transistors T1 to T19 of the first sub-pixel SP1 in the third direction DR3. The second reflection film SRFL2 may overlap the first to nineteenth transistors T1 to T19 of the second sub-pixel SP2 in the third direction DR3. Since the first reflection film SRFL1 and the second reflection film SRFL2 are spaced apart from each other, a gap may exist between the first reflection film SRFL1 and the second reflection film SRFL2.

[0270] because Fig. 20 Each of the first reflective film SRFL1 and the second reflective film SRFL2 shown in FIG. Figure 7 and Figure 8 The described first selective reflection film RFL1 is substantially the same, so the description of the first reflection film SRFL1 and the second reflection film SRFL2 is omitted.

[0271] Fig.21 is a perspective view showing a spliced ​​display device including a plurality of display devices according to one or more embodiments.

[0272] refer to Fig.21 , the spliced ​​display device TDIS may include a plurality of display devices 11, 12, 13 and 14 and a connecting member SM. The plurality of display devices 11, 12, 13 and 14 may be arranged in a matrix form with M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the spliced ​​display device TDIS may include a first display device 11, a second display device 12, a third display device 13 and a fourth display device 14.

[0273] The first display device 11 and the second display device 12 may be adjacent to each other in the first direction DR1. The first display device 11 and the third display device 13 may be adjacent to each other in the second direction DR2. The third display device 13 and the fourth display device 14 may be adjacent to each other in the first direction DR1. The second display device 12 and the fourth display device 14 may be adjacent to each other in the second direction DR2.

[0274] However, the number and arrangement of the plurality of display devices 11, 12, 13 and 14 in the spliced ​​display device TDIS are not limited to Fig.21 The number and arrangement of the display devices 11, 12, 13 and 14 in the tiled display device TDIS may be determined according to the sizes of the display device 10 and the tiled display device TDIS and the shape of the tiled display device TDIS.

[0275] The plurality of display devices 11, 12, 13, and 14 may have the same size as each other, but the embodiments of the present disclosure are not limited thereto. For example, the plurality of display devices 11, 12, 13, and 14 may have different sizes.

[0276] Each of the plurality of display devices 11, 12, 13, and 14 may have a rectangular shape including a long side and a short side. The plurality of display devices 11, 12, 13, and 14 may be arranged so that their long sides or short sides are connected to each other. Some or all of the plurality of display devices 11, 12, 13, and 14 may be arranged at the edge of the splicing display device TDIS, and may form one side of the splicing display device TDIS. At least one of the plurality of display devices 11, 12, 13, and 14 may be arranged at at least one corner of the splicing display device TDIS, and may form two adjacent sides of the splicing display device TDIS. At least one of the plurality of display devices 11, 12, 13, and 14 may be surrounded by other display devices.

[0277] Each of the plurality of display devices 11, 12, 13, and 14 may be connected to a reference Figure 1 and Figure 2 The display devices 10 described are substantially the same. Therefore, the description of each of the plurality of display devices 11, 12, 13, and 14 will be omitted.

[0278] The connection member SM may include a coupling member or an adhesive member. In this case, the plurality of display devices 11, 12, 13, and 14 may be connected to each other by the coupling member or the adhesive member of the connection member SM. The connection member SM may be provided between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0279] Fig. 22 It is shown in detail Fig.21 An enlarged layout diagram of area W.

[0280] refer to Fig. 22 , the connection member SM may have a plane shape of a cross or a plus sign in a central area of ​​the spliced ​​display device TDIS where the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14 are adjacent to each other. The connection member SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0281] The first display device 11 may include first pixels PX1 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The second display device 12 may include second pixels PX2 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image.

[0282] A minimum distance between first pixels PX1 adjacent in the first direction DR1 may be defined as a first horizontal spacing distance GH1, and a minimum distance between second pixels PX2 adjacent in the first direction DR1 may be defined as a second horizontal spacing distance GH2. The first horizontal spacing distance GH1 and the second horizontal spacing distance GH2 may be substantially the same.

[0283] The connection member SM may be disposed between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1. The minimum distance G12 between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1 may be the sum of the minimum distance GHS1 in the first direction DR1 between the first pixel PX1 and the connection member SM, the minimum distance GHS2 in the first direction DR1 between the second pixel PX2 and the connection member SM, and the width GSM1 in the first direction DR1 of the connection member SM.

[0284] The minimum distance G12, the first horizontal spacing distance GH1, and the second horizontal spacing distance GH2 between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1 may be substantially the same. To this end, the minimum distance GHS1 in the first direction DR1 between the first pixel PX1 and the connection member SM may be smaller than the first horizontal spacing distance GH1, and the minimum distance GHS2 in the first direction DR1 between the second pixel PX2 and the connection member SM may be smaller than the second horizontal spacing distance GH2. In addition, the width GSM1 of the connection member SM in the first direction DR1 may be smaller than the first horizontal spacing distance GH1 or the second horizontal spacing distance GH2.

[0285] A minimum distance between third pixels PX3 adjacent in the first direction DR1 may be defined as a third horizontal spacing distance GH3, and a minimum distance between fourth pixels PX4 adjacent in the first direction DR1 may be defined as a fourth horizontal spacing distance GH4. The third and fourth horizontal spacing distances GH3 and GH4 may be substantially the same.

[0286] The connection member SM may be disposed between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1. The minimum distance G34 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1 may be the sum of the minimum distance GHS3 in the first direction DR1 between the third pixel PX3 and the connection member SM, the minimum distance GHS4 in the first direction DR1 between the fourth pixel PX4 and the connection member SM, and the width GSM1 in the first direction DR1 of the connection member SM.

[0287] The minimum distance G34, the third horizontal spacing distance GH3, and the fourth horizontal spacing distance GH4 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1 may be substantially the same. To this end, the minimum distance GHS3 in the first direction DR1 between the third pixel PX3 and the connection member SM may be smaller than the third horizontal spacing distance GH3, and the minimum distance GHS4 in the first direction DR1 between the fourth pixel PX4 and the connection member SM may be smaller than the fourth horizontal spacing distance GH4. In addition, in the first direction DR1, the width GSM1 of the connection member SM may be smaller than the third horizontal spacing distance GH3 or the fourth horizontal spacing distance GH4.

[0288] A minimum distance between first pixels PX1 adjacent in the second direction DR2 may be defined as a first vertical spacing distance GV1, and a minimum distance between third pixels PX3 adjacent in the second direction DR2 may be defined as a third vertical spacing distance GV3. The first vertical spacing distance GV1 and the third vertical spacing distance GV3 may be substantially the same.

[0289] The connection member SM may be disposed between the first pixel PX1 and the third pixel PX3 adjacent in the second direction DR2. The minimum distance GP13 between the first pixel PX1 and the third pixel PX3 adjacent in the second direction DR2 may be the sum of the minimum distance GVS1 in the second direction DR2 between the first pixel PX1 and the connection member SM, the minimum distance GVS3 in the second direction DR2 between the third pixel PX3 and the connection member SM, and the width GSM2 in the second direction DR2 of the connection member SM.

[0290] The minimum distance GP13, the first vertical spacing distance GV1, and the third vertical spacing distance GV3 between the first pixel PX1 and the third pixel PX3 adjacent in the second direction DR2 may be substantially the same. To this end, the minimum distance GVS1 in the second direction DR2 between the first pixel PX1 and the connection member SM may be smaller than the first vertical spacing distance GV1, and the minimum distance GVS3 in the second direction DR2 between the third pixel PX3 and the connection member SM may be smaller than the third vertical spacing distance GV3. In addition, in the second direction DR2, the width GSM2 of the connection member SM may be smaller than the first vertical spacing distance GV1 or the third vertical spacing distance GV3.

[0291] A minimum distance between second pixels PX2 adjacent in the second direction DR2 may be defined as a second vertical spacing distance GV2, and a minimum distance between fourth pixels PX4 adjacent in the second direction DR2 may be defined as a fourth vertical spacing distance GV4. The second vertical spacing distance GV2 and the fourth vertical spacing distance GV4 may be substantially the same.

[0292] The connection member SM may be disposed between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2. The minimum distance G24 between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2 may be the sum of the minimum distance GVS2 in the second direction DR2 between the second pixel PX2 and the connection member SM, the minimum distance GVS4 in the second direction DR2 between the fourth pixel PX4 and the connection member SM, and the width GSM2 in the second direction DR2 of the connection member SM.

[0293] The minimum distance G24, the second vertical spacing distance GV2, and the fourth vertical spacing distance GV4 between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2 may be substantially the same. To this end, the minimum distance GVS2 in the second direction DR2 between the second pixel PX2 and the connection member SM may be smaller than the second vertical spacing distance GV2, and the minimum distance GVS4 in the second direction DR2 between the fourth pixel PX4 and the connection member SM may be smaller than the fourth vertical spacing distance GV4. In addition, in the second direction DR2, the width GSM2 of the connection member SM may be smaller than the second vertical spacing distance GV2 or the fourth vertical spacing distance GV4.

[0294] like Fig. 22 As shown in , the minimum distance between pixels of adjacent display devices may be substantially equal to the minimum distance between each of the pixels to prevent the connection member SM from being recognized between images displayed by the plurality of display devices 11 , 12 , 13 , and 14 .

[0295] Fig.23 It is shown along Fig. 22 A cross-sectional view of an example of a spliced ​​display device taken along line N-N'.

[0296] refer to Fig.23 The first display device 11 includes a first display module DPM1 and a first front cover COV1. The second display device 12 includes a second display module DPM2 and a second front cover COV2.

[0297] Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a thin film transistor layer TFTL, and a light emitting element EL.

[0298] The display panel 100 may include a thin film transistor layer TFTL and a light emitting element EL disposed on a substrate SUB. The thin film transistor layer TFTL may be a layer in which a thin film transistor is formed. The thin film transistor may include Figure 5 The first transistor T1 to the nineteenth transistor T19 are shown in FIG.

[0299] The thin film transistor layer TFTL includes an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, a second source metal layer, a third source metal layer, a fourth source metal layer and a transparent metal layer TCO. The thin film transistor layer TFTL also includes a buffer film BF, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a first planarizing film 160, a first inorganic insulating film 161, a second planarizing film 180, a second inorganic insulating film 181, a third planarizing film 190, a third inorganic insulating film 191 and a protective film PVX.

[0300] Because the above reference Figure 7 The thin film transistor layer TFTL is described, so a redundant description will be omitted.

[0301] The first source metal layer may further include a first anode connection electrode ANDE1 that may be connected to the seventeenth drain electrode D17 of the seventeenth transistor T17 through a first anode contact hole ACT1 that passes through the gate insulating film 130 , the first interlayer insulating film 141 , and the second interlayer insulating film 142 .

[0302] The second source metal layer may further include a second anode connection electrode ANDE2 The second anode connection electrode ANDE2 may be connected to the first anode connection electrode ANDE1 through a second anode contact hole ACT2 penetrating the first planarization film 160 and the first inorganic insulating film 161 .

[0303] The third source metal layer may further include a third anode connection electrode ANDE3 The third anode connection electrode ANDE3 may be connected to the second anode connection electrode ANDE2 through a third anode contact hole ACT3 passing through the second planarization film 180 and the second inorganic insulating film 181 .

[0304] The anode pad electrode APD may be connected to the third anode connection electrode ANDE3 through a fourth anode contact hole ACT4 passing through the third planarization film 190 and the third inorganic insulating film 191. The cathode pad electrode CPD may be electrically connected to a third power line VSL.

[0305] A distance GSUB between the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 may be greater than a distance GCOV between the first front cover COV1 and the second front cover COV2.

[0306] Each of the first front cover COV1 and the second front cover COV2 may include an adhesive member 51 , a transmittance control layer 52 disposed on the adhesive member 51 , and an anti-glare layer 53 disposed on the transmittance control layer 52 .

[0307] The adhesive member 51 of the first front cover COV1 is used to attach the light emitting element EL of the first display module DPM1 and the first front cover COV1. The adhesive member 51 of the second front cover COV2 is used to attach the light emitting element of the second display module DPM2 and the second front cover COV2. The adhesive member 51 may be a transparent adhesive member capable of transmitting light. For example, the adhesive member 51 may be an optically transparent adhesive film or an optically transparent resin.

[0308] The anti-glare layer 53 may be designed to diffusely reflect external light to prevent degradation of visibility of an image by reflecting the external light as it is. Therefore, due to the anti-glare layer 53, the contrast of images displayed by the first display device 11 and the second display device 12 may be increased.

[0309] The transmittance control layer 52 may be designed to reduce the transmittance of external light or light reflected from the first and second display modules DPM1 and DPM2. Therefore, the gap GSUB between the substrate SUB of the first and second display modules DPM1 and DPM2 may be prevented from being recognized from the outside.

[0310] The anti-glare layer 53 may be implemented as a polarizing plate, and the transmittance control layer 52 may be implemented as a phase retardation layer, but the present disclosure is not limited thereto.

[0311] Because along Fig. 22 Example and combination of splicing display device TDIS cut by line O-O', line P-P' and line Q-Q' Fig.23 The described examples of the spliced ​​display device TDIS cut along the line N-N' are substantially the same, so the description thereof is omitted.

[0312] However, it should be understood that the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the claims and their equivalents included therein.

Claims

1. A display device, characterized in that The display device comprises: substrate; a plurality of transistors on a surface of the substrate; a plurality of light emitting elements on the plurality of transistors; a plurality of bottom wirings on a rear surface of the substrate; and a first selective reflection film between the substrate and the plurality of bottom wirings, wherein the first selective reflection film comprises M pairs of first and second layers, wherein M is an integer greater than or equal to 2, and Wherein, the refractive index of the first layer is higher than the refractive index of the second layer.

2. The display device according to claim 1, characterized in that A difference between the refractive index of the first layer and the refractive index of the second layer is 0.55 or more.

3. The display device according to claim 1, characterized in that The first layer includes TiO2, and the second layer includes SiO2 or HfO2.

4. The display device according to claim 1, characterized in that The first layer comprises Si3N4 and the second layer comprises SiO2.

5. The display device according to claim 1, characterized in that The thickness of the first layer is smaller than the thickness of the second layer.

6. The display device according to claim 1, characterized in that The display device further includes a second selective reflection film between the substrate and the plurality of transistors, wherein the second selective reflection film comprises N pairs of third layers and fourth layers, wherein N is an integer greater than or equal to 2, and wherein the refractive index of the third layer is higher than the refractive index of the fourth layer, and The third layer is arranged closer to the substrate than the fourth layer.

7. The display device according to claim 6, characterized in that Each of a target reflection wavelength of the first selective reflection film and a target reflection wavelength of the second selective reflection film is 310 nm or less.

8. The display device according to claim 6, characterized in that The target reflection wavelength of the first selective reflection film is the same as the target reflection wavelength of the second selective reflection film, or the target reflection wavelength of the second selective reflection film is smaller than the target reflection wavelength of the first selective reflection film.

9. The display device according to claim 6, characterized in that The thickness of the second selective reflection film is smaller than the thickness of the first selective reflection film.

10. The display device according to claim 1, characterized in that The display device further includes a second selective reflection film between the substrate and the plurality of transistors, wherein the second selective reflection film comprises N pairs of third layers and fourth layers, wherein N is an integer greater than or equal to 2, and wherein the refractive index of the third layer is higher than the refractive index of the fourth layer, and The fourth layer is arranged closer to the substrate than the third layer.

Images