B code generation circuit with millisecond time service
By designing a B code generation circuit with millisecond timing, using the coordinated work of a single pulse generation unit, a frequency division unit, a pulse synchronization gate unit and a synchronization unit, the problem of complex B code generation process and difficulty in realizing high-precision time-on-time edge encoding in the prior art is solved, and the B code signal output at the high-precision time-on-time edge is achieved, and the application scope of B code timing is broadened.
Patent Information
- Application Number
- CN202421837477.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-05-09
- Estimated Expiration
- 2034-07-31
AI Technical Summary
In the prior art, most of the B code generation technologies are combined with CPU control and FPGA encoding. The implementation process is relatively complex, and it is difficult to generate high-precision time-on-time edge encoding. It is easy to have uncertain spike pulse interference, affecting the output quality of B code.
A B code generation circuit with millisecond timing is designed, including a single pulse generation unit, a frequency division unit, a pulse synchronization gate unit and a synchronization unit. Through the coordinated work of these units, a B code signal with millisecond punctual edge is generated.
The B-code timing information not only contains the whole second time signal, but also contains an accurate millisecond signal, which greatly broadens the application range of B-code timing, and has a simple circuit and takes up less resources, so that the B-code signal at the high-speed time edge can be obtained.
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Figure CN222850860U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of time synchronization and timing equipment, in particular to a B code generating circuit with millisecond timing. Background Art
[0002] B code is a time synchronization code that is widely used in time synchronization. In this code communication, not only the time code information is transmitted, but also the high-precision time information of the whole second is transmitted through the rising edge of the frame header pulse. Therefore, in time synchronization, B code is indispensable as a means of transmitting high-precision time synchronization.
[0003] In the prior art, for example, the technical solution described in the patent with publication number: CN210401666U: a B code generating unit and device, including a signal receiving circuit, used to receive a time signal and a position signal, and transmit the received time signal and position signal to a signal processing circuit; a signal processing circuit, used to process the time signal and position signal to generate a B code digital signal carrying position information.
[0004] In the prior art, most B-code generation technologies combine CPU control with FPGA coding to generate B-code encoding time information and frame header PPS on-time edge output. The implementation process is relatively complex. If high-precision on-time edge coding is required, the timing relationship of the combinational logic needs to be strictly controlled. Once the arrangement order is not reasonable or the number of data chain bits of the frequency division count is too long, uncertain spike pulse interference will easily occur, affecting the quality of B-code output. Summary of the invention
[0005] The purpose of the utility model is to provide a B code generating circuit with millisecond timing, so as to solve the problem that in the prior art proposed in the background technology, most of the B code generating technologies are a combination of CPU control and FPGA coding, and the implementation process is relatively complicated. If high-precision time punctual coding is required, the timing relationship of the combinational logic needs to be strictly controlled, which is not convenient to implement.
[0006] In order to solve the above technical problems, the technical solution adopted by the utility model is:
[0007] A B code generating circuit with millisecond timing includes a single pulse generating unit, a frequency dividing unit, a pulse synchronization gating unit and a synchronization unit: one end of the single pulse generating unit is respectively connected to the frequency dividing unit, the pulse synchronization gating unit and the synchronization unit, and the other end of the single pulse generating unit is used to receive a start enable signal and a time reference signal;
[0008] One end of the frequency division unit is also connected to the pulse synchronization gating unit, and the other end of the frequency division unit is connected to the synchronization unit; the pulse synchronization gating unit is also used to receive a start enable signal and an external input PPS signal;
[0009] One end of the synchronization unit also receives a time code signal, and the other end of the synchronization unit outputs a B code signal with a millisecond punctual edge.
[0010] According to the above technical solution, the single pulse generating unit includes a resistor R1, a capacitor C1, and a chip U2A; wherein pin No. 1 of the chip U2A is respectively connected to the pulse synchronization selection unit and pin No. 2 of the chip U2A; pin No. 3 of the chip U2A is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to one end of the capacitor C1 and the pulse synchronization selection unit; the other end of the capacitor C1 is grounded.
[0011] According to the above technical solution, the single pulse generating unit also includes chip U2B; pin 5 of chip U2B is connected to the pulse synchronization selection unit, and pin 6 of chip U2B is used to receive the time reference signal; pin 4 of chip U2B is connected to the frequency division unit.
[0012] According to the above technical solution, the frequency division unit includes chip U4A, chip U4B, chip U5A and chip U5B; wherein pin 7 of chip U4A is respectively connected to pin 15 of chip U4B, pin 7 of U5A, pin 15 of chip U5B, pulse synchronization gating unit and synchronization unit;
[0013] Pin 2 of chip U4A is grounded, pin 1 of chip U4A is connected to pin 4 of chip U2B; pin 4 of chip U4A is connected to pin 9 of chip U4B; pin 10 of chip U4B is grounded; pin 14 of chip U4B is connected to pin 1 of chip U5A; pin 2 of U5A is grounded; pin 2 and pin 6 of U5A are connected to pin 9 of chip U5B, pin 10 of chip U5B is grounded, and pin 14 of chip U5B is connected to the synchronization unit.
[0014] According to the above technical solution, the pulse synchronization selection unit includes chip U3A; pin 3 of chip U3A is connected to pin 1 of chip U2A, pin 5 of chip U2A is used to receive the external input PPS signal, pin 1 of chip U2A is connected to pin 5 of chip U2B; pin 1 of U2A is respectively connected to chip U4A, chip U4B, chip U5A, chip U5B and the synchronization unit.
[0015] According to the above technical scheme, the pulse synchronization selection unit also includes chip U2C; pin 8 of chip U2C is respectively connected to pin 1 of chip U2A and pin 3 of chip U3A; pins 8 and 9 of chip U2C are respectively connected to resistor R1 and capacitor C1, and pin 10 of chip U2C is respectively connected to pin 4 of chip U3A, chip U4A, chip U4B, chip U5A, chip U5B and the synchronization unit.
[0016] According to the above technical solution, pin 1 of chip U2A, pin 3 of chip U3A and pin 8 of chip U2C are all used to receive the start enable signal.
[0017] According to the above technical solution, the synchronization unit includes chip U3B, pin 11 of chip U3B is connected to pin 14 of chip U5B, pin 10 of chip U3B is respectively connected to pin 4 of chip U3A, chip U4A, chip U4B, chip U5A, chip U5B and pin 10 of chip U2C, pin 9 of chip U3B is used to receive time coding signals, and pin 13 of chip U3B is used to output B code signals with millisecond punctual edges.
[0018] Compared with the prior art, the utility model has the following beneficial effects:
[0019] The time B code information generated by the system of the utility model has a simple generation method, which not only retains the time coding content specified by the communication protocol of the original B code, but also ensures the punctual time edge of all time information coding pulses, so that the B code timing information contains not only the whole second time signal but also the accurate millisecond signal, which greatly broadens the application scope of the B code timing.
[0020] The device receiving the timing signal can use its millisecond timing edge signal to tame the low-precision crystal oscillator to obtain a high-precision frequency source output.
[0021] The B code generation circuit is simple and occupies few resources. Only a few logic chips are needed to obtain the B code signal with a high-precision time edge. The channel occupancy time of the B code transmission process is the same as the source B code timing method and does not change. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is the overall schematic diagram of the circuit of the utility model. DETAILED DESCRIPTION
[0023] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0024] Embodiment 1
[0025] like Figure 1 As shown, a B code generating circuit with millisecond timing includes a single pulse generating unit, a frequency dividing unit, a pulse synchronization gating unit and a synchronization unit: one end of the single pulse generating unit is respectively connected to the frequency dividing unit, the pulse synchronization gating unit and the synchronization unit, and the other end of the single pulse generating unit is used to receive a start enable signal and a time reference signal;
[0026] One end of the frequency division unit is also connected to the pulse synchronization gating unit, and the other end of the frequency division unit is connected to the synchronization unit; the pulse synchronization gating unit is also used to receive a start enable signal and an external input PPS signal;
[0027] One end of the synchronization unit also receives a time code signal, and the other end of the synchronization unit outputs a B code signal with a millisecond punctual edge.
[0028] The time B code information generated by the system of the utility model has a simple generation method, which not only retains the time coding content specified by the communication protocol of the original B code, but also ensures the punctual time edge of all time information coding pulses, so that the B code timing information contains not only the whole second time signal but also the accurate millisecond signal, which greatly broadens the application scope of the B code timing.
[0029] The device receiving the timing signal can use its millisecond timing edge signal to tame the low-precision crystal oscillator to obtain a high-precision frequency source output.
[0030] The B code generation circuit is simple and occupies few resources. Only a few logic chips are needed to obtain the B code signal with a high-precision time edge. The channel occupancy time of the B code transmission process is the same as the source B code timing method and does not change.
[0031] Embodiment 2
[0032] This embodiment is a further refinement of the first embodiment.
[0033] The single pulse generating unit includes a resistor R1, a capacitor C1, and a chip U2A; wherein pin No. 1 of the chip U2A is respectively connected to the pulse synchronization gating unit and pin No. 2 of the chip U2A; pin No. 3 of the chip U2A is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to one end of the capacitor C1 and the pulse synchronization gating unit; the other end of the capacitor C1 is grounded.
[0034] The single pulse generating unit also includes a chip U2B; pin No. 5 of the chip U2B is connected to the pulse synchronization selection unit, and pin No. 6 of the chip U2B is used to receive a time reference signal; and pin No. 4 of the chip U2B is connected to the frequency dividing unit.
[0035] The frequency division unit includes chip U4A, chip U4B, chip U5A and chip U5B; wherein, pin 7 of chip U4A is respectively connected to pin 15 of chip U4B, pin 7 of U5A, pin 15 of chip U5B, a pulse synchronization gating unit and a synchronization unit;
[0036] Pin 2 of chip U4A is grounded, pin 1 of chip U4A is connected to pin 4 of chip U2B; pin 4 of chip U4A is connected to pin 9 of chip U4B; pin 10 of chip U4B is grounded; pin 14 of chip U4B is connected to pin 1 of chip U5A; pin 2 of U5A is grounded; pin 2 and pin 6 of U5A are connected to pin 9 of chip U5B, pin 10 of chip U5B is grounded, and pin 14 of chip U5B is connected to the synchronization unit.
[0037] The pulse synchronization selection unit includes chip U3A; pin 3 of chip U3A is connected to pin 1 of chip U2A, pin 5 of chip U2A is used to receive the external input PPS signal, pin 1 of chip U2A is connected to pin 5 of chip U2B; pin 1 of U2A is respectively connected to chip U4A, chip U4B, chip U5A, chip U5B and the synchronization unit.
[0038] The pulse synchronization selection unit also includes chip U2C; pin 8 of chip U2C is respectively connected to pin 1 of chip U2A and pin 3 of chip U3A; pins 8 and 9 of chip U2C are respectively connected to resistor R1 and capacitor C1, and pin 10 of chip U2C is respectively connected to pin 4 of chip U3A, chip U4A, chip U4B, chip U5A, chip U5B and the synchronization unit.
[0039] Pin 1 of chip U2A, pin 3 of chip U3A, and pin 8 of chip U2C are all used to receive a start enable signal.
[0040] The synchronization unit includes chip U3B, pin 11 of chip U3B is connected to pin 14 of chip U5B, pin 10 of chip U3B is respectively connected to pin 4 of chip U3A, chip U4A, chip U4B, chip U5A, chip U5B and pin 10 of chip U2C, pin 9 of chip U3B is used to receive time coding signals, and pin 13 of chip U3B is used to output B code signals with millisecond punctual edges.
[0041] The start enable signal is a level control signal generated by the single-chip CPU. When the start enable signal is activated, the level changes from low to high, and the control single pulse circuit generates a low-level narrow pulse to reset the divider and D flip-flop circuits. The reset pulse is generated only once the start enable signal is activated. At the same time, the start enable signal level is added to the input of chip U3A, and the external PPS pulse is added to the CLK input of chip U3A. When the start enable signal level becomes high, the output Q end of the D flip-flop will change with the input D end signal only at the rising edge of the external PPS pulse, so that the rising edge of the level signal output from the output Q end of the chip U3A is synchronized with the rising edge of the external PPS pulse. This signal controls the pulse selection gate circuit U2B to select the crystal oscillator time base pulse signal output to generate a signal, which is added to the counting divider composed of U4 and U5 for frequency division. After 10,000 times of frequency division, the 10MHz time base signal is converted into a 1kHz time base signal; the signal time interval is 1MS and is strictly synchronized with the PPS signal; the time reference millisecond signal at this time is used as the CLK clock signal of the synchronizer D flip-flop B, and synchronized with the CPU's time coding information B code, and a B code encoding output consistent with the punctual edge of the reference millisecond signal is obtained at the Q end of the D flip-flop B.
[0042] In order to avoid the jitter error of the B code encoded pulse generated by the CPU causing its rising edge to lag behind the punctual edge of the PPS moment, resulting in the punctual edge error of the B code encoding PPS moment, it is required that the rising edge of the frame header pulse of the B code encoded pulse should be ahead of the jitter amount of the punctual edge of the PPS moment, and it can also be selected to be ahead of about 1MS. Obviously, due to the action of the synchronizer, the jitter of the B code encoding of the microcontroller will not affect the B code output of the punctual edge.
[0043] The input signals are the start enable signal, the external input PPS signal, the time reference signal and the time coding signal;
[0044] The output signal is a B-code signal with a millisecond punctual edge.
[0045] The input signals include the start enable signal, the external input PPS signal, the time reference signal and the time coding signal. The output signal is a B code signal with a millisecond punctual edge.
[0046] Start enable signal: It is an external random level signal that controls the reset of the entire circuit, usually generated by a single-chip microcomputer. When the signal changes from low to high, the entire circuit is reset once.
[0047] The external input PPS signal is an external input second pulse punctual signal, and the rising edge of the pulse is the punctual edge.
[0048] Time reference signal: usually generated by a tamed frequency source inside the device, and its pulse rising edge is synchronized with the PPS pulse rising edge.
[0049] Time coding signal: This signal is generated by the single-chip microcomputer according to the B code protocol with the currently received time information to generate a time coding pulse string; the timing accuracy of the rising and falling edges of the coded pulse string allows millisecond-level error jitter.
[0050] B code signal: It is a B code coded signal with a punctual edge. The rising edge and falling edge of each coded pulse are synchronized with the PPS pulse punctual edge of the whole second and the punctual edge of the millisecond respectively. The synchronization accuracy is better than 1nS.
[0051] The utility model adopts a simple synchronization circuit form, so that the B code time coding generated by the single chip microcomputer without strict time accuracy, or called rough B code coding, is encoded with its time information through a first-level synchronization circuit and a single D trigger to realize a B code coding signal with a punctual edge, and the rising edge and falling edge of each coding pulse are respectively synchronized with the PPS pulse full second punctual time edge and millisecond punctual time edge, and the synchronization accuracy can be less than 1nS.
[0052] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.
[0053] Finally, it should be noted that the above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. Although the utility model is described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions recorded in the above embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.
Claims
1. A B code generating circuit with millisecond timing, characterized in that: It includes a single pulse generating unit, a frequency dividing unit, a pulse synchronization gating unit and a synchronization unit: one end of the single pulse generating unit is connected to the frequency dividing unit, the pulse synchronization gating unit and the synchronization unit respectively, and the other end of the single pulse generating unit is used to receive a start enable signal and a time reference signal; One end of the frequency division unit is also connected to the pulse synchronization gating unit, and the other end of the frequency division unit is connected to the synchronization unit; the pulse synchronization gating unit is also used to receive a start enable signal and an external input PPS signal; One end of the synchronization unit also receives a time code signal, and the other end of the synchronization unit outputs a B code signal with a millisecond punctual edge.
2. A B code generating circuit with millisecond timing according to claim 1, characterized in that: The single pulse generating unit includes a resistor R1, a capacitor C1, and a chip U2A; wherein pin No. 1 of the chip U2A is respectively connected to the pulse synchronization gating unit and pin No. 2 of the chip U2A; pin No. 3 of the chip U2A is connected to one end of the resistor R1, and the other end of the resistor R1 is respectively connected to one end of the capacitor C1 and the pulse synchronization gating unit; the other end of the capacitor C1 is grounded.
3. A B code generating circuit with millisecond timing according to claim 1, characterized in that: The single pulse generating unit also includes a chip U2B; pin No. 5 of the chip U2B is connected to the pulse synchronization selection unit, and pin No. 6 of the chip U2B is used to receive a time reference signal; and pin No. 4 of the chip U2B is connected to the frequency dividing unit.
4. A B code generating circuit with millisecond timing according to claim 3, characterized in that: The frequency division unit includes chip U4A, chip U4B, chip U5A and chip U5B; wherein, pin 7 of chip U4A is respectively connected to pin 15 of chip U4B, pin 7 of U5A, pin 15 of chip U5B, a pulse synchronization gating unit and a synchronization unit; Pin 2 of chip U4A is grounded, pin 1 of chip U4A is connected to pin 4 of chip U2B; pin 4 of chip U4A is connected to pin 9 of chip U4B; pin 10 of chip U4B is grounded; pin 14 of chip U4B is connected to pin 1 of chip U5A; pin 2 of U5A is grounded; pin 2 and pin 6 of U5A are connected to pin 9 of chip U5B, pin 10 of chip U5B is grounded, and pin 14 of chip U5B is connected to the synchronization unit.
5. A B code generating circuit with millisecond timing according to claim 4, characterized in that: The pulse synchronization selection unit includes chip U3A; pin 3 of chip U3A is connected to pin 1 of chip U2A, pin 5 of chip U2A is used to receive the external input PPS signal, pin 1 of chip U2A is connected to pin 5 of chip U2B; pin 1 of U2A is respectively connected to chip U4A, chip U4B, chip U5A, chip U5B and the synchronization unit.
6. A B code generating circuit with millisecond timing according to claim 5, characterized in that: The pulse synchronization selection unit also includes a chip; pin 8 of chip U2C is respectively connected to pin 1 of chip U2A and pin 3 of chip U3A; pins 8 and 9 of chip U2C are respectively connected to resistor R1 and capacitor C1, and pin 10 of chip U2C is respectively connected to pin 4 of chip U3A, chip U4A, chip U4B, chip U5A, chip U5B and the synchronization unit.
7. A B code generating circuit with millisecond timing according to claim 6, characterized in that: Pin 1 of chip U2A, pin 3 of chip U3A, and pin 8 of chip U2C are all used to receive a start enable signal.
8. A B code generating circuit with millisecond timing according to claim 7, characterized in that: The synchronization unit includes chip U3B, pin 11 of chip U3B is connected to pin 14 of chip U5B, pin 10 of chip U3B is respectively connected to pin 4 of chip U3A, chip U4A, chip U4B, chip U5A, chip U5B and pin 10 of chip U2C, pin 9 of chip U3B is used to receive time coding signals, and pin 13 of chip U3B is used to output B code signals with millisecond punctual edges.
Citation Information
Patent Citations
B code generation unit and device
CN210401666U