Printer consumable chip with reduced GND terminals

Abstract

According to the printer consumable chip with the reduced GND terminals, the function of the GND terminals is simulated through the analog circuit, it is ensured that one terminal can be reduced on the front face of the substrate, the number of through holes needing to be punched from an integrated chip ASIC on the back face of the substrate to the terminals on the front face of the substrate is reduced, and then the machining procedures are reduced; based on the technical scheme in the invention, the overall production cost can be reduced on the basis of keeping the function of the consumable chip.

Description

Technical Field

[0001] The utility model relates to the technical field of consumable chips, in particular to a printer consumable chip with reduced GND terminals. Background Art

[0002] Printer consumables usually refer to consumable products for printers such as toner cartridges and ink cartridges. In smart printers, consumables usually have chips for functions such as identification of consumables, printing technology, and reading of remaining consumables. Consumable chips include: substrates and integrated chips ASIC. The technical solution shown in the patent with publication number CN219405854U discloses a printer consumable chip that our company is using. Figure 1 As shown, a plurality of metal contact terminals (pads) are provided on the front side of the substrate of the consumable chip of the prior art, including: a select terminal (CS, sometimes also called a reset terminal), a clock terminal (SCLK), a data terminal (DATA), a power terminal (VDD) and a ground terminal (GND).

[0003] ASIC is set on the back of the substrate, and ASIC includes: memory, digital circuit and analog circuit; depending on the specific packaging method, the connection method of the analog circuit and the metal terminal on the front of the substrate is slightly different. In COB (Chips on Board) packaging, multiple solder joints of the analog circuit are electrically connected to the conductor on the back of the substrate through bonding wires, and the conductor is electrically connected to the contact terminal on the front of the substrate through the substrate via hole to form a consumable chip; in SMD (Surface Mounted Devices) packaging, multiple solder joints of the analog circuit are electrically connected to the pins / leads of the package body through bonding wires, and the pins / leads of the package body are electrically connected to the conductor on the back of the substrate through SMT (Surface Mounted Technology) technology, and the conductor is electrically connected to the contact terminal on the front of the substrate through the substrate via hole to form a consumable chip. When the consumable chip is installed on the consumable container, the printer contact is connected through the terminal on the front of the substrate to establish communication with the printer. With the current process, it is difficult to reduce the cost of consumable chips with existing structures in large-scale production. Therefore, how to further reduce the cost while maintaining the function of the consumables is a problem that needs to be faced. Utility Model Content

[0004] In order to further reduce the processing cost of consumable chips, the utility model provides a printer consumable chip with reduced GND terminals, which can reduce the overall production cost while maintaining the functions of the consumable chip.

[0005] The technical solution of the utility model is as follows: a printer consumable chip with reduced GND terminals, comprising: a substrate and an integrated chip ASIC, wherein the terminals are arranged on the front side of the substrate, and the integrated chip ASIC is arranged on the back side of the substrate; the integrated chip ASIC comprises: an analog circuit, wherein the pressure welding points in the analog circuit are respectively electrically connected to the corresponding terminals on the front side of the substrate;

[0006] The terminals include: a clock terminal, a data terminal, a strobe terminal and a power terminal;

[0007] It is characterized in that the analog circuit includes: an analog circuit of the ground terminal.

[0008] It is further characterized by:

[0009] The analog circuit of the ground terminal includes: diodes D1-D4, N-channel MOS transistors MN5, MN6 and MN7, and capacitor C8;

[0010] The cathode of the diode D1 is connected to the welding point of the selection terminal and the g-pole of the MOS transistor MN5, the anode of the diode D1 is connected to the anode of the diode D2, the anode of the diode D3, the d-pole of the MOS transistor MN5, the d-pole of the MOS transistor MN6, the d-pole of the MOS transistor MN7 and the cathode of the diode D4, the cathode of the diode D2 is connected to the welding point of the clock terminal and the g-pole of the MOS transistor MN6, the cathode of the diode D3 is connected to the welding point of the data terminal and the g-pole of the MOS transistor MN7, the S-pole of the MOS transistors MN5, MN6 and MN7, the anode of the diode D4 and one end of the capacitor C8 are connected to each other as a virtual ground xGND; the other end of the capacitor C8 is connected to the power supply VCC;

[0011] The integrated chip ASIC also includes: a digital circuit and a memory, wherein the digital circuit is connected to the analog circuit and the memory respectively.

[0012] The present application provides a printer consumable chip with a reduced GND terminal, which simulates the function of the ground terminal GND through an analog circuit, ensuring that one terminal can be reduced on the front side of the substrate, and also reducing the number of vias required to be drilled from the integrated chip ASIC on the back side of the substrate to the terminal on the front side, thereby reducing the processing steps; based on the technical solution in the present application, the overall production cost can be reduced while maintaining the function of the consumable chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the chip structure in the prior art;

[0014] Figure 2This is a schematic diagram of the chip structure without the GND contact point in this application;

[0015] Figure 3 Generates a circuit diagram for virtual xGND; DETAILED DESCRIPTION

[0016] like Figure 2 As shown, the present application includes a printer consumable chip with reduced GND terminals, which includes: a substrate and an integrated chip ASIC, a terminal pad is set on the front of the substrate, and an integrated chip ASIC is set on the back of the substrate. The integrated chip ASIC includes: an analog circuit, a digital circuit and a memory, the digital circuit is respectively connected to the analog circuit and the memory; the terminal solder joints in the analog circuit are electrically connected to the corresponding contact terminals on the front of the substrate based on different packaging methods.

[0017] The terminals arranged on the front side of the substrate include: a clock terminal SCLK, a data terminal DATA, a power supply terminal VDD, and a strobe terminal CS. That is, the number of contact terminals on the substrate in the technical solution of the present application is changed from 5 terminals in the prior art to 4 terminals, which can also reduce the bonding of one solder joint, and also reduce the number of vias required to be drilled from the integrated chip ASIC on the back side of the substrate to the terminals on the front side, thereby reducing the processing steps and reducing the overall cost.

[0018] When the ground terminal is removed from the front side of the substrate, in order to realize the function of the ground terminal GND, the present application sets an analog circuit of the ground terminal GND in the analog circuit.

[0019] When the chip is working, there needs to be a voltage difference between the power supply and the ground. The specific value of the voltage difference provided by the chip is determined by the working mechanism of the low-dropout linear regulator LDO integrated inside the chip. For example, if the voltage provided by the LDO is 1.5V, the voltage difference provided by the external device should theoretically be greater than or equal to 1.5V before the internal integrated LDO can start working, that is, VCC-GND>= 1.5V voltage. Therefore, if you want to reduce the GND terminal on the substrate while VCC remains unchanged, then how to simulate a virtual ground "xGND" is the key technology to reduce the GND solution.

[0020] Generally speaking, during the operation of the chip, the VCC in the analog circuit is always kept at a normal working voltage and remains stable. CS will remain in a high level state only when there is communication, and SCLK and DATA will flip periodically. The technical solution of "virtual ground xGND" in this application is based on the working characteristics of these terminals, and xGND is extracted through the analog circuit by using the low level gap.

[0021] like Figure 3As shown, the analog circuit of the ground terminal in the present application includes: diodes D1~D4, N-channel MOS transistors MN5, MN6 and MN7, and capacitor C8; the cathode of diode D1 is connected to the welding point of the selection terminal and the g-pole of MOS transistor MN5, the anode of diode D1 is connected to the anode of diode D2, the anode of diode D3, the d-pole of MOS transistor MN5, the d-pole of MOS transistor MN6, the d-pole of MOS transistor MN7 and the cathode of diode D4, the cathode of diode D2 is connected to the welding point of the clock terminal and the g-pole of MOS transistor MN6, the cathode of diode D3 is connected to the welding point of the data terminal and the g-pole of MOS transistor MN7, the S-pole of MOS transistors MN5, MN6 and MN7, the anode of diode D4 and one end of capacitor C8 are connected to each other as a virtual ground xGND; the other end of capacitor C8 is connected to the power supply VCC.

[0022] In the analog circuit of the ground terminal, there are three branches, each including a diode and a MOS transistor, and each branch is respectively connected to the pad of the clock terminal SCLK, the pad of the data terminal DATA and the pad of the select terminal CS in the ASIC; the diode and MOS transistor in the branch are used to reverse cutoff current.

[0023] Based on the above analog circuit, after the chip starts working, VCC is at a high level, and CS is at a low level when not working. At this time, based on the analog circuit of the ground terminal, xGND is connected to the CS terminal solder joint based on diodes D1 and D4, and CS is used as xGND at a low level to maintain the operating voltage difference of the chip.

[0024] When CS starts to work and a high level appears at the CS terminal solder joint, MOS transistor MN5 is turned on, MOS transistors MN6 and MN7 are turned off, and the high level from CS is cut off in diodes D1~D4 and MOS transistor MN5. If a low level exists at any terminal solder joint of the other two terminals at this time, the low level of this terminal solder joint is used as the virtual ground xGND. For example, when a high level appears at the CS terminal solder joint, the SCLK terminal solder joint is at a low level, MOS transistor MN5 is turned on, and MOS transistors MN6 and MN7 are turned off. Then the xGND in the circuit is connected to the SCLK terminal solder joint based on the short circuit of diodes D4 and D2. At this time, xGND is simulated based on the low level of the SCLK terminal solder joint.

[0025] In actual work, there are also situations where the three terminal soldering points are high at the same time in milliseconds for a short time. When the three terminal soldering points of SCLK, CS and DATA output high level at the same time, MOS transistors MN5, MN6 and MN7 are turned on at the same time, and with diodes D1~D4, the currents of the three terminal soldering points are instantly cut off at the same time. At this time, xGND will appear in a short virtual connection state, because in the previous work, the capacitor C8 stores the electric quantity, and the discharge of the capacitor is very slow, so at this time, the capacitor C8 can be used to keep xGND as the reference ground. Because the time when the three terminal soldering points of SCLK, CS and DATA output high level at the same time in actual work is very short, once any terminal soldering point has a low level, xGND can be turned on to the low level terminal soldering point again to keep the virtual ground. That is, in this application, the analog circuit of the ground terminal is used to simulate the level signal to replace the function of the original GND terminal on the substrate.

[0026] In specific practical applications, the terminals on the substrate also include: test terminals, and whether to set the test terminals is selected according to actual needs. The specific setting method is implemented based on the existing technology.

Claims

1. A printer consumable chip with reduced GND terminals, comprising: A substrate and an integrated chip ASIC, wherein terminals are arranged on the front side of the substrate and the integrated chip ASIC is arranged on the back side of the substrate; The integrated chip ASIC comprises: an analog circuit, wherein the pads in the analog circuit are electrically connected to corresponding terminals on the front side of the substrate; The terminals include: a clock terminal, a data terminal, a strobe terminal and a power terminal; The feature of the invention is that the analog circuit comprises: an analog circuit of a ground terminal.

2. According to claim 1, a printer consumable chip with reduced GND terminals, characterized in that: The analog circuit of the ground terminal includes: diodes D1-D4, N-channel MOS transistors MN5, MN6 and MN7, and capacitor C8; The cathode of the diode D1 is connected to the soldering point of the selection terminal and the g-pole of the MOS transistor MN5, the anode of the diode D1 is connected to the anode of the diode D2, the anode of the diode D3, the d-pole of the MOS transistor MN5, the d-pole of the MOS transistor MN6, the d-pole of the MOS transistor MN7 and the cathode of the diode D4, the cathode of the diode D2 is connected to the soldering point of the clock terminal and the g-pole of the MOS transistor MN6, the cathode of the diode D3 is connected to the soldering point of the data terminal and the g-pole of the MOS transistor MN7, the S-pole of the MOS transistors MN5, MN6 and MN7, the anode of the diode D4 and one end of the capacitor C8 are connected to each other as a virtual ground xGND; the other end of the capacitor C8 is connected to the power supply VCC.

3. According to claim 1, a printer consumable chip with reduced GND terminals, characterized in that: The integrated chip ASIC also includes: a digital circuit and a memory, wherein the digital circuit is connected to the analog circuit and the memory respectively.

Images