Control circuit and integrated circuit

Abstract

The utility model relates to a control circuit and an integrated circuit. The control circuit includes a first flip-flop, a data terminal configured to receive a first scan enable signal, a clock terminal configured to receive a first clock signal, and an output terminal configured to provide a first latched scan enable signal. The control circuit comprises a first OR gate, a first input end of which is configured to receive a first scanning enable signal and a second input end of which is configured to receive a fourth test control signal; and a second OR gate having a first input coupled to an output of the first OR gate and a second input configured to receive an output signal from the second multiplexer according to the third test control signal. The control circuit further includes a first clock gating circuit including a first latch coupled to the first AND gate, a data terminal coupled to an output of the second OR gate, a gated negative set terminal configured to receive a first clock signal, the first clock gating circuit configured to provide a second clock signal.

Description

Technical Field

[0001] The present disclosure relates generally to design for test (DFT), and in particular embodiments to at-speed scan coverage. Background Art

[0002] As semiconductor manufacturing processes continue to advance, the size of silicon chips increases and the number of logic levels in silicon-on-chip (SoC) rises. Over time, these processes allow transistors and other components to be manufactured in smaller dimensions, making it possible to integrate more functionality into a single chip. As the size of the chip increases, more transistors can be packed onto the chip, resulting in higher complexity and functionality. This growth in complexity coupled with the increase in the number of logic levels poses a challenge to power consumption. With more transistors switching states and performing operations, the power requirements of the chip can become critical. This increase in power consumption raises several issues, such as heat dissipation, battery life in portable devices, and overall power efficiency.

[0003] During the chip design and implementation phase, various techniques are used to address power consumption. These techniques include power gating, voltage scaling, clock gating, and low-power design methodologies. Power gating involves selectively shutting down or reducing the power to inactive or idle portions of a chip. Voltage scaling reduces the operating voltage of a chip to reduce power consumption, while clock gating involves dynamically disabling the clocks to inactive circuit blocks. Low-power design methodologies optimize the overall chip architecture and circuit design to reduce power consumption.

[0004] Automatic test pattern generation (ATPG) tools generate test patterns that can detect faults or defects in the design. These patterns are typically generated based on a logical representation of the design without considering physical layout information. ATPG tools are designed to achieve high fault coverage and ensure that the test patterns can effectively exercise the logic of the design. In contrast, the physical design team provides a timing exception file, Synopsys Design Constraints (SDC). The SDC contains information about the timing constraints and exceptions that are specific to the physical implementation of the design. This file helps guide the implementation tools to meet the required timing specifications during the place and route phase.

[0005] Typically, ATPG tools do not directly understand SDC files or their timing exceptions. However, during the test and verification process, test patterns generated by ATPG are often applied at a lower level of abstraction where the physical design and timing constraints are considered. These patterns are then simulated or tested against the timing model of the design in conjunction with the SDC file information. Timing simulations take into account the SDC file to ensure that the generated test patterns avoid violating the specified timing constraints. In this way, ATPG tools indirectly take into account timing exceptions by leveraging the timing models and rules used during the simulation or test phase. This can help prevent the generation of test patterns that fail timing simulations due to violations of specified constraints.

[0006] At-speed capture refers to capturing or sampling signals within a chip or circuit while operating at the maximum clock frequency or speed. It is an essential technique for testing and verifying the functionality and performance of high-speed designs. During at-speed capture, the inputs of the design are driven by test patterns, while the outputs are observed or captured using specialized circuitry. This allows for the detection of potential timing violations, functional errors, or failures that may occur at the operating frequency of the design.

[0007] As mentioned earlier, handling timing exceptions involves dealing with specific timing constraints and exceptions that arise during the physical design and implementation phase of the chip, such as those specified in the SDC file. Timing exceptions play a vital role when it comes to at-speed capture. Some timing paths in a design may not have to meet strict timing requirements for various reasons, such as physical limitations or trade-offs in the design. These exceptions are usually defined in the SDC file to relax the timing constraints for specific paths. The test patterns generated by the ATPG tool are usually designed to accommodate these exceptions and avoid creating patterns that violate the specified timing constraints for the exempted paths.

[0008] The ATPG tool considers the timing exceptions specified in the SDC file during at-speed capture test generation when generating test patterns to ensure that the generated patterns avoid violating the timing constraints of the exempted paths, which requires the ATPG tool to consider the exceptions and create test patterns that meet the relaxed timing requirements. During at-speed capture test verification, once the test patterns are generated, they are simulated or applied to the design for verification. Additionally, the timing exceptions specified in the SDC file are used to simulate the exempted paths with relaxed timing constraints.

[0009] Therefore, it is desirable to reduce power consumption and the handling of timing exceptions during full-speed capture. Utility Model Content

[0010] Technical advantages are generally achieved by embodiments of the present disclosure, which describe power reduction in full-speed capture.

[0011] A first aspect relates to a control circuit, comprising a first flip-flop, a first NOT gate, a first multiplexer, a second multiplexer, a first OR gate, a second OR gate, and a first clock gating circuit. A data terminal of the first flip-flop is configured to receive a first scan enable signal, a clock terminal of the first flip-flop is configured to receive a first clock signal, and an output terminal of the first flip-flop is configured to provide a first latched scan enable signal. The first NOT gate is configured to receive the first latched scan enable signal and provide an inverted first latched scan enable signal. A first input terminal of the first multiplexer is configured to receive a first test control signal, a second input terminal of the first multiplexer is configured to receive a second test control signal, a third input terminal of the first multiplexer is configured to receive the first latched scan enable signal, a fourth input terminal of the first multiplexer is configured to receive an inverted first latched scan enable signal, a first selection terminal of the first multiplexer is configured to receive a first selection signal, and a second selection terminal of the first multiplexer is configured to receive a second selection signal. The first input of the second multiplexer is configured to receive the functional logic signal, the second input of the second multiplexer is configured to receive the output signal from the first multiplexer according to the first selection signal and the second selection signal, and the selection terminal of the second multiplexer is configured to receive the third test control signal. The first input of the first OR gate is configured to receive the first scan enable signal, and the second input of the first OR gate is configured to receive the fourth test control signal. The first input of the second OR gate is coupled to the output of the first OR gate, and the second input of the second OR gate is configured to receive the output signal from the second multiplexer according to the third test control signal. The first clock gating circuit has a first latch coupled to the first AND gate, the data terminal of the first latch is coupled to the output of the second OR gate, and the gated negative set terminal of the first latch is configured to receive the first clock signal. The first clock gating circuit is configured to provide a second clock signal.

[0012] In one example, the first clock gating circuit is configured to provide a second clock signal to a first scan flip-flop in a scan chain.

[0013] In one example, the first test control signal, the second test control signal, the third test control signal, and the fourth test control signal are generated by a test control unit coupled to an integrated circuit including the control circuit.

[0014] In one example, the control circuit further includes: a second flip-flop, wherein a data terminal of the second flip-flop is configured to receive a first scan enable signal, a clock terminal of the second flip-flop is configured to receive a first clock signal, and an output terminal of the second flip-flop is configured to provide a second latched scan enable signal; a second NOT gate, configured to receive the second latched scan enable signal from the second flip-flop and provide an inverted second latched scan enable signal; a third multiplexer, wherein a first input terminal of the third multiplexer is configured to receive a first test control signal, a second input terminal of the third multiplexer is configured to receive a second test control signal, and a The third input terminal of the three multiplexers is configured to receive the second latched scan enable signal, the fourth input terminal of the third multiplexer is configured to receive the inverted second latched scan enable signal, the first selection terminal of the third multiplexer is configured to receive the first selection signal, and the second selection terminal of the third multiplexer is configured to receive the second selection signal, the third multiplexer is configured such that the inverted second latched scan enable signal is provided at the output terminal of the third multiplexer in response to the first latched scan enable signal being provided at the output terminal of the first multiplexer, and the third multiplexer is configured such that the inverted second latched scan enable signal is provided at the output terminal of the third multiplexer in response to the first latched scan enable signal being provided at the output terminal of the first multiplexer. The first multiplexer provides an inverted first latched scan enable signal at an output terminal and the third multiplexer provides a second latched scan enable signal at an output terminal; a fourth multiplexer, wherein a first input terminal of the fourth multiplexer is configured to receive a second functional logic signal, a second input terminal of the fourth multiplexer is configured to receive an output signal from the third multiplexer according to the first selection signal and the second selection signal, and a selection terminal of the fourth multiplexer is configured to receive a third test control signal; a third OR gate, wherein a first input terminal of the third OR gate is configured to receive the first scan enable signal, and a second input terminal of the third OR gate is configured to receive a third test control signal. an input terminal of the fourth OR gate configured to receive a fourth test control signal; a fourth OR gate, a first input terminal of the fourth OR gate being coupled to the output terminal of the third OR gate, a second input terminal of the fourth OR gate being configured to receive an output signal from a fourth multiplexer according to the third test control signal; and a second clock gating circuit, comprising a second latch coupled to the second AND gate, a data terminal of the second latch being coupled to the output terminal of the fourth OR gate, a gated negative set terminal of the second latch being configured to receive the first clock signal, the second clock gating circuit being configured to provide a third clock signal, and the third clock signal being delayed by one clock pulse from the second clock signal.

[0015] In one example, the second clock gating circuit is configured to provide a third clock signal to a last scan flip-flop in the scan chain.

[0016] In one example, each of the first latch, the second latch, or both are gated D latch types.

[0017] In one example, the first selection signal and the second selection signal are provided by a scan decoder.

[0018] A second aspect relates to an integrated circuit. The integrated circuit includes a control circuit and a scan chain. The control circuit is configured to receive a first clock signal and a first scan enable signal, and generate a second clock signal and a third clock signal based on the first clock signal and the first scan enable signal, the third clock signal is delayed by one clock pulse from the second clock signal, and the first clock signal, the second clock signal and the third clock signal have the same duty cycle. The scan chain includes a first scan trigger and a last scan trigger, the clock terminal of the first scan trigger is configured to receive the second clock signal, the clock terminal of the last scan trigger is configured to receive the third clock signal, the scan enable input of the first scan trigger is configured to receive the second scan enable signal, and the scan enable input of the last scan trigger is configured to receive the third scan enable signal.

[0019] In one example, the scan chain includes a plurality of scan flip-flops, a scan input terminal of a first scan flip-flop is configured to receive a test pattern, and a scan input terminal of each subsequent scan flip-flop in the scan chain is coupled to an output terminal of a previous scan flip-flop.

[0020] In one example, the first scan enable signal is a logical AND function of the second scan enable signal and the third scan enable signal.

[0021] In one example, the first scan enable signal is provided from a logic built-in self-test (LBIST) or using a scan enable pad from an automatic test pattern generation (ATPG) test tool.

[0022] In one example, the control circuit includes: a first flip-flop, a data terminal of the first flip-flop is configured to receive a first scan enable signal, a clock terminal of the first flip-flop is configured to receive a first clock signal, and an output terminal of the first flip-flop is configured to provide a first latched scan enable signal; a first NOT gate is configured to receive the first latched scan enable signal and provide an inverted first latched scan enable signal; a first multiplexer, a first input terminal of the first multiplexer is configured to receive a first test control signal, a second input terminal of the first multiplexer is configured to receive a second test control signal, a third input terminal of the first multiplexer is configured to receive the first latched scan enable signal, a fourth input terminal of the first multiplexer is configured to receive the inverted first latched scan enable signal, a first selection terminal of the first multiplexer is configured to receive a first selection signal, and a second selection terminal of the first multiplexer is configured to receive a second selection signal; a second multiplexer, a second multiplexer a first input terminal of a first multiplexer configured to receive a functional logic signal, a second input terminal of a second multiplexer configured to receive an output signal from the first multiplexer according to a first selection signal and a second selection signal, and a selection terminal of the second multiplexer configured to receive a third test control signal; a first OR gate, a first input terminal of the first OR gate configured to receive a first scan enable signal, a second input terminal of the first OR gate configured to receive a fourth test control signal; a second OR gate, a first input terminal of the second OR gate coupled to an output terminal of the first OR gate, a second input terminal of the second OR gate configured to receive an output signal from the second multiplexer according to the third test control signal; and a first clock gating circuit, including a first latch and an AND gate, a data terminal of the first latch coupled to an output terminal of the second OR gate, a gated negative set terminal of the first latch configured to receive a first clock signal, and the first clock gating circuit configured to provide a second clock signal or a third clock signal.

[0023] In one example, the logic value of the first selection signal is equal to the logic value of the second scan enable signal, and the logic value of the second selection signal is equal to the logic value of the third scan enable signal.

[0024] In one example, the logic value of the first selection signal is equal to the inverted logic value of the second scan enable signal, and the logic value of the second selection signal is equal to the inverted logic value of the third scan enable signal.

[0025] A third aspect relates to a method for testing a scan chain in an integrated circuit. The method includes: receiving a first clock signal and a first scan enable signal by a control circuit; generating a second clock signal and a third clock signal based on the first clock signal and the first scan enable signal by the control circuit, wherein the third clock signal is delayed by one clock pulse from the second clock signal, and the first clock signal, the second clock signal and the third clock signal have the same duty cycle; providing the second clock signal to a clock terminal of a first scan trigger of the scan chain, wherein the scan enable input of the first scan trigger is configured to receive the second scan enable signal; and providing the third clock signal to a clock terminal of a last scan trigger of the scan chain, wherein the scan enable input of the last scan trigger is configured to receive the third scan enable signal.

[0026] Embodiments may be implemented in hardware, software, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 It is a block diagram of the standard architecture of a gate-controlled circuit;

[0029] Figure 2 is a block diagram of an embodiment controller circuit for managing power consumption in an integrated circuit;

[0030] Figure 3 is based on the launch-on-capture (LoC) scan test implementation and Figure 2 An illustration of a timing diagram of an embodiment waveform associated with a controller circuit in;

[0031] Figure 4 and Figure 5 A block diagram illustrating an example implementation of an embodiment of the present disclosure in a dual cycle path (ie, a multi-cycle path);

[0032] Figure 6 and Figure 7 A block diagram illustrating an example implementation of an embodiment of the present disclosure in a dual cycle path (multi-cycle path); and

[0033] Figure 8 A flow chart of an embodiment method for testing a scan chain in an integrated circuit is illustrated. DETAILED DESCRIPTION

[0034] The present disclosure provides many applicable inventive concepts that can be implemented in various specific contexts. Specific embodiments are only used to illustrate specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, the features of different embodiments can be combined to form further embodiments.

[0035] The changes or modifications described in one embodiment may also be applied to other embodiments. In addition, various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0036] Although the inventive aspects are primarily described in the context of test design, it will also be appreciated that they may also be applied to other digital circuits. In particular, aspects of the present disclosure may be applied to automotive, industrial, aerospace, or any other application that may benefit from improved scan coverage.

[0037] When automatic test pattern generation (ATPG) generates a test pattern, it typically involves manipulating the inputs of a circuit to activate specific paths and observing the outputs to detect faults or verify functionality. Capturing the output involves latching or storing the output value in a memory element (such as a flip-flop or latch) for subsequent analysis or comparison. During this capture phase, power consumption is associated with the switching activity in the circuit. Power consumption depends on various factors, including the size and complexity of the circuit, the number of flip-flops or latches used for capture, the activity and switching patterns of the signals, and the underlying technology and implementation details. Excessive power consumption during the capture phase can affect the overall power budget, reliability, and the ability to perform testing effectively. High capture power can lead to problems such as overheating, potential timing violations, or voltage drop issues.

[0038] By employing various techniques to manage capture power, designers can mitigate the impact of capture power, thereby ensuring efficient testing while keeping power consumption within acceptable limits. A common approach includes hardware masking of timing exceptions, such as Figure 1 , where hardware such as multiplexers 108, 110 are added to endpoint flip-flops (e.g., endpoint scan flip-flops 104, 106) of a multi-cycle path or false path.

[0039] A multi-cycle path in an integrated circuit requires multiple clock cycles to propagate a signal from source to destination. This occurs when combinational logic elements or clock domain crossings on the path introduce delays, making the signal take multiple clock cycles to reach the destination.

[0040] In scan chain testing, multi-cycle paths can present challenges because scan chains typically operate on a single clock cycle. Since test patterns are shifted into and through the scan chains in a serial fashion, multi-cycle paths may not be fully exercised during a single test cycle, which can result in reduced observability or controllability of internal signals on these paths, potentially affecting the fault coverage achieved through scan testing.

[0041] On the other hand, a false path is a path in an integrated circuit that is determined to be functionally irrelevant or intentionally excluded from timing analysis. It is usually declared as a false path by the designer or a timing analysis tool (e.g., ATPG tool).

[0042] False paths are usually excluded from timing analysis because they are either unlikely to be activated during normal operation or their timing requirements are intentionally relaxed. These paths can include non-critical paths, paths with special-purpose constraints, or paths that are known to be inactive in certain operating modes. False paths can be important in scan chain testing because they should not be used or subject to timing constraints during the test process.

[0043] Both multi-cycle paths and false paths affect scan coverage and scan chain testing by affecting observability, controllability, and timing considerations during testing. Proper identification and treatment of these paths is critical to achieving comprehensive test coverage and accurate circuit behavior analysis.

[0044] Other common methods to mitigate the impact of capture power include clock gating, power gating, test compression, and design optimization. In clock gating, the clock signals of unused or idle flip-flops or latches (e.g., functional logic) during the capture phase are disabled to reduce unnecessary switching activity and power consumption. In power gating (e.g., applying a power budget), inactive or idle portions of the circuit are selectively disabled or reduced during the capture phase to minimize power consumption. In test compression, compression techniques are used to reduce the number of test patterns required for testing, thereby reducing overall capture power. In design optimization, low-power design techniques (such as voltage scaling) reduce power consumption during the capture phase. Conventionally, these methods result in coverage loss.

[0045] For example, in large designs with many timing exceptions, the ATPG tool cannot fully follow the timing constraints and exceptions specific to the physical implementation of the design from, for example, a Synopsys Design Constraints (SDC) file, which can cause the ATPG tool to generate incorrect test patterns. The solution to this problem, which leads to coverage loss, is to mask the endpoint flip-flops (e.g., mask the inputs of the endpoint scan flip-flops using multiplexers) or use ATPG tool commands to prevent full-speed faults from being generated from the start-point flip-flops. Adding hardware (such as multiplexers) at the endpoints further increases complexity.

[0046] Additionally, even if the ATPG tool correctly reads the timing exceptions from the SDC file, the result is coverage loss due to the inherent exceptions provided by the SDC file (e.g., multi-cycle constraints, false paths, etc.) and the exceptions taken into account by the ATPG tool in test pattern generation.

[0047] As another example, multiple test passes are often required to fully cover multi-cycle paths, such as at a lower frequency than the capture frequency speed of non-multi-cycle paths. This constraint results in full-speed coverage loss because non-multi-cycle paths with combinational logic common to multi-cycle paths are tested at a lower frequency than the capture frequency speed, and the capture frequency speed coverage of multi-cycle paths during full-speed coverage is limited. Similarly, error paths are not covered during full-speed coverage, resulting in full-speed coverage loss. Moreover, timing exceptions cannot cover full-speed logic built-in self-test (LBIST). Therefore, conventional solutions only provide coverage that gets stuck with LBIST.

[0048] For example, in a path including a first flip-flop, a second flip-flop, and a third flip-flop, the clock frequency is 1 gigahertz (GHz), and the paths from the first flip-flop to the second flip-flop and the second flip-flop to the third flip-flop are satisfied at a single cycle (i.e., 1 GHz); however, the path from the first flip-flop to the third flip-flop with common combinational logic (i.e., a multi-cycle of two) is satisfied at two cycles (i.e., 500 megahertz (MHz)). Therefore, the path with two multi-cycles will have two rounds. In the first round, the path from the first flip-flop to the second flip-flop is covered, while the paths from the second flip-flop to the third flip-flop (with common combinational logic with the first flip-flop to the third flip-flop) and from the first flip-flop to the third flip-flop are masked-due to the multi-cycle constraint. During the second scanning round, the clock pulse will be provided at 500 MHz, and the multi-cycle constraint will not be maintained for the path from the first flip-flop to the third flip-flop, which will cover the full speed. However, the path from the second flip-flop to the third flip-flop is covered at a lower frequency of 500 MHz, but disadvantageously, the necessary check for 1 GHz is not performed. Embodiments of the present disclosure advantageously provide a solution to this problem.

[0049] As another example, to achieve power reduction through clock gating in a design with millions of gates, the functional logic of all clock gates must be controlled simultaneously, which is a complex problem. Generally speaking, due to the limitation of controlling the functional logic blocks, this solution either increases the test pattern count or reduces the coverage.

[0050] Embodiments of the present disclosure provide a control circuit, an integrated circuit, and a method for testing a scan chain in an integrated circuit. In an embodiment, the method includes receiving a first clock signal and a first scan enable signal by a control circuit. The method also includes generating a second clock signal and a third clock signal by a control circuit based on the first clock signal and the first scan enable signal. Moreover, the method includes providing the second clock signal to a clock terminal of a first scan trigger of the scan chain. The scan enable input of the first scan trigger is configured to receive the second scan enable signal. In addition, the method includes providing a third clock signal to a clock terminal of a last scan trigger of the scan chain. The scan enable input of the last scan trigger is configured to receive the third scan enable signal.

[0051] In an embodiment, the third clock signal is delayed by one clock pulse than the second clock signal. In an embodiment, the first clock signal, the second clock signal and the third clock signal have the same duty cycle. These details and further details will be discussed in more detail below.

[0052] Figure 1 A block diagram of a standard architecture of a gated circuit 100 is illustrated. In the gated circuit 100, power consumption is managed using hardware masking of endpoint scan flip-flops 104, 106 during full-speed capture, controlling clock gates of functional logic blocks based on a power budget using ATPG tool commands, and reading timing exceptions provided by, for example, an SDC file (i.e., a software solution).

[0053] The gating circuit 100 is used to test a scan chain 102, which includes a plurality of scan flip-flops. Note that the number and arrangement of the scan flip-flops in the scan chain 102 are non-limiting. The scan chain 102 includes a first scan flip-flop 104 at the beginning (i.e., the first end) of the scan chain 102 and a last scan flip-flop 106 at the end (i.e., the second end) of the scan chain 102. The scan chain 102 may include additional scan flip-flops between the first scan flip-flop 104 and the last scan flip-flop 106. The output at the output terminal (Q) of each scan flip-flop in the scan chain 102 is coupled to the scan input terminal (SI) of the next scan flip-flop in the scan chain 102. Each scan flip-flop in the scan chain 102 receives a scan enable signal (scan_en) at a corresponding scan enable input terminal (SE).

[0054] As understood by a person of ordinary skill in the art, when the scan mode is disabled (i.e., the scan enable signal (SCAN_EN) is equal to "0"), the output terminal (Q) provides an output for the input at the data terminal (D), and when the scan mode is enabled (i.e., the scan enable signal (SCAN_EN) is equal to "1"), the output terminal (Q) provides an output for the input at the scan input terminal (SI).

[0055] For example, the SDC file may provide information that the scan chain 102 includes multi-cycle or false paths, which the ATPG tool may use to provide hardware masking of the endpoint scan flip-flops 104 , 106 using the multiplexers 108 , 110 during at-speed capture (eg, during LBIST).

[0056] Automatic test equipment (ATE) may be used to implement scan testing on the scan chain 102. In an embodiment, the ATE provides, for example, a test pattern vector to a scan input terminal (SI) of the first scan flip-flop 104 and evaluates the result (the data shifted out) at the output terminal (Q) of the last scan flip-flop 106 to determine a fault in the scan chain 102.

[0057] Scan testing can also be performed as a logic built-in self-test (LBIST). The integrated circuit applies a test vector to itself (e.g., using a pseudo-random number generator) and uses an integrated circuit LBIST controller to determine if a fault has occurred. The execution of a scan test or LBIST can provide a way to detect the presence of a fault.

[0058] In an embodiment, a phase locked loop (PLL) 112 and an on-chip clock (OCC) generator 114 coupled to an output of the phase locked loop 112 generate a clock signal (OCC_CLK).

[0059] The clock gating circuits 116, 118, the multiplexers 108, 110, the first two-input OR gates 120, 124, and the second two-input OR gates 122, 126 are coupled to the clock terminals (CLK) of the endpoint scan flip-flops (i.e., the first scan flip-flop 104 and the last scan flip-flop 106) of the scan chain 102. The first two-input OR gates 120, 124 have a first input terminal coupled to the scan enable signal (SE) and a second input terminal coupled to the second test control signal (TCU_BIT_1). The output terminals of the first two-input OR gates 120, 124 are coupled to the first input terminals of the second two-input OR gates 122, 126.

[0060] In an embodiment, clock gating circuit 116 includes latch 115 and dual-input AND gate 117. The output terminal (Q L ) is coupled to a first input of a dual-input AND gate 117. The gated negative set terminal (G L ) is coupled to the second input terminal of the dual-input AND gate 117. The input terminal (D L ) is coupled to the output terminal of the second two-input OR gate 122. The output terminal of the two-input AND gate 117 is coupled to the clock terminal (CLK) of the first scan flip-flop 102, which provides a clock signal (CLK_A).

[0061] In an embodiment, clock gating circuit 118 includes latch 119 and dual-input AND gate 121. The output terminal (Q L ) is coupled to a first input of a dual-input AND gate 121. The gated negative set terminal (G L ) is coupled to the second input terminal of the dual-input AND gate 121. The input terminal (D L ) is coupled to the output terminal of the second two-input OR gate 126. The output terminal of the two-input AND gate 121 providing the clock signal (CLK_B) is coupled to the clock terminal (CLK) of the last scan flip-flop 106.

[0062] In an embodiment, each of latches 115 and 119 is a gated D latch.

[0063] The multiplexer 108 includes a first input terminal coupled to the first functional logic block and a second input terminal coupled to the first test control signal (TCU_BIT_0). The multiplexer 110 includes a second input terminal coupled to the first test control signal (TCU_BIT_0) and a first input terminal coupled to the second functional logic block. In addition, the multiplexers 108, 110 include a selection terminal coupled to the third test control signal (TCU_BIT_2). The output terminals of the multiplexers 108, 110 are coupled to the second input terminals of the second two-input OR gates 122, 126.

[0064] In an embodiment, a test controller (not shown) selectively provides a logic high or low signal to each test control signal.

[0065] The multiplexers 108, 110 are configured such that in response to the third test control signal (TCU_BIT_2), for example, being asserted, the first test control signal (TCU_BIT_0) is provided at the output of the multiplexers 108, 110. The multiplexers 108, 110 are configured such that in response to the third test control signal (TCU_BIT_2), for example, being de-asserted, the functional logic block is provided at the output of the multiplexers 108, 110.

[0066] The clock gating circuits 116 and 118 are configured so that when the negative set terminal (G L ) input, the output terminal (Q L ) is forced to "0" regardless of the input terminal (D L ) is the value on the gate. The clock signal (OCC_CLK) is provided as input to the negative set terminal (G L When its input terminal (DL ) is "1", the output terminal (Q L ) at its gate negative set terminal (G L ) receives OCC_CLK, and when its input terminal (D L ) is "0" or its gate negative set terminal (G L ) is "0", the output terminal (Q L ) is forced to "0".

[0067] Therefore, by selectively setting (eg, by a test tool) the third test control signal (TCU_BIT_2) and controlling different functional logics, different clock signals may be provided to the endpoint scan flip-flops 104 and 106.

[0068] Figure 2 A block diagram of an embodiment controller circuit 200 for managing power consumption in an integrated circuit is illustrated. Portions of the controller circuit 200 are similar in structure to the gating circuit 100. In addition to the components common between the two circuits (which are not described again for simplicity of discussion), the controller circuit 200 also includes a third multiplexer 202, a fourth multiplexer 204, a first NOT gate 206, a second NOT gate 208, a third flip-flop 210, and a fourth flip-flop 212, which may (or may not) be arranged as shown. The controller circuit 200 may include additional components not shown. Advantageously, the hardware solution of the controller circuit 200 provides different clock signals (CLK_A and CLK_B) to the endpoint scan flip-flops 104, 106 compared to the software solution in the gating circuit 100.

[0069] In contrast to the gate control circuit 100, the first scan flip-flop 104 has a scan enable input (SE) coupled to a first scan enable signal (SCAN_EN_A), while the second scan flip-flop 106 has a scan enable input (SE) coupled to a second enable signal (SCAN_EN_B). Thus, the scan enable inputs of the endpoint scan flip-flops of the scan chain 102 are coupled to different scan enable signals, thereby allowing independent scan handling.

[0070] The clock terminal (CLK) of each of the third flip-flop 210 and the fourth flip-flop 212 is configured to receive the clock signal (OCC_CLK) generated by the phase-locked loop 112 and the on-chip clock generator 114. In addition, the input terminal (D) of each of the third flip-flop 210 and the fourth flip-flop 212 is configured to receive the third scan enable signal (SCAN_EN_AB).

[0071] The third multiplexer 202 and the fourth multiplexer 204 have four input terminals and two selection terminals. In an embodiment, the first input terminals of the third multiplexer 202 and the fourth multiplexer 204 are configured to receive the first test control signal (TCU_BIT_0). In an embodiment, the second input terminals of the third multiplexer 202 and the fourth multiplexer 204 are configured to receive the fourth test control signal (TCU_BIT_3). In an embodiment, the third input terminals of the third multiplexer 202 and the fourth multiplexer 204 are coupled to the output terminals (Q) of the third flip-flop 210 and the fourth flip-flop 212, respectively. In an embodiment, the third input terminals of the third multiplexer 202 and the fourth multiplexer 204 are configured to receive the latched third scan enable signal (SCAN_EN_AB_L) of the third scan enable signal (SCAN_EN_AB). In an embodiment, the first NOT gate 206 and the second NOT gate 208 provide a third scan enable signal (SCAN_EN_AB_Ln) that is an inverted latch of the third scan enable signal (SCAN_EN_AB).

[0072] In an embodiment, a test controller (not shown) selectively provides a logic high or low signal to each test control signal.

[0073] In an embodiment, the first selection terminals of the third multiplexer 202 and the fourth multiplexer 204 are coupled to a first selection signal (SEL_1). In an embodiment, the second selection terminals of the third multiplexer 202 and the fourth multiplexer 204 are coupled to a second selection signal (SEL_2).

[0074] In contrast to the gate control circuit 100 where the inputs of the multiplexers 108 , 110 are configured to receive the first test control signal ( TCU_BIT_0 ), in the controller circuit 200 , the inputs of the multiplexers 108 , 110 are coupled to the outputs of the multiplexers 202 , 204 , respectively.

[0075] Additionally, in contrast to the gate control circuit 100 in which the first dual-input OR gates 120, 124 have first input terminals coupled to the scan enable signal (SE), in the controller circuit 200, the first input terminal of each of the first dual-input OR gates 120, 124 is coupled to the third scan enable signal (SCAN_EN_AB).

[0076] The structural and functional differences in the controller circuit 200 allow independent clock control of the clock terminal (CLK) using the first clock signal (CLK_A) and the second clock signal (CLK_B), and independent scan enable handling of the scan enable terminals (SE) of the endpoint scan flip-flops 104 , 106 .

[0077] Figure 3 A timing diagram of an example waveform 300 associated with the controller circuit 200 according to a start-on-capture (LoC) scan test implementation is illustrated. The waveform 300 includes a clock signal (OCC_CLK) 302, a third scan enable signal (SCAN_EN_AB) 304, a latched third scan enable signal (SCAN_EN_AB_L) 306, a first select signal (SEL_1) 308, a second select signal (SEL_2) 310, a clock signal (CLK_A) 312, and a clock signal (CLK_B) 314.

[0078] In an embodiment, the clock signal (OCC_CLK) 302 is provided by the phase-locked loop 112 and the on-chip clock generator 114 and is gated at the negative set terminals (G L ) and is received at the clock terminals (CLK) of the flip-flops 210 and 212.

[0079] A third scan enable signal (SCAN_EN_AB) 304 is received at the input terminals (D) of the flip-flops 210 , 212 and the inputs of the OR gates 120 , 124 .

[0080] In an embodiment, in response to the first scan enable signal (SCAN_EN_A) and the second scan enable signal (SCAN_EN_B) being generated outside the integrated circuit (e.g., ATE testing), the third scan enable signal (SCAN_EN_AB) 304 is equal to the functional AND logic of the first scan enable signal (SCAN_EN_A) and the second scan enable signal (SCAN_EN_B). For example, when the first scan enable signal (SCAN_EN_A) is logic low (e.g.,

[0081] “0”) and the second scan enable signal (SCAN_EN_B) is logic high (eg, “1”), the value of the third scan enable signal (SCAN_EN_AB) is equal to “0”.

[0082] In an embodiment, in response to the first scan enable signal (SCAN_EN_A) and the second scan enable signal (SCAN_EN_B) being generated inside the integrated circuit (e.g., LBIST, ATPG), the third scan enable signal (SCAN_EN_AB) 304 is equal to the value on the LBIST_SE and PAD_SE pads of the integrated circuit. In an embodiment, the third scan enable signal (SCAN_EN_AB) 304 is equal to the value on the LBIST_SE and PAD_SE pads of the integrated circuit. Figure 1 Corresponding to the scan enable signal (SCAN_EN) in the gating circuit 100.

[0083] The latched third scan enable signal (SCAN_EN_AB_L) 306 is a latched output from the output terminal (Q) of the flip-flops 210, 212 and is received at the third input terminal of the multiplexers 202, 204. Although not shown, the inverted latched third scan enable signal (SCAN_EN_AB_Ln) is an inverted logic signal of the latched third scan enable signal (SCAN_EN_AB_L) 306, which is provided at the output of the NOT gates 206, 208 and is received at the fourth input terminal of the multiplexers 202, 204.

[0084] A first selection signal ( SEL_1 ) 308 and a second selection signal ( SEL_2 ) 310 are provided as selection control signals for the multiplexers 202 , 204 , which selectively control outputs of the multiplexers 202 , 204 according to input signals of the multiplexers 202 , 204 .

[0085] In an embodiment, the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 have logic values ​​equal to the first scan enable signal (SCAN_EN_A) and the second scan enable signal (SCAN_EN_B), respectively. In an embodiment, the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 have logic values ​​equal to the inverted logic values ​​of the first scan enable signal (SCAN_EN_A) and the second scan enable signal (SCAN_EN_B), respectively. In an embodiment, the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 have logic values ​​equal to the fourth scan enable signal (SCAN_EN_C) and the fifth scan enable signal (SCAN_EN_D), respectively. In an embodiment, the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 are provided by a scan decoder (not shown) coupled to the multiplexers 202, 204.

[0086] In an embodiment, in response to the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 having logic values ​​“0” and “0” respectively (non-limiting), the first control signal (TCU_BIT_0) at the first input of the multiplexers 202, 204 is provided at the output of the multiplexers 202, 204.

[0087] In an embodiment, in response to the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 having logic values ​​of "1" and "1" respectively (non-limiting), the fourth control signal (TCU_BIT_3) at the second input terminal of the multiplexers 202, 204 is provided at the output terminal of the multiplexers 202, 204.

[0088] In an embodiment, in response to the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 having logic values ​​"1" and "0", respectively, the latched third scan enable signal (SCAN_EN_AB_L) 306 at the third input terminal of the third multiplexer 202 is provided at the output terminal of the third multiplexer 202. In this embodiment, in response to the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 having logic values ​​"0" and "1", respectively, the latched third scan enable signal (SCAN_EN_AB_L) 306 at the third input terminal of the multiplexer 204 is provided at the output terminal of the fourth multiplexer 204. In addition, in response to the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 having logic values ​​"0" and "1", respectively, the inverted latched third scan enable signal (SCAN_EN_AB_Ln) at the fourth input terminal of the third multiplexer 202 is provided at the output terminal of the third multiplexer 202. Moreover, in response to the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 having logic values ​​"1" and "0", respectively, the inverted latched third scan enable signal (SCAN_EN_AB_Ln) at the fourth input terminal of the multiplexer 204 is provided at the output terminal of the fourth multiplexer 204.

[0089] In an embodiment where the first selection signal (SEL_1) 308 is set as the first scan enable signal (SCAN_EN_A) and the second selection signal (SEL_2) 310 is set as the second scan enable signal (SCAN_EN_B), the start pulse on the clock signal (CLK_A) 312 and the capture pulse on the clock signal (CLK_B) 314 correspond to the first selection signal (SEL_1) 308 having a logic value of “1” and the second selection signal (SEL_2) 310 having a logic value of “0”. Similarly, the start pulse on the clock signal (CLK_B) 314 and the capture pulse on the clock signal (CLK_A) 312 correspond to the first selection signal (SEL_1) 308 having a logic value of “0” and the second selection signal (SEL_2) 310 having a logic value of “1”.

[0090] In an embodiment where the first selection signal (SEL_1) 308 is different from the first scan enable signal (SCAN_EN_A) and the second selection signal (SEL_2) 310 is different from the second scan enable signal (SCAN_EN_B), the start pulse on the clock signal (CLK_A) 312 and the capture pulse on the clock signal (CLK_B) 314 (as well as the start pulse on the clock signal (CLK_B) 314 and the capture pulse on the clock signal (CLK_A) 312) correspond to the user selection values ​​of the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310, respectively.

[0091] In an embodiment, at time T3 to T4, the clock signal (CLK_A) 312 is asserted, while the clock signal (CLK_B) 314 is de-asserted. At time T4 to T5, the clock signal (CLK_A) 312 is de-asserted, while the clock signal (CLK_B) 314 is asserted. The assertion and de-assertion of the clock signals (CLK_A and CLK_B) are based on the latched third scan enable signal (SCAN_EN_AB_L) 306 controlling the clock gating circuit 116 (i.e., providing the clock signal (CLK_A) 312) and the inverted latched third scan enable signal (SCAN_EN_AB_Ln) controlling the clock gating circuit 118 (i.e., providing the clock signal (CLK_B) 314).

[0092] In the embodiment, at time T9 to T 10 At time T, the clock signal (CLK_B) is asserted and the clock signal (CLK_A) is deasserted, and at time T 10 To T 11 At , the clock signal (CLK_B) is de-asserted and the clock signal (CLK_A) is asserted. The assertion and de-assertion of the clock signals (CLK_A and CLK_B) are based on the latched third scan enable signal (SCAN_EN_AB_L) 306 that controls the clock gating circuit 118 (i.e., provides the clock signal (CLK_B) 314) and the inverted latched third scan enable signal (SCAN_EN_AB_Ln) that controls the clock gating circuit 116 (i.e., provides the clock signal (CLK_A) 312).

[0093] When the latched third scan enable signal (SCAN_EN_AB_L) 306 controls the clock gating circuit 116 and the inverted latched third scan enable signal (SCAN_EN_AB_Ln) controls the clock gating circuit 118, the first scan trigger 104 receiving the clock signal (CLK_A) will provide a start pulse, and the last scan trigger 106 receiving the clock signal (CLK_B) will provide a capture pulse for full-speed capture.

[0094] When the inverted latched third scan enable signal (SCAN_EN_AB_Ln) controls the clock gating circuit 116 and the latched third scan enable signal (SCAN_EN_AB_L) 306 controls the clock gating circuit 118, the last scan trigger 106 receiving the clock signal (CLK_B) will provide a start pulse, and the first scan trigger 104 receiving the clock signal (CLK_A) will provide a capture pulse for full-speed capture.

[0095] Therefore, full coverage can be provided without simultaneously providing the clock signal (CLK_A) 312 and the clock signal (CLK_B) 314 to the endpoint scan flip-flops 104, 106. Additionally, power management can be provided without the use of an SDC file.

[0096] In an embodiment, in response to the first select signal (SEL_1) 308 and the second select signal (SEL_2) 310 having logic values ​​of “0” and “1” respectively, a latched third scan enable signal (SCAN_EN_AB_L) 306 at the third input of the third multiplexer 202 is provided at the output of the third multiplexer 202 .

[0097] In this embodiment, in response to the first select signal (SEL_1) 308 and the second select signal (SEL_2) 310 having logic values ​​of "1" and "0", respectively, a latched third scan enable signal (SCAN_EN_AB_L) 306 at the third input terminal of the multiplexer 204 is provided at the output terminal of the fourth multiplexer 204.

[0098] Additionally, in response to the first select signal (SEL_1) 308 and the second select signal (SEL_2) 310 having logic values ​​of “1” and “0”, respectively, an inverted latched third scan enable signal (SCAN_EN_AB_Ln) at the fourth input of the third multiplexer 202 is provided at the output of the third multiplexer 202 .

[0099] Moreover, in response to the first selection signal (SEL_1) 308 and the second selection signal (SEL_2) 310 having logic values ​​"0" and "1" respectively (non-limiting), an inverted latched third scan enable signal (SCAN_EN_AB_Ln) at the fourth input terminal of the multiplexer 204 is provided at the output terminal of the fourth multiplexer 204.

[0100] It should be noted that the selection of the inputs at the outputs of the multiplexers 202, 204 is not limited to the arrangement or selection signal table provided above. In other embodiments, different configurations are contemplated.

[0101] The clock signal (CLK_A) 312 is provided by the clock gating circuit 116 at the clock terminal (CLK) of the first scan flip-flop 104 in the scan chain 102. The clock signal (CLK_B) 314 is provided by the clock gating circuit 118 at the clock terminal (CLK) of the last scan flip-flop 106 in the scan chain 102. It is noted that while the clock signal (OCC_CLK) in the controller circuit 200 provides a pair of clock signals (i.e., CLK_A and CLK_B) that are offset in time from one another, it should be appreciated that in other embodiments, additional clock signals (i.e., greater than two) that are similarly offset from one another may be similarly generated from the clock signal (OCC_CLK) during the capture phase of an implementation of a scan coverage test initiated at capture.

[0102] In the endpoint scan flip-flops 104, 106, in response to the scan enable signals (e.g., SCAN_EN_A and SCAN_EN_B) being asserted (e.g., logic level high) at the scan enable terminal (SE), data (e.g., test vector, test pattern, vector or pattern) are input at times T0 to T1, T1 to T2, T5 to T6, T6 to T7, T7 to T8, and T9. 11 To T 12 Each clock signal pulse (ie, corresponding to clock signal (CLK_A) 312 and clock signal (CLK_B) 314 ) is shifted into scan chain 102 .

[0103] In response to the scan enable signals (e.g., SCAN_EN_A and SCAN_EN_B) being de-asserted (e.g., logic level low), the first pulse of the clock signal (i.e., corresponding to the clock signal (CLK_A) 312 and the clock signal (CLK_B) 314) causes the logic circuit having the input terminal coupled to the scan chain 102 to be turned on from time T3 to T4 (for the first scan flip-flop 104) and from time T9 to T10. 10 (For the last scan flip-flop 106) Transition to a step generally referred to as startup. During the startup phase of the first scan flip-flop 104, when the clock signal (CLK_A) 312 is asserted, the clock signal (CLK_B) 314 is not asserted. Similarly, during the startup phase of the last scan flip-flop 106, when the clock signal (CLK_B) 314 is asserted, the clock signal (CLK_A) 312 is not asserted.

[0104] The second pulse of the clock signal causes the capture phase to start at time T 10 To T 11The output of the simulated logic circuit is loaded into the flip-flops of the scan chain 102 at time T4 to T5 (for the first scan flip-flop 104) and time T4 to T5 (for the last scan flip-flop 106). Full-speed capture includes two clock pulses. The first pulse corresponds to the start pulse (or start phase) and the second pulse corresponds to the capture pulse (or capture phase). During the capture phase of the first scan flip-flop 104, when the clock signal (CLK_A) 312 is asserted, the clock signal (CLK_B) 314 is not asserted. Similarly, during the capture phase of the last scan flip-flop 106, when the clock signal (CLK_B) 314 is asserted, the clock signal (CLK_A) 312 is not asserted. Then, the capture phases at T5 to T6, T6 to T7, T7 to T8, and T9 are repeated. 11 To T 12 The data removed is used for fault assessment.

[0105] Therefore, embodiments of the present disclosure provide separate clock signals (i.e., CLK_A and CLK_B) to the endpoint scan flip-flops 104, 106 of the scan chain 102, rather than using a common clock signal at the clock terminals, such as the clock signal in the gating circuit 100. In effect, the controller circuit 200 provides a hardware implementation in which the launch or capture clock is split into two full-speed pulses for the launch implementation when capturing. Therefore, this solution requires less power than a normal implementation of the full-speed ATPG test mode (i.e., without a power budgeting approach), while providing greater scan coverage.

[0106] Advantageously, the embodiments disclosed herein provide a hardware implementation that reduces power consumption, increases scan coverage, and reduces test patterns compared to a pure software implementation. In implementing the controller circuit 200, a hardware circuit system is used to handle multi-cycle paths (MCPs) that covers timing constraints and exceptions provided by a Synopsys design constraint (SDC) file while reducing the amount of operations required to provide scan coverage through an ATPG tool.

[0107] Although the controller circuit 200 can be used as a pure hardware solution to reduce power consumption and increase scan coverage, it is noted that a hybrid hardware and software solution based on an embodiment of the present disclosure can also advantageously reduce power consumption and increase scan coverage. In an embodiment, a hardware solution can have priority (i.e., precedence) over a software solution, thereby reducing errors.

[0108] Compared to software solutions that only use SDC files, which often result in the generation of incorrect test patterns, the hybrid hardware and software solution may help achieve high scan coverage while leveraging timing constraints and exceptions provided by, for example, SDC files.

[0109] The controller circuit 200 combined with software solutions (such as power gating) can help achieve reduced power consumption and increased scan coverage without relying on test mode bloat common in pure hardware solutions. For example, in an embodiment, a software solution can be used for debug mode, resulting in reduced coverage but significantly reduced power consumption (i.e., achieving minimum debug coverage with minimum power consumption).

[0110] In an embodiment, the clock signal (OCC_CLK) 302 with two pulses (ie, CLK_A and CLK_B) may be used in subsequent rounds to achieve scan coverage for the multi-cycle path.

[0111] In embodiments where the start-point and endpoint flip-flops in a multi-cycle path receive clock signals from different clock gating circuits (e.g., Figure 4 The scan trigger 420 in receives the third clock signal (CLK_C), and the scan coverage can be achieved in a single round using the clock signal (OCC_CLK) 302 having more than two pulses (ie, CLK_A, CLK_B, ..., CLK_N).

[0112] In an embodiment, additional logic is generally added before each clock gate to achieve general power consumption reduction while increasing scan coverage in an integrated circuit without requiring specific circuit design knowledge or understanding. For example, each functional IP clock gate may have a single pulse, which may be randomly selected, providing additional scan coverage if any multi-cycle or false paths occur along the test path.

[0113] In some embodiments, additional logic is selectively added in multi-cycle paths, false paths, or both using information provided, for example, in a timing exception file (e.g., a Synopsys design constraint file). For example, implementations of the disclosed embodiments can be based on specific knowledge or understanding of a design microarchitecture (e.g., a new IP, a new system on a chip), or multi-cycle or false paths of an integrated circuit used in an integrated circuit, derivative, or reuse of IP from the same family.

[0114] In an embodiment, scan coverage is increased because other valid single-cycle paths (sharing combinational logic with multi-cycle paths or false paths) are not masked and properly positioned for full-speed scan coverage. This is in contrast to conventional solutions where valid single-cycle paths (sharing combinational logic with multi-cycle paths) are checked at a lower speed (i.e., corresponding to the frequency of multi-cycle path coverage).

[0115] In an embodiment, full-speed LBIST may be achieved while reducing power consumption without introducing delays on the functional data path.

[0116] In an embodiment, multiple ATPG rounds are avoided, while in LBIST, additional valid paths (e.g., multi-cycle paths) are available for easy observation. Therefore, the number of test insertion points is reduced, and the number of test patterns is reduced to achieve similar or increased scan coverage with more inferable logic.

[0117] In an embodiment, reduced test modes are utilized to reduce capture power without the need for conventional functional logic to control clock terminals according to power budgeting methods, nor the need to control multi-cycle paths in multi-million gate designs based on information provided in, for example, timing exception files (e.g., Synopsys design constraint files).

[0118] In an embodiment, multi-cycle path scan coverage is accomplished in the same ATPG pass based on the hardware solution provided herein and information provided in, for example, a timing exception file (eg, a Synopsys design constraint file).

[0119] In an embodiment, capture power is reduced without providing a power budget to an ATPG tool, which conventionally uses a power budget to control functional logic of clock gates in a multi-million gate design.

[0120] Thus, embodiments of the present disclosure advantageously reduce the amount of operations required to generate ATPG test patterns, reduce the number of ATPG test patterns, reduce test time, and reduce capture power while increasing scan coverage at the correct full-speed frequency.

[0121] Figure 4 and Figure 5 A block diagram illustrating an example implementation of an embodiment of the present disclosure in a dual cycle path (ie, a multi-cycle path) is illustrated. Figure 4 and Figure 5 Illustrated are a write data path 400, a first-in-first-out (FIFO) path 500, and a read data path 450, which may be arranged as a single embodiment.

[0122] In the first full-speed capture, the write data path 400 is the initiating path, and the FIFO path 500 is the target path. Therefore, the scan enable terminals (SE) of the scan flip-flops 402, 404, 406, and 408 are coupled to the first scan enable signal (SCAN_EN_A), while the scan enable terminals (SE) of the scan flip-flops 502, 504, 506, and 508 are coupled to the second scan enable signal (SCAN_EN_B). In addition, the clock terminals (CLK) of the scan flip-flops 402, 404, 406, and 408 are coupled to the clock signal (CLK_A) provided by the controller circuit 200, while the clock terminals (CLK) of the scan flip-flops 502, 504, 506, and 508 are coupled to the clock signal (CLK_B). Therefore, the scan flip-flops in the write data path 400 have independent scan enable handling and clock gate control from the scan flip-flops in the FIFO path 500.

[0123] In the first full-speed capture, in the start-on-capture implementation, the scan flip-flops in the write data path 400 receive only the start clock pulse, while the scan flip-flops in the FIFO path 500 receive only the capture clock pulse (e.g., time T3 to T4 for the scan flip-flops in the write data path 400 and time T4 to T5 for the scan flip-flops in the FIFO path 500). Advantageously, because the clock signals are not provided to the scan flip-flops in the write data path 400 and the FIFO path 500 at the same time, power consumption is reduced while maintaining scan coverage.

[0124] In the second full-speed capture, the FIFO path 500 is the initiator path, and the read data path 450 is the target. Therefore, the scan enable terminals (SE) of the scan flip-flops 502, 504, 506, and 508 are coupled to the second scan enable signal (SCAN_EN_B), while the scan enable terminal (SE) of the scan flip-flop 420 is coupled to the first scan enable signal (SCAN_EN_A). In addition, the clock terminals (CLK) of the scan flip-flops 502, 504, 506, and 508 are coupled to the clock signal (CLK_B) provided by the controller circuit 200, while the clock terminal (CLK) of the scan flip-flop 420 is coupled to the clock signal (CLK_A). Therefore, the scan flip-flops in the FIFO path 500 have independent scan enable handling and clock gate control from the scan flip-flops 420 in the read data path 450.

[0125] In the second full-speed capture, in the start-on-capture implementation, the scan flip-flops in the FIFO path 500 receive only the start clock pulse, while the scan flip-flops 420 in the read data path 450 receive only the capture clock pulse (e.g., for the scan flip-flops in the FIFO path 500 at times T9 to T 10and the time T for the scan flip-flop 420 in the read data path 450 10 To T 11 Advantageously, because the clock signal is not provided to the scan flip-flops in the FIFO path 500 and the read data path 450 at the same time, power consumption is reduced while maintaining scan coverage.

[0126] It is noted that by extending the controller circuit 200 to generate the third clock signal (CLK_C) from the clock signal (OCC_CLK) and the functional logic AND combination of the first scan enable signal (SCAN_EN_A), the second scan enable signal (SCAN_EN_B) and the sixth scan enable signal (SCAN_EN_E), the select enable terminal (SE) and the clock terminal (CLK) of the scan flip-flop 420 can be coupled to the sixth scan enable signal (e.g., SCAN_EN_E—assuming that the first select signal (SEL_1) and the second select signal (SEL_2) are set to the third scan enable signal (SCAN_EN_C) and the fourth scan enable signal (SCAN_EN_D), respectively) and the clock signal (CLK_C). Therefore, a hardware solution of the controller circuit 200 with more than two shifted clock pulses is similarly expected.

[0127] The write data path 400 includes a first scan trigger 402, a second scan trigger 404, a third scan trigger 406, and a fourth scan trigger 408, which may (or may not) be arranged as shown. The FIFO path 500 coupled to the write data path 400 includes a first scan trigger 502, a second scan trigger 504, a third scan trigger 506, and a fourth scan trigger 508, which may (or may not) be arranged as shown. The write data path 400 and the FIFO path 500 may include additional scan triggers (not shown). Therefore, Figure 4 and Figure 5 The number of scan flip-flops in is non-limiting, and fewer or greater numbers are similarly contemplated.

[0128] In an embodiment, the data terminals (D) of the scan flip-flops 402 , 404 , 406 , and 408 are configured to receive data signals from, for example, a test controller.

[0129] The first scan trigger 402 is configured to receive, for example, a first serially shifted test pattern (SCAN_IN_1) at a scan input terminal (SI), which is propagated through the scan chain. In an embodiment, the test pattern is applied to the scan input terminal (SI) one bit at a time and in synchronization with the clock signal (CLK_A). The shifted-in test pattern is observed at the output terminal (Q) of the first scan trigger 402 and provided as the first write data address (A1) at the scan input terminal (SI) of the second scan trigger 404. The shifted-in test pattern is then observed at the output terminal (Q) of the second scan trigger 404 and provided as the second write data address (A2) at the scan input terminal (SI) of the third scan trigger 406. The shifted-in test pattern is observed at the output terminal (Q) of the third scan trigger 406 and provided as a write enable (WEN) at the scan input terminal (SI) of the fourth scan trigger 408. Finally, the shifted-in test pattern is observed as write data (MDW) at the output terminal (Q) of the fourth scan trigger 408.

[0130] The data terminal (D) of the first scan flip-flop 502 is coupled to the output terminal of the first four-input AND gate 510. The first four-input AND gate 510 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the write data (MDW). In response to the first write data address (A1) and the second write data address (A2) being logic "0" and "0", respectively, and the write enable (WEN) being logic "0", the write data (MDW) is provided at the input terminal (D) of the first scan flip-flop 502.

[0131] The data terminal (D) of the second scan flip-flop 504 is coupled to the output terminal of the second four-input AND gate 512. The second four-input AND gate 512 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the write data (MDW). In response to the first write data address (A1) and the second write data address (A2) being logic "0" and "1", respectively, and the write enable (WEN) being logic "0", the write data (MDW) is provided at the input terminal (D) of the second scan flip-flop 504.

[0132] The data terminal (D) of the third scan flip-flop 506 is coupled to the output terminal of the third four-input AND gate 514. The third four-input AND gate 514 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the write data (MDW). In response to the first write data address (A1) and the second write data address (A2) being logic "1" and "0", respectively, and the write enable (WEN) being logic "0", the write data (MDW) is provided at the input terminal (D) of the third scan flip-flop 506.

[0133] The data terminal (D) of the fourth scan flip-flop 508 is coupled to the output terminal of the fourth four-input AND gate 516. The fourth four-input AND gate 516 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the write data (MDW). In response to the first write data address (A1) and the second write data address (A2) being logic "1" and "1", respectively, and the write enable (WEN) being logic "0", the write data (MDW) is provided at the input terminal (D) of the fourth scan flip-flop 508.

[0134] In an embodiment, scan triggers 402, 404, 406, 408, 502, 504, 506, and 508 with different scan enable signals (i.e., SCAN_EN_A and SCAN_EN_B) are mixed in the same scan chain. For example, (i) the first scan trigger 402 and the first scan trigger 502, (ii) the second scan trigger 404 and the second scan trigger 504, (iii) the third scan trigger 406 and the third scan trigger 506, and (iv) the fourth scan trigger 408 and the fourth scan trigger 508, each can be an endpoint in a corresponding scan chain. In an embodiment, the scan triggers 402, 404, 406, and 408 are the first scan triggers in the corresponding scan chain. In an embodiment, the scan triggers 502, 504, 506, and 508 are the last scan triggers in the corresponding scan chain.

[0135] The first scan flip-flop 502 is configured to receive, for example, a second serially shifted test pattern (SCAN_IN_2) at a scan input terminal (SI), which is propagated through the scan chain. In an embodiment, the test pattern is applied to the scan input terminal (SI) one bit at a time and in synchronization with the clock signal (CLK_B). The shifted-in test pattern is observed at the output terminal (Q) of the first scan flip-flop 502 and provided as the first data (F1D) at the scan input terminal (SI) of the second scan flip-flop 504. The shifted-in test pattern is then observed at the output terminal (Q) of the second scan flip-flop 504 and provided as the second data (F2D) at the scan input terminal (SI) of the third scan flip-flop 506. The shifted-in test pattern is observed at the output terminal (Q) of the third scan flip-flop 506 and provided as the third data (F3D) at the scan input terminal (SI) of the fourth scan flip-flop 508. Finally, the shifted-in test pattern is observed at the output terminal (Q) of the fourth scan flip-flop 508 as the fourth data (F4D).

[0136] In an embodiment, a data terminal (D) of a scan flip-flop 420 in the read data path 450 is coupled to the write data path 400 and the FIFO path 500, and is coupled to an output terminal of a four-input OR gate 418. A clock terminal (CLK), a scan enable terminal (SE), and a scan input terminal (SI) of the scan flip-flop 420 are coupled to a clock signal (CLK_A), a first scan enable signal (SCAN_EN_A), and write data (MDW), respectively. The scan flip-flop 420 is configured to provide a latched output signal (SO_1) at an output terminal (Q).

[0137] The first four-input AND gate 410 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the first data (F1D). In response to the first write data address (A1) and the second write data address (A2) being logic "0" and "0", respectively, and the write enable (WEN) being logic "1" (i.e., the read enable is asserted), the first data (F1D) is provided at the first input terminal of the four-input OR gate 418.

[0138] The second four-input AND gate 412 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the third data (F3D). In response to the first write data address (A1) and the second write data address (A2) being logic "1" and "0", respectively, and the write enable (WEN) being logic "1" (i.e., the read enable is asserted), the third data (F3D) is provided at the second input terminal of the four-input OR gate 418.

[0139] The third four-input AND gate 414 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the fourth data (F4D). In response to the first write data address (A1) and the second write data address (A2) being logic "1" and "1", respectively, and the write enable (WEN) being logic "1" (i.e., the read enable is asserted), the fourth data (F4D) is provided at the third input terminal of the four-input OR gate 418.

[0140] The fourth four-input AND gate 416 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the second data (F2D). In response to the first write data address (A1) and the second write data address (A2) being logic "0" and "1", respectively, and the write enable (WEN) being logic "1" (i.e., the read enable is asserted), the second data (F2D) is provided at the fourth input terminal of the four-input OR gate 418.

[0141] Figure 6 and Figure 7 A block diagram illustrating an example implementation of an embodiment of the present disclosure in a dual cycle path (multi-cycle path) is illustrated. Figure 6 and Figure 7 Illustrated are a write data path 600, a first-in-first-out (FIFO) path 700, and a read data path 650, which may be arranged as a single embodiment.

[0142] In the first full-speed capture, the write data path 600 is the initiating path, and the FIFO path 700 is the target path. Therefore, the scan enable terminals (SE) of the scan flip-flops 602, 702, 606, and 706 are coupled to the first scan enable signal (SCAN_EN_A), and the scan enable terminals (SE) of the scan flip-flops 704, 604, 708, and 608 are coupled to the second scan enable signal (SCAN_EN_B). In addition, the clock terminals (CLK) of the scan flip-flops 602, 604, 606, and 608 are coupled to the clock signal (CLK_A) provided by the controller circuit 200, and the clock terminals (CLK) of the scan flip-flops 702, 704, 706, and 708 are coupled to the clock signal (CLK_B). Therefore, the alternate scan flip-flops in the write data path 600 have an independent scan enable handling from the alternate scan flip-flops in the FIFO path 700.

[0143] In an embodiment, the clock terminals (CLK) of the scan flip-flops 602, 604, 606, 608, 620 are coupled to the output of the clock gating circuit 116, and the clock terminals (CLK) of the scan flip-flops 702, 704, 706, 708 are coupled to the output of the clock gating circuit 118. The first selection signal (SEL_1) and the second selection signal (SEL_2) are set to the fourth scan enable signal (SCAN_EN_C) and the fifth scan enable signal (SCAN_EN_D), respectively.

[0144] In the first full-speed capture, in the start-on-capture implementation, the scan flip-flops in the write data path 600 receive only the start clock pulse, while the scan flip-flops in the FIFO path 700 receive only the capture clock pulse (e.g., time T3 to T4 for the scan flip-flops in the write data path 600 and time T4 to T5 for the scan flip-flops in the FIFO path 700). Advantageously, because the clock signals are not provided to the scan flip-flops in the write data path 600 and the FIFO path 700 at the same time, power consumption is reduced while maintaining scan coverage.

[0145] In the second full-speed capture, the FIFO path 700 is the initiating path, and the read data path 650 is the target. Therefore, the scan enable terminals (SE) of the scan flip-flops 704 and 708 are coupled to the second scan enable signal (SCAN_EN_B), while the scan enable terminals (SE) of the scan flip-flops 702, 706, and 620 are coupled to the first scan enable signal (SCAN_EN_A). In addition, the clock terminals (CLK) of the scan flip-flops 702, 704, 706, and 708 are coupled to the clock signal (CLK_B) provided by the controller circuit 200, while the clock terminal (CLK) of the fifth scan flip-flop 620 is coupled to the clock signal (CLK_A). Therefore, the alternate scan flip-flops in the FIFO path 700 have independent scan enable handling, and the scan flip-flops in the FIFO path 700 have independent clock gate control from the scan flip-flops 620 in the read data path 650.

[0146] It should be noted that by expanding the control circuit 200 to generate a third clock signal (CLK_C) from a functional logic AND combination of the clock signal (OCC_CLK) and the first scan enable signal (SCAN_EN_A), the second scan enable signal (SCAN_EN_B), and the sixth scan enable signal (SCAN_EN_E), the selection enable terminal (SE) and the clock terminal (CLK) of the scan trigger 620 can be coupled to the sixth scan enable signal (SCAN_EN_E) and the clock signal (CLK_C), respectively.

[0147] The write data path 600 includes a first scan trigger 602, a second scan trigger 604, a third scan trigger 606, and a fourth scan trigger 608, which may (or may not) be arranged as shown. The FIFO path 700 coupled to the write data path 600 includes a first scan trigger 702, a second scan trigger 704, a third scan trigger 706, and a fourth scan trigger 708, which may (or may not) be arranged as shown. The write data path 600 and the FIFO path 700 may include additional scan triggers (not shown). Therefore, Figure 6 and Figure 7 The number of scan triggers in is non-limiting, and a smaller or larger number may also be envisioned.

[0148] In an embodiment, the data terminals (D) of the scan flip-flops 602 , 604 , 606 , and 608 are configured to receive data signals from, for example, a test controller.

[0149] In an embodiment, the clock terminals (CLK) of the scan flip-flops 602 , 604 , 606 , and 608 are coupled to a clock signal (CLK_A) generated by the phase-locked loop 112 and the on-chip clock generator 114 .

[0150] In an embodiment, the scan enable terminals (SE) of the scan flip-flops 602 and 606 are coupled to a first scan enable signal (SCAN_EN_A). The scan enable terminals (SE) of the scan flip-flops 604 and 608 are coupled to a second scan enable signal (SCAN_EN_B).

[0151] The first scan trigger 602 is configured to receive, for example, a first serially shifted test pattern (SCAN_IN_1) at a scan input terminal (SI), which is propagated through the scan chain. In an embodiment, the test pattern is applied to the scan input terminal (SI) one bit at a time and in synchronization with the clock signal (CLK). The shifted-in test pattern is observed at the output terminal (Q) of the first scan trigger 602 and provided as the first write data address (A1) at the scan input terminal (SI) of the second scan trigger 604. The shifted-in test pattern is then observed at the output terminal (Q) of the second scan trigger 604 and provided as the second write data address (A2) at the scan input terminal (SI) of the third scan trigger 606. The shifted-in test pattern is observed at the output terminal (Q) of the third scan trigger 606 and provided as a write enable (WEN) at the scan input terminal (SI) of the fourth scan trigger 608. Finally, the shifted-in test pattern is observed at the output terminal (Q) of the fourth scan trigger 608 as write data (MDW).

[0152] The data terminal (D) of the first scan flip-flop 702 is coupled to the output terminal of the first four-input AND gate 710. The first four-input AND gate 710 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the write data (MDW). In response to the first write data address (A1) and the second write data address (A2) being logic "0" and "0", respectively, and the write enable (WEN) being logic "0", the write data (MDW) is provided at the input terminal (D) of the first scan flip-flop 702.

[0153] The data terminal (D) of the second scan flip-flop 704 is coupled to the output terminal of the second four-input AND gate 712. The second four-input AND gate 712 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the write data (MDW). In response to the first write data address (A1) and the second write data address (A2) being logic "0" and "1", respectively, and the write enable (WEN) being logic "0", the write data (MDW) is provided at the input terminal (D) of the second scan flip-flop 704.

[0154] The data terminal (D) of the third scan flip-flop 706 is coupled to the output terminal of the third four-input AND gate 714. The third four-input AND gate 714 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the write data (MDW). In response to the first write data address (A1) and the second write data address (A2) being logic "1" and "0", respectively, and the write enable (WEN) being logic "0", the write data (MDW) is provided at the input terminal (D) of the third scan flip-flop 706.

[0155] The data terminal (D) of the fourth scan flip-flop 708 is coupled to the output terminal of the fourth four-input AND gate 716. The fourth four-input AND gate 716 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the write data (MDW). In response to the first write data address (A1) and the second write data address (A2) being logic "1" and "1", respectively, and the write enable (WEN) being logic "0", the write data (MDW) is provided at the input terminal (D) of the fourth scan flip-flop 708.

[0156] In an embodiment, the clock terminals (CLK) of the scan flip-flops 702 , 704 , 706 , and 708 are coupled to a clock signal (CLK_B) generated by the phase-locked loop 112 and the on-chip clock generator 114 .

[0157] In an embodiment, the scan enable terminals (SE) of the scan flip-flops 702 and 706 are coupled to a first scan enable signal (SCAN_EN_A). The scan enable terminals (SE) of the scan flip-flops 704 and 708 are coupled to a second scan enable signal (SCAN_EN_B).

[0158] In an embodiment, scan triggers 602, 604, 606, 608, 702, 704, 706, and 708 with different scan enable signals (i.e., SCAN_EN_A and SCAN_EN_B) are mixed in the same scan chain. For example, (i) the first scan trigger 602 and the first scan trigger 702, (ii) the second scan trigger 604 and the second scan trigger 704, (iii) the third scan trigger 606 and the third scan trigger 706, and (iv) the fourth scan trigger 608 and the fourth scan trigger 708, each can be an endpoint in a corresponding scan chain. In an embodiment, the scan triggers 602, 604, 606, and 608 are the first scan triggers in the corresponding scan chain. In an embodiment, the scan triggers 702, 704, 706, and 708 are the last scan triggers in the corresponding scan chain.

[0159] The first scan trigger 702 is configured to receive, for example, a second serial shift test pattern (SCAN_IN_2) at a scan input terminal (SI), which is propagated through the scan chain. In an embodiment, the test pattern is applied to the scan input terminal (SI) one bit at a time and in synchronization with the clock signal (CLK_B). The shifted-in test pattern is observed at the output terminal (Q) of the first scan trigger 702 and provided as the first data (F1D) at the scan input terminal (SI) of the second scan trigger 704. The shifted-in test pattern is then observed at the output terminal (Q) of the second scan trigger 704 and provided as the second data (F2D) at the scan input terminal (SI) of the third scan trigger 706. The shifted-in test pattern is observed at the output terminal (Q) of the third scan trigger 706 and provided as the third data (F3D) at the scan input terminal (SI) of the fourth scan trigger 708. Finally, the shifted-in test pattern is observed at the output terminal (Q) of the fourth scan trigger 708 as the fourth data (F4D).

[0160] In an embodiment, the data terminal (D) of the fifth scan flip-flop 620 in the read data path 650 is coupled to the write data path 600 and the FIFO path 700, and is coupled to the output terminal of the four-input OR gate 618. The clock terminal (CLK), the scan enable terminal (SE), and the scan input terminal (SI) of the fifth scan flip-flop 620 are coupled to the clock signal (CLK_A), the first scan enable signal (SCAN_EN_A), and the write data (MDW), respectively. The fifth scan flip-flop 620 is configured to provide a latched output signal (SO_1) at the output terminal (Q).

[0161] The first four-input AND gate 610 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the first data (F1D). In response to the first write data address (A1) and the second write data address (A2) being logic "0" and "0", respectively, and the write enable (WEN) being logic "1" (i.e., the read enable is asserted), the first data (F1D) is provided at the first input terminal of the four-input OR gate 618.

[0162] The second four-input AND gate 612 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the third data (F3D). In response to the first write data address (A1) and the second write data address (A2) being logic "1" and "0", respectively, and the write enable (WEN) being logic "1" (i.e., the read enable is asserted), the third data (F3D) is provided at the second input terminal of the four-input OR gate 618.

[0163] The third four-input AND gate 614 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the fourth data (F4D). In response to the first write data address (A1) and the second write data address (A2) being logic "1" and "1", respectively, and the write enable (WEN) being logic "1" (i.e., the read enable is asserted), the fourth data (F4D) is provided at the third input terminal of the four-input OR gate 618.

[0164] The fourth four-input AND gate 616 has first, second, third and fourth input terminals, which are respectively coupled to the first write data address (A1), the second write data address (A2), the write enable (WEN) and the second data (F2D). In response to the first write data address (A1) and the second write data address (A2) being logic "0" and "1", respectively, and the write enable (WEN) being logic "1" (i.e., the read enable is asserted), the second data (F2D) is provided at the fourth input terminal of the four-input OR gate 618.

[0165] In an embodiment, a hardware implementation as disclosed may be combined with software solutions such as power gating. However, it should be appreciated that an implementation using only hardware is also contemplated.

[0166] Figure 8A flow chart of an embodiment method 800 for testing a scan chain 102 in an integrated circuit is illustrated. In step 802, the controller circuit 200 receives a first clock signal (OCC_CLK) and a first scan enable signal (SCAN_EN_AB).

[0167] In step 804, the control circuit 200 generates a second clock signal (CLK_A) and a third clock signal (CLK_B) based on the first clock signal (OCC_CLK) and the first scan enable signal (SCAN_EN_AB). The third clock signal (CLK_B) is delayed by one clock pulse relative to the second clock signal (CLK_A). The first clock signal (OCC_CLK), the second clock signal (CLK_A), and the third clock signal (CLK_B) have the same duty cycle.

[0168] At step 806, the controller circuit 200 provides a second clock signal (CLK_A) to a clock terminal (CLK) of the first scan flip-flop 104 of the scan chain 102. The scan enable input (SE) of the first scan flip-flop 104 is configured to receive a second scan enable signal (SCAN_EN_A).

[0169] At step 808, the controller circuit 200 provides a third clock signal (CLK_B) to the clock terminal (CLK) of the last scan flip-flop 106 of the scan chain 102. The scan enable input (SE) of the last scan flip-flop 106 is configured to receive the third scan enable signal (SCAN_EN_B).

[0170] It is noted that all steps listed in the flowchart of method 800 are not required and may be optional. In addition, changes to the arrangement of steps, removal of one or more steps and path connections, and addition of steps and path connections are similarly contemplated.

[0171] A first aspect relates to a control circuit, comprising a first flip-flop, a first NOT gate, a first multiplexer, a second multiplexer, a first OR gate, a second OR gate, and a first clock gating circuit. A data terminal of the first flip-flop is configured to receive a first scan enable signal, a clock terminal of the first flip-flop is configured to receive a first clock signal, and an output terminal of the first flip-flop is configured to provide a first latched scan enable signal. The first NOT gate is configured to receive the first latched scan enable signal and provide an inverted first latched scan enable signal. A first input terminal of the first multiplexer is configured to receive a first test control signal, a second input terminal of the first multiplexer is configured to receive a second test control signal, a third input terminal of the first multiplexer is configured to receive the first latched scan enable signal, a fourth input terminal of the first multiplexer is configured to receive an inverted first latched scan enable signal, a first selection terminal of the first multiplexer is configured to receive a first selection signal, and a second selection terminal of the first multiplexer is configured to receive a second selection signal. The first input of the second multiplexer is configured to receive the functional logic signal, the second input of the second multiplexer is configured to receive the output signal from the first multiplexer according to the first selection signal and the second selection signal, and the selection terminal of the second multiplexer is configured to receive the third test control signal. The first input of the first OR gate is configured to receive the first scan enable signal, and the second input of the first OR gate is configured to receive the fourth test control signal. The first input of the second OR gate is coupled to the output of the first OR gate, and the second input of the second OR gate is configured to receive the output signal from the second multiplexer according to the third test control signal. The first clock gating circuit has a first latch coupled to the first AND gate, the data terminal of the first latch is coupled to the output of the second OR gate, and the gated negative set terminal of the first latch is configured to receive the first clock signal. The first clock gating circuit is configured to provide a second clock signal.

[0172] In a first implementation form of the control circuit according to the first aspect per se, the first clock gating circuit is configured to provide the second clock signal to a first scan flip-flop in the scan chain.

[0173] In a second implementation form of the control circuit according to the first aspect itself or any of the preceding implementation forms of the first aspect, the first test control signal, the second test control signal, the third test control signal and the fourth test control signal are generated by a test control unit coupled to an integrated circuit including the control circuit.

[0174] In a third implementation form of the control circuit according to the first aspect itself or any of the foregoing implementation forms of the first aspect, the control circuit further comprises a second flip-flop, a second NOT gate, a third multiplexer, a fourth multiplexer, a third OR gate, a fourth OR gate, and a second clock gating circuit. The data terminal of the second flip-flop is configured to receive the first scan enable signal, the clock terminal of the second flip-flop is configured to receive the first clock signal, and the output terminal of the second flip-flop is configured to provide a second latched scan enable signal. The second NOT gate is configured to receive the second latched scan enable signal from the second flip-flop and provide an inverted second latched scan enable signal. The first input of the third multiplexer is configured to receive the first test control signal, the second input of the third multiplexer is configured to receive the second test control signal, the third input of the third multiplexer is configured to receive the second latched scan enable signal, the fourth input of the third multiplexer is configured to receive the inverted second latched scan enable signal, the first selection terminal of the third multiplexer is configured to receive the first selection signal, and the second selection terminal of the third multiplexer is configured to receive the second selection signal, the third multiplexer is configured such that the inverted second latched scan enable signal is provided at the output of the third multiplexer in response to the first latched scan enable signal being provided at the output of the first multiplexer, and the third multiplexer is configured such that the second latched scan enable signal is provided at the output of the third multiplexer in response to the inverted first latched scan enable signal being provided at the output of the first multiplexer. A fourth multiplexer, a first input of the fourth multiplexer is configured to receive a second functional logic signal, a second input of the fourth multiplexer is configured to receive an output signal from the third multiplexer according to a first selection signal and a second selection signal, and a selection terminal of the fourth multiplexer is configured to receive a third test control signal. A first input of the third OR gate is configured to receive a first scan enable signal, and a second input of the third OR gate is configured to receive a fourth test control signal. A first input of the fourth OR gate is coupled to an output of the third OR gate, and a second input of the fourth OR gate is configured to receive an output signal from the fourth multiplexer according to the third test control signal. A second clock gating circuit includes a second latch coupled to a second AND gate, a data terminal of the second latch is coupled to an output of the fourth OR gate, a gated negative set terminal of the second latch is configured to receive a first clock signal, and the second clock gating circuit is configured to provide a third clock signal, and the third clock signal is delayed by one clock pulse from the second clock signal.

[0175] In a fourth implementation form of the control circuit according to the first aspect itself or any of the preceding implementation forms of the first aspect, the second clock gating circuit is configured to provide a third clock signal to a last scan flip-flop in the scan chain.

[0176] In a fifth implementation form of the control circuit according to the first aspect as such or any of the preceding implementation forms of the first aspect, each or both of the first latch, the second latch are of gated D latch type.

[0177] In a sixth implementation form of the control circuit according to the first aspect as such or any of the preceding implementation forms of the first aspect, the first selection signal and the second selection signal are provided by a scan decoder.

[0178] A second aspect relates to an integrated circuit. The integrated circuit includes a control circuit and a scan chain. The control circuit is configured to receive a first clock signal and a first scan enable signal, and generate a second clock signal and a third clock signal based on the first clock signal and the first scan enable signal, the third clock signal is delayed by one clock pulse from the second clock signal, and the first clock signal, the second clock signal and the third clock signal have the same duty cycle. The scan chain includes a first scan trigger and a last scan trigger, the clock terminal of the first scan trigger is configured to receive the second clock signal, the clock terminal of the last scan trigger is configured to receive the third clock signal, the scan enable input of the first scan trigger is configured to receive the second scan enable signal, and the scan enable input of the last scan trigger is configured to receive the third scan enable signal.

[0179] In a first implementation form of the integrated circuit according to the second aspect itself, the scan chain comprises a plurality of scan flip-flops. A scan input terminal of a first scan flip-flop is configured to receive a test pattern. A scan input terminal of each subsequent scan flip-flop in the scan chain is coupled to an output terminal of a previous scan flip-flop.

[0180] In a second implementation form of the integrated circuit according to the second aspect as such or any preceding implementation form of the second aspect, the first scan enable signal is a logical AND function of the second scan enable signal and the third scan enable signal.

[0181] In a third implementation form of the integrated circuit according to the second aspect as such or any preceding implementation form of the second aspect, the first scan enable signal is provided from a logic built-in self-test (LBIST) or using a scan enable pad from an automatic test pattern generation (ATPG) test tool.

[0182] In a fourth implementation form of the integrated circuit according to the second aspect itself or any of the preceding implementation forms of the second aspect, the control circuit comprises a first flip-flop, a first NOT gate, a first multiplexer, a second multiplexer, a first OR gate, a second OR gate, and a first clock gating circuit. The data terminal of the first flip-flop is configured to receive a first scan enable signal. The clock terminal of the first flip-flop is configured to receive a first clock signal. The output terminal of the first flip-flop is configured to provide a first latched scan enable signal. The first NOT gate is configured to receive the first latched scan enable signal and provide an inverted first latched scan enable signal. The first input of the first multiplexer is configured to receive the first test control signal, the second input of the first multiplexer is configured to receive the second test control signal, the third input of the first multiplexer is configured to receive the first latched scan enable signal, the fourth input of the first multiplexer is configured to receive the inverted first latched scan enable signal, the first selection terminal of the first multiplexer is configured to receive the first selection signal, and the second selection terminal of the first multiplexer is configured to receive the second selection signal. The first input of the second multiplexer is configured to receive the functional logic signal, the second input of the second multiplexer is configured to receive the output signal from the first multiplexer according to the first selection signal and the second selection signal, and the selection terminal of the second multiplexer is configured to receive the third test control signal. The first input of the first OR gate is configured to receive the first scan enable signal. The second input of the first OR gate is configured to receive the fourth test control signal. The first input of the second OR gate is coupled to the output of the first OR gate. The second input of the second OR gate is configured to receive an output signal from the second multiplexer according to the third test control signal. The first clock gating circuit includes a first latch and an AND gate. The data terminal of the first latch is coupled to the output of the second OR gate. The gated negative set terminal of the first latch is configured to receive the first clock signal. The first clock gating circuit is configured to provide the second clock signal or the third clock signal.

[0183] In a fifth implementation form of the integrated circuit according to the second aspect itself or any of the preceding implementation forms of the second aspect, the logic value of the first selection signal is equal to the logic value of the second scan enable signal, and the logic value of the second selection signal is equal to the logic value of the third scan enable signal.

[0184] In a sixth implementation form of the integrated circuit according to the second aspect itself or any of the foregoing implementation forms of the second aspect, the logic value of the first selection signal is equal to the inverted logic value of the second scan enable signal, and the logic value of the second selection signal is equal to the inverted logic value of the third scan enable signal.

[0185] A third aspect relates to a method for testing a scan chain in an integrated circuit. The method includes: receiving a first clock signal and a first scan enable signal by a control circuit; generating a second clock signal and a third clock signal based on the first clock signal and the first scan enable signal by the control circuit, wherein the third clock signal is delayed by one clock pulse from the second clock signal, and the first clock signal, the second clock signal and the third clock signal have the same duty cycle; providing the second clock signal to a clock terminal of a first scan trigger of the scan chain, wherein the scan enable input of the first scan trigger is configured to receive the second scan enable signal; and providing the third clock signal to a clock terminal of a last scan trigger of the scan chain, wherein the scan enable input of the last scan trigger is configured to receive the third scan enable signal.

[0186] In a first implementation form of the method according to the third aspect itself, the scan chain comprises a plurality of scan flip-flops. The method further comprises receiving a test pattern at a scan input terminal of a first scan flip-flop. The scan input terminal of each subsequent scan flip-flop in the scan chain is coupled to an output terminal of a previous scan flip-flop.

[0187] In a second implementation form of the method according to the third aspect as such or any preceding implementation form of the third aspect, the first scan enable signal is a logical AND function of the second scan enable signal and the third scan enable signal.

[0188] In a third implementation form of the method according to the third aspect itself or any preceding implementation form of the third aspect, the first scan enable signal is provided from a logic built-in self-test (LBIST) or using a scan enable pad from an automatic test pattern generation (ATPG) test tool.

[0189] In a fourth implementation form of the method according to the third aspect as such or any of the preceding implementation forms of the third aspect, the scan flip-flops of the scan chain have multi-cycle paths or include false paths.

[0190] In a second implementation form of the method according to the third aspect itself or any of the preceding implementation forms of the third aspect, the method further comprises providing a test pattern to a scan input terminal of a first scan trigger and observing an output terminal of a last scan trigger to detect errors in the scan chain.

[0191] Although this specification has been described in detail, it should be understood that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In the various figures, the same elements are represented by the same reference numerals. Moreover, the scope of the present disclosure is not limited to the specific embodiments described herein, because those of ordinary skill in the art will readily recognize from this disclosure that processes, machines, manufactures, material compositions, means, methods or steps currently existing or developed later may perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Thus, the appended claims are intended to include such processes, machines, manufactures, material compositions, means, methods or steps within their scope.

[0192] Accordingly, the specification and drawings should be regarded as illustrative only of the present disclosure as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents falling within the scope of the present disclosure.

Claims

1. A control circuit, characterized in that include: a first flip-flop, a data terminal of the first flip-flop being configured to receive a first scan enable signal, a clock terminal of the first flip-flop being configured to receive a first clock signal, and an output terminal of the first flip-flop being configured to provide a first latched scan enable signal; a first NOT gate configured to receive the first latched scan enable signal and provide an inverted first latched scan enable signal; a first multiplexer, a first input of the first multiplexer configured to receive a first test control signal, a second input of the first multiplexer configured to receive a second test control signal, a third input of the first multiplexer configured to receive a first latched scan enable signal, a fourth input of the first multiplexer configured to receive an inverted first latched scan enable signal, a first select terminal of the first multiplexer configured to receive a first select signal, and a second select terminal of the first multiplexer configured to receive a second select signal; a second multiplexer, a first input terminal of the second multiplexer configured to receive the functional logic signal, a second input terminal of the second multiplexer configured to receive an output signal from the first multiplexer according to the first selection signal and the second selection signal, and a selection terminal of the second multiplexer configured to receive a third test control signal; a first OR gate, wherein a first input terminal of the first OR gate is configured to receive a first scan enable signal, and a second input terminal of the first OR gate is configured to receive a fourth test control signal; a second OR gate, a first input terminal of the second OR gate being coupled to the output terminal of the first OR gate, and a second input terminal of the second OR gate being configured to receive an output signal from the second multiplexer according to a third test control signal; as well as The first clock gating circuit includes a first latch coupled to the first AND gate, a data terminal of the first latch is coupled to the output of the second OR gate, a gated negative set terminal of the first latch is configured to receive a first clock signal, and the first clock gating circuit is configured to provide a second clock signal.

2. The control circuit according to claim 1, characterized in that: The first clock gating circuit is configured to provide a second clock signal to a first scan flip-flop in the scan chain.

3. The control circuit according to claim 1, characterized in that: The first test control signal, the second test control signal, the third test control signal, and the fourth test control signal are generated by a test control unit coupled to an integrated circuit including the control circuit.

4. The control circuit according to claim 1, characterized in that Also includes: a second flip-flop, a data terminal of the second flip-flop being configured to receive the first scan enable signal, a clock terminal of the second flip-flop being configured to receive the first clock signal, and an output terminal of the second flip-flop being configured to provide a second latched scan enable signal; a second NOT gate configured to receive the second latched scan enable signal from the second flip-flop and provide an inverted second latched scan enable signal; a third multiplexer, a first input of the third multiplexer configured to receive the first test control signal, a second input of the third multiplexer configured to receive the second test control signal, a third input of the third multiplexer configured to receive the second latched scan enable signal, a fourth input of the third multiplexer configured to receive the inverted second latched scan enable signal, a first select terminal of the third multiplexer configured to receive the first select signal, and a second select terminal of the third multiplexer configured to receive the second select signal, the third multiplexer configured such that the inverted second latched scan enable signal is provided at an output of the third multiplexer in response to providing the first latched scan enable signal at an output of the first multiplexer, and the third multiplexer configured such that the second latched scan enable signal is provided at an output of the third multiplexer in response to providing the inverted first latched scan enable signal at an output of the first multiplexer; a fourth multiplexer, a first input terminal of the fourth multiplexer configured to receive the second functional logic signal, a second input terminal of the fourth multiplexer configured to receive an output signal from the third multiplexer according to the first selection signal and the second selection signal, and a selection terminal of the fourth multiplexer configured to receive a third test control signal; a third OR gate, wherein a first input terminal of the third OR gate is configured to receive the first scan enable signal, and a second input terminal of the third OR gate is configured to receive a fourth test control signal; a fourth OR gate, a first input terminal of the fourth OR gate being coupled to the output terminal of the third OR gate, and a second input terminal of the fourth OR gate being configured to receive an output signal from a fourth multiplexer according to a third test control signal; as well as The second clock gating circuit includes a second latch coupled to the second AND gate, a data terminal of the second latch is coupled to the output of the fourth OR gate, a gated negative set terminal of the second latch is configured to receive the first clock signal, the second clock gating circuit is configured to provide a third clock signal, and the third clock signal is delayed from the second clock signal by one clock pulse.

5. The control circuit according to claim 4, characterized in that The second clock gating circuit is configured to provide a third clock signal to a last scan flip-flop in the scan chain.

6. The control circuit according to claim 4, characterized in that Each of the first latch, the second latch, or both are of a gated D latch type.

7. The control circuit according to claim 1, characterized in that The first selection signal and the second selection signal are provided by a scan decoder.

8. An integrated circuit, characterized in that include: The control circuit is configured as follows: receiving a first clock signal and a first scan enable signal, and generating a second clock signal and a third clock signal based on the first clock signal and the first scan enable signal, wherein the third clock signal is delayed by one clock pulse from the second clock signal, and the first clock signal, the second clock signal and the third clock signal have the same duty cycle; as well as A scan chain comprises a first scan trigger and a last scan trigger, wherein a clock terminal of the first scan trigger is configured to receive a second clock signal, a clock terminal of the last scan trigger is configured to receive a third clock signal, a scan enable input of the first scan trigger is configured to receive a second scan enable signal, and a scan enable input of the last scan trigger is configured to receive a third scan enable signal.

9. The integrated circuit as claimed in claim 8, characterized in that The scan chain includes a plurality of scan flip-flops, a scan input terminal of a first scan flip-flop is configured to receive a test pattern, and a scan input terminal of each subsequent scan flip-flop in the scan chain is coupled to an output terminal of a previous scan flip-flop.

10. The integrated circuit of claim 8, wherein The first scan enable signal is a logical AND function of the second scan enable signal and the third scan enable signal.

11. The integrated circuit of claim 8, wherein The first scan enable signal is provided from a logic built-in self-test or using a scan enable pad from an automatic test pattern generation test tool.

12. The integrated circuit of claim 8, wherein The control circuit includes: a first flip-flop, a data terminal of the first flip-flop being configured to receive a first scan enable signal, a clock terminal of the first flip-flop being configured to receive a first clock signal, and an output terminal of the first flip-flop being configured to provide a first latched scan enable signal; a first NOT gate configured to receive the first latched scan enable signal and provide an inverted first latched scan enable signal; a first multiplexer, a first input of the first multiplexer configured to receive a first test control signal, a second input of the first multiplexer configured to receive a second test control signal, a third input of the first multiplexer configured to receive a first latched scan enable signal, a fourth input of the first multiplexer configured to receive an inverted first latched scan enable signal, a first select terminal of the first multiplexer configured to receive a first select signal, and a second select terminal of the first multiplexer configured to receive a second select signal; a second multiplexer, a first input terminal of the second multiplexer configured to receive the functional logic signal, a second input terminal of the second multiplexer configured to receive an output signal from the first multiplexer according to the first selection signal and the second selection signal, and a selection terminal of the second multiplexer configured to receive a third test control signal; a first OR gate, wherein a first input terminal of the first OR gate is configured to receive a first scan enable signal, and a second input terminal of the first OR gate is configured to receive a fourth test control signal; a second OR gate having a first input terminal coupled to the output terminal of the first OR gate and a second input terminal of the second OR gate configured to receive an output signal from the second multiplexer according to the third test control signal; and The first clock gating circuit includes a first latch and an AND gate, wherein the data terminal of the first latch is coupled to the output terminal of the second OR gate, the gated negative set terminal of the first latch is configured to receive the first clock signal, and the first clock gating circuit is configured to provide the second clock signal or the third clock signal.

13. The integrated circuit of claim 12, wherein The logic value of the first selection signal is equal to the logic value of the second scan enable signal, and the logic value of the second selection signal is equal to the logic value of the third scan enable signal.

14. The integrated circuit of claim 12, wherein The logic value of the first selection signal is equal to the inverted logic value of the second scan enable signal, and the logic value of the second selection signal is equal to the inverted logic value of the third scan enable signal.

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