Display device

Abstract

A display device is provided. The display device includes: a substrate; a thin film transistor positioned on the substrate and including a source electrode, a drain electrode, and an active layer positioned between the source electrode and the drain electrode; a gate electrode positioned on the thin film transistor and overlapping the active layer in plan view; a gate protection layer positioned on the gate electrode and overlapping the active layer in plan view; an insulating layer positioned on the gate protection layer; and a gate capping layer positioned between a side surface of the gate electrode and the insulating layer, in which the gate capping layer includes a first portion and a second portion, the second portion is spaced apart from the first portion by the gate electrode interposed between the first portion and the second portion, and the first portion and the second portion are in contact with the gate protection layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0095815 filed on Jul. 24, 2023 and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has been increasing and becoming diversified. For example, display devices have been applied to various electronic devices, such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. In such a flat panel display device, because each pixel in the display panel includes a light emitting element that can emit light by itself, the light emitting display device can display an image without providing light to a backlight unit of the display panel. Utility Model Content

[0005] Aspects of the present disclosure provide a display device including a low-resistance line capable of high resolution and high-speed driving.

[0006] Aspects of the present disclosure also provide a method of manufacturing a display device in which a thickness of a gate electrode is increased.

[0007] However, the aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0008] In an embodiment of the present disclosure, a display device includes: a substrate; a thin film transistor, which is positioned on the substrate and includes a source electrode, a drain electrode, and an active layer positioned between the source electrode and the drain electrode; a gate electrode, which is positioned on the thin film transistor and overlaps with the active layer in a plan view; a gate protection layer, which is positioned on the gate electrode and overlaps with the active layer in a plan view; an insulating layer, which is positioned on the gate protection layer; and a gate covering layer, which is positioned between a side surface of the gate electrode and the insulating layer, wherein the gate covering layer includes a first portion and a second portion, the second portion is separated from the first portion by the gate electrode disposed between the first portion and the second portion, and the first portion and the second portion are in contact with the gate protection layer.

[0009] In an implementation, the gate protection layer may include a first surface facing the insulating layer, the first portion includes a second surface facing the insulating layer, and the first surface and the second surface are aligned with each other in a direction parallel to a main surface of the substrate.

[0010] In an implementation, the second portion may include a third surface facing the insulating layer, and the first surface may be positioned between the second surface and the third surface.

[0011] In an implementation, the first surface, the second surface, and the third surface may be aligned with each other in a direction parallel to the main surface of the substrate.

[0012] In an implementation, the first surface, the second surface, and the third surface may be in contact with the insulating layer.

[0013] In an implementation, the gate electrode may include a lower surface facing the substrate, and an inclination angle formed between a side surface of the gate electrode and the lower surface of the gate electrode is equal to or greater than 60° and less than 90°.

[0014] In an implementation, the gate electrode may have a thickness of about 0.5 micrometers (μm) or more.

[0015] In an implementation, the thickness of the gate cap layer may be equal to or greater than about 0.05 μm and equal to or less than about 0.25 μm.

[0016] In an embodiment, the gate capping layer may surround the entirety of the gate protection layer in a plan view, and wherein the first portion and the second portion may be monolithic in a plan view.

[0017] In an implementation, the entirety of the gate protection layer may be surrounded by the gate electrode, the gate capping layer, and the insulating layer.

[0018] In an implementation, a side surface of the gate electrode may be in contact with the gate capping layer.

[0019] In an implementation, the gate protection layer may cover a side surface of the gate electrode, and the gate protection layer is in contact with the side surface of the gate electrode.

[0020] In an implementation, the display device may further include a buffer layer positioned between the thin film transistor and the gate electrode, wherein the entirety of the gate electrode may be surrounded by the buffer layer and the gate protection layer.

[0021] In an implementation, the gate capping layer may not contact the gate electrode.

[0022] In an implementation, the gate protection layer may include a metal oxide and an inorganic insulating film.

[0023] In an embodiment of the present disclosure, a display device includes: a substrate; a thin film transistor, which is positioned on the substrate and includes a source electrode, a drain electrode, and an active layer positioned between the source electrode and the drain electrode; a gate electrode, which is positioned on the thin film transistor and overlaps with the active layer in a plan view; an insulating layer, which is positioned on the gate electrode; and a gate covering layer, which is positioned between a side surface of the gate electrode and the insulating layer, wherein the gate covering layer includes a first portion and a second portion and exposes an upper surface of the gate electrode, and the second portion is spaced apart from the first portion, the first portion includes a first surface facing the insulating layer, and the upper surface of the gate electrode and the first surface of the first portion are aligned with each other in a direction parallel to the main surface of the substrate.

[0024] In an implementation, the second portion may include a second surface facing the insulating layer, and an upper surface of the gate electrode may be positioned between the first surface and the second surface.

[0025] In an implementation, an upper surface of the gate electrode and first and second surfaces of the gate capping layer may be in contact with the insulating layer.

[0026] In an implementation, the entirety of the gate electrode may be surrounded by the gate capping layer in a plan view.

[0027] In the display device according to the embodiment, a low-resistance line capable of high resolution and high-speed driving can be provided by increasing the thickness of the gate electrode.

[0028] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0030] Figure 1 is a perspective view showing a display device according to an embodiment;

[0031] Figure 2 is a plan view showing a display panel according to an embodiment;

[0032] Figure 3 It is along Figure 1 A cross-sectional view of the display device taken along line Y1-Y1';

[0033] Figure 4 It is shown Figure 3 A schematic plan view of a display panel;

[0034] Figure 5 It is shown Figure 4 a plan view of an arrangement of emission regions in a display area of;

[0035] Figure 6 It is along Figure 5 A cross-sectional view of the display panel taken along line X1-X1';

[0036] Figure 7 yes Figure 6 An enlarged cross-sectional view of region A;

[0037] Figure 8 yes Figure 7 an enlarged cross-sectional view of region C;

[0038] Fig. 9 yes Figure 7 A schematic enlarged plan view of a region C of FIG.

[0039] Fig.10 According to another embodiment Figure 7 an enlarged cross-sectional view of region C;

[0040] Fig.11 According to yet another embodiment Figure 7 an enlarged cross-sectional view of region C;

[0041] Fig.12 According to another embodiment, Figure 5 A cross-sectional view of the display device taken along line X1-X1';

[0042] Fig.13 yes Fig.12 an enlarged cross-sectional view of a region T of ; and

[0043] Fig.14 yes Fig.12 Schematic enlarged plan view of a region T of FIG. DETAILED DESCRIPTION

[0044] It should be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first area", "first layer" or "first part" discussed below can be referred to as a second element, second component, second area, second layer or second part.

[0045] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should be further understood that when used in this specification, the terms "comprises" and / or "comprising", or "includes" and / or "including" specify the presence of the features, regions, wholes, steps, operations, elements and / or parts described, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts, and / or clusters thereof.

[0046] Further, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device other than the orientation depicted in the figures. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will be oriented to be on the "upper" side of the other elements. Therefore, the term "lower" can include both the orientations of "lower" and "upper", depending on the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "beneath" of the other elements will be oriented to be "above" of the other elements. Therefore, the term "below" or "below" can include both the orientations of the upper and lower parts.

[0047] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). Terms such as "about" can mean within one or more standard deviations, or, for example, within ±30%, 20%, 10%, 5% of the stated value.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0049] Hereinafter, illustrative embodiments will be described with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view showing a display device 10 according to an embodiment. Figure 2 1 is a plan view showing the display panel 100 according to the embodiment. As used herein, a "plan view" is a view in a third direction (Z-axis direction).

[0051] refer to Figure 1 and Figure 2 The display device 10 according to the embodiment is a device that displays moving images or still images and can be used as a display screen for various products (such as televisions, laptop computers, monitors, billboards, and Internet of Things (“IoT”) devices) and portable electronic devices (such as mobile phones, smart phones, tablet personal computers (“PCs”), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (“PMPs”), navigation devices, and ultra mobile PCs (“UMPCs”)).

[0052] The display device 10 according to the embodiment may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micron or nanometer light-emitting diode (micron LED or nano LED). Hereinafter, the display device 10 will be mainly described as an organic light-emitting display device, but the present disclosure is not limited thereto.

[0053] The display device 10 according to the embodiment may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0054] The display panel 100 may have a rectangular shape having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction) intersecting with the first direction (X-axis direction) in a plan view. The corner where the long side in the first direction (X-axis direction) and the short side in the second direction (Y-axis direction) meet may be a right angle or rounded with a certain curvature. The shape of the display panel 100 in a plan view is not limited to a rectangular shape, and may be other polygonal shapes, circular shapes, or elliptical shapes. In the accompanying drawings, the first direction (X-axis direction) and the second direction (Y-axis direction) are each horizontal directions and intersect with each other. For example, the first direction (X-axis direction) and the second direction (Y-axis direction) may be orthogonal to each other. In addition, the third direction (Z-axis direction) may be a vertical direction intersecting (e.g., orthogonal) with the first direction (X-axis direction) and the second direction (Y-axis direction). In the present disclosure, the direction indicated by the arrow from the first direction to the third direction (X-axis direction, Y-axis direction, and Z-axis direction) may be referred to as one side, and the direction opposite to the one side may be referred to as the other side.

[0055] The display panel 100 may be formed to be flat, but is not limited thereto. For another example, the display panel 100 may include a bent surface portion formed at the left and right ends thereof and having a constant curvature or a variable curvature. In addition, the display panel 100 may be flexibly formed to be bent, curved, folded, or rolled.

[0056] The display panel 100 may include a main area MA, a bending area BA, and a pad area PDA. The main area MA may include a display area DA displaying an image and a non-display area NDA disposed around the display area DA.

[0057] The display area DA may occupy most of the area of ​​the display panel 100. The display area DA may be disposed at the center of the display panel 100. A plurality of pixels each including a plurality of emission areas to display an image may be disposed in the display area DA.

[0058] The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be disposed to surround the display area DA. The non-display area NDA may be an edge area of ​​the display panel 100.

[0059] The bending area BA may be disposed between the main area MA and the pad area PDA in the second direction (Y-axis direction). The bending area BA may be an area bent under the display panel 100. When the bending area BA is bent under the display panel 100, a plurality of display drivers 200 and a circuit board 300 may be disposed under the display panel 100.

[0060] The pad area PDA may be a lower edge area of ​​the display panel 100. The pad area PDA may include the display driver 200, the display pad PD, and the circuit board 300.

[0061] The display driver 200 may be disposed in the pad area PDA. Each of the plurality of display drivers 200 may be attached to the non-display area NDA of the display panel 100 in a chip on glass (“COG”) manner. In another embodiment, each of the plurality of display drivers 200 may also be attached to the circuit board 300 in a chip on plastic (“COP”) manner.

[0062] The circuit board 300 may be disposed on a display pad PD disposed on an edge of one side of the display panel 100. The circuit board 300 may be attached to the display pad PD using a conductive adhesive member such as an anisotropic conductive film and an anisotropic conductive adhesive. Accordingly, the circuit board 300 may be electrically connected to a signal line of the display panel 100. Each of the plurality of circuit boards 300 may be a flexible printed circuit board or a flexible film such as a chip on film.

[0063] Figure 3 It is along Figure 1 1 is a cross-sectional view of the display device 10 taken along line Y1 - Y1 ′.

[0064] refer to Figure 3 The display device 10 may include a display panel 100, a color filter layer 190, a display driver 200, and a circuit board 300. The display panel 100 may include a substrate 110, a thin film transistor layer 130, a display element layer 150, a thin film encapsulation layer 170, and a touch sensor layer 180.

[0065] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, and rolled. For example, the substrate 110 may include a polymer resin such as polyimide ("PI"), but is not limited thereto. For another example, the substrate 110 may include a glass material or a metal material.

[0066] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may include a plurality of thin film transistors. Each of the plurality of thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In addition, the thin film transistor layer 130 may further include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line to each other, and a lead connecting the display driver 200 and the pad portion to each other. For example, when the gate driver is disposed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0067] The thin film transistor layer 130 may be disposed in the main area MA, the bending area BA, and the pad area PDA. The thin film transistors, gate lines, data lines, and power lines of the thin film transistor layer 130 may be disposed in the display area DA of the main area MA, and the gate control lines and fan-out lines of the thin film transistor layer 130 may be disposed in the non-display area NDA of the main area MA. In addition, the leads of the thin film transistor layer 130 may be disposed in the bending area BA and the pad area PDA.

[0068] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may include a plurality of light emitting elements each including a pixel electrode, a light emitting layer, and a common electrode to emit light, a pixel defining layer, a bank structure, and the like.

[0069] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a voltage through the thin film transistor of the thin film transistor layer 130 and the common electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light-emitting layer to emit light. In another embodiment, the light-emitting element may include a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, or a micro light-emitting diode.

[0070] The thin film encapsulation layer 170 may cover the upper surface and the side surface of the display element layer 150 and may protect the display element layer 150. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the display element layer 150.

[0071] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may include a plurality of touch electrodes and a plurality of touch lines for sensing the touch of a user in a capacitive manner. For example, the touch sensor layer 180 may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner.

[0072] The color filter layer 190 may be disposed on the thin film encapsulation layer 170. The color filter layer 190 may include a plurality of color filters each corresponding to a plurality of emission regions. Each of the plurality of color filters may selectively transmit light of a specific wavelength therethrough and block or absorb light of other wavelengths. The color filter layer 190 may absorb a portion of the light introduced from outside the display device 10 to reduce reflected light of external light. Accordingly, the color filter layer 190 may prevent distortion of color caused by reflection of external light.

[0073] Since the color filter layer 190 is directly disposed on the thin film encapsulation layer 170 , the display device 10 may not require a separate substrate for the color filter layer 190 .

[0074] Although not shown in the drawings, the pad area PDA of the display device 10 may be bent by the bending area BA. When the pad area PDA is bent by the bending area BA, the display driver 200 and the circuit board 300 positioned in the pad area PDA may overlap the main area MA in the third direction (Z-axis direction).

[0075] Figure 4 It is shown Figure 3 Schematic plan view of a display panel 100.

[0076] refer to Figure 4 , a plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in a display area DA of the display panel 100. Each of the plurality of pixels PX may be defined as a minimum unit emitting light.

[0077] The plurality of gate lines GL may supply gate signals received from the gate driver 210 to the plurality of pixels PX. The plurality of gate lines GL may extend in a first direction X, and may be spaced apart from each other in a second direction Y intersecting the first direction X.

[0078] The plurality of data lines DL may supply data voltages received from the display driver 200 to the plurality of pixels PX. The plurality of data lines DL may extend in the second direction Y, and may be spaced apart from each other in the first direction X.

[0079] The plurality of power lines VL may supply a source voltage received from the display driver 200 to the plurality of pixels PX. Here, the source voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. The plurality of power lines VL may extend in the second direction Y and may be spaced apart from each other in the first direction X.

[0080] The gate driver 210 , the fan-out lines FOL, and the gate control lines GCL may be disposed in the non-display area NDA of the display panel 100 .

[0081] The gate driver 210 may generate a plurality of gate signals based on the gate control signal and may sequentially supply the plurality of gate signals to the plurality of gate lines GL according to a set order.

[0082] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0083] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0084] The pad area PDA of the display panel 100 may include a display driver 200 and a plurality of display pads PD.

[0085] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be supplied to a plurality of pixels PX and may control the brightness of the plurality of pixels PX. The display driver 200 may supply gate control signals to the gate driver 210 through the gate control lines GCL.

[0086] The plurality of display pads PD may be connected to the graphic system through the circuit board 300. The plurality of display pads PD may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0087] Figure 5 It is shown Figure 4 FIG. 1 is a plan view of an arrangement of emission areas EA1, EA2, and EA3 in a display area DA.

[0088] refer to Figure 5 The display device 10 may include a plurality of emission areas EA1, EA2 and EA3 and a non-emission area NLA arranged in the display area DA (hereinafter, for the convenience of explanation, the emission area EAn and the nth emission area EAn indicate the same features and are not particularly distinguished in the description).

[0089] The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The plurality of emission areas EA1, EA2, and EA3 may emit red light, green light, or blue light, respectively, and the colors of light emitted from the respective emission areas EA1, EA2, and EA3 may be different from each other, with the light emitting element ED described later (see Figure 6 ). In an embodiment, the first emission area EA1 may emit the first light as red light, the second emission area EA2 may emit the second light as green light, and the third emission area EA3 may emit the third light as blue light. However, the present disclosure is not limited thereto.

[0090] Multiple emission areas EA1, EA2 and EA3 can be set as Type, for example, diamond For example, the first emission area EA1 and the third emission area EA3 may be disposed to be spaced apart from each other in the first direction X and may be alternately disposed in the first direction X and the second direction Y. In the arrangement of the emission areas EA1, EA2, and EA3, the first emission area EA1 and the third emission area EA3 may be alternately disposed in the first row R1 and the third row R3 in the first direction X. The first emission area EA1 and the third emission area EA3 may be alternately disposed in the first column C1 and the third column C3 in the second direction Y.

[0091] The second emission area EA2 may be spaced apart from other adjacent second emission areas EA2 in the first direction X and the second direction Y, and may be spaced apart from the adjacent first emission area EA1 and the third emission area EA3 in the fourth direction DR4 or the fifth direction DR5. A plurality of second emission areas EA2 may be repeatedly disposed along the first direction X and the second direction Y, and the second emission area EA2 and the first emission area EA1 or the second emission area EA2 and the third emission area EA3 may be alternately disposed along the fourth direction DR4 or the fifth direction DR5. In the arrangement of the emission areas EA1, EA2, and EA3, the second emission area EA2 may be repeatedly disposed in the second row R2 and the fourth row R4 in the first direction X, and the second emission area EA2 may be repeatedly disposed in the second column C2 and the fourth column C4 in the second direction Y.

[0092] The pixel defining layer 151 described later (see Figure 6 ) to define each of the multiple emission areas EA1, EA2 and EA3.

[0093] The non-emission area NLA may be positioned while surrounding the emission areas EA1, EA2, and EA3. The non-emission area NLA may be a region in which light is not emitted. A pixel defining layer 151 described later may be positioned in the non-emission area NLA.

[0094] Figure 6 It is along Figure 5 1 is a cross-sectional view of the display panel 100 taken along line X1 - X1 ′. Figure 7 yes Figure 6 An enlarged cross-sectional view of area A.

[0095] refer to Figure 6 , the display panel 100 may include a substrate 110 , a thin film transistor layer 130 , a display element layer 150 , a thin film encapsulation layer 170 , and a touch sensor layer 180 .

[0096] The substrate 110 has been described above, and thus a description thereof will be omitted.

[0097] The thin film transistor layer 130 may include a first buffer layer 111 , a thin film transistor TFT, a first insulating layer 113 , a gate protection layer 115 , a gate capping layer 117 , a second insulating layer 119 , a third insulating layer 121 , a first connection electrode CNE1 , a first passivation layer 125 , a second connection electrode CNE2 , and a second passivation layer 127 .

[0098] The first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first buffer layer 111 may include a plurality of inorganic films alternately stacked.

[0099] The thin film transistor TFT may be disposed on the first buffer layer 111 and may constitute a pixel circuit of each pixel in a plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE. The semiconductor layer ACT may overlap with the gate electrode GE in a third direction (Z-axis direction) and may be insulated from the gate electrode GE by a first insulating layer 113. The semiconductor layer ACT may be referred to as an "active layer" and is disposed between the source electrode SE and the drain electrode DE. The first insulating layer 113 may be referred to as a "second buffer layer". The material of the semiconductor layer ACT in a portion of the semiconductor layer ACT may become a conductor to form a source electrode SE and a drain electrode DE. The semiconductor layer ACT may include polycrystalline silicon, but is not limited thereto. For another example, the semiconductor layer ACT may include amorphous silicon or the like.

[0100] The first insulating layer 113 may be disposed on the semiconductor layer ACT. For example, the first insulating layer 113 may cover the semiconductor layer ACT, the source electrode SE, the drain electrode DE, and the first buffer layer 111, and may insulate the semiconductor layer ACT from the gate electrode GE. The first insulating layer 113 may be disposed along the profile of the thin film transistor TFT with substantially the same thickness. That is, the distance (thickness) between the two closest surfaces of the first insulating layer 113 facing each other is substantially the same at each position. The first insulating layer 113 may include an inorganic insulating material and may be formed into a plurality of layers. For example, the first insulating layer 113 may be configured to be made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a single layer made of silicon nitride (SiN x ) and silicon oxide (SiO x The first insulating layer 113 may define a first contact hole CNTH1 through which the first connection electrode CNE1 penetrates.

[0101] refer to Figure 6 and Figure 7, the gate electrode GE may be disposed on the first insulating layer 113. The gate electrode GE may overlap the semiconductor layer ACT in a third direction (Z-axis direction) with the first insulating layer 113 interposed therebetween.

[0102] The gate electrode GE may include a metal. For example, the gate electrode GE may include one or more metals selected from a group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0103] The gate protection layer 115 may be disposed on the gate electrode GE. The gate protection layer 115 may be used to protect the upper surface of the gate electrode GE so that the upper surface of the gate electrode GE is not polished by a chemical mechanical polishing process during the manufacturing process of the display device 10.

[0104] The gate protection layer 115 may include a transparent conductive material or an inorganic insulating film, and all metal layers constituting the lines of the display device 10. For example, the gate protection layer 115 may include indium tin oxide (ITO), indium zinc oxide (IZO), silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum (Al), aluminum alloys, molybdenum (Mo), molybdenum alloys, copper (Cu), copper alloys, titanium (Ti), titanium alloys, molybdenum-titanium alloys (MoTi), and the like. In another embodiment, the gate protection layer 115 may be omitted.

[0105] The gate capping layer 117 may be disposed on the gate electrode GE and the first insulating layer 113. The gate capping layer 117 may be positioned to cover the upper surface of the first insulating layer 113 and the side surface of the gate electrode GE, and may expose the gate protection layer 115 in the third direction (Z-axis direction). The gate capping layer 117 may define a first contact hole CNTH1 through which the first connection electrode CNE1 penetrates.

[0106] The gate capping layer 117 may be positioned between the side surface of the gate electrode GE and the second insulating layer 119 described later to ease the step that the second insulating layer 119 should cover. In other words, the gate capping layer 117 may serve to reduce the profile that the second insulating layer 119 should cover.

[0107] The gate capping layer 117 may include an inorganic insulating material and may be formed in a plurality of layers. For example, the gate capping layer 117 may be configured of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a single layer made of silicon nitride (SiN x ) and silicon oxide (SiOx ) made of multiple layers.

[0108] The second insulating layer 119 may be disposed on the gate protection layer 115 and the gate capping layer 117. The second insulating layer 119 may be disposed with substantially the same thickness along the contours of the gate capping layer 117 and the gate electrode GE. That is, the distance (thickness) between the two closest surfaces of the second insulating layer 119 facing each other is substantially the same at various locations. The second insulating layer 119 may include the same material as the first insulating layer 113.

[0109] The capacitor electrode CAE may be disposed on the second insulating layer 119. The capacitor electrode CAE may overlap the gate electrode GE of the thin film transistor TFT in the third direction (Z-axis direction). Since the second insulating layer 119 has a predetermined dielectric constant, a capacitor may be formed by the capacitor electrode CAE, the gate electrode GE, and the second insulating layer 119 disposed between the capacitor electrode CAE and the gate electrode GE. The second insulating layer 119 may define a first contact hole CNTH1 through which the first connection electrode CNE1 penetrates.

[0110] The capacitor electrode CAE may include a metal. For example, the capacitor electrode CAE may include one or more metals selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0111] The third insulating layer 121 may be disposed on the second insulating layer 119 and the capacitor electrode CAE. The third insulating layer 121 may cover the second insulating layer 119 and the capacitor electrode CAE. The third insulating layer 121 may define a first contact hole CNTH1 through which the first connection electrode CNE1 penetrates. The first contact hole CNTH1 may extend to penetrate the third insulating layer 121, the second insulating layer 119, the gate cap layer 117, and the first insulating layer 113.

[0112] The first connection electrode CNE1 may be disposed on the third insulating layer 121. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a first contact hole CNTH1 defined in the third insulating layer 121, the second insulating layer 119, the gate cover layer 117, and the first insulating layer 113 to contact the drain electrode DE of the thin film transistor TFT.

[0113] The first passivation layer 125 may cover the first connection electrode CNE1 and the third insulating layer 121. The first passivation layer 125 may protect the thin film transistor TFT. The first passivation layer 125 may define a second contact hole CNTH2 through which the second connection electrode CNE2 penetrates.

[0114] The second connection electrode CNE2 may be disposed on the first passivation layer 125. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED to each other (hereinafter, for convenience of explanation, the pixel electrode AEn and the n-th pixel electrode AEn indicate the same features and are not particularly distinguished in the description). The second connection electrode CNE2 may contact the first connection electrode CNE1 through a second contact hole CNTH2 defined in the first passivation layer 125.

[0115] The second passivation layer 127 may cover the second connection electrode CNE2 and the first passivation layer 125. The second passivation layer 127 may define a third contact hole CNTH3 through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED penetrate.

[0116] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may include a light emitting element ED and a pixel defining layer 151. The light emitting element ED may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 overlapping the emission areas EA1, EA2, and EA3, respectively. Specifically, the first light emitting element ED1 may overlap the first emission area EA1, the second light emitting element ED2 may overlap the second emission area EA2, and the third light emitting element ED3 may overlap the third emission area EA3. In addition, the first light emitting element ED1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a common electrode CE, the second light emitting element ED2 may include a second pixel electrode AE2, a second light emitting layer EL2, and a common electrode CE, and the third light emitting element ED3 may include a third pixel electrode AE3, a third light emitting layer EL3, and a common electrode CE.

[0117] exist Figure 6 In the present invention, for convenience of explanation, the first light emitting element ED1 and the third light emitting element ED3 have been shown and described, but the second light emitting element ED2 may also have the same structure and features as the first light emitting element ED1 and the third light emitting element ED3.

[0118] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer 127 to overlap the emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may be disposed to overlap the opening defined by the pixel defining layer 151 in the third direction (Z-axis direction). The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0119] The pixel defining layer 151 may be positioned to overlap the non-emission area NLA. The pixel defining layer 151 may be disposed on the second passivation layer 127 and portions of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer 151 may define an opening, and the emission areas EA1, EA2, and EA3 of the display device 10 may be defined by the opening defined by the pixel defining layer 151.

[0120] The pixel defining layer 151 may include a light absorbing material that prevents light reflection. For example, the pixel defining layer 151 may include a polyimide (PI)-based binder and a mixture of red, green, and blue pigments, or a cardo-based binder resin, a mixture of lactam-based black and blue pigments, and carbon black.

[0121] The light-emitting layers EL1, EL2 and EL3 may be positioned on the pixel electrodes AE1, AE2 and AE3, respectively (hereinafter, for the convenience of explanation, the light-emitting layer ELn indicates the same features as the nth light-emitting layer ELn and is not particularly distinguished in the description). The light-emitting layers EL1, EL2 and EL3 may be organic light-emitting layers made of organic materials. In the case where the light-emitting layers EL1, EL2 and EL3 correspond to the organic light-emitting layers, when the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2 and AE3 of the light-emitting elements ED1, ED2 and ED3 and the common electrode CE of the light-emitting elements ED1, ED2 and ED3 receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layers EL1, EL2 and EL3, respectively, through the hole transport layer and the electron transport layer, and may be combined with each other in the light-emitting layers EL1, EL2 and EL3 to emit light (hereinafter, for the convenience of explanation, the light-emitting element EDn indicates the same features as the nth light-emitting element EDn and is not particularly distinguished in the description).

[0122] The common electrode CE may be disposed on the light emitting layers EL1, EL2, and EL3 and the pixel defining layer 151. The common electrode CE is not divided for each of the plurality of pixels and may be disposed on the entire surface of the display area DA in the form of an electrode common to all pixels.

[0123] The common electrode CE may receive a common voltage or a low potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the common electrode CE receives a low potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrode CE, so that the light emitting layers EL1, EL2, and EL3 may emit light.

[0124] The thin film encapsulation layer 170 may be disposed on the common electrode CE to cover the plurality of light emitting elements ED1, ED2, and ED3. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film to prevent oxygen, moisture, or foreign matter such as dust from penetrating into the display element layer 150.

[0125] The thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 sequentially stacked in a third direction (Z-axis direction). The first encapsulation layer 171 and the third encapsulation layer 175 may be inorganic layers, and the second encapsulation layer 173 disposed between the first encapsulation layer 171 and the third encapsulation layer 175 may be an organic layer.

[0126] Each of the first encapsulation layer 171 and the third encapsulation layer 175 may include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. Zinc oxide may be ZnO and / or ZnO 2 .

[0127] The second encapsulation layer 173 may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy resin, a polyimide, a polyethylene, and the like. For example, the second encapsulation layer 173 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer 173 may be formed by curing a monomer or applying a polymer.

[0128] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may include a touch buffer layer 181, a touch insulating layer 183, touch electrodes TE, and a touch protection layer 185.

[0129] The touch buffer layer 181 may be disposed on the thin film encapsulation layer 170. The touch buffer layer 181 may have an insulating function and an optical function. The touch buffer layer 181 may include at least one inorganic film. Optionally, the touch buffer layer 181 may be omitted. Although not shown in the drawings, a connection electrode may be disposed on the touch buffer layer 181. The connection electrode may electrically connect the touch electrodes TE to each other.

[0130] The touch insulating layer 183 may be disposed on the touch buffer layer 181. The touch insulating layer 183 may have an insulating function. For example, the touch insulating layer 183 may include a silicon nitride (SiN) layer, a silicon oxynitride (SiON) layer, a silicon oxide (SiO 2 ) layer, titanium oxide (TiO 2 ) layer and aluminum oxide (Al 2 O 3 ) layer.

[0131] The touch electrode TE may be disposed on the touch insulating layer 183 to overlap the non-emission area NLA. Each of the plurality of touch electrodes TE may not overlap the first to third emission areas EA1, EA2, and EA3.

[0132] The touch electrode TE may include a conductive metal. For example, the touch electrode TE may be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide ("ITO"), or as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0133] The touch protection layer 185 may cover the touch electrode TE and the touch insulating layer 183 . The touch protection layer 185 may have an insulating function and an optical function. The touch protection layer 185 may be made of the materials exemplified in the touch insulating layer 183 .

[0134] Figure 8 yes Figure 7 An enlarged cross-sectional view of area C of FIG.

[0135] refer to Figure 8 , the gate electrode GE of the display device 10 may be positioned on the first insulating layer 113, and may include a lower surface g1, an upper surface g2, a first side surface g3, and a second side surface g4. The lower surface g1 of the gate electrode GE may be a surface in contact with the first insulating layer 113, and the upper surface g2 of the gate electrode GE may be a surface opposite to the lower surface g1. The upper surface g2 and the lower surface g1 of the gate electrode GE may be connected to each other through the first side surface g3 and the second side surface g4. The width of the upper surface g2 of the gate electrode GE may be smaller than the width of the lower surface g1 of the gate electrode GE, and the gate electrode GE may have a trapezoidal shape, but is not limited thereto.

[0136] The first side surface g3 and the second side surface g4 of the gate electrode GE may be inclined surfaces. A first inclination angle θ formed between the lower surface g1 of the gate electrode GE and the first side surface g3 of the gate electrode GE is geIt can be an acute angle. For example, the first inclination angle θ ge The angle may be about 60° or more, and specifically, equal to or greater than about 60° and less than 90°. The thickness W1 of the gate electrode GE in the third direction (Z-axis direction) may be about 0.5 micrometers (μm) or more.

[0137] The gate protection layer 115 may be positioned to contact the upper surface g2 of the gate electrode GE. The gate protection layer 115 may include a lower surface p1 in contact with the gate electrode GE, an upper surface p2, a first side surface p3, and a second side surface p4. The upper surface p2 of the gate protection layer 115 may be a surface opposite to the lower surface p1 of the gate protection layer 115, and the first side surface p3 and the second side surface p4 of the gate protection layer 115 may connect the upper surface p2 and the lower surface p1 of the gate protection layer 115 to each other. In some embodiments, the first side surface g3 of the gate electrode GE and the first side surface p3 of the gate protection layer 115 may extend while being aligned with each other, but are not limited thereto.

[0138] The entirety of the gate protection layer 115 according to the present embodiment may be surrounded by the gate electrode GE, the gate capping layer 117 , and the second insulating layer 119 .

[0139] In some embodiments, a surface of the gate cap layer 117 may be selectively polished using a chemical mechanical polishing (“CMP”) device that performs a chemical mechanical polishing process during the manufacturing process of the display device 10. The gate protection layer 115 may be used to protect the gate electrode GE so that the gate electrode GE is not polished. In addition, the gate protection layer 115 may also be used to protect the gate electrode GE so that the gate electrode GE is not corroded by chemicals included in the CMP device. For example, the chemicals included in the CMP device may include CeO x 、AlO x 、SiO x , zirconium oxide and the like, and may not include H 2 O 2 .

[0140] The gate capping layer 117 may be positioned on opposite side surfaces of the gate electrode GE and opposite side surfaces of the gate protection layer 115. The gate capping layer 117 may prevent defects caused by steps of the gate electrode GE. As described above, the gate electrode GE may have a thickness W1 of about 0.5 μm or more in the third direction (Z-axis direction) and have a first inclination angle θ of about 60° or more. ge Specifically, the first inclination angle θ ge is equal to or greater than about 60° and less than 90°. That is, the gate electrode GE according to the present embodiment may have a structure including a high taper angle.

[0141] Generally, when the second insulating layer 119 is directly disposed on the gate electrode GE without the gate capping layer 117, a portion of the gate electrode GE including a high taper angle may not be covered and may be exposed due to a step coverage feature of the second insulating layer 119. Accordingly, the portion of the gate electrode GE that is not covered by the second insulating layer 119 and is exposed may cause various defects in subsequent photolithography and etching processes.

[0142] The gate cover layer 117 of the display device 10 according to the present embodiment can be positioned between the gate electrode GE and the second insulating layer 119, and can be used to reduce the step of the gate electrode GE covered by the second insulating layer 119. Accordingly, the display according to the embodiment can include a high taper angle of the gate electrode GE and a high thickness in the third direction (Z-axis direction). Accordingly, the display device according to the embodiment can provide high resolution and low resistance lines.

[0143] The gate cover layer 117 may be formed to completely cover the gate electrode GE and the gate protection layer 115 during the manufacturing process, and then a portion of the gate cover layer 117 positioned on the upper surface p2 of the gate protection layer 115 may be completely removed by a subsequent chemical mechanical polishing process. Accordingly, the gate cover layer 117 may be positioned only on the opposite side surfaces of the gate electrode GE and the gate protection layer 115. In other words, a portion of the gate cover layer 117 positioned on the upper surface p2 of the gate protection layer 115 is removed, and therefore, the gate cover layer 117 may reduce the step of the lower structure that the second insulating layer 119 should cover. For this reason, the second insulating layer 119 may cover the entirety of the gate electrode GE and the entirety of the gate cover layer 117. The thickness W2 of the gate cover layer 117 may be equal to or greater than approximately 0.05 μm and equal to or less than approximately 0.25 μm.

[0144] In some embodiments, the chemical mechanical polishing process for removing a portion of the gate cap layer 117 positioned on the upper surface p2 of the gate protection layer 115 may be performed once or may be performed multiple times in a manner that divides and polishes the same thickness applied to the chemical mechanical polishing process performed a small amount at a time.

[0145] like Figure 8 As shown in FIG. 1 , the gate cover layer 117 may include a first portion 117a and a second portion 117b. The first portion 117a of the gate cover layer 117 may be positioned on the first side surface g3 of the gate electrode GE and the first side surface p3 of the gate protection layer 115. The first portion 117a of the gate cover layer 117 may contact and cover the first side surface g3 of the gate electrode GE and the first side surface p3 of the gate protection layer 115.

[0146] The second portion 117b of the gate capping layer 117 may be positioned on the second side surface g4 of the gate electrode GE and the second side surface p4 of the gate protection layer 115. The second portion 117b of the gate capping layer 117 may contact and cover the second side surface g4 of the gate electrode GE and the second side surface p4 of the gate protection layer 115.

[0147] The first portion 117a of the gate capping layer 117 may be disposed to be spaced apart from the second portion 117b of the gate capping layer 117 by the gate electrode GE interposed therebetween. In other words, the first portion 117a and the second portion 117b of the gate capping layer 117 may be disposed to be spaced apart from each other by the gate electrode GE and the gate protection layer 115 interposed therebetween.

[0148] The first portion 117a of the gate cover layer 117 may include a first surface c1 in a direction toward the second insulating layer 119, and the second portion 117b of the gate cover layer 117 may include a second surface c3 in a direction toward the second insulating layer 119. The first surface c1 and the second surface c3 may be formed by removing a portion of the gate cover layer 117 positioned on the upper surface p2 of the gate protection layer 115. The first surface c1 and the second surface c3 of the gate cover layer 117 may be positioned to be spaced apart from each other by the upper surface p2 of the gate protection layer 115 interposed therebetween, and may extend while being aligned with the upper surface p2 of the gate protection layer 115. In other words, the first surface c1 and the second surface c3 of the gate cover layer 117 and the upper surface p2 of the gate protection layer 115 may be positioned on the same line (e.g., parallel to the main surface of the substrate 110 defined by the X-axis direction and the Y-axis direction).

[0149] The entirety of the second insulating layer 119 may cover the gate protection layer 115 and the gate cover layer 117. The second insulating layer 119 may be positioned to contact the gate protection layer 115 and the gate cover layer 117. Specifically, the second insulating layer 119 may be positioned to contact the first surface c1 and the second surface c3 of the gate cover layer 117 and the upper surface p2 of the gate protection layer 115. The second insulating layer 119 may be formed with the same thickness along the contour formed by the gate cover layer 117. That is, the distance (thickness) between the two closest surfaces of the second insulating layer 119 facing each other is the same at each position. The contour included in the second insulating layer 119 may be flattened by the third insulating layer 121.

[0150] Fig. 9 yes Figure 7 Schematic enlarged plan view of area C.

[0151] refer to Fig. 9, the entirety of the gate protection layer 115 may be surrounded by the gate capping layer 117 in a plan view. The first portion 117a and the second portion 117b of the gate capping layer 117 are positioned to be spaced apart from each other in cross section, but may be integrally formed (ie, monolithic) in a plan view.

[0152] Fig.10 and Fig.11 According to other embodiments Figure 7 An enlarged cross-sectional view of area C of FIG.

[0153] refer to Fig.10 and Fig.11 The display device 30 and the display device 50 included in the present embodiment are different from the display device 10 according to the above-described embodiment in that the gate protection layer 115 covers opposite side surfaces of the gate electrode GE.

[0154] The gate electrode GE of each of the display devices 30 and 50 may be positioned on the first insulating layer 113 and may include an upper surface g2, a lower surface g1, a first side surface g3, and a second side surface g4. The gate electrode GE may have a thickness W1 of about 0.5 μm or more in the third direction (Z-axis direction) and a first inclination angle θ of about 60° or more. ge Specifically, the first inclination angle θ ge Equal to or greater than about 60° and less than 90°. Other repetitive descriptions will be omitted.

[0155] The gate protection layer 115 of each of the display devices 30 and 50 may be positioned on the gate electrode GE. The entirety of the gate protection layer 115 of each of the display devices 30 and 50 may cover the gate electrode GE. The gate protection layer 115 of each of the display devices 30 and 50 may cover the gate electrode GE with the same thickness along the contour of the gate electrode GE. That is, the distance (thickness) between the two closest surfaces of the gate protection layer 115 facing each other is the same at each position. Specifically, the gate protection layer 115 may be positioned to contact the first side surface g3, the upper surface g2, and the second side surface g4 of the gate electrode GE.

[0156] In some embodiments, the entirety of the gate electrode GE of each of the display device 30 and the display device 50 may be surrounded by the gate protection layer 115 and the first insulating layer 113 .

[0157] The gate protection layer 115 of each of the display devices 30 and 50 may include a lower surface p1, an upper surface p2, a first side surface p5, and a second side surface p7. The lower surface p1 of the gate protection layer 115 may be positioned to contact the upper surface g2 of the gate electrode GE, and the upper surface p2 of the gate protection layer 115 may be a surface opposite to the lower surface p1. The first side surface p5 of the gate protection layer 115 may be positioned on the first side surface g3 of the gate electrode GE, and the second side surface p7 of the gate protection layer 115 may be positioned on the second side surface g4 of the gate electrode GE.

[0158] refer to Fig.10 , the gate protection layer 115 of the display device 30 may extend while covering the first insulating layer 113 in the portion overlapping with the outside of the gate electrode GE in the third direction. In other words, the gate protection layer 115 of the display device 30 may cover the first insulating layer 113 while extending to the other side in the first direction (X-axis direction) in the portion overlapping with the outside of the gate electrode GE in the third direction. In addition, the gate protection layer 115 of the display device 30 may cover the first insulating layer 113 while extending to one side in the first direction (X-axis direction) in the portion overlapping with the outside of the gate electrode GE in the third direction. In other words, the entirety of the gate electrode GE may be surrounded by the first insulating layer 113 and the gate protection layer 115.

[0159] In some embodiments, the gate cover layer 117 of the display device 30 may include a first portion 117a and a second portion 117b, which are spaced apart from each other by the gate electrode GE interposed therebetween. The first portion 117a of the gate cover layer 117 may be positioned on the first side surface p5 of the gate protection layer 115. The first portion 117a of the gate cover layer 117 may be in contact with the first side surface p5 of the gate protection layer 115. In addition, the first portion 117a of the gate cover layer 117 may extend while covering the gate protection layer 115 in a portion overlapping with the outside of the gate electrode GE in a third direction. In other words, the gate protection layer 115 may be positioned between the first insulating layer 113 and the first portion 117a of the gate cover layer 117 in a portion overlapping with the outside of the gate electrode GE in the third direction, and the first portion 117a of the gate cover layer 117 may be positioned between the gate protection layer 115 and the second insulating layer 119 in a portion overlapping with the outside of the gate electrode GE.

[0160] The second portion 117b of the gate cover layer 117 may be positioned on the second side surface p7 of the gate protection layer 115. The second portion 117b of the gate cover layer 117 may be in contact with the second side surface p7 of the gate protection layer 115. In addition, the second portion 117b of the gate cover layer 117 may extend while covering the gate protection layer 115 in a portion overlapping with the outside of the gate electrode GE in the third direction. In other words, the gate protection layer 115 may be positioned between the first insulating layer 113 and the second portion 117b of the gate cover layer 117 in a portion overlapping with the outside of the gate electrode GE in the third direction, and the second portion 117b of the gate cover layer 117 may be positioned between the gate protection layer 115 and the second insulating layer 119 in a portion overlapping with the outside of the gate electrode GE.

[0161] The first portion 117a of the gate cover layer 117 may include a first surface c1 facing the second insulating layer 119, and the second portion 117b of the gate cover layer 117 may include a second surface c3 facing the second insulating layer 119. The first surface c1 and the second surface c3 of the gate cover layer 117 may be positioned to be spaced apart from each other by the upper surface p2 of the gate protection layer 115 interposed therebetween, and the first surface c1 and the second surface c3 of the gate cover layer 117 and the upper surface p2 of the gate protection layer 115 may be disposed on the same line. Other repetitive descriptions will be omitted.

[0162] The second insulating layer 119 of the display device 30 may be positioned on the gate protection layer 115 and the gate cover layer 117 and may cover the entirety of the gate protection layer 115 and the entirety of the gate cover layer 117. The first surface c1 and the second surface c3 of the gate cover layer 117 may contact the second insulating layer 119.

[0163] In some embodiments, the gate cover layer 117 of the display device 30 may surround the entire gate protection layer 115 of the display device 30 in a plan view. The arrangement relationship between the gate cover layer 117 and the gate protection layer 115 of the display device 30 in a plan view may be similar to Fig. 9 That is, the first portion 117a and the second portion 117b of the gate capping layer 117 are positioned to be spaced apart from each other in cross section, but may be integrally formed (ie, monolithic) in plan view.

[0164] refer to Fig.11, the gate protection layer 115 of the display device 50 may be positioned on the first side surface g3 and the second side surface g4 of the gate electrode GE, and may not cover the upper surface of the first insulating layer 113 in a portion overlapping with the outside of the gate electrode GE in the third direction. Accordingly, the gate protection layer 115 may not be positioned between the first insulating layer 113 and the second insulating layer 119 in a portion overlapping with the outside of the gate electrode GE of the display device 50 in the third direction. In other words, the gate cover layer 117 may be positioned between the first insulating layer 113 and the second insulating layer 119.

[0165] The gate cover layer 117 of the display device 50 may be positioned on the first side surface p5 and the second side surface p7 of the gate protection layer 115. The gate cover layer 117 may include a first portion 117a positioned on the first side surface p5 of the gate protection layer 115 and a second portion 117b positioned on the second side surface p7 of the gate protection layer 115. The first portion 117a and the second portion 117b of the gate cover layer 117 may be positioned to be spaced apart from each other by the gate electrode GE interposed therebetween. In other words, the first portion 117a and the second portion 117b of the gate cover layer 117 may be positioned to be spaced apart from each other by the gate protection layer 115 interposed therebetween.

[0166] The first portion 117a of the gate cover layer 117 may include a first surface c1 facing the second insulating layer 119, and the second portion 117b of the gate cover layer 117 may include a second surface c3 facing the second insulating layer 119. The first surface c1 and the second surface c3 of the gate cover layer 117 may be positioned to be spaced apart from each other by the upper surface p2 of the gate protection layer 115 interposed therebetween, and the first surface c1 and the second surface c3 of the gate cover layer 117 and the upper surface p2 of the gate protection layer 115 may extend on the same line. Other repetitive descriptions will be omitted.

[0167] In some embodiments, the gate cover layer 117 of the display device 50 may surround the entire gate protection layer 115 of the display device 50 in a plan view. The arrangement relationship between the gate cover layer 117 and the gate protection layer 115 of the display device 50 in a plan view may be similar to Fig. 9 That is, the first portion 117a and the second portion 117b of the gate capping layer 117 are positioned to be spaced apart from each other in cross section, but may be integrally formed (ie, monolithic) in plan view.

[0168] Fig.12 According to another embodiment, Figure 5 1 is a cross-sectional view of the display device 10 taken along line X1 - X1 ′. Fig.13 yes Fig.12 An enlarged cross-sectional view of area T.

[0169] refer to Fig.12 and Fig.13 The display device 70 is different from the display device according to the above-described embodiment in that the display device 70 does not include a gate protection layer 115 on the gate electrode GE.

[0170] The gate electrode GE of the display device 70 may be positioned on the first insulating layer 113, and the gate cover layer 117 may be positioned on opposite side surfaces of the gate electrode GE. The second insulating layer 119 may be positioned on the gate electrode GE and the gate cover layer 117, and may cover the entirety of the gate electrode GE and the entirety of the gate cover layer 117. Accordingly, the entirety of the gate electrode GE of the display device 70 may be surrounded by the gate cover layer 117, the first insulating layer 113, and the second insulating layer 119.

[0171] The gate electrode GE of the display device 70 may include an upper surface g2, a lower surface g1, a first side surface g3, and a second side surface g4. In addition, the gate electrode GE may have a thickness W1 of about 0.5 μm or more in the third direction (Z-axis direction) and a first inclination angle θ of about 60° or more. ge Specifically, the first inclination angle θ ge Equal to or greater than about 60° and less than 90°. Other repetitive descriptions will be omitted.

[0172] The gate cover layer 117 of the display device 70 may be positioned on the first side surface g3 and the second side surface g4 of the gate electrode GE. The gate cover layer 117 of the display device 70 may be formed while the gate cover layer 117 of the display device 70 covers the upper surface of the gate electrode GE, and then the portion of the gate cover layer 117 positioned on the upper surface of the gate electrode GE may be completely removed by a chemical mechanical polishing process during the manufacturing process. The thickness W2 of the gate cover layer 117 of the display device 70 may be equal to or greater than about 0.05 μm and equal to or less than about 0.25 μm.

[0173] like Fig.13 As shown in FIG. 1 , the gate cover layer 117 may include a first portion 117a and a second portion 117b, which are spaced apart from each other by the gate electrode GE interposed therebetween. The first portion 117a of the gate cover layer 117 may be positioned on the first side surface g3 of the gate electrode GE. The first portion 117a of the gate cover layer 117 may be in contact with the first side surface g3 of the gate electrode GE. In addition, the first portion 117a of the gate cover layer 117 of the display device 70 may extend while covering the first insulating layer 113 in a portion overlapping with the outside of the gate electrode GE in a third direction. In other words, the first portion 117a of the gate cover layer 117 may be positioned between the first insulating layer 113 and the second insulating layer 119 in a portion overlapping with the outside of the gate electrode GE in the third direction.

[0174] The second portion 117b of the gate cover layer 117 may be positioned on the second side surface g4 of the gate electrode GE. The second portion 117b of the gate cover layer 117 may be in contact with the second side surface g4 of the gate electrode GE. In addition, the second portion 117b of the gate cover layer 117 may extend while covering the first insulating layer 113 in a portion overlapping with the outside of the gate electrode GE in the third direction. In other words, the second portion 117b of the gate cover layer 117 may be positioned between the first insulating layer 113 and the second insulating layer 119 in a portion overlapping with the outside of the gate electrode GE in the third direction.

[0175] The first portion 117a of the gate cover layer 117 according to the present embodiment may include a first surface c1 facing the second insulating layer 119, and the second portion 117b of the gate cover layer 117 may include a second surface c3 facing the second insulating layer 119. The first surface c1 and the second surface c3 of the gate cover layer 117 may be spaced apart from each other by the upper surface g2 of the gate electrode GE interposed therebetween. In addition, the first surface c1 and the second surface c3 of the gate cover layer 117 may be aligned with the upper surface g2 of the gate electrode GE and positioned on the same line as the upper surface g2 of the gate electrode GE.

[0176] The second insulating layer 119 of the display device 70 may be positioned on the gate electrode GE and the gate cover layer 117 and may cover the entirety of the gate electrode GE and the entirety of the gate cover layer 117. The first surface c1 and the second surface c3 of the gate cover layer 117 may contact the second insulating layer 119.

[0177] In some embodiments, the second insulating layer 119 of the display device 70 may cover the gate cover layer 117 along the contour of the gate cover layer 117. Accordingly, the step of the gate electrode GE of the display device 70 may be reduced by the gate cover layer 117. For this reason, even if the gate electrode GE of the display device 70 has a thickness W1 of about 0.5 μm or more in the third direction (Z-axis direction) and has a first inclination angle θ of about 60° or more, ge Specifically, the first inclination angle θ ge The second insulating layer 119 of the display device 70 may also cover the entire gate electrode GE at an angle equal to or greater than about 60° and less than 90°.

[0178] Fig.14 yes Fig.12 Schematic enlarged plan view of a region T of FIG.

[0179] refer to Fig.14, the entirety of the gate electrode GE of the display device 70 may be surrounded by the gate cover layer 117 in a plan view. The first and second portions 117a and 117b of the gate cover layer 117 are positioned to be spaced apart from each other in cross section, but may be integrally formed (ie, monolithic) in a plan view.

[0180] However, the effects of the present disclosure are not limited to the effects described herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device, characterized in that: include: substrate; a thin film transistor positioned on the substrate and comprising a source electrode, a drain electrode, and an active layer positioned between the source electrode and the drain electrode; a gate electrode positioned on the thin film transistor and overlapping the active layer in a plan view; a gate protection layer, the gate protection layer being positioned on the gate electrode and overlapping the active layer in the plan view; an insulating layer, the insulating layer being positioned on the gate protection layer; as well as a gate cover layer positioned between a side surface of the gate electrode and the insulating layer, wherein the gate cover layer comprises a first portion and a second portion, the second portion is separated from the first portion by the gate electrode disposed between the first portion and the second portion, and The first portion and the second portion are in contact with the gate protection layer.

2. The display device according to claim 1, characterized in that The gate protection layer includes a first surface facing the insulating layer, The first portion includes a second surface facing the insulating layer, and The first surface and the second surface are aligned with each other in a direction parallel to a main surface of the substrate.

3. The display device according to claim 2, characterized in that: The second portion includes a third surface facing the insulating layer, and The first surface is positioned between the second surface and the third surface.

4. The display device according to claim 3, characterized in that: The first surface, the second surface, and the third surface are aligned with each other in the direction parallel to the main surface of the substrate.

5. The display device according to claim 4, characterized in that: The first surface, the second surface, and the third surface are in contact with the insulating layer.

6. The display device according to claim 1, characterized in that: The gate cover layer surrounds the entirety of the gate protection layer in the plan view, and Wherein, the first part and the second part are integral in the plan view.

7. The display device according to claim 1, characterized in that The entire gate protection layer is surrounded by the gate electrode, the gate capping layer and the insulating layer.

8. The display device according to claim 1, characterized in that: The gate protection layer covers the side surface of the gate electrode, and The gate protection layer contacts the side surface of the gate electrode.

9. The display device according to claim 8, characterized in that: further comprising a buffer layer positioned between the thin film transistor and the gate electrode, Wherein, the entire gate electrode is surrounded by the buffer layer and the gate protection layer.

10. A display device, characterized in that: include: substrate; a thin film transistor positioned on the substrate and comprising a source electrode, a drain electrode, and an active layer positioned between the source electrode and the drain electrode; a gate electrode positioned on the thin film transistor and overlapping the active layer in a plan view; an insulating layer positioned on the gate electrode; as well as a gate cover layer positioned between a side surface of the gate electrode and the insulating layer, wherein the gate cover layer includes a first portion and a second portion and exposes an upper surface of the gate electrode, and the second portion is spaced apart from the first portion, The first portion includes a first surface facing the insulating layer, and The upper surface of the gate electrode and the first surface of the first portion are aligned with each other in a direction parallel to a main surface of the substrate.

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