Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a plurality of sub-pixels, and each sub-pixel comprises a pixel driving circuit and a light-emitting device. The pixel driving circuit at least comprises a second transistor and a node electrode, the second transistor at least comprises a second active layer, and the node electrode is connected with a second area of the second active layer through a node via hole; the light-emitting device at least comprises a first electrode and a pixel definition layer, the first electrode is connected with the node electrode through the anode via hole, and a pixel opening for exposing the first electrode is formed in the pixel definition layer; in at least one sub-pixel, the orthographic projection of the node via hole on the plane of the display substrate is not overlapped with the orthographic projection of the pixel opening on the plane of the display substrate, and the anode via hole is formed in the side, away from the pixel opening, of the node via hole. According to the invention, poor display such as watermarks is effectively eliminated, and the display quality is improved.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technologies, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, flexibility, and low cost. With the continuous development of display technologies, display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFTs) have become the mainstream products in the current display field.

[0003] Currently, problems such as display Mura exist in OLED display devices. Summary of the Utility Model

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a display device to solve the problems such as display Mura existing in existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, including a plurality of repeating units, at least one repeating unit including a plurality of sub-pixels, and at least one sub-pixel including a pixel driving circuit and a light-emitting device; the pixel driving circuit at least includes a second transistor as a driving transistor and a node electrode, the second transistor at least includes a second active layer, the node electrode is connected to a second region of the second active layer through a node via, and a first region of the second active layer is connected to a first power supply line; the light-emitting device at least includes a first electrode and a pixel definition layer, the first electrode is connected to the node electrode through an anode via, and a pixel opening exposing the first electrode is provided on the pixel definition layer; in at least one sub-pixel, a positive projection of the node via on the display substrate plane does not overlap with a positive projection of the pixel opening on the display substrate plane, and the anode via is provided on a side of the node via away from the pixel opening.

[0007] In an exemplary embodiment, the pixel driving circuit further includes a shielding electrode and a transparent storage capacitor. The storage capacitor includes a first electrode plate and a second electrode plate. The orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the shielding electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer on the display substrate plane. The shielding electrode is connected to the first electrode plate; in at least one sub-pixel, the node electrode is further connected to the shielding electrode through the node via hole.

[0008] In an exemplary embodiment, the node electrode at least includes a first sub-electrode and a second sub-electrode connected to each other. The first sub-electrode is simultaneously connected to the second region of the second active layer and the shielding electrode through the node via hole. The first electrode is connected to the second sub-electrode through an anode via hole. The second sub-electrode is disposed on a side of the first sub-electrode away from the pixel opening.

[0009] In an exemplary embodiment, the orthographic projection of the second sub-electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer on the display substrate plane. The orthographic projection of the anode via hole on the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer on the display substrate plane.

[0010] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening on the display substrate plane. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening on the display substrate plane.

[0011] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate at least includes a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, a semiconductor layer disposed on a side of the first conductive layer away from the substrate, and a second conductive layer disposed on a side of the semiconductor layer away from the substrate. The first electrode plate is disposed in the first transparent conductive layer. The shielding electrode is disposed in the first conductive layer. The second electrode plate and the second active layer are disposed in the semiconductor layer. The node electrode is disposed in the second conductive layer.

[0012] In an exemplary embodiment, the second transistor further includes a second gate electrode. The pixel driving circuit further includes a first connection electrode; in at least one sub-pixel, the first connection electrode is simultaneously connected to the second electrode plate and the second gate electrode through a first transfer via hole.

[0013] In an exemplary embodiment, in at least one sub-pixel, a positive projection of the second gate electrode on the display substrate plane at least partially overlaps with a positive projection of the second electrode plate on the display substrate plane.

[0014] In an exemplary embodiment, in at least one first transfer via hole, a positive projection of the second gate electrode on the display substrate plane at least partially overlaps with a positive projection of the second electrode plate on the display substrate plane.

[0015] In an exemplary embodiment, at least one repeating unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in sequence along a first direction. The first power supply line is in a straight line shape or a broken line shape extending along a second direction, and is respectively disposed in the first sub-pixel and the fourth sub-pixel. The first direction and the second direction intersect. The first power supply line in the first sub-pixel is connected to a first region of the second active layer in the first sub-pixel through a power supply via hole. The first power supply line in the first sub-pixel is connected to a first region of the second active layer in the second sub-pixel through a power supply connection line and a power supply connection electrode. The first power supply line in the fourth sub-pixel is connected to a first region of the second active layer in the third sub-pixel through a power supply connection line and a power supply connection electrode. The first power supply line in the fourth sub-pixel is connected to a first region of the second active layer in the fourth sub-pixel through a power supply via hole.

[0016] In an exemplary embodiment, the pixel driving circuit further includes a shielding electrode. A positive projection of the shielding electrode on the display substrate plane at least partially overlaps with a positive projection of the second active layer on the display substrate plane. In the first sub-pixel and the fourth sub-pixel, a positive projection of the power supply via hole on the display substrate plane does not overlap with a positive projection of the shielding electrode on the display substrate plane.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a shielding electrode. A positive projection of the shielding electrode on the display substrate plane at least partially overlaps with a positive projection of the second active layer on the display substrate plane. In the second sub-pixel and the third sub-pixel, a first end of the power supply connection electrode is connected to a first region of the second active layer through a power supply via hole. A second end of the power supply connection electrode is connected to the first power supply line through the power supply connection line. A positive projection of the power supply via hole on the display substrate plane at least partially overlaps with a positive projection of the shielding electrode on the display substrate plane.

[0018] In an exemplary embodiment, at least one sub-pixel further includes a data signal line connected to the pixel driving circuit. The shape of the data signal line is a broken line extending along the second direction, and includes at least a straight first sub-line and a second sub-line, and an oblique third sub-line. The third sub-line is disposed between the first sub-line and the second sub-line, and both ends of the third sub-line are respectively connected to the first sub-line and the second sub-line. In at least one sub-pixel of the first sub-pixel and the fourth sub-pixel, there is a first distance between the first sub-line and the first power supply line, and a second distance between the second sub-line and the first power supply line. The first distance is greater than the second distance, and the first distance and the second distance are dimensions in the first direction.

[0019] In an exemplary embodiment, at least one sub-pixel further includes a compensation signal line connected to the pixel driving circuit. The compensation signal line is disposed between the second sub-pixel and the third sub-pixel. In at least one sub-pixel of the second sub-pixel and the third sub-pixel, there is a third distance between the first sub-line and the compensation signal line, and a fourth distance between the second sub-line and the compensation signal line. The third distance is less than the fourth distance, and the third distance and the fourth distance are dimensions in the first direction.

[0020] In an exemplary embodiment, the orthographic projection of the compensation signal line on the display substrate plane does not overlap with the orthographic projection of the power supply connection line on the display substrate plane.

[0021] In an exemplary embodiment, the pixel driving circuit further includes a first transistor serving as a data writing transistor and a third transistor serving as a compensation transistor. In at least one sub-pixel, the gate electrodes of the first transistor and the third transistor are connected to the same scanning signal line.

[0022] In an exemplary embodiment, in at least one repeating unit, the gate electrodes of multiple first transistors and the gate electrodes of multiple third transistors are connected to the same scanning signal line.

[0023] In an exemplary embodiment, in at least one repeating unit, at least one via hole is provided on the scanning signal line, and the orthographic projection of the via hole on the display substrate plane at least partially overlaps with the orthographic projection of the first power supply line on the display substrate plane.

[0024] On the other hand, the present disclosure also provides a display device including the foregoing display substrate.

[0025] The embodiments of the present disclosure provide a display substrate and a display device. By disposing the anode via hole away from the pixel opening, light leakage is effectively reduced, display defects such as watermarks are effectively eliminated, and the display quality and display performance are improved.

[0026] Other aspects will be apparent upon reading the accompanying drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are provided to further understand the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure.

[0028] Figure 1 is a schematic structural diagram of a display device;

[0029] Figure 2 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure;

[0030] Figure 3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure;

[0031] Figure 4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 5 is Figure 4 a cross-sectional view taken along the line A-A in

[0033] Figure 6 is a schematic diagram after forming a first transparent conductive layer pattern according to an embodiment of the present disclosure;

[0034] Figure 7A and Figure 7B is a schematic diagram after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0035] Figure 8A and Figure 8B is a schematic diagram after forming a semiconductor layer pattern according to an embodiment of the present disclosure;

[0036] Figure 9A and Figure 9B is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0037] Figure 10 is a schematic diagram after forming a third insulating layer pattern according to an embodiment of the present disclosure;

[0038] Figure 11A and Figure 11B is a schematic diagram after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0039] Figure 12Schematic diagram after forming the pattern of the fourth insulating layer and the planarization layer in an embodiment of the present disclosure;

[0040] Figure 13 Schematic diagram after forming the pattern of the second transparent conductive layer in an embodiment of the present disclosure;

[0041] Figure 14 Schematic diagram after forming the pattern of the pixel definition layer in an embodiment of the present disclosure.

[0042] Description of reference numerals:

[0043] 11 - First electrode plate; 12 - Connection plate; 13 - Connection wire;

[0044] 21 - Power supply connection wire; 22 - Compensation connection wire; 22-1 - Compensation connection block;

[0045] 23 - Shielding electrode; 24 - Interlayer connection electrode; 31 - First active layer;

[0046] 32 - Second active layer; 33 - Third active layer; 34 - Second electrode plate;

[0047] 42 - Second gate electrode; 50 - Scanning signal line; 51 - First connection electrode;

[0048] 52 - Second connection electrode; 52-1 - First sub - electrode; 52-2 - Second sub - electrode;

[0049] 53 - Third connection electrode; 54 - Fourth connection electrode; 55 - Fifth connection electrode;

[0050] 56 - Power supply connection electrode; 60 - First power supply line; 70 - Data signal line;

[0051] 70-1 - First sub - line; 70-2 - Second sub - line; 70-3 - Third sub - line;

[0052] 80 - Compensation signal line; 90 - First electrode; 90A - Pixel opening;

[0053] 100 - Repeating unit; 200 - Substrate; 201 - First insulating layer;

[0054] 202 - Second insulating layer; 203 - Third insulating layer; 204 - Fourth insulating layer;

[0055] 205 - Planarization layer; 206 - Pixel definition layer; DV - Power via; JV - Node via; ZV - First transfer via; YV - Anode via. Detailed implementation manners

[0056] To make the objectives, technical solutions, and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. The embodiments and the features in the embodiments in the present disclosure can be combined arbitrarily with each other without conflict.

[0057] The drawing ratios in the present disclosure can be used as a reference in actual processes, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are only schematic diagrams of the structure, and one implementation manner of the present disclosure is not limited to the shapes, values, etc. shown in the drawings.

[0058] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit in terms of quantity.

[0059] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationships of the components are appropriately changed according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0060] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0061] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current mainly flows.

[0062] In this specification, the first pole may be the drain electrode and the second pole may be the source electrode, or the first pole may be the source electrode and the second pole may be the drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes switch with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be switched with each other, and the "source terminal" and "drain terminal" can be switched with each other.

[0063] In this specification, "electrically connected" includes cases where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0064] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0065] In this specification, "film" and "layer" can be switched with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0066] In this specification, triangles, rectangles, trapezoids, pentagons, hexagons, etc. are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There may be some small deformations due to tolerances, and there may be chamfers, rounded edges, and deformations, etc.

[0067] "About" in this disclosure means not strictly defining the boundary and allowing values within the range of process and measurement errors.

[0068] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each pixel sub-PXij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may at least include a circuit unit and a display unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may at least include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. The sub-pixel PXij may refer to the sub-pixel in which the pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines 531, D2, D3,..., and Dn. For example, the data driver may sample the gray value using the clock signal and apply the data voltage corresponding to the gray value to the data signal lines 531 to Dn in units of pixel rows. n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having a conductive level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal. m may be a natural number. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0069] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of sub-pixels, wherein at least one sub-pixel comprises a pixel driving circuit and a light-emitting device; the pixel driving circuit comprises at least a second transistor as a driving transistor and a node electrode, the second transistor comprises at least a second active layer, the node electrode is connected to a second region of the second active layer through a node via, and a first region of the second active layer is connected to a first power line; the light-emitting device comprises at least a first electrode and a pixel definition layer, the first electrode is connected to the node electrode through an anode via, and a pixel opening exposing the first electrode is provided on the pixel definition layer; in at least one sub-pixel, an orthographic projection of the node via on a plane of the display substrate does not overlap with an orthographic projection of the pixel opening on a plane of the display substrate, and the anode via is provided on a side of the node via away from the pixel opening.

[0070] In an exemplary embodiment, the pixel driving circuit also includes a blocking electrode and a transparent storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane, the orthographic projection of the blocking electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer on the display substrate plane, and the blocking electrode is connected to the first electrode plate; in at least one sub-pixel, the node electrode is also connected to the blocking electrode through the node via.

[0071] In an exemplary embodiment, the second transistor further includes a second gate electrode, and the pixel driving circuit further includes a first connecting electrode; in at least one sub-pixel, the first connecting electrode is simultaneously connected to the second electrode plate and the second gate electrode through a first transfer via.

[0072] In an exemplary embodiment, in at least one sub-pixel, an orthographic projection of the second gate electrode on the plane of the display substrate at least partially overlaps with an orthographic projection of the second electrode plate on the plane of the display substrate.

[0073] In an exemplary embodiment, in at least one first transfer via, an orthographic projection of the second gate electrode on the display substrate plane at least partially overlaps with an orthographic projection of the second electrode plate on the display substrate plane.

[0074] In an exemplary embodiment, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel sequentially arranged along a first direction. The first power line is in a straight or broken line shape extending along a second direction, and is respectively disposed in the first sub-pixel and the fourth sub-pixel. The first direction and the second direction intersect; the first power line in the first sub-pixel is connected to a first region of the second active layer in the first sub-pixel through a power via, the first power line in the first sub-pixel is connected to a first region of the second active layer in the second sub-pixel through a power connection line and a power connection electrode, the first power line in the fourth sub-pixel is connected to a first region of the second active layer in the third sub-pixel through a power connection line and a power connection electrode, and the first power line in the fourth sub-pixel is connected to a first region of the second active layer in the fourth sub-pixel through a power via.

[0075] In an exemplary embodiment, at least one sub-pixel further includes a data signal line connected to the pixel driving circuit. The data signal line is in a broken line shape extending along the second direction, and at least includes a straight first sub-line and a second sub-line, and an oblique third sub-line. The third sub-line is disposed between the first sub-line and the second sub-line, and both ends of the third sub-line are respectively connected to the first sub-line and the second sub-line; in at least one of the first sub-pixel and the fourth sub-pixel, there is a first distance between the first sub-line and the first power line, and a second distance between the second sub-line and the first power line. The first distance is greater than the second distance, and the first distance and the second distance are dimensions in the first direction.

[0076] In an exemplary embodiment, at least one sub-pixel further includes a compensation signal line connected to the pixel driving circuit. The compensation signal line is disposed between the second sub-pixel and the third sub-pixel; in at least one of the second sub-pixel and the third sub-pixel, there is a third distance between the first sub-line and the compensation signal line, and a fourth distance between the second sub-line and the compensation signal line. The third distance is less than the fourth distance, and the third distance and the fourth distance are dimensions in the first direction.

[0077] The following illustrates the display substrate of the present disclosure through some exemplary embodiments.

[0078] Figure 2 It is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure. As Figure 2As shown, in an exemplary embodiment, in a direction parallel to the display substrate, the display substrate may include a plurality of repeating units 100, and at least one repeating unit 100 may include a plurality of sub-pixels. In an exemplary embodiment, the repeating unit is a basic unit that composes the display substrate, and the display substrate is formed by continuously arranging the repeating units repeatedly and along at least one direction, that is, the display substrate is formed by splicing a plurality of repeating units.

[0079] In an exemplary embodiment, one repeating unit 100 may include four sub-pixels. The four sub-pixels may include a first sub-pixel P1 that emits first-color light, a second sub-pixel P2 that emits second-color light, a third sub-pixel P3 that emits third-color light, and a fourth sub-pixel P4 that emits fourth-color light. The four sub-pixels may be arranged in a horizontal side-by-side manner, which can effectively increase the aperture ratio.

[0080] In an exemplary embodiment, in at least one repeating unit 100, the second sub-pixel P2 may be disposed on one side of the first sub-pixel P1 in the first direction X, the third sub-pixel P3 may be disposed on one side of the second sub-pixel P2 in the first direction X, and the fourth sub-pixel P4 may be disposed on one side of the third sub-pixel P3 in the first direction X. In an exemplary embodiment, a plurality of sub-pixels arranged in sequence along the first direction X may be referred to as a pixel row, and a plurality of sub-pixels arranged in sequence along the second direction Y may be referred to as a pixel column. A plurality of pixel rows and a plurality of pixel columns form a pixel array arranged in an array, and the first direction X intersects with the second direction Y.

[0081] In an exemplary embodiment, the first direction X may be a horizontal direction, the second direction Y may be a vertical direction, and the first direction X and the second direction Y are perpendicular to each other.

[0082] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a white sub-pixel (W) that emits white light, the third sub-pixel P3 may be a blue sub-pixel (B) that emits blue light, and the fourth sub-pixel P4 may be a green sub-pixel (G) that emits green light. In some possible implementation manners, the arrangement manner of RWBG may be adjusted according to actual needs, and the present disclosure does not make specific limitations herein.

[0083] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may at least include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate. In at least one repeating unit, the driving circuit layer may include a plurality of circuit units, and the circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to a scanning signal line and a data signal line, etc. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and output a corresponding current to the light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, and the light-emitting unit may at least include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit of the corresponding sub-pixel, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the corresponding sub-pixel.

[0084] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may at least include a driving circuit layer disposed on a substrate, a color filter structure layer disposed on a side of the driving circuit layer away from the substrate, and a light-emitting structure layer disposed on a side of the color filter structure layer away from the substrate. In at least one repeating unit, the color filter structure layer may include a plurality of color filter units, and the color filter unit may at least include a color filter layer. The color filter layer is configured to allow the corresponding sub-pixel to emit light of a required color.

[0085] In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to a region divided according to the pixel driving circuit. The color filter unit referred to in the present disclosure refers to a region divided according to the color filter layer. The light-emitting unit referred to in the present disclosure refers to a region divided according to the light-emitting device. The positions of the orthographic projection of the circuit unit on the substrate, the orthographic projection of the color filter layer on the substrate, and the orthographic projection of the light-emitting unit on the substrate may be corresponding, or may not be corresponding.

[0086] In an exemplary embodiment of the present disclosure, the positions of the orthographic projection of the circuit unit on the substrate, the orthographic projection of the color filter unit on the substrate, and the orthographic projection of the light-emitting unit on the substrate are substantially corresponding. The circuit unit, the color filter unit, and the light-emitting unit form a sub-pixel. In the following content, the sub-pixel is uniformly used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0087] Figure 3 Equivalent circuit diagram of the pixel driving circuit in one repeating unit of an exemplary embodiment of the present disclosure. As Figure 3 shown, at least one repeating unit may include 4 pixel driving circuits. The 4 pixel driving circuits may be arranged in a horizontal side-by-side manner, and the pixel driving circuit may be of a 3T1C structure.

[0088] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and one storage capacitor C. The pixel driving circuit is respectively connected to a scan signal line 50, a first power supply line 60, a data signal line 70, and a compensation signal line 80.

[0089] In an exemplary embodiment, at least one pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is respectively connected to a second pole of the first transistor T1, a gate electrode of the second transistor T2, and a first end of the storage capacitor C. The second node N2 is respectively connected to a second pole of the second transistor T2, a second pole of the third transistor T3, and a second end of the storage capacitor C.

[0090] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the second node N2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0091] In an exemplary embodiment, the first transistor T1 may be referred to as a data writing transistor, the second transistor T2 may be referred to as a driving transistor, and the third transistor T3 may be referred to as a compensation transistor.

[0092] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the scan signal line 50, the first pole of the first transistor T1 is connected to the data signal line 70, and the second pole of the first transistor T1 is connected to the first node N1. The gate electrode of the second transistor T2 is connected to the first node N1, the first pole of the second transistor T2 is connected to the first power supply line 60, and the second pole of the second transistor T2 is connected to the second node N2. The gate electrode of the third transistor T3 is connected to the scan signal line 50, the first pole of the third transistor T3 is connected to the compensation signal line 80, and the second pole of the third transistor T3 is connected to the second node N2.

[0093] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrodes of the first transistor T1 and the third transistor T3 are connected to the same scan signal line 50.

[0094] In an exemplary embodiment, in the pixel driving circuits of at least one repeating unit, the gate electrodes of multiple first transistors T1 are connected to the same scan signal line 50.

[0095] In an exemplary embodiment, in the pixel driving circuits of at least one repeating unit, the gate electrodes of multiple third transistors T3 are connected to the same scan signal line 50.

[0096] In an exemplary embodiment, in a plurality of pixel driving circuits of at least one repeating unit, gate electrodes of a plurality of first transistors T1 and gate electrodes of a plurality of third transistors T3 are connected to the same scanning signal line 50.

[0097] In an exemplary embodiment, in a plurality of pixel driving circuits of at least one pixel row, gate electrodes of a plurality of first transistors T1 and gate electrodes of a plurality of third transistors T3 are connected to the same scanning signal line 50.

[0098] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or may be a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power supply line VSS. In an exemplary embodiment, the first electrode may be an anode and the second electrode may be a cathode; or, the first electrode may be a cathode and the second electrode may be an anode.

[0099] In an exemplary embodiment, the signal of the first power supply line 60 is a continuously provided high-level signal, and the signal of the second power supply line VSS is a continuously provided low-level signal.

[0100] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the third transistor T3 may include P-type transistors and N-type transistors.

[0101] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may adopt low-temperature poly-silicon thin-film transistors, or may adopt oxide thin-film transistors, or may adopt low-temperature poly-silicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature poly-silicon thin-film transistor adopts low-temperature poly-silicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor adopts an oxide semiconductor (Oxide). The low-temperature poly-silicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature poly-silicon thin-film transistor and the oxide thin-film transistor on one display substrate, that is, an LTPS+Oxide (abbreviated as LTPO) display substrate, can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve the display quality.

[0102] Figure 4This is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, showing the structure of a repeating unit (four sub-pixels) in a bottom-emission display substrate. Figure 5 is Figure 4 a cross-sectional view taken along line A-A in Figure 4 and Figure 5 As shown in

[0103] In an exemplary embodiment, at least one repeating unit may include a scan signal line 50, two first power supply lines 60, four data signal lines 70, and a compensation signal line 80. All of the above signal lines are connected to the pixel driving circuits in the four sub-pixels.

[0104] In an exemplary embodiment, multiple scan signal lines 50 in the display substrate may be arranged along the second direction Y, and at least one scan signal line 50 may extend along the first direction X. In at least one repeating unit, the shape of the scan signal line 50 may be a straight line or a broken line extending along the first direction X, and the shapes of the first power supply line 60, the data signal line 70, and the compensation signal line 80 may be straight lines or broken lines extending along the second direction Y. The two first power supply lines 60 may be respectively disposed on both sides of the repeating unit in the first direction X. The four data signal lines 70 and a compensation signal line 80 may be disposed between the two first power supply lines 60. Two of the four data signal lines 70 may be located between the compensation signal line 80 and one of the first power supply lines 60, and the other two of the four data signal lines 70 may be located between the compensation signal line 80 and the other first power supply line 60.

[0105] In an exemplary embodiment, a first sub-pixel P1 is formed between a first power supply line 60 and a data signal line 70 adjacent to the first direction X, a second sub-pixel P2 is formed between a compensation signal line 80 and a data signal line 70 adjacent to the opposite direction of the first direction X, a third sub-pixel P3 is formed between the compensation signal line 80 and a data signal line 70 adjacent to the first direction X, and a fourth sub-pixel P4 is formed between the other first power supply line 60 and a data signal line 70 adjacent to the opposite direction of the first direction X. That is, the two first power supply lines 60 are respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4, the compensation signal line 80 is disposed between the second sub-pixel P2 and the third sub-pixel P3, and the four data signal lines 70 are respectively disposed in the first sub-pixel P1 to the fourth sub-pixel P4.

[0106] In an exemplary embodiment, the pixel driving circuit of at least one sub-pixel may include a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, a third transistor T3 as a compensation transistor, and a transparent storage capacitor. The first transistor T1, the second transistor T2, and the third transistor T3 may each include an active layer, a gate electrode, a first pole, and a second pole, and the storage capacitor may include a transparent first electrode plate 11 and a transparent second electrode plate 34.

[0107] In an exemplary embodiment, in at least one sub-pixel, the gate electrodes of the first transistor T1 and the third transistor T3 are connected to the scan signal line 50, the first pole of the first transistor T2 is connected to the data signal line 70, the second pole of the first transistor T1 is respectively connected to the gate electrode of the second transistor T2 and the second electrode plate 34, the first pole of the second transistor T2 is connected to the first power supply line 60, the second pole of the second transistor T2 is respectively connected to the first pole of the third transistor T3 and the first electrode plate 11, and the first pole of the third transistor T3 is connected to the compensation signal line 80.

[0108] In an exemplary embodiment, at least one repeating unit may further include two power connection lines 21 extending along the first direction X and two power connection electrodes 56 extending along the second direction Y. One power connection line 21 may straddle the first sub-pixel P1 and the second sub-pixel P2, the other power connection line 21 may straddle the third sub-pixel P3 and the fourth sub-pixel P4, one power connection electrode 56 may be disposed in the second sub-pixel P2, and the other power connection electrode 56 may be disposed in the third sub-pixel P3.

[0109] In an exemplary embodiment, the second transistor T2 may at least include a second active layer 32 and a second gate electrode 42. The first power line 60 in the first sub-pixel P1 may be connected to the first region of the second active layer through a power via DV, and at the same time, connected to the first end of the power connection line 21 through a via. The first end of the power connection electrode 56 in the second sub-pixel P2 may be connected to the first region of the second active layer through a power via DV, and the second end of the power connection electrode 56 may be connected to the second end of the power connection line 21 through a via, that is, the first power line 60 in the first sub-pixel P1 is connected to the first region of the second active layer in the second sub-pixel P2 through the power connection line 21 and the power connection electrode 56. The first power line 60 in the fourth sub-pixel P4 may be connected to the first region of the second active layer through a power via DV, and at the same time, connected to the first end of the power connection line 21 through a via. The first end of the power connection electrode 56 in the third sub-pixel P3 is connected to the first region of the second active layer through a power via DV, and the second end of the power connection electrode 56 is connected to the second end of the power connection line 21 through a via, that is, the first power line 60 in the fourth sub-pixel P4 is connected to the first region of the second active layer in the third sub-pixel P3 through the power connection line 21 and the power connection electrode 56. In this way, the first power line 60 in the first sub-pixel P1 can provide a power signal to the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2, and the first power line 60 in the fourth sub-pixel P4 can provide a power signal to the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4, forming a one-driving-two structure of the first power line.

[0110] In an exemplary embodiment, at least one repeating unit may further include two compensation connection lines 22 extending along the first direction X. One compensation connection line 22 may straddle the first sub-pixel P1 and the second sub-pixel P2. On the one hand, this compensation connection line 22 is connected to the compensation signal line 80 through a compensation connection block 22-1, and on the other hand, is respectively connected to the first pole of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2. The other compensation connection line 22 may straddle the third sub-pixel P3 and the fourth sub-pixel P4. On the one hand, this compensation connection line 22 is connected to the compensation signal line 80 through a compensation connection block 22-1, and on the other hand, is respectively connected to the first pole of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4. In this way, one compensation signal line 80 can provide a compensation signal to the pixel driving circuits of the four sub-pixels, forming a one-driving-four structure of the compensation signal line.

[0111] In an exemplary embodiment, at least one sub-pixel may further include a shielding electrode 23. The orthographic projection of the shielding electrode 23 on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer 32 on the display substrate plane, and is connected to the first electrode plate 11 of the storage capacitor.

[0112] In an exemplary embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the positive projection of the power via DV on the display substrate plane does not overlap with the positive projection of the shielding electrode 23 on the display substrate plane.

[0113] In an exemplary embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the positive projection of the power via DV on the display substrate plane at least partially overlaps with the positive projection of the shielding electrode 23 on the display substrate plane.

[0114] In an exemplary embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the positive projection of the power via DV on the display substrate plane may be located within the range of the positive projection of the shielding electrode 23 on the display substrate plane.

[0115] In an exemplary embodiment, at least one sub-pixel may further include a first connection electrode 51, and the first connection electrode 51 may be connected to the second electrode plate 34 and the second gate electrode 42 simultaneously through the same first transfer via ZV.

[0116] In an exemplary embodiment, in at least one sub-pixel, the positive projection of the second gate electrode 42 on the display substrate plane at least partially overlaps with the positive projection of the second electrode plate 34 on the display substrate plane.

[0117] In an exemplary embodiment, in the first transfer via ZV, the positive projection of the second gate electrode 42 on the display substrate plane at least partially overlaps with the positive projection of the second electrode plate 34 on the display substrate plane.

[0118] In an exemplary embodiment, at least one sub-pixel may further include a second connection electrode 52 as a node electrode, and the second connection electrode 52 may be connected to the second region of the second active layer and the shielding electrode 23 simultaneously through the same node via JV.

[0119] In an exemplary embodiment, the light-emitting device of at least one sub-pixel may at least include a first electrode 90 and a pixel defining layer. The first electrode 90 may be connected to the second connection electrode 52 through an anode via YV. A pixel opening 90A may be provided on the pixel defining layer, and the pixel opening 90A exposes the surface of the first electrode 90.

[0120] In an exemplary embodiment, in at least one sub-pixel, the node via JV may be located on one side of the pixel opening 90A in the second direction Y, and the positive projection of the node via JV on the display substrate plane does not overlap with the positive projection of the pixel opening 90A on the display substrate plane.

[0121] In an exemplary embodiment, in at least one sub-pixel, the anode via YV may be located on one side of the node via JV in the second direction Y, that is, the anode via YV may be located on the side of the node via JV away from the pixel opening 90A.

[0122] In an exemplary embodiment, in at least one sub-pixel, the second connection electrode 52 may include at least a first sub-electrode 52-1 and a second sub-electrode 52-2 that are connected to each other. The second sub-electrode 52-2 may be located on a side of the first sub-electrode 52-1 away from the pixel opening 90A. The first sub-electrode 52-1 may be connected to the second region of the second active layer and the shielding electrode 23 through a node via JV, and the first electrode 90 may be connected to the second sub-electrode 52-2 through an anode via YV.

[0123] In an exemplary embodiment, in at least one sub-pixel, a positive projection of the second sub-electrode 52-2 on the display substrate plane and a positive projection of the second region of the second active layer on the display substrate plane at least partially overlap.

[0124] In an exemplary embodiment, in at least one sub-pixel, a positive projection of the anode via YV on the display substrate plane and a positive projection of the second region of the second active layer on the display substrate plane at least partially overlap.

[0125] In an exemplary embodiment, in at least one sub-pixel, a positive projection of the transparent storage capacitor on the display substrate plane and a positive projection of the pixel opening 90A on the display substrate plane at least partially overlap, that is, a positive projection of the first electrode plate 11 on the display substrate plane and a positive projection of the pixel opening 90A on the display substrate plane at least partially overlap, and a positive projection of the second electrode plate 34 on the display substrate plane and a positive projection of the pixel opening 90A on the display substrate plane at least partially overlap.

[0126] In an exemplary embodiment, in at least one sub-pixel, the data signal line 70 may include a first sub-line 70-1, a second sub-line 70-2, and a third sub-line 70-3. The first sub-line 70-1 and the second sub-line 70-2 are in a straight line shape extending along the second direction Y, and the third sub-line 70-3 is in a straight line shape or a broken line shape extending along an inclined direction. The third sub-line 70-3 may be disposed between the first sub-line 70-1 and the second sub-line 70-2, and both ends of the third sub-line 70-3 are respectively connected to the first sub-line 70-1 and the second sub-line 70-2.

[0127] In an exemplary embodiment, in at least one sub-pixel of the first sub-pixel P1 and the fourth sub-pixel P4, there may be a first distance L1 between the first sub-line 70-1 and the first power supply line 60, and there may be a second distance L2 between the second sub-line 70-2 and the first power supply line 60. The first distance L1 may be greater than the second distance L2, and the first distance L1 and the second distance L2 may be dimensions in the first direction X.

[0128] In an exemplary embodiment, in at least one of the second sub-pixel P2 and the third sub-pixel P3, a third distance L3 may exist between the first sub-line 70-1 and the compensation signal line 80, and a fourth distance L4 may exist between the second sub-line 70-2 and the compensation signal line 80. The third distance L3 may be smaller than the fourth distance L4, and the third distance L3 and the fourth distance L4 may be dimensions in the first direction X.

[0129] In an exemplary embodiment, in at least one repeating unit, the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2 and the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4 may be disposed substantially symmetrically with respect to the center line of the repeating unit. The center line of the repeating unit is a broken line that bisects the repeating unit in the first direction X and extends along the second direction Y.

[0130] In an exemplary embodiment, in at least one repeating unit, the data signal lines 70 in the first sub-pixel P1 and the second sub-pixel P2 and the data signal lines 70 in the third sub-pixel P3 and the fourth sub-pixel P4 may be disposed substantially symmetrically with respect to the center line of the repeating unit. The positions and shapes of the two first power supply lines 60 may be disposed substantially symmetrically with respect to the center line of the repeating unit. The orthographic projection of the compensation signal line 80 on the display substrate plane and the orthographic projection of the center line of the repeating unit on the display substrate plane at least partially overlap.

[0131] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may at least include: a first transparent conductive layer disposed on the substrate 200, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate 200, a first insulating layer 201 disposed on a side of the first conductive layer away from the substrate 200, a semiconductor layer disposed on a side of the first insulating layer 201 away from the substrate 200, a second insulating layer 202 disposed on a side of the semiconductor layer away from the substrate 200, a second conductive layer disposed on a side of the second insulating layer 202 away from the substrate 200, a third insulating layer 203 disposed on a side of the second conductive layer away from the substrate 200, a third conductive layer disposed on a side of the third insulating layer 203 away from the substrate 200, a fourth insulating layer 204 disposed on a side of the third conductive layer away from the substrate 200, a planarizing layer 205 disposed on a side of the fourth insulating layer 204 away from the substrate 200, a second transparent conductive layer disposed on a side of the planarizing layer 205 away from the substrate 200, and a pixel defining layer 206 disposed on a side of the second transparent conductive layer away from the substrate 200.

[0132] In an exemplary embodiment, the first transparent conductive layer may at least include a first electrode plate 11, the first conductive layer may at least include a power connection line 21, a compensation connection line 22, a shielding electrode 23, and an interlayer connection electrode 24, the semiconductor layer may at least include a second active layer 32, a third active layer 33, and a second electrode plate 34, the second conductive layer may at least include a second gate electrode 42 and a scanning signal line 50, the third conductive layer may at least include a first connection electrode 51, a second connection electrode 52, a fourth connection electrode 54, and a fifth connection electrode 55, the second transparent conductive layer may at least include a first electrode 90, and the pixel definition layer may at least include a pixel opening 90A.

[0133] An exemplary description will be given below through the manufacturing process of the display substrate. The "patterning process" as referred to in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, stripping the photoresist, etc. For organic materials, it includes coating the organic materials, mask exposure, and development, etc. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out by any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out by any one of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed in the same layer" as referred to in the present disclosure means that A and B are simultaneously formed by the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0134] In an exemplary embodiment, taking an example that one repeating unit includes four sub-pixels (a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4), the manufacturing process of the display substrate in the exemplary embodiment of the present disclosure may include the following operations.

[0135] (1) Form a first transparent conductive layer pattern. In an exemplary embodiment, forming the first transparent conductive layer pattern may include: depositing a first transparent conductive thin film on a substrate, patterning the first transparent conductive thin film through a patterning process, and forming a first transparent conductive layer pattern on the substrate, such as Figure 6As shown. In an exemplary embodiment, the first transparent conductive layer may be referred to as the ITO1 layer.

[0136] In an exemplary embodiment, the first transparent conductive layer pattern of each sub-pixel in the repeating unit may at least include a first electrode plate 11 of a storage capacitor, a connection plate 12, and a connection line 13.

[0137] In an exemplary embodiment, the shape of the first electrode plate 11 may be rectangular, chamfers or grooves may be provided at the corners of the rectangular shape, the edges of the rectangular shape may be straight lines or broken lines, the first electrode plate 11 may be disposed in the middle region of the second direction Y of the sub-pixel, and the first electrode plate 11 is configured to form a transparent electrode plate of a transparent storage capacitor.

[0138] In an exemplary embodiment, the shape of the connection plate 12 may be block-shaped (such as rectangular), the connection plate 12 may be disposed on one side of the first electrode plate 11 in the second direction Y and connected to the first electrode plate 11, and the connection plate 12 is configured to be connected to a shielding electrode formed subsequently.

[0139] In an exemplary embodiment, the shape of the connection line 13 may be strip-shaped extending along the second direction Y, the connection line 13 may be disposed on the side of the first electrode plate 11 away from the connection plate 12 and connected to the first electrode plate 11. A connection block 13-1 may be provided at the end of the connection line 13 away from the first electrode plate 11, the shape of the connection block 13-1 may be strip-shaped extending along the first direction X and connected to the connection line 13, and the connection block 13-1 is configured to be connected to an interlayer connection electrode formed subsequently.

[0140] In an exemplary embodiment, the first electrode plate 11, the connection plate 12, and the connection line 13 of each sub-pixel may be an integrally connected structure.

[0141] In an exemplary embodiment, the first transparent conductive layers in the first sub-pixel P1 and the second sub-pixel P2 may be disposed substantially symmetrically with respect to the center line of the repeating unit as compared with the first transparent conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4. For example, the positions and shapes of the first electrode plate 11, the connection plate 12, and the connection line 13 in the first sub-pixel P1 and the fourth sub-pixel P4 may be disposed substantially symmetrically with respect to the center line of the repeating unit. Another example is that the positions and shapes of the first electrode plate 11, the connection plate 12, and the connection line 13 in the second sub-pixel P2 and the third sub-pixel P3 may be disposed substantially symmetrically with respect to the center line of the repeating unit.

[0142] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on the substrate on which the foregoing pattern is formed, patterning the first conductive thin film through a patterning process, and forming a first conductive layer pattern on the first transparent conductive layer, such as Figure 7A andFigure 7B as shown Figure 7B is Figure 7A a plan view of the first conductive layer in

[0143] In an exemplary embodiment, the first conductive layer pattern of each sub-pixel in the repeating unit may at least include a shielding electrode 23 and an interlayer connection electrode 24.

[0144] In an exemplary embodiment, the shape of the shielding electrode 23 may be rectangular, chamfers or grooves may be provided at the corners of the rectangular shape, the edges of the rectangular shape may be straight lines or broken lines, the shielding electrode 23 may be provided in the middle region of the second direction Y of the sub-pixel, the orthographic projection of the shielding electrode 23 on the substrate at least partially overlaps with the orthographic projection of the connection plate 12 on the substrate, and the shielding electrode 23 is directly lapped with the connection plate 12. In an exemplary embodiment, the shielding electrode 23 is configured to provide shielding for the second transistor T2 to prevent light from affecting the channel region of the second transistor T2, reduce leakage current, thereby avoiding the influence of light on the characteristics of the second transistor T2, and ensuring the electrical performance of the second transistor T2.

[0145] In an exemplary embodiment, the orthographic projection of the shielding electrode 23 on the substrate may be within the range of the orthographic projection of the connection plate 12 on the substrate, or the orthographic projection of the shielding electrode 23 on the substrate may include the orthographic projection of the connection plate 12 on the substrate.

[0146] In an exemplary embodiment, the shape of the interlayer connection electrode 24 may be block-shaped (such as rectangular), the orthographic projection of the interlayer connection electrode 24 on the substrate at least partially overlaps with the orthographic projection of the connection block 13-1 in the connection line 13 on the substrate, and the interlayer connection electrode 24 is directly lapped with the connection block 13-1. In an exemplary embodiment, the interlayer connection electrode 24 is configured to be connected to a subsequent formed fourth connection electrode.

[0147] In an exemplary embodiment, the first conductive layer pattern of the repeating unit may further include a power supply connection line 21 and a compensation connection line 22.

[0148] In an exemplary embodiment, the shape of the power supply connection line 21 may be strip-shaped extending along the first direction X, and may be provided on the side of the shielding electrode 23 away from the interlayer connection electrode 24. One power supply connection line 21 may straddle the first sub-pixel P1 and the second sub-pixel P2, and another power supply connection line 21 may straddle the third sub-pixel P3 and the fourth sub-pixel P4. The power supply connection line 21 may be reused as the power supply horizontal connection line of the repeating unit, and by connecting to a subsequent formed first power supply line, a power supply signal is provided to the second transistors T2 of the second sub-pixel P2 and the third sub-pixel P3.

[0149] In an exemplary embodiment, the shape of the compensation connection line 22 may be a strip shape extending along the first direction X, and may be disposed on a side of the interlayer connection electrode 24 away from the shielding electrode 23. One compensation connection line 22 may straddle the first sub-pixel P1 and the second sub-pixel P2, and another compensation connection line 22 may straddle the third sub-pixel P3 and the fourth sub-pixel P4. The compensation connection line 22 may be multiplexed as a compensation lateral connection line of a repeating unit, and by connecting with a subsequently formed compensation signal line, a compensation signal is provided to the third transistor T3 of the first sub-pixel P1 to the fourth sub-pixel P4.

[0150] In an exemplary embodiment, at least one repeating unit may further include a compensation connection block 22-1. The shape of the compensation connection block 22-1 may be a broken line shape extending along the first direction X, and may be disposed between two compensation connection lines 22, and both ends of the compensation connection block 22-1 are respectively connected to the two compensation connection lines 22.

[0151] In an exemplary embodiment, in at least one repeating unit, the compensation connection lines 22, the compensation connection block 22-1 in the first sub-pixel P1 and the second sub-pixel P2, and the compensation connection lines 22 in the third sub-pixel P3 and the fourth sub-pixel P4 may be an integrally connected structure.

[0152] In an exemplary embodiment, the first conductive layers in the first sub-pixel P1 and the second sub-pixel P2 and the first conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4 may be disposed substantially symmetrically with respect to the center line of the repeating unit. For example, the positions and shapes of the power connection line 21, the compensation connection line 22, the shielding electrode 23, and the interlayer connection electrode 24 in the first sub-pixel P1 and the fourth sub-pixel P4 may be disposed substantially symmetrically with respect to the center line of the repeating unit. Another example is that the positions and shapes of the power connection line 21, the compensation connection line 22, the shielding electrode 23, and the interlayer connection electrode 24 in the second sub-pixel P2 and the third sub-pixel P3 may be disposed substantially symmetrically with respect to the center line of the repeating unit.

[0153] (3) Form a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the foregoing pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as Figure 8A and Figure 8B shown, Figure 8B is Figure 8A a plan view of the semiconductor layer in

[0154] In an exemplary embodiment, the semiconductor layer pattern of each sub-pixel in the repeating unit may at least include a first active layer 31, a second active layer 32, a third active layer 33, and a second electrode plate 34.

[0155] In an exemplary embodiment, the shape of the second electrode plate 34 may be rectangular, chamfers or grooves may be provided at the corners of the rectangular shape, the edges of the rectangular shape may be straight lines or broken lines, the orthographic projection of the second electrode plate 34 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate, the second electrode plate 34 is configured to form another transparent electrode plate of the transparent storage capacitor, and the first electrode plate 11 and the second electrode plate 34 constitute the transparent storage capacitor.

[0156] In an exemplary embodiment, the first active layer 31 may serve as the active layer of the first transistor T1, the second active layer 32 may serve as the active layer of the second transistor T2, the third active layer 33 may serve as the active layer of the third transistor T3, the first active layer 31 and the third active layer 33 may be disposed on a side of the second electrode plate 34 away from the power connection line 21, and the second active layer 32 may be disposed on a side of the second electrode plate 34 close to the power connection line 21.

[0157] In an exemplary embodiment, the first active layer 31, the second active layer 32, and the third active layer 33 may each include a channel region and a first region and a second region located on both sides of the channel region.

[0158] In an exemplary embodiment, the shape of the first active layer 31 may be in an "I" shape, the first region 31-1 of the first active layer may be located on a side of the channel region of the first active layer away from the second electrode plate 34, and the second region 31-2 of the first active layer may be located on a side of the channel region of the first active layer close to the second electrode plate 34.

[0159] In an exemplary embodiment, the first active layer 31 may be provided with an electrode plate connection bar 31-1. The shape of the electrode plate connection bar 31-1 may be a strip shape extending along the second direction Y, and may be disposed between the first active layer 31 and the second electrode plate 34. The first end of the electrode plate connection bar 31-1 is connected to the second region 31-2 of the first active layer, and the second end of the electrode plate connection bar 31-1 is connected to the second electrode plate 34.

[0160] In an exemplary embodiment, the first active layer 31, the electrode plate connection bar 31-1, and the second electrode plate 34 may be an integrally connected structure.

[0161] In an exemplary embodiment, the shape of the second active layer 32 may be in an "L" shape, and the orthographic projection of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 23 on the substrate. Among the first sub-pixel P1 and the second sub-pixel P2, the first region 32-1 of the second active layer may be located on one side opposite to the first direction X of the channel region of the second active layer, and the second region 32-2 of the second active layer may be located on one side of the first direction X of the channel region of the second active layer. Among the third sub-pixel P3 and the fourth sub-pixel P4, the first region 32-1 of the second active layer may be located on one side of the first direction X of the channel region of the second active layer, and the second region 32-2 of the second active layer may be located on one side opposite to the first direction X of the channel region of the second active layer.

[0162] In an exemplary embodiment, the orthographic projection of the channel region of the second active layer and the second region 32-2 of the second active layer on the substrate may be within the range of the orthographic projection of the shielding electrode 23 on the substrate. The shielding electrode 23 may shield the channel region of the second active layer 32 to prevent light from affecting the channel, reduce leakage current, and thus avoid the influence of light on the transistor characteristics.

[0163] In an exemplary embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the first region 32-1 of the second active layer on the substrate does not overlap with the orthographic projection of the shielding electrode 23 on the substrate. In the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the first region 32-1 of the second active layer on the substrate may be within the range of the orthographic projection of the shielding electrode 23 on the substrate.

[0164] In an exemplary embodiment, the shape of the third active layer 33 may be in an "I" shape, and the orthographic projection of the third active layer 33 on the substrate is spaced from the orthographic projection of the second electrode plate 34 on the substrate, that is, there is no overlapping region between the third active layer 33 and the second electrode plate 42, which is beneficial to designing the channel width-to-length ratio of the third transistor according to relevant requirements. The first region 33-1 of the third active layer may be located on the side of the channel region of the third active layer away from the second electrode plate 34, and the orthographic projection of the first region 33-1 of the third active layer on the substrate at least partially overlaps with the orthographic projection of the compensation connection line 22 on the substrate. The second region 33-2 of the third active layer may be located on the side of the channel region of the third active layer close to the second electrode plate 34, and the orthographic projection of the second region 33-2 of the third active layer on the substrate at least partially overlaps with the orthographic projection of the interlayer connection electrode 24 on the substrate.

[0165] In an exemplary embodiment, the semiconductor layer may be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, or may be a double layer, or may be multiple layers.

[0166] In an exemplary embodiment, the semiconductor layers in the first sub-pixel P1 and the second sub-pixel P2 may be disposed substantially symmetrically with respect to the center line of the repeating unit as compared with the semiconductor layers in the third sub-pixel P3 and the fourth sub-pixel P4. For example, the positions and shapes of the first active layer 31, the second active layer 32, the third active layer 33, and the second electrode plate 34 in the first sub-pixel P1 and the fourth sub-pixel P4 may be disposed substantially symmetrically with respect to the center line of the repeating unit. Also for example, the positions and shapes of the first active layer 31, the second active layer 32, the third active layer 33, and the second electrode plate 34 in the second sub-pixel P2 and the third sub-pixel P3 may be disposed substantially symmetrically with respect to the center line of the repeating unit.

[0167] (4) Form a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on the substrate on which the foregoing patterns are formed, and patterning the second conductive film and the second insulating film through a patterning process to form a second insulating layer disposed on the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as Figure 9A and Figure 9B shown, Figure 9B is Figure 9A a plan view of the second conductive layer in

[0168] In an exemplary embodiment, the second conductive layer pattern of each sub-pixel in the repeating unit may at least include a second gate electrode 42 and a scanning signal line 50.

[0169] In an exemplary embodiment, the shape of the scanning signal line 50 may be a strip shape extending along the first direction X, and the scanning signal line 50 may be located between the compensation connection line 22 and the second electrode plate 34. The positive projection of the scanning signal line 50 on the substrate at least partially overlaps with the positive projection of the first active layer 31 in each sub-pixel on the substrate, and the scanning signal line 50 in the overlapping region may serve as the gate electrode of the first transistor T1. The positive projection of the scanning signal line 50 on the substrate at least partially overlaps with the positive projection of the third active layer 33 in each sub-pixel on the substrate, and the scanning signal line 50 in the overlapping region may serve as the gate electrode of the third transistor T3.

[0170] In an exemplary embodiment, the scan signal line 50 may be set with a non-uniform width, and the width is the dimension of the scan signal line 50 in the second direction Y. The scan signal line 50 may include a first region overlapping with the first active layer 31 and the third active layer 33, and a second region not overlapping with the first active layer 31 and the third active layer 33, and the width of the first region may be smaller than the width of the second region.

[0171] In an exemplary embodiment, in the second region of the scan signal line 50, a plurality of vias 50-1 may be provided on the scan signal line 50. The shape of the via 50-1 may be a strip shape extending along the first direction X. The orthographic projection of the via 50-1 on the substrate overlaps at least partially with the orthographic projection of the subsequent formed first power supply line, data signal line, or compensation signal line on the substrate. The via 50-1 is configured to reduce the parasitic capacitance between the scan signal line 50 and the first power supply line, data signal line, or compensation signal line.

[0172] In an exemplary embodiment, in at least one sub-pixel, one scan signal line 50 may simultaneously serve as the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3.

[0173] In an exemplary embodiment, in a plurality of sub-pixels of at least one repeating unit, the gate electrodes of four first transistors T1 are connected to the same scan signal line 50. One scan signal line 50 may simultaneously serve as the gate electrodes of the four first transistors T1. The scan signal line 50 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 in the four sub-pixels of the repeating unit.

[0174] In an exemplary embodiment, in a plurality of sub-pixels of at least one repeating unit, the gate electrodes of four third transistors T3 are connected to the same scan signal line 50. One scan signal line 50 may simultaneously serve as the gate electrodes of the four third transistors T3. The scan signal line 50 is configured to simultaneously control the conduction or disconnection of all the third transistors T3 in the four sub-pixels of the repeating unit.

[0175] In an exemplary embodiment, in a plurality of sub-pixels of at least one repeating unit, the gate electrodes of four first transistors T1 and the gate electrodes of four third transistors T3 are connected to the same scan signal line 50. One scan signal line 50 may simultaneously serve as the gate electrodes of the four first transistors T1 and the gate electrodes of the four third transistors T3. The scan signal line 50 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0176] In an exemplary embodiment, in a plurality of sub-pixels of at least one pixel row, one scan signal line 50 may simultaneously serve as the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3.

[0177] In an exemplary embodiment, the shape of the second gate electrode 42 may be a strip shape extending along the second direction Y, and the second gate electrode 42 may serve as the gate electrode of the second transistor T2. On the one hand, the positive projection of the second gate electrode 42 on the substrate at least partially overlaps with the positive projection of the second active layer 32 on the substrate, and the second active layer 32 in the overlapping region is the channel region of the second active layer. On the other hand, the positive projection of the second gate electrode 42 on the substrate at least partially overlaps with the positive projection of the second electrode plate 34 on the substrate.

[0178] In an exemplary embodiment, the second conductive layers in the first sub-pixel P1 and the second sub-pixel P2 may be substantially symmetrically arranged with respect to the center line of the repeating unit relative to the second conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4. For example, the positions and shapes of the second gate electrode 42 and the scan signal line 50 in the first sub-pixel P1 and the fourth sub-pixel P4 may be substantially symmetrically arranged with respect to the center line of the repeating unit. For another example, the positions and shapes of the second gate electrode 42 and the scan signal line 50 in the second sub-pixel P2 and the third sub-pixel P3 may be substantially symmetrically arranged with respect to the center line of the repeating unit.

[0179] In an exemplary embodiment, the second insulating layer pattern and the second conductive layer pattern formed in this process may be substantially the same, that is, the positive projection of the second insulating layer on the substrate may be substantially the same as the positive projection of the second conductive layer on the substrate.

[0180] In an exemplary embodiment, this process further includes a conductorization process. The conductorization process is to perform plasma processing using the second conductive layer as a mask after forming the second conductive layer pattern. The semiconductor layer shielded by the second conductive layer serves as the channel region of the transistor, and the semiconductor layer not shielded by the second conductive layer is processed into a conductorized layer to form a conductorized second electrode plate and conductorized first and second regions.

[0181] (5) Form a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating thin film on the substrate on which the foregoing patterns are formed, and patterning the third insulating thin film using a patterning process to form a third insulating layer covering the second conductive layer. Multiple vias are provided on the third insulating layer, as Figure 10 shown.

[0182] In an exemplary embodiment, the multiple vias in each sub-pixel of the repeating unit at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7.

[0183] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate may be within the range of the orthographic projection of the first region of the first active layer on the substrate. The third insulating layer and the second insulating layer in the first via V1 are etched away to expose the surface of the first region of the first active layer. The first via V1 is configured to enable a subsequently formed data signal line to be connected to the first region of the first active layer through this via.

[0184] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate may be within the range of the orthographic projection of the second region of the first active layer on the substrate. The third insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second region of the first active layer. The second via V2 is configured to enable a subsequently formed third connection electrode to be connected to the second region of the first active layer through this via.

[0185] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate may be within the range of the orthographic projection of the first region of the second active layer on the substrate. The third insulating layer and the second insulating layer in the third via V3 are etched away to expose the surface of the first region of the second active layer. The third via V3 is configured to enable a subsequently formed first power supply line or a power supply connection electrode to be connected to the first region of the second active layer through this via. In an exemplary embodiment, the third via V3 may serve as the power supply via of the present disclosure.

[0186] In an exemplary embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the third via V3 on the substrate does not overlap with the orthographic projection of the shielding electrode 23 on the substrate.

[0187] In an exemplary embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the third via V3 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 23 on the substrate.

[0188] In an exemplary embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the third via V3 on the substrate may be within the range of the orthographic projection of the shielding electrode 23 on the substrate.

[0189] In an exemplary embodiment, the fourth via hole V4 may be located on one side of the second direction Y of the second electrode plate 34, and the orthographic projection of the fourth via hole V4 on the substrate overlaps at least partially with the orthographic projection of the second region of the second active layer and the shielding electrode 23 on the substrate at the same time. The fourth via hole V4 is a transfer via hole, which is composed of two half holes, one half hole is formed on the second region of the second active layer, and the third insulating layer and the second insulating layer in the half hole are etched away to expose the surface of the second region of the second active layer, and the other half hole is formed on the shielding electrode 23, and the third insulating layer, the second insulating layer and the first insulating layer in the half hole are etched away to expose the surface of the shielding electrode 23, so that the transfer via hole composed of the two half holes simultaneously exposes the second region of the second active layer and the surface of the shielding electrode 23. In an exemplary embodiment, the fourth via hole V4 is configured to allow the second connecting electrode formed subsequently to be connected to the second region of the second active layer and the shielding electrode 23 through the via hole at the same time, and the fourth via hole V4 can be used as a node via of the present disclosure.

[0190] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate overlaps at least partially with the orthographic projection of the first area of ​​the third active layer and the compensation connection line 22 on the substrate. The fifth via hole V5 is a transfer via hole, which is composed of two half holes, one half hole is formed on the first area of ​​the third active layer, and the third insulating layer and the second insulating layer in the half hole are etched away to expose the surface of the first area of ​​the third active layer, and the other half hole is formed on the compensation connection line 22, and the third insulating layer, the second insulating layer and the first insulating layer in the half hole are etched away to expose the surface of the compensation connection line 22, so that the transfer via hole composed of the two half holes simultaneously exposes the first area of ​​the third active layer and the surface of the compensation connection line 22. In an exemplary embodiment, the fifth via hole V5 is configured to allow the fifth connection electrode formed subsequently to be connected to the first area of ​​the third active layer and the compensation connection line 22 through the via hole at the same time.

[0191] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate overlaps at least partially with the orthographic projection of the second region of the third active layer and the interlayer connection electrode 24 on the substrate. The sixth via hole V6 is a transfer via hole, which is composed of two half holes, one half hole is formed on the second region of the third active layer, the third insulating layer and the second insulating layer in the half hole are etched away, exposing the surface of the second region of the third active layer, and the other half hole is formed on the interlayer connection electrode 24, the third insulating layer, the second insulating layer and the first insulating layer in the half hole are etched away, exposing the surface of the interlayer connection electrode 24, so that the transfer via hole composed of the two half holes simultaneously exposes the second region of the third active layer and the surface of the interlayer connection electrode 24. In an exemplary embodiment, the sixth via hole V6 is configured to allow the fourth connection electrode formed subsequently to be connected to the second region of the third active layer and the interlayer connection electrode 24 through the via hole at the same time.

[0192] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate overlaps at least partially with the orthographic projections of the second electrode plate 34 and the second gate electrode 42 on the substrate. The seventh via V7 is a transfer via, which is composed of two half holes, one half hole is formed on the second electrode plate 34, and the third insulating layer and the second insulating layer in the half hole are etched away to expose the surface of the second electrode plate 34, and the other half hole is formed on the second gate electrode 42, and the third insulating layer in the half hole is etched away to expose the surface of the second gate electrode 42, so that the transfer via composed of the two half holes exposes the surfaces of the second electrode plate 34 and the second gate electrode 42 at the same time. In an exemplary embodiment, the seventh via V7 is configured to allow the first connecting electrode formed subsequently to be connected to the second electrode plate 34 and the second gate electrode 42 at the same time through the via, and the seventh via V7 can serve as the first transfer via of the present disclosure.

[0193] In an exemplary embodiment, in the seventh via hole V7, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 34 on the substrate. Studies have shown that if the second electrode plate 34 and the second gate electrode 42 in the seventh via hole V7 do not overlap, over-etching is likely to occur during the dry etching process of the via hole, and over-etching will cause the shielding electrode 23 to be exposed, so that the first connecting electrode formed subsequently is connected to the shielding electrode 23, thereby causing a short circuit and causing a dark spot defect. The present disclosure can effectively avoid short circuits and dark spot defects by setting the second electrode plate 34 and the second gate electrode 42 in the first transfer via hole to overlap.

[0194] In an exemplary embodiment, the repeating unit may further include an eighth via hole V8 , a ninth via hole V9 , and a tenth via hole V10 .

[0195] In an exemplary embodiment, the eighth via hole V8 can be arranged in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first end of the power connection line 21 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighth via hole V8 are etched away to expose the surface of the first end of the power connection line 21, and the eighth via hole V8 is configured to connect the subsequently formed first power line to the first end of the power connection line 21 through the via hole.

[0196] In an exemplary embodiment, the ninth via hole V9 can be arranged in the second sub-pixel P2 and the third sub-pixel P3, and the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second end of the power connection line 21 on the substrate, and the third insulating layer, the second insulating layer and the first insulating layer in the ninth via hole V9 are etched away to expose the surface of the second end of the power connection line 21, and the ninth via hole V9 is configured to connect the subsequently formed power connection electrode to the second end of the power connection line 21 through the via hole.

[0197] In an exemplary embodiment, the tenth via V10 may be disposed between the second sub-pixel P2 and the third sub-pixel P3. The orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the compensation connection block 22-1 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the tenth via V10 are etched away to expose the surface of the compensation connection block 22-1. The tenth via V10 is configured to enable a compensation signal line formed subsequently to be connected to the compensation connection block 22-1 through this via.

[0198] (6) Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the third conductive thin film using a patterning process to form a third conductive layer disposed on the third insulating layer, as Figure 11A and Figure 11B shown, Figure 11B is Figure 11A a plan view of the third conductive layer in

[0199] In an exemplary embodiment, the third conductive layer pattern of each sub-pixel in the repeating unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, and a fifth connection electrode 55.

[0200] In an exemplary embodiment, the shape of the first connection electrode 51 may be a strip shape extending along the second direction Y. The first connection electrode 51 is connected to both the second electrode plate 34 and the second gate electrode 42 through the seventh via V7, realizing that the gate electrode of the second transistor T2 and the second electrode plate 34 of the storage capacitor have the same potential. Since the second gate electrode 42 and the second electrode plate 34 overlap within the seventh via V7, the seventh via V7 will not be over-etched to expose the shielding electrode 23, thus effectively avoiding a short circuit between the second gate electrode 42 and the second electrode plate 34 and the shielding electrode 23, and effectively avoiding dark spot defects.

[0201] In an exemplary embodiment, the shape of the second connection electrode 52 may be a strip shape extending along the second direction Y. The second connection electrode 52 is connected to the second region of the second active layer and the shielding electrode 23 through the fourth via V4. Since the shielding electrode 23 overlaps with the connection plate 12, and the connection plate 12 is connected to the first electrode plate 11, the second connection electrode 52 realizes that the second pole of the second transistor T2 and the first electrode plate 11 of the storage capacitor have the same potential. In an exemplary embodiment, the second connection electrode 52 may be used as the node electrode of the present disclosure.

[0202] In an exemplary embodiment, the second connection electrode 52 includes a first sub - electrode 52 - 1 and a second sub - electrode 52 - 2. The shapes of the first sub - electrode 52 - 1 and the second sub - electrode 52 - 2 may be block - shaped (such as rectangular), and the second sub - electrode 52 - 2 may be disposed on a side of the first sub - electrode 52 - 1 away from the second electrode plate 34 and connected to the first sub - electrode 52 - 1. The first sub - electrode 52 - 1 is connected to the second region of the second active layer and the shielding electrode 23 through the fourth via V4, and the second sub - electrode 52 - 2 is configured to be connected to a first electrode formed subsequently.

[0203] In an exemplary embodiment, the shape of the third connection electrode 53 may be block - shaped (such as rectangular), and the third connection electrode 53 is connected to the second region of the first active layer through the second via V2. Since the second region of the first active layer is connected to the second electrode plate 34 through the electrode plate connection strip 31 - 1, the third connection electrode 53 enables the second pole of the first transistor T1 and the second electrode plate 34 of the storage capacitor to have the same potential.

[0204] In an exemplary embodiment, since the first connection electrode 51 enables the gate electrode of the second transistor T2 and the second electrode plate 34 of the storage capacitor to have the same potential, and the third connection electrode 53 enables the second pole of the first transistor T1 and the second electrode plate 34 of the storage capacitor to have the same potential, the first connection electrode 51 and the third connection electrode 53 enable the second pole of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 34 of the storage capacitor to have the same potential, that is, the potential of the first node N1 in the pixel driving circuit.

[0205] In an exemplary embodiment, the shape of the fourth connection electrode 54 may be strip - shaped extending along the second direction Y, and the fourth connection electrode 54 is connected to the second region of the third active layer and the inter - layer connection electrode 24 through the sixth via V6. Since the inter - layer connection electrode 24 is connected to the connection line 13, and the connection line 13 is connected to the first electrode plate 11, the fourth connection electrode 54 enables the second pole of the third transistor T3 and the first electrode plate 11 of the storage capacitor to have the same potential.

[0206] In an exemplary embodiment, since the second connection electrode 52 enables the second pole of the second transistor T2 and the first electrode plate 11 of the storage capacitor to have the same potential, and the fourth connection electrode 54 enables the second pole of the third transistor T3 and the first electrode plate 11 of the storage capacitor to have the same potential, the second connection electrode 52 and the fourth connection electrode 54 enable the second pole of the second transistor T2, the second pole of the third transistor T3, and the first electrode plate 11 of the storage capacitor to have the same potential, that is, the potential of the second node N2 in the pixel driving circuit.

[0207] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a strip extending along the second direction Y. The fifth connection electrode 55 is connected to the first region of the third active layer and the compensation connection line 22 through the fifth via V5. Since the compensation connection line 22 is configured to be connected to the compensation signal line, the fifth connection electrode 55 enables the compensation signal line to write the compensation signal to the first pole of the third transistor T3 in each sub-pixel.

[0208] In an exemplary embodiment, the third conductive layer pattern of the repeating unit may further include a power connection electrode 56, a first power supply line 60, and a compensation signal line 80.

[0209] In an exemplary embodiment, the first power supply line 60 may be in the shape of a straight line or a broken line with a main body extending along the second direction Y, and may be respectively disposed on one side of the first sub-pixel P1 away from the second sub-pixel P2 and on one side of the fourth sub-pixel P4 away from the third sub-pixel P3. On the one hand, the first power supply line 60 is connected to the first region of the second active layer through the third via V3 (power supply via), enabling the first power supply line 60 to write the first power signal to the first pole of the second transistor T2 in the first sub-pixel P1 and the fourth sub-pixel P4. On the other hand, the first power supply line 60 is connected to the first end of the power connection line 21 through the eighth via V8, enabling the first power supply line 60 located in the first sub-pixel P1 to transmit the power signal to the second sub-pixel P2 through the power connection line 21, and enabling the first power supply line 60 located in the fourth sub-pixel P4 to transmit the power signal to the third sub-pixel P3 through the power connection line 21.

[0210] In an exemplary embodiment, the first power supply line 60 may be a non-uniform-width straight line or broken line, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance.

[0211] In an exemplary embodiment, the power connection electrode 56 may be in the shape of a strip extending along the second direction Y, and may be respectively disposed in the second sub-pixel P2 and the third sub-pixel P3. The first end of the power connection electrode 56 is connected to the first region of the second active layer through the third via V3 (power supply via), and the second end of the power connection electrode 56 is connected to the second end of the power connection line 21 through the ninth via V9. Since the first end of the power connection line 21 is connected to the first power supply line 60, the first power supply line 60 enables the first power signal to be written to the first pole of the second transistor T2 in the second sub-pixel P2 and the third sub-pixel P3.

[0212] In an exemplary embodiment, the first power line 60 in the first sub-pixel P1 can be connected to the first region of the second active layer through the third via V3 and to the first end of the power connection line 21 through the eighth via V8. The first end of the power connection electrode 56 in the second sub-pixel P2 can be connected to the first region of the second active layer through the third via V3, and the second end of the power connection electrode 56 can be connected to the second end of the power connection line 21 through the ninth via V9. That is, the first power line 60 in the first sub-pixel P1 is connected to the first region of the second active layer in the second sub-pixel P2 through the power connection line 21 and the power connection electrode 56. The first power line 60 in the fourth sub-pixel P4 can be connected to the first region of the second active layer through the third via V3 and to the first end of the power connection line 21 through the eighth via V8. The first end of the power connection electrode 56 in the third sub-pixel P3 is connected to the first region of the second active layer through the third via V3, and the second end of the power connection electrode 56 is connected to the second end of the power connection line 21 through the ninth via V9. That is, the first power line 60 in the fourth sub-pixel P4 is connected to the first region of the second active layer in the third sub-pixel P3 through the power connection line 21 and the power connection electrode 56. In this way, the first power line 60 in the first sub-pixel P1 can supply a power signal to the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2, and the first power line 60 in the fourth sub-pixel P4 can supply a power signal to the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4. In the present disclosure, by providing two power connection lines 21 extending along the first direction X and two first power lines 60 extending along the second direction Y in the repeating unit, a one-to-two structure of the first power line for writing the power signal into the second transistors T2 of the four sub-pixels is realized.

[0213] In an exemplary embodiment, the shape of the compensation signal line 80 can be a straight line or a broken line with the main body part extending along the second direction Y. It can be disposed between the second sub-pixel P2 and the third sub-pixel P3. The compensation signal line 80 is connected to the compensation connection block 22-1 through the tenth via V10. Since the compensation connection block 22-1 is connected to the compensation connection lines 22 in the first sub-pixel P1 and the second sub-pixel P2 on the one hand and to the compensation connection lines 22 in the third sub-pixel P3 and the fourth sub-pixel P4 on the other hand, one compensation connection line 22 is connected to the first pole of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2 through the fifth connection electrode 55, and the other compensation connection line 22 is connected to the first pole of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4 through the fifth connection electrode 55. In this way, one compensation signal line 80 can supply a compensation signal to the pixel driving circuits of the four sub-pixels, forming a one-to-four structure of the compensation signal line.

[0214] The present disclosure realizes writing the compensation signal into the third transistor T3 of four sub-pixels respectively by providing a compensation signal line 80 extending along the second direction Y and two compensation connection lines 22 extending along the first direction X in the repeating unit, which can ensure that the RC delays of the compensation signals are basically the same before being written into the transistors, thereby ensuring display uniformity.

[0215] In an exemplary embodiment, the pattern of the third conductive layer of each sub-pixel in the repeating unit may further include a data signal line 70.

[0216] In an exemplary embodiment, the shape of the data signal line 70 may be a broken line shape with a main body portion extending along the second direction Y. The data signal line 70 is connected to the first region of the first active layer through the first via V1, realizing that the data signal line 70 writes the data signal into the first pole of the first transistor T1.

[0217] In an exemplary embodiment, in the first sub-pixel P1 and the third sub-pixel P3, the data signal line 70 may be disposed on one side of the storage capacitor (the first electrode plate 11 and the second electrode plate 34) in the first direction X. In the second sub-pixel P2 and the fourth sub-pixel P4, the data signal line 70 may be disposed on one side opposite to the first direction X of the storage capacitor.

[0218] In an exemplary embodiment, in at least one sub-pixel, the data signal line 70 may include a first sub-line 70-1, a second sub-line 70-2, and a third sub-line 70-3. The shapes of the first sub-line 70-1 and the second sub-line 70-2 are straight line shapes extending along the second direction Y, and the shape of the third sub-line 70-3 is a straight line shape or a broken line shape extending along an inclined direction. The third sub-line 70-3 may be disposed between the first sub-line 70-1 and the second sub-line 70-2. The first end of the third sub-line 70-3 is connected to the first sub-line 70-1, and the second end of the third sub-line 70-3 is connected to the second sub-line 70-2.

[0219] In an exemplary embodiment, in at least one of the first sub-pixel P1 and the fourth sub-pixel P4, there may be a first distance L1 between the first sub-line 70-1 and the first power supply line 60, and a second distance L2 between the second sub-line 70-2 and the first power supply line 60. The first distance L1 may be greater than the second distance L2. The first distance L1 may be the distance between the edge of the first sub-line 70-1 close to the first power supply line 60 and the edge of the first power supply line 60 close to the first sub-line 70-1, which is the dimension in the first direction X. The second distance L2 may be the distance between the edge of the second sub-line 70-2 close to the first power supply line 60 and the edge of the first power supply line 60 close to the second sub-line 70-2, which is the dimension in the first direction X.

[0220] In an exemplary embodiment, in at least one of the second sub-pixel P2 and the third sub-pixel P3, a third distance L3 may exist between the first sub-line 70-1 and the compensation signal line 80, a fourth distance L4 may exist between the second sub-line 70-2 and the compensation signal line 80, and the third distance L3 may be less than the fourth distance L4. The third distance L3 may be the distance between the edge of the first sub-line 70-1 closer to the compensation signal line 80 and the edge of the compensation signal line 80 closer to the first sub-line 70-1, and is a dimension in the first direction X. The fourth distance L4 may be the distance between the edge of the second sub-line 70-2 closer to the compensation signal line 80 and the edge of the compensation signal line 80 closer to the second sub-line 70-2, and is a dimension in the first direction X.

[0221] In an exemplary embodiment, the first distance L1 may be equal to the third distance L3.

[0222] In an exemplary embodiment, since power connection lines 21 and power connection electrodes 56 for connecting the first region of the second active layer to the first power supply line 60 are provided in the second sub-pixel P2 and the third sub-pixel P3, and the first region of the second active layer in the first sub-pixel P1 and the fourth sub-pixel P4 is directly connected to the first power supply line 60, the layout space requirements for the layout in the second sub-pixel P2 and the third sub-pixel P3 are larger, and the layout space requirements for the layout in the first sub-pixel P1 and the fourth sub-pixel P4 are smaller. By providing the data signal line 70 in a zigzag shape and bending the zigzag portion away from the compensation signal line 80, the present disclosure can effectively increase the areas of the second sub-pixel P2 and the third sub-pixel P3, meet the layout space requirements for the layout in the second sub-pixel P2 and the third sub-pixel P3, and is conducive to realizing high-resolution display.

[0223] In an exemplary embodiment, the data signal line 70 may be a zigzag line with equal width or non-equal width, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance.

[0224] In an exemplary embodiment, the third conductive layers in the first sub-pixel P1 and the second sub-pixel P2 may be arranged substantially symmetrically with respect to the center line of the repeating unit relative to the third conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4. For example, the positions and shapes of the first connection electrode 51 to the fifth connection electrode 55, the power connection electrode 56, the first power supply line 60, the data signal line 70, and the compensation signal line 80 in the first sub-pixel P1 and the fourth sub-pixel P4 may be arranged substantially symmetrically with respect to the center line of the repeating unit. For another example, the positions and shapes of the first connection electrode 51 to the fifth connection electrode 55, the power connection electrode 56, the first power supply line 60, the data signal line 70, and the compensation signal line 80 in the second sub-pixel P2 and the third sub-pixel P3 may be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0225] (7) Form a fourth insulating layer and a planarization layer pattern. In an exemplary embodiment, forming the fourth insulating layer and the planarization layer pattern may include: on the substrate on which the foregoing pattern is formed, first deposit a fourth insulating thin film, then coat a planarizing thin film, and use a patterning process to pattern the planarizing thin film and the fourth insulating thin film to form a fourth insulating layer covering the third conductive layer and a planarization layer provided on the fourth insulating layer. A plurality of vias are formed in the planarization layer and the fourth insulating layer, as Figure 12 shown.

[0226] In an exemplary embodiment, the plurality of vias in each sub-pixel of the repeating unit at least include an anode via YV.

[0227] In an exemplary embodiment, the orthographic projection of the anode via YV on the substrate is within the range of the orthographic projection of the second sub-electrode 52-2 in the second connection electrode 52 on the substrate. The planarization layer and the fourth insulating layer within the anode via YV are removed to expose the surface of the second sub-electrode 52-2. The anode via YV is configured to connect the first electrode formed subsequently to the second sub-electrode 52-2 through this via.

[0228] In an exemplary embodiment, the orthographic projection of the anode via YV on the substrate does not overlap with the orthographic projection of the fourth via V4 (node via) on the substrate, and the anode via YV is located on the side of the fourth via V4 away from the second electrode plate 34.

[0229] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the anode via YV on the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer on the display substrate plane.

[0230] In some other embodiments, the display substrate may include a color filter layer. On the substrate on which the foregoing pattern is formed, first form a fourth insulating layer, then form a color filter layer on the fourth insulating layer, and then coat a planarizing thin film to form a fourth insulating layer covering the third conductive layer, a color filter layer provided on the fourth insulating layer, and a planarization layer covering the color filter layer. The fourth insulating layer, the color filter layer, and the planarization layer within the anode via are removed to expose the surface of the second connection electrode.

[0231] (8) Form a second transparent conductive layer pattern. In an exemplary embodiment, forming the second transparent conductive layer pattern may include: on the substrate on which the foregoing pattern is formed, deposit a second transparent conductive thin film, and use a patterning process to pattern the second transparent conductive thin film to form a second transparent conductive layer pattern provided on the planarization layer, as Figure 13 shown.

[0232] In an exemplary embodiment, the second transparent conductive layer pattern in each sub-pixel of the repeating unit at least includes a first electrode 90.

[0233] In an exemplary embodiment, the shape of the first electrode 90 may be a strip shape extending along the second direction Y. A convex portion is provided on one side of the first electrode 90 in the second direction Y, and the convex portion is connected to the second sub-electrode 52-2 through an anode via hole YV. Since the second connection electrode 52 including the second sub-electrode 52-2 has the potential of the second node N2 in the pixel driving circuit, the connection between the first electrode 90 and the second node N2 is realized.

[0234] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first electrode 90 on the substrate at least partially overlaps with the orthographic projection of the storage capacitor (the first electrode plate 11 and the second electrode plate 34) in the sub-pixel on the substrate.

[0235] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first electrode 90 on the substrate may include the orthographic projection of the storage capacitor in the sub-pixel on the substrate.

[0236] In an exemplary embodiment, the second transparent conductive layers in the first sub-pixel P1 and the second sub-pixel P2 may be symmetrically arranged with respect to the center line of the repeating unit substantially as compared with the second transparent conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4. For example, the positions and shapes of the first electrodes 90 in the first sub-pixel P1 and the fourth sub-pixel P4 may be symmetrically arranged with respect to the center line of the repeating unit substantially. Also, for example, the positions and shapes of the first electrodes 90 in the second sub-pixel P2 and the third sub-pixel P3 may be symmetrically arranged with respect to the center line of the repeating unit substantially.

[0237] (9) Form a pixel defining layer pattern. In an exemplary embodiment, forming the pixel defining layer pattern may include: coating a pixel defining thin film on the substrate on which the foregoing patterns are formed, and patterning the pixel defining thin film by a patterning process to form a pixel defining layer pattern, as Figure 14 shown.

[0238] In an exemplary embodiment, the pixel defining layer pattern of each sub-pixel in the repeating unit at least includes a pixel opening 90A.

[0239] In an exemplary embodiment, the shape of the pixel opening 90A may be a strip shape extending along the second direction Y. The orthographic projection of the pixel opening 90A on the substrate may be within the range of the orthographic projection of the first electrode 90 on the substrate. The pixel defining thin film within the pixel opening 90A is removed to expose the surface of the first electrode 90.

[0240] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the pixel opening 90A on the substrate at least partially overlaps with the orthographic projection of the storage capacitor in the sub-pixel on the substrate.

[0241] In an exemplary embodiment, in at least one sub-pixel, a fourth via V4 (node via) may be located on one side of the pixel opening 90A in the second direction Y, and the orthographic projection of the fourth via V4 on the substrate does not overlap with the orthographic projection of the pixel opening 90A on the substrate.

[0242] In an exemplary embodiment, in at least one sub-pixel, an anode via YV may be located on one side of the fourth via V4 in the second direction Y, that is, the anode via YV may be located on the side of the fourth via V4 away from the pixel opening 90A, and the orthographic projection of the anode via YV on the substrate does not overlap with the orthographic projection of the pixel opening 90A on the substrate.

[0243] In an exemplary embodiment, the shapes and areas of the pixel openings of different sub-pixels may be different. By designing the four sub-pixels to have different aperture ratios in the exemplary embodiments of the present disclosure, the transmittance of the color filter layers of different sub-pixels can be adapted, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, maximizing the service life of the light-emitting devices of the four sub-pixels and ensuring the product life.

[0244] In an exemplary embodiment, the shape of the pixel opening may include any one or more of the following: triangle, rectangle, trapezoid, parallelogram, pentagon, hexagon, circle, and ellipse.

[0245] In an exemplary embodiment, the subsequent preparation process may include: forming an organic light-emitting layer by using an evaporation or inkjet printing process. The organic light-emitting layer is connected to the first electrode through the pixel opening, a second electrode is formed on the organic light-emitting layer, and the second electrode is connected to the organic light-emitting layer. A packaging structure layer is formed. The packaging structure layer may include a first packaging layer, a second packaging layer, and a third packaging layer stacked on top of each other. The first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. The second packaging layer is disposed between the first packaging layer and the third packaging layer, which can ensure that external moisture cannot enter the light-emitting structure layer.

[0246] Thus far, a driving circuit layer, a light-emitting structure layer disposed on the driving circuit layer, and a packaging structure layer disposed on the light-emitting structure layer are prepared on the substrate. In a plane perpendicular to the display substrate, the driving circuit layer may include a first transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer stacked in sequence on the substrate. The light-emitting structure layer may include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The packaging structure layer may include a first packaging layer, a second packaging layer, and a third packaging layer stacked on top of each other.

[0247] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The material of the semiconductor layer may be amorphous silicon (a-si).

[0248] In an exemplary embodiment, the first transparent conductive layer and the second transparent conductive layer may adopt a transparent conductive material, such as indium tin oxide ITO or indium zinc oxide IZO, etc. The first conductive layer, the second conductive layer, and the third conductive layer may adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). It may be a single layer, a multi-layer, or a composite layer. The planarization layer may adopt an organic material, such as resin, etc. The pixel definition layer may adopt polyimide, acrylic, or polyethylene terephthalate.

[0249] Studies by the inventors of the present application have shown that in a bottom-emitting OLED display device, when the pixel aperture is close to the anode via, due to the waveguide effect formed between the first electrode (ITO) in the anode via and the pixel aperture, part of the light of the light-emitting device will exit from the boundary of the planarization layer, resulting in display defects such as watermarks in the OLED display device.

[0250] The exemplary embodiment of the present disclosure provides a display substrate. By setting the node via at a position close to the pixel aperture and setting the anode via at a position far from the pixel aperture, not only can light leakage be effectively reduced, display defects such as watermarks be eliminated, but also the maximization of the pixel aperture can be ensured, the afterimage can be effectively improved, and the display quality and display performance can be improved.

[0251] By setting the positive projection of the second gate electrode on the substrate to at least partially overlap with the positive projection of the second electrode plate on the substrate, the present disclosure can effectively avoid short circuits and effectively avoid dark spot defects.

[0252] By setting the data signal line in a zigzag shape, and the zigzag part is bent away from the compensation signal line, the present disclosure realizes the differential design of sub-pixels within the repeating unit, which can effectively increase the areas of the second sub-pixel and the third sub-pixel, meet the layout space requirements of the second sub-pixel and the third sub-pixel, and is beneficial to realizing high-resolution and high aperture ratio displays.

[0253] By adopting a transparent storage capacitor, which is composed of a transparent first transparent conductive layer and a transparent semiconductor layer, since light can pass through the transparent storage capacitor and exit, the storage capacitor can be arranged within the pixel aperture. This can not only effectively increase the capacitance of the storage capacitor, but also effectively increase the pixel aperture, which is beneficial to realizing high storage capacitance and high aperture ratio displays.

[0254] By setting the one-to-two structure of the first power supply line and the one-to-four structure of the compensation signal line, the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, makes full use of the layout space, improves the space utilization rate, and is beneficial to improving the resolution.

[0255] In the display substrate of the embodiment of the present disclosure, a 3T1C pixel driving circuit with one scanning signal line is adopted. One scanning signal line is connected to all the first transistors and all the third transistors in a pixel row, which effectively reduces the number of scanning signal lines. This can not only simplify the structure of the pixel driving circuit, reduce the occupied area of the pixel driving circuit, and is beneficial to realizing high-resolution displays, but also effectively increase the light-transmitting area of the light-transmitting region and improve the space occupancy ratio of the light-transmitting region, which is beneficial to realizing high transparency displays. In addition, since only one scanning signal line is required to drive one repeating unit, the number of its corresponding gate driving circuit (GOA) and clock signal line (CLK) can be reduced by multiples, effectively reducing the occupied area of the gate driving circuit and the clock signal line, which is beneficial to realizing narrow borders and improving the product advantages.

[0256] The preparation process of the present disclosure can be realized by using existing mature preparation equipment, has little improvement on the existing process, can be well compatible with the existing preparation process, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield.

[0257] The structure shown in the present disclosure and its preparation process are only an exemplary illustration. In the exemplary embodiment, the corresponding structure can be changed according to actual needs, and patterning processes can be added or reduced. The present disclosure does not make any limitations here.

[0258] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED), or quantum dot light emitting diode display (QDLED), etc., and the present disclosure does not make any limitation here.

[0259] The exemplary embodiment of the present disclosure also provides a method for manufacturing a display substrate to manufacture the display substrate of the foregoing embodiment. In the exemplary embodiment, the display substrate includes a plurality of sub-pixels; the manufacturing method includes:

[0260] Forming a pixel driving circuit and a light emitting device in at least one sub-pixel; the pixel driving circuit at least includes a second transistor as a driving transistor and a node electrode, the second transistor at least includes a second active layer, the node electrode is connected to the second region of the second active layer through a node via, the first region of the second active layer is connected to a first power supply line; the light emitting device at least includes a first electrode and a pixel defining layer, the first electrode is connected to the node electrode through an anode via, and a pixel opening exposing the first electrode is provided on the pixel defining layer; in at least one sub-pixel, the positive projection of the node via on the display substrate plane does not overlap with the positive projection of the pixel opening on the display substrate plane, and the anode via is provided on a side of the node via away from the pixel opening.

[0261] The present disclosure also provides a display device including the display substrate of the foregoing embodiment. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component having a display function.

[0262] Although the disclosed embodiments are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: The invention comprises a plurality of repeating units, at least one of which comprises a plurality of sub-pixels, and at least one of which comprises a pixel driving circuit and a light-emitting device; the pixel driving circuit comprises at least a second transistor as a driving transistor and a node electrode, the second transistor comprises at least a second active layer, the node electrode is connected to a second region of the second active layer through a node via hole, and a first region of the second active layer is connected to a first power line; the light-emitting device comprises at least a first electrode and a pixel definition layer, the first electrode is connected to the node electrode through an anode via hole, and a pixel opening exposing the first electrode is provided on the pixel definition layer; In at least one sub-pixel, an orthographic projection of the node via on the display substrate plane does not overlap with an orthographic projection of the pixel opening on the display substrate plane, and the anode via is arranged on a side of the node via away from the pixel opening.

2. The display substrate according to claim 1, characterized in that: The pixel driving circuit further includes a shielding electrode and a transparent storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane, the orthographic projection of the shielding electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer on the display substrate plane, and the shielding electrode is connected to the first electrode plate; In at least one sub-pixel, the node electrode is further connected to the shielding electrode through the node via.

3. The display substrate according to claim 2, characterized in that: The node electrode includes at least a first sub-electrode and a second sub-electrode connected to each other, the first sub-electrode is connected to the second region of the second active layer and the blocking electrode at the same time through the node via, the first electrode is connected to the second sub-electrode through the anode via, and the second sub-electrode is arranged on a side of the first sub-electrode away from the pixel opening.

4. The display substrate according to claim 3, characterized in that: The orthographic projection of the second sub-electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second area of ​​the second active layer on the display substrate plane, and the orthographic projection of the anode via on the display substrate plane at least partially overlaps with the orthographic projection of the second area of ​​the second active layer on the display substrate plane.

5. The display substrate according to claim 2, characterized in that: In at least one sub-pixel, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening on the display substrate plane, and the orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening on the display substrate plane.

6. The display substrate according to claim 2, characterized in that: In a direction perpendicular to the display substrate, the display substrate at least includes a first transparent conductive layer arranged on a substrate, a first conductive layer arranged on a side of the first transparent conductive layer away from the substrate, a semiconductor layer arranged on a side of the first conductive layer away from the substrate, and a second conductive layer arranged on a side of the semiconductor layer away from the substrate, the first electrode plate is arranged in the first transparent conductive layer, the shielding electrode is arranged in the first conductive layer, the second electrode plate and the second active layer are arranged in the semiconductor layer, and the node electrode is arranged in the second conductive layer.

7. The display substrate according to claim 2, characterized in that: The second transistor further includes a second gate electrode, and the pixel driving circuit further includes a first connecting electrode; in at least one sub-pixel, the first connecting electrode is simultaneously connected to the second electrode plate and the second gate electrode through a first transfer via.

8. The display substrate according to claim 7, characterized in that: In at least one sub-pixel, an orthographic projection of the second gate electrode on the plane of the display substrate at least partially overlaps with an orthographic projection of the second electrode plate on the plane of the display substrate.

9. The display substrate according to claim 7, characterized in that: In at least one first transfer via, an orthographic projection of the second gate electrode on the display substrate plane at least partially overlaps with an orthographic projection of the second electrode plate on the display substrate plane.

10. The display substrate according to any one of claims 1 to 9, characterized in that: At least one repeating unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along a first direction, the first power line is in the shape of a straight line or a broken line extending along a second direction, and is respectively arranged in the first sub-pixel and the fourth sub-pixel, and the first direction and the second direction intersect; the first power line in the first sub-pixel is connected to the first area of ​​the second active layer in the first sub-pixel through a power via hole, the first power line in the first sub-pixel is connected to the first area of ​​the second active layer in the second sub-pixel through a power connection line and a power connection electrode, the first power line in the fourth sub-pixel is connected to the first area of ​​the second active layer in the third sub-pixel through a power connection line and a power connection electrode, and the first power line in the fourth sub-pixel is connected to the first area of ​​the second active layer in the fourth sub-pixel through a power via hole.

11. The display substrate according to claim 10, characterized in that: The pixel driving circuit also includes a blocking electrode, and the orthographic projection of the blocking electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer on the display substrate plane; in the first sub-pixel and the fourth sub-pixel, the orthographic projection of the power via on the display substrate plane does not overlap with the orthographic projection of the blocking electrode on the display substrate plane.

12. The display substrate according to claim 10, characterized in that: The pixel driving circuit also includes a shielding electrode, and the orthographic projection of the shielding electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer on the display substrate plane; in the second sub-pixel and the third sub-pixel, the first end of the power connection electrode is connected to the first area of ​​the second active layer through a power via, and the second end of the power connection electrode is connected to the first power line through the power connection line, and the orthographic projection of the power via on the display substrate plane at least partially overlaps with the orthographic projection of the shielding electrode on the display substrate plane.

13. The display substrate according to claim 10, characterized in that: At least one sub-pixel also includes a data signal line connected to the pixel driving circuit, the data signal line is in the shape of a zigzag line extending along the second direction, and includes at least a first sub-line and a second sub-line in a straight line, and a third sub-line in a diagonal line, the third sub-line is arranged between the first sub-line and the second sub-line, and the two ends of the third sub-line are respectively connected to the first sub-line and the second sub-line; in at least one sub-pixel of the first sub-pixel and the fourth sub-pixel, the first sub-line has a first distance from the first power line, the second sub-line has a second distance from the first power line, the first distance is greater than the second distance, and the first distance and the second distance are the dimensions of the first direction.

14. The display substrate according to claim 13, characterized in that: At least one sub-pixel also includes a compensation signal line connected to the pixel driving circuit, and the compensation signal line is arranged between the second sub-pixel and the third sub-pixel; in at least one sub-pixel of the second sub-pixel and the third sub-pixel, there is a third distance between the first sub-line and the compensation signal line, and there is a fourth distance between the second sub-line and the compensation signal line, the third distance is smaller than the fourth distance, and the third distance and the fourth distance are the dimensions in the first direction.

15. The display substrate according to claim 14, characterized in that: The orthographic projection of the compensation signal line on the display substrate plane does not overlap with the orthographic projection of the power connection line on the display substrate plane.

16. The display substrate according to any one of claims 1 to 9, characterized in that: The pixel driving circuit further includes a first transistor as a data writing transistor and a third transistor as a compensation transistor. In at least one sub-pixel, a gate electrode of the first transistor and a gate electrode of the third transistor are connected to the same scanning signal line.

17. The display substrate according to claim 16, characterized in that: In at least one repetitive unit, gate electrodes of a plurality of the first transistors and gate electrodes of a plurality of the third transistors are connected to the same scanning signal line.

18. The display substrate according to claim 16, characterized in that: In at least one repeating unit, at least one through hole is provided on the scanning signal line, and an orthographic projection of the through hole on the plane of the display substrate at least partially overlaps with an orthographic projection of the first power line on the plane of the display substrate.

19. A display device, characterized in that: Comprising the display substrate as claimed in any one of claims 1 to 18.

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