Display device

Abstract

The display device includes: a first layer disposed in a light emitting region of a substrate; a second layer disposed on the first layer; an insulating layer disposed on the second layer; a first electrode disposed on the insulating layer; a light-emitting structure disposed on the first electrode; and a second electrode disposed on the light-emitting structure, the first electrode including a first region on the first layer and the second layer and a second region electrically separated from the first region.

Description

Technical Field

[0001] The utility model relates to a display device. Background Art

[0002] Recently, as interest in information displays has increased, research and development of display devices has been ongoing. Utility Model Content

[0003] The problem to be solved by the utility model is to provide an ultra-high resolution display device with improved reliability.

[0004] The problems of the present invention are not limited to the problems mentioned above, and those skilled in the art can clearly understand other problems not mentioned from the following description.

[0005] A display device according to an embodiment for solving the above-mentioned problem includes: a first layer, which is arranged in a light-emitting area of ​​a substrate; a second layer, which is arranged on the first layer; an insulating layer, which is arranged on the second layer; a first electrode, which is arranged on the insulating layer; a light-emitting structure, which is arranged on the first electrode; and a second electrode, which is arranged on the light-emitting structure, wherein the first electrode includes a first area on the first layer and the second layer and a second area electrically separated from the first area.

[0006] It may be that the width of the second layer in the first direction is greater than the width of the first layer in the first direction.

[0007] It may be that the length by which the second layer protrudes from the first layer is greater than the thickness of the first electrode.

[0008] The light-emitting structure may be at least partially separated from the second region of the first electrode.

[0009] It may be that the first electrode includes a first electrode layer configured on the insulating layer and a second electrode layer configured on the first electrode layer.

[0010] It may be that the first electrode further includes: a third electrode layer, arranged on the second electrode layer.

[0011] The first electrode layer and the third electrode layer may be formed of the same material.

[0012] It may be that the thickness of the first layer is greater than the sum of the thickness of the insulating layer and the thickness of the first electrode.

[0013] The insulating layer may cover the first layer and the second layer.

[0014] The first region of the first electrode may be electrically connected to the second layer through a contact hole penetrating the insulating layer.

[0015] The substrate may include a first sub-pixel and a second sub-pixel that are adjacent to each other, and the second region of the first electrode is arranged at a boundary between the first sub-pixel and the second sub-pixel.

[0016] The light-emitting structure of the first sub-pixel and the light-emitting structure of the second sub-pixel may be separated on the second region of the first electrode.

[0017] The second electrode of the first sub-pixel and the second electrode of the second sub-pixel may be connected on the second region of the first electrode.

[0018] The first layer and the second layer may include a conductive substance.

[0019] A display device according to an embodiment for solving the above-mentioned problem includes: a first layer, which is arranged in a light-emitting area of ​​a substrate; a second layer, which is arranged on the first layer; an anode electrode, which is arranged on the second layer; a conductive pattern, which is arranged on the same layer as the first layer and is electrically separated from the anode electrode; a light-emitting structure, which is arranged on the anode electrode and the conductive pattern; and a cathode electrode, which is arranged on the light-emitting structure, and the anode electrode and the conductive pattern include the same substance.

[0020] Alternatively, the display device may further include: a circuit layer disposed between the substrate and the anode electrode.

[0021] It may be that the second layer is electrically connected to the circuit layer through a contact hole penetrating the first layer.

[0022] The anode electrode may be electrically connected to the circuit layer through a contact hole penetrating the second layer and the first layer.

[0023] It may be that the first layer includes an insulating material, and the second layer includes a conductive material.

[0024] It may be that the first layer and the second layer include insulating materials.

[0025] Details of other embodiments are included in the detailed description and drawings.

[0026] Through the above-mentioned embodiment, the first electrode can be separated without a separate etching process, so an ultra-high resolution display device can be realized. In addition, part or all of the light-emitting structure can be separated in the boundary area between adjacent sub-pixels, so the current flowing out to the adjacent sub-pixels can be minimized.

[0027] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0029] Figure 2 It is shown Figure 1 A block diagram of an embodiment of any one of the sub-pixels.

[0030] Figure 3 It is shown Figure 2 Circuit diagram of an embodiment of a sub-pixel.

[0031] Figure 4 It is shown Figure 1 A plan view of an embodiment of a display panel.

[0032] Figure 5 It is shown Figure 4 An exploded perspective view of a portion of a display panel.

[0033] Figure 6 It is shown Figure 5 A plan view of an embodiment of any one of the pixels.

[0034] Figure 7 It is shown along Figure 6 A cross-sectional view of an embodiment of the line II'.

[0035] Figure 8 It is shown Figure 7 A cross-sectional view of an embodiment of an anode electrode.

[0036] Fig. 9 It is shown Figure 7 A cross-sectional view of another embodiment of an anode electrode.

[0037] Fig.10 It is shown along Figure 6 FIG. 1 is a cross-sectional view of another embodiment of the line II'.

[0038] Fig.11 It is shown along Figure 6 A cross-sectional view of yet another embodiment of the line II'.

[0039] Fig.12 It is shown that the Figure 7 A cross-sectional view of an embodiment of a light emitting structure in any one of the first to third light emitting elements.

[0040] Fig.13 It is shown that the Figure 7A cross-sectional view of another embodiment of a light emitting structure in any one of the first to third light emitting elements.

[0041] Fig.14 It is shown Figure 5 A plan view of another embodiment of any one of the pixels.

[0042] Fig.15 It is shown Figure 5 A plan view of yet another embodiment of any one of the pixels.

[0043] Fig.16 is a block diagram illustrating an embodiment of a display system.

[0044] Fig.17 It is shown Fig.16 A three-dimensional diagram of an application example of a display system.

[0045] Fig.18 It is shown Fig.17 Figure 1 is a diagram of a head mounted display device worn on a user.

[0046] Figures 19 to 26 4 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention according to process steps. DETAILED DESCRIPTION

[0047] Hereinafter, the preferred embodiments according to the present invention may be described in detail with reference to the attached drawings. It may be noted that, in order not to obscure the main points of the present invention, only the parts necessary for understanding the work according to the present invention are described in the following description, and the description of the parts other than these is omitted. The present invention is not limited to the embodiments described herein, and may also be embodied in other forms. However, the embodiments described herein are provided in order to explain the technical concept of the present invention in detail to a person having general knowledge in the technical field to which the present invention belongs to so as to be easily implemented.

[0048] Throughout the specification, when any part is "connected" to other parts, it includes not only the case of "direct connection", but also the case of "indirect connection" with other parts in between. The terms used herein are only used to illustrate specific embodiments and are not used to limit the present invention. Throughout the specification, when any part "includes" any constituent element, this means that unless there is a special record to the contrary, other constituent elements may also be included, rather than excluding other constituent elements. "At least any one of X, Y and Z" and "at least any one selected from the group consisting of X, Y and Z" can be interpreted as one X, one Y, one Z or any combination of two or more of X, Y and Z (for example, XYZ, XYY, YZ, ZZ). Here, "and / or" can include all combinations of one or more of the corresponding components.

[0049] Here, although the terms first, second, etc. may be used to describe a variety of constituent elements, these constituent elements are not limited by these terms. These terms may be used only to distinguish one constituent element from other constituent elements. Therefore, without departing from the scope of this disclosure, the first constituent element may also be the second constituent element.

[0050] Spatially relative terms such as "below" or "above" can be used for illustrative purposes, by which the relationship between an element or feature and other elements or features can be described as shown in the accompanying drawings. Spatially relative terms mean that in addition to the directions described in the accompanying drawings, they also include different directions when used, working and / or manufactured. For example, if the device shown in the accompanying drawings is turned over, the element described as being "below" other elements or features can be located in the direction "above" other elements or features. Therefore, in an embodiment, terms such as "below" can include both upper and lower directions. Moreover, the device can be oriented in other directions besides this (for example, rotated 90 degrees or in other directions), and thus, the spatially relative terms used here can be interpreted according to the circumstances.

[0051] Various embodiments may be described with reference to the accompanying drawings that illustrate ideal embodiments. Thus, for example, it is contemplated that the shapes may vary depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the characteristic shapes shown, and should be construed to include variations in shape that result from manufacturing, for example. Thus, the shapes shown in the accompanying drawings may not represent the actual shape of a region of the device, and the embodiments are not limited thereto.

[0052] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0053] Reference Figure 1 The display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0054] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through the first to m-th gate lines GL1 ˜GLm. The sub-pixels SP may be connected to the data driver 130 through the first to n-th data lines DL1 ˜DLn.

[0055] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Thus, each of the sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels in the sub-pixel SP may constitute a pixel PXL. For example, Figure 1 As shown, three sub-pixels SP can constitute one pixel PXL.

[0056] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first to m-th gate lines GL1-GLm. The gate driver 120 may output a gate signal to the first to m-th gate lines GL1-GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, and the like.

[0057] In an embodiment, first to mth emission control lines EL1 ˜ELm connected to the sub-pixels SP in the row direction may also be provided. In this case, the gate driver 120 may include an emission control driver configured to control the first to mth emission control lines EL1 ˜ELm, and the emission control driver may operate according to the control of the controller 150 .

[0058] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiment is not limited thereto. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically divided, and such drivers may be disposed on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. In this way, the gate driver 120 may be disposed around the display panel 110 in various forms according to the embodiment.

[0059] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first to nth data lines DL1-DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0060] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to nth data lines DL1-DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to mth gate lines GL1-GLm, a data signal corresponding to the image data DATA may be applied to the data lines DL1-DLm. Thus, the corresponding sub-pixel SP may generate light corresponding to the data signal. Thus, an image may be displayed on the display panel 110.

[0061] In an embodiment, the gate driver 120 and the data driver 130 may include CMOS (complementary metal-oxide semiconductor) circuit elements.

[0062] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and provide the generated voltages to the components of the display device 100. For example, the voltage generator 140 may be configured to receive an input voltage from outside the display device 100, adjust the received voltage, and adjust the adjusted voltage, thereby generating a plurality of voltages.

[0063] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first and second power supply voltages VDD and VSS may be provided to the sub-pixel SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a voltage level lower than the first power supply voltage VDD. In another embodiment, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0064] In addition, the voltage generator 140 may also generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, in a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a predetermined reference voltage may be applied to the first to nth data lines DL1 to DLn, and the voltage generator 140 may generate such a reference voltage.

[0065] The controller 150 may control all operations of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling their display from the outside. The controller 150 may respond to the control signal CTRL to provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0066] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110 and output the image data DATA. In an embodiment, the controller 150 may align the input image data IMG to be suitable for sub-pixels SP of a row unit and output the image data DATA.

[0067] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be assembled into one integrated circuit. Figure 1 As shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally distinguished components within one driver integrated circuit DIC. In another embodiment, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component distinguished from the driver integrated circuit DIC.

[0068] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature of its surroundings and generate temperature data TEP representing the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0069] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust the data signal and the first and second power supply voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0070] Figure 2 It is shown Figure 1 A block diagram of any embodiment of a sub-pixel. Figure 2 The configuration in Figure 1 The sub-pixel SPij in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) of the sub-pixels SP.

[0071] Reference Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0072] The light emitting element LD may be connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN may be a transmission node. Figure 1The first power supply voltage node VDD and the second power supply voltage node VSSN are transmitted Figure 1 A node of a second power supply voltage VSS.

[0073] The anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light emitting element LD may be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0074] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first to m-th gate lines GL1-GLm, Figure 1 The i-th light emitting control line ELi among the first to m-th light emitting control lines EL1-ELm and Figure 1 The sub-pixel circuit SPC may be configured to control the light emitting element LD according to a signal received through such a signal line.

[0075] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. Figure 2 As shown, the i-th gate line GLi may include first and second sub-gate lines SGL1 and SGL2. The sub-pixel circuit SPC may operate in response to gate signals received through the first and second sub-gate lines SGL1 and SGL2. Thus, when the i-th gate line GLi includes more than two sub-gate lines, the sub-pixel circuit SPC may operate in response to gate signals received through corresponding sub-gate lines.

[0076] The sub-pixel circuit SPC may operate in response to a light emission control signal received through the i-th light emission control line ELi. In an embodiment, the i-th light emission control line ELi may include one or more sub-light emission control lines. In the case where the i-th light emission control line ELi includes more than two sub-light emission control lines, the sub-pixel circuit SPC may operate in response to a light emission control signal received through the corresponding sub-light emission control line.

[0077] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may respond to at least one of the gate signals received through the first and second sub-gate lines SGL1 and SGL2, thereby storing a voltage corresponding to the data signal. The sub-pixel circuit SPC may respond to the light emission control signal received through the i-th light emission control line ELi, thereby adjusting a current flowing from the first power supply voltage node VDDN through the light emitting element LD to the second power supply voltage node VSSN according to the stored voltage. Thus, the light emitting element LD may generate light of a brightness corresponding to the data signal.

[0078] Figure 3 It is shown Figure 2 Circuit diagram of an embodiment of a sub-pixel.

[0079] Reference Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0080] The sub-pixel circuit SPC can be connected to the i-th gate line GLi', the i-th light emitting control line ELi' and the j-th data line DLj. Figure 2 When compared with the i-th gate line GLi, the i-th gate line GLi' may further include a third sub-gate line SGL3. Figure 2 When compared with the i-th light emitting control line ELi′, the i-th light emitting control line ELi′ may include a first sub-light emitting control line SEL1 and a second sub-light emitting control line SEL2.

[0081] The sub-pixel circuit SPC may include first to sixth transistors T1 ˜ T6 and first and second capacitors C1 , C2 .

[0082] The first transistor T1 may be connected between the first power supply voltage node VDDN and the first node N1. The gate of the first transistor T1 may be connected to the second node N2, whereby the first transistor T1 is turned on according to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0083] The second transistor T2 may be connected between the jth data line DLj and the second node N2. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1, whereby the second transistor T2 is turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0084] The third transistor T3 may be connected between the first node N1 and the second node N2. A gate of the third transistor T3 may be connected to the second sub-gate line SGL2, and thus the third transistor T3 is turned on in response to a gate signal of the second sub-gate line SGL2.

[0085] The fourth transistor T4 may be connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. A gate of the fourth transistor T4 may be connected to the second sub-light emitting control line SEL2, and thus the fourth transistor T4 is turned on in response to the light emitting control signal of the second sub-light emitting control line SEL2.

[0086] The fifth transistor T5 may be connected between the anode electrode AE ​​of the light emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN may be configured to transmit an initialization voltage. In an embodiment, the initialization voltage may be transmitted by Figure 1 The initialization voltage may be provided by the voltage generator 140. In another embodiment, the initialization voltage may be provided by an external device of the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3, and thus, the fifth transistor T5 is turned on in response to the gate signal of the third sub-gate line SGL3.

[0087] The sixth transistor T6 may be connected between the first power supply voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 may be connected to the first sub-light emitting control line SEL1, whereby the sixth transistor T6 is turned on in response to the light emitting control signal of the first sub-light emitting control line SEL1.

[0088] The first capacitor C1 may be connected between the second transistor T2 and the second node N2. The second capacitor C2 may be connected between the first power supply voltage node VDDN and the second node N2.

[0089] In this way, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2. However, the embodiment is not limited thereto. The sub-pixel circuit SPC may be implemented as any of various forms of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include 2 transistors and one capacitor. According to an embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-light-emitting control lines included in the i-th light-emitting control line ELi' may change.

[0090] The first to sixth transistors T1 to T6 may be P-type transistors. Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal Oxide Silicon Field Effect Transistor). However, the embodiment is not limited thereto. For example, at least one of the first to sixth transistors T1 to T6 may be replaced by an N-type transistor.

[0091] In an embodiment, the first to sixth transistors T1 ˜ T6 may include an amorphous silicon semiconductor, a monocrystalline silicon, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0092] The light emitting element LD may include an anode electrode AE, a cathode electrode CE, and a light emitting layer. The light emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. When the data signal transmitted through the j-th data line DLj is reflected to the voltage of the second node N2, when the light emitting control signals of the first and second sub-light emitting control lines SEL1 and SEL2 are enabled at a low level, the fourth and sixth transistors T4 and T6 may be turned on. The first transistor T1 may be turned on according to the voltage of the second node N2, whereby a current may flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light according to the amount of the flowing current.

[0093] Figure 4 It is shown Figure 1 A plan view of an embodiment of a display panel.

[0094] Reference Figure 4 , as Figure 1 The display panel DP of the embodiment of the display panel 110 may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be configured around the display area DA.

[0095] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0096] In the case where the display panel DP is used as a display screen for a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP may be disposed very close to the user's eyes. In this case, a relatively high integration of sub-pixels SP may be required. In order to increase the integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on the silicon substrate, i.e., the substrate SUB. A display device 100 (see FIG. 1 ) including a display panel DP formed on a silicon substrate, i.e., the substrate SUB Figure 1 ) can be called OLEDoS (OLED on Silicon) display device.

[0097] The sub-pixels SP may be arranged in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a pentile form. It may be that the first direction DR1 is a row direction and the second direction DR2 is a column direction.

[0098] Two or more sub-pixels among the plurality of sub-pixels SP may constitute one pixel PXL.

[0099] The non-display area NDA on the substrate SUB may be configured to control the components of the sub-pixel SP. Figure 1 Wiring lines connected to the sub-pixels SP, such as the first to m-th gate lines GL1 ˜GLm and the first to n-th data lines DL1 ˜DLn, may be disposed in the non-display area NDA.

[0100] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 may be integrated in the non-display area NDA of the display panel DP. In an embodiment, Figure 1 The gate driver 120 is mounted on the display panel DP and configured in the non-display area NDA. In another embodiment, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 can be configured in the non-display area NDA to sense the temperature of the display panel DP.

[0101] The non-display area NDA on the substrate SUB may be provided with a pad PD. The pad PD may be electrically connected to the sub-pixel SP through a wiring. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 ˜DLn.

[0102] The pad PD can connect the display panel DP to the display device 100 (see Figure 1 In the embodiment, the voltage and signal required for the operation of the components included in the display panel DP can be obtained from Figure 1 The driver integrated circuit DIC is provided through the pad PD. For example, the first to nth data lines DL1-DLn can be connected to the driver integrated circuit DIC through the pad PD. For example, the first and second power supply voltages VDD and VSS can be received from the driver integrated circuit DIC through the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0103] In an embodiment, the circuit board can be electrically connected to the pad PD using a conductive adhesive component such as an anisotropic conductive film. In this case, the circuit board can be a flexible circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC can be mounted on the circuit board and electrically connected to the pad PD.

[0104] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight and / or curved edges. For example, the display area DA may have a polygonal, circular, semicircular, elliptical, or other shapes.

[0105] In an embodiment, the display panel DP may have a flat display surface. In another embodiment, the display panel DP may have a display surface that is at least partially round. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In this case, the display panel DP and / or the substrate SUB may include a material having a flexible property.

[0106] Figure 5 It is shown Figure 4 An exploded perspective view of a portion of a display panel. Figure 5 In order to make the description clear and concise, the following can be shown schematically: Figure 4 The portion of the display panel DP corresponding to two pixels PXL1 and PXL2 among the pixels PXL. The portion of the display panel DP corresponding to the remaining pixels may also be configured in the same manner.

[0107] Reference Figure 4 as well as Figure 5 Each of the first and second pixels PXL1 and PXL2 may include first to third sub-pixels SP1, SP2, and SP3. However, the embodiment is not limited thereto. For example, each of the first and second pixels PXL1 and PXL2 may include four sub-pixels or two sub-pixels.

[0108] exist Figure 5 It can be shown that when viewed in the third direction DR3 intersecting the first and second directions DR1 and DR2, the first to third sub-pixels SP1, SP2, SP3 have a quadrilateral shape and have the same size as each other. However, the embodiment is not limited thereto. The first to third sub-pixels SP1, SP2, SP3 can be deformed to have various shapes.

[0109] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0110] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may also be provided from a bulk wafer, an epitaxial layer, an SOI (Silicon On Insulator) layer or a SeOI (Semiconductor On Insulator) layer, etc. In another embodiment, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a PI (Polyimide) substrate.

[0111] A pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and an electrode pattern disposed between the insulating layers. The electrode pattern of the pixel circuit layer PCL may function as at least a portion of a circuit element, wiring, etc. The electrode pattern may include copper, but the embodiment is not limited thereto.

[0112] The circuit element may include a sub-pixel circuit SPC of each of the first to third sub-pixels SP1, SP2, SP3 (refer to Figure 2 ). The sub-pixel circuit SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as an electrode pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes separated from each other. For example, each capacitor may include electrodes separated from each other on a plane defined by the first and second directions DR1 and DR2. For example, each capacitor may include electrodes separated from each other in a third direction DR3 via an insulating layer.

[0113] The wiring of the pixel circuit layer PCL may include a signal line connected to each of the first to third sub-pixels SP1, SP2, SP3, such as a gate line, a light emitting control line, and a data line. The wiring may also include a signal line connected to each of the first to third sub-pixels SP1, SP2, SP3. Figure 2 The wiring may also include a wiring connected to the first power supply voltage node VDDN. Figure 2 Wiring of the second power supply voltage node VSSN.

[0114] The light emitting element layer LDL may include an anode electrode AE, a light emitting structure EMS, and a cathode electrode CE.

[0115] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may be electrically connected to the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0116] The light emitting structure EMS may be disposed on the anode electrode AE. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0117] In an embodiment, the light emitting structure EMS may extend across the first to third sub-pixels SP1 ˜ SP3 . In this case, at least a portion of the layers within the light emitting structure EMS may be at least partially separated (or disconnected) or bent at the boundaries between the first to third sub-pixels SP1 ˜ SP3 .

[0118] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third sub-pixels SP1 to SP3. In this way, the cathode electrode CE may be provided as a common electrode for the first to third sub-pixels SP1 to SP3.

[0119] The cathode electrode CE may be a thin metal layer having a thickness that allows light emitted from the light emitting structure EMS to be transmitted. The cathode electrode CE may be formed of a metal substance or a conductive substance to have a thin thickness. In an embodiment, the cathode electrode CE may include at least one of various transparent conductive substances including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In another embodiment, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a mixture thereof. However, the material of the cathode electrode CE is not limited thereto.

[0120] It can be understood that any one of the anode electrodes AE, the portion of the light emitting structure EMS overlapping with them, and the portion of the cathode electrode CE overlapping with them constitute a light emitting element LD (see Figure 2). Each of the light-emitting elements of the first to third sub-pixels SP1-SP3 may include an anode electrode AE, a portion of the light-emitting structure EMS overlapping with it, and a portion of the cathode electrode CE overlapping with it. In each of the first to third sub-pixels SP1-SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transferred to the light-emitting layer of the light-emitting structure EMS to form excitons, and when the excitons transition from an excited state to a ground state, light may be generated. The brightness of the light may be determined according to the amount of current flowing through the light-emitting layer. According to the structure of the light-emitting layer, the wavelength range of the generated light may be determined.

[0121] An encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ). For example, the organic film may include an organic insulating material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, or benzocyclobutene (BCB). However, the materials of the organic film and the inorganic film of the encapsulation layer TFE are not limited thereto.

[0122] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (AlO x The thin film including aluminum oxide may be located on the upper side of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower side of the encapsulation layer TFE facing the light emitting element layer LDL.

[0123] The thin film including aluminum oxide may be formed by atomic layer deposition (ALD). However, the embodiment is not limited thereto. The encapsulation layer TFE may further include a thin film formed of at least one of various substances suitable for improving encapsulation efficiency.

[0124] The optical function layer OFL may be disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0125] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the light emitting structure EMS and selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively, and each of such color filters CF allows light of a wavelength range corresponding to the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. At least a portion of the color filter CF may be omitted depending on the light emitted from the light emitting structure EMS of each sub-pixel.

[0126] The lens array LA may be configured on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may output light emitted from the light-emitting structure EMS to a predetermined path, thereby improving light extraction efficiency. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the outer coating OC. In an embodiment, the lens LS may include an organic substance. In an embodiment, the lens LS may include an acrylic substance. However, the material of the lens LS is not limited thereto.

[0127] The outer coating OC may be disposed on the lens array LA. The outer coating OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS and / or the pixel circuit layer PCL. The outer coating OC may include various substances suitable for protecting its lower layer from foreign matter such as dust and moisture. For example, the outer coating OC may include at least one of an inorganic insulating film and an organic insulating film. For example, the outer coating OC may include epoxy resin, but the embodiment is not limited thereto. The outer coating OC may have a lower refractive index than the lens array LA.

[0128] The cover window CW may be disposed on the outer coating layer OC. The cover window CW may be configured to protect its lower layer. The cover window CW may have a higher refractive index than the outer coating layer OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect the constituent elements disposed thereunder. In another embodiment, the cover window CW may be omitted.

[0129] Figure 6 It is shown Figure 5 A plan view of any one embodiment of a pixel. Figure 6 For the sake of clarity and simplicity, it can be shown schematically Figure 5 The first pixel PXL1 of the first and second pixels PXL1 and PXL2 may be configured similarly to the first pixel PXL1.

[0130] Reference Figure 5 as well as Figure 6 , the first pixel PXL1 may include first to third sub-pixels SP1 ˜ SP3 arranged in the first direction DR1 .

[0131] The first subpixel SP1 may include a first light emitting area EMA1 and a non-light emitting area NEA around the first light emitting area EMA1. The second subpixel SP2 may include a second light emitting area EMA2 and a non-light emitting area NEA around the second light emitting area EMA2. The third subpixel SP3 may include a third light emitting area EMA3 and a non-light emitting area NEA around the third light emitting area EMA3.

[0132] The first light emitting area EMA1 may be formed from a light emitting structure EMS (see Figure 5 ) portion emits light. The second light emitting area EMA2 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third light emitting area EMA3 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3.

[0133] Figure 7 It is shown along Figure 6 A cross-sectional view of an embodiment of the line II'. Figure 8 It is shown Figure 7 A cross-sectional view of an embodiment of an anode electrode. Fig. 9 It is shown Figure 7 A cross-sectional view of another embodiment of an anode electrode.

[0134] Reference Figure 7, a pixel circuit layer PCL may be provided on a substrate SUB. The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon-germanium.

[0135] The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. It may be that the transistor T_SP1 of the first sub-pixel SP1 is included in the sub-pixel circuit SPC of the first sub-pixel SP1 (refer to Figure 2 ), the transistor T_SP2 of the second sub-pixel SP2 is any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 is any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 In the figure, for the sake of clarity and simplicity of description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0136] The transistor T_SP1 of the first subpixel SP1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0137] The source region SRA and the drain region DRA may be disposed in the substrate SUB. Alternatively, a well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed separately from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0138] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0139] The multiple layers included in the pixel circuit layer PCL include insulating layers and electrode patterns arranged between the insulating layers, and such electrode patterns may include first and second electrode patterns CP1 and CP2. The first electrode pattern CP1 may be electrically connected to the drain region DRA via a drain connection portion DRC penetrating one or more insulating layers. The second electrode pattern CP2 may be electrically connected to the source region SRA via a source connection portion SRC penetrating one or more insulating layers.

[0140] As the gate electrode GE and the first and second electrode patterns CP1 and CP2 are connected to other circuit elements and / or wirings, the transistor T_SP1 of the first sub-pixel SP1 may be provided as any one of the transistors of the first sub-pixel SP1.

[0141] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 may be configured similarly to the transistor T_SP1 of the first sub-pixel SP1 .

[0142] As such, the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first to third sub-pixels SP1 ˜ SP3 .

[0143] A through hole layer VIAL may be configured on the pixel circuit layer PCL. The through hole layer VIAL may cover the pixel circuit layer PCL and have an overall flat surface. The through hole layer VIAL may be configured to flatten the steps on the pixel circuit layer PCL. The through hole layer VIAL may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbon nitride (SiCN), but the embodiment is not limited thereto.

[0144] The light emitting element layer LDL may be disposed on the via layer VIAL and may include first to third reflective electrodes RE1-RE3, a planarization layer PLNL, a first layer L1, a second layer L2, an insulating layer INS, first to third anode electrodes AE1-AE3, a light emitting structure EMS, and a cathode electrode CE.

[0145] On the via layer VIAL, the first to third reflective electrodes RE1 to RE3 may be respectively disposed in the first to third sub-pixels SP1 to SP3. Each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element disposed in the pixel circuit layer PCL through a via hole penetrating the via layer VIAL.

[0146] The first to third reflective electrodes RE1 to RE3 may function as a full mirror that reflects light emitted from the light emitting structure EMS toward the display surface (or the cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may respectively include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more substances selected from them, but the embodiment is not limited thereto.

[0147] In an embodiment, a connection electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connection electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited thereto. In an embodiment, the corresponding reflective electrode may be located between the multiple layers of the connection electrode.

[0148] A buffer pattern BFP may be disposed under at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbon nitride, but the embodiment is not limited thereto. By configuring the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0149] The first to third reflective electrodes RE1 to RE3 may function as full reflectors, and the cathode electrode CE may function as a half reflector. The light emitted from the light-emitting layer of the light-emitting structure EMS may be amplified by at least partially traveling back and forth between the corresponding reflective electrodes and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE may be understood as a resonance distance for the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0150] The first sub-pixel SP1 may have a resonance distance shorter than other sub-pixels by the buffer pattern BFP. The resonance distance adjusted in this way can effectively and efficiently amplify light of a specific wavelength range (e.g., red color). Thus, the first sub-pixel SP1 can effectively and efficiently output light of the corresponding wavelength range.

[0151] exist Figure 7 It is shown that the buffer pattern BFP is provided to the first sub-pixel SP1 but not to the second and third sub-pixels SP2 and SP3, but the embodiment is not limited thereto. The buffer pattern may also be provided in at least one of the second and third sub-pixels SP2 and SP3 to adjust the resonance distance of at least one of the second and third sub-pixels SP2 and SP3. For example, the first to third sub-pixels SP1 to SP3 correspond to red, green, and blue, respectively, the distance between the first reflective electrode RE1 and the cathode electrode CE is shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE is shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0152] In order to flatten the steps between the first to third reflective electrodes RE1-RE3, a planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1-RE3. The planarization layer PLNL may entirely cover the first to third reflective electrodes RE1-RE3 and the via layer VIAL, thereby having a flat surface. In an embodiment, the planarization layer PLNL may be omitted.

[0153] The first layer L1 may be disposed in the first to third light emitting regions EMA1 to EMA3 (see Figure 6 ). The first layer L1 may be disposed on the planarization layer PLNL. The first layer L1 may be directly disposed on the planarization layer PLNL. The first layer L1 of the first to third sub-pixels SP1 to SP3 may be electrically connected to the first to third reflective electrodes RE1 to RE3 disposed thereunder through through holes respectively penetrating the planarization layer PLNL. The first layer L1 of the first sub-pixel SP1 may be electrically connected to the first reflective electrode RE1 through the first through hole VIA1 penetrating the planarization layer PLNL. The first layer L1 of the second sub-pixel SP2 may be electrically connected to the second reflective electrode RE2 through the second through hole VIA2 penetrating the planarization layer PLNL. The first layer L1 of the third sub-pixel SP3 may be electrically connected to the third reflective electrode RE3 through the third through hole VIA3 penetrating the planarization layer PLNL. The first layer L1 of the first to third sub-pixels SP1 to SP3 may be electrically connected to the pixel circuit layer PCL through the first to third reflective electrodes RE1 to RE3, respectively. In an embodiment, the first layer L1 may include a conductive material. As an example, the first layer L1 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and an alloy of two or more substances selected from them, but the embodiment is not limited thereto.

[0154] The second layer L2 may be disposed on the first layer L1. The second layer L2 may be directly disposed on the first layer L1. The second layer L2 may be electrically connected to the first layer L1. The second layer L2 may be electrically connected to the pixel circuit layer PCL through the first layer L1 and the first to third reflective electrodes RE1 to RE3. In an embodiment, the second layer L2 may include a conductive material. As an example, the second layer L2 may include at least one of titanium (Ti), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and an alloy of two or more substances selected from them, but the embodiment is not limited thereto.

[0155] The insulating layer INS may be disposed on the first layer L1 and the second layer L2. The insulating layer INS may cover the first layer L1 and the second layer L2. The insulating layer INS may cover the first layer L1 and the second layer L2 to prevent the conductive pattern AE' (or the second region of the first electrode) described later from contacting the first layer L1 and the second layer L2. The insulating layer INS may play a role in electrically separating the first layer L1, the second layer L2 and / or the first to third anode electrodes AE1, AE2, AE3 from the conductive pattern AE'. The insulating layer INS may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium nitride (ZrO x ), hafnium nitride (HfO x ) or titanium nitride (TiO x ) include various types of inorganic insulating materials, but are not necessarily limited to them.

[0156] The first to third anode electrodes AE1, AE2, AE3 (or the first region of the first electrode) and the conductive pattern AE' (or the second region of the first electrode) may be disposed on the insulating layer INS. The first to third anode electrodes AE1, AE2, AE3 and the conductive pattern AE' may include the same material. The first to third anode electrodes AE1, AE2, AE3 and the conductive pattern AE' may be formed simultaneously in the same process, but are not necessarily limited thereto.

[0157] The first to third anode electrodes AE1, AE2, AE3 and the conductive pattern AE' may be separated by the first layer L1 and the second layer L2. Thus, the first to third anode electrodes AE1, AE2, AE3 and the conductive pattern AE' may be electrically separated. The first to third anode electrodes AE1, AE2, AE3 may be disposed on the first layer L1 and the second layer L2. The first to third anode electrodes AE1, AE2, AE3 may overlap with the first layer L1 and the second layer L2 in the third direction DR3.

[0158] In an embodiment, the first to third anode electrodes AE1, AE2, AE3 and the conductive pattern AE' may be separated by the tip structure of the first layer L1 and the second layer L2. As an example, the first electrode may be fully evaporated to form the first region of the first electrode, i.e., the first to third anode electrodes AE1, AE2, AE3, on the first layer L1 and the second layer L2, and the second region, i.e., the conductive pattern AE', separated from the first region of the first electrode may be formed at the boundary between the first to third sub-pixels SP1-SP3. In this case, a separate etching process for separating the first to third anode electrodes AE1, AE2, AE3 is not required, and thus an ultra-high resolution display device may be realized.

[0159] The conductive pattern AE' may be disposed between the first layer L1 of the first to third sub-pixels SP1 to SP3. The conductive pattern AE' may be disposed in the second layer L2 of the first to third sub-pixels SP1 to SP3. The conductive pattern AE' may be disposed at the boundary between the first to third sub-pixels SP1 to SP3. The conductive pattern AE' may be disposed in the boundary area BDA between adjacent sub-pixels.

[0160] The first to third anode electrodes AE1, AE2, and AE3 may overlap the first to third reflective electrodes RE1 to RE3 in the third direction DR3, respectively. When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may have the same Figure 6 The first to third light emitting areas EMA1 to EMA3 have similar shapes.

[0161] The first to third anode electrodes AE1, AE2, and AE3 may be electrically connected to the second layer L2 through contact holes penetrating the insulating layer INS, respectively. The first to third anode electrodes AE1, AE2, and AE3 may be electrically connected to the pixel circuit layer PCL through the second layer L2, the first layer L1, and the first to third reflective electrodes RE1 to RE3. The first anode electrode AE1 may be electrically connected to the second layer L2 of the first sub-pixel SP1 through a contact hole penetrating the insulating layer INS. The second anode electrode AE2 may be electrically connected to the second layer L2 of the second sub-pixel SP2 through a contact hole penetrating the insulating layer INS. The third anode electrode AE3 may be electrically connected to the second layer L2 of the third sub-pixel SP3 through a contact hole penetrating the insulating layer INS.

[0162] In an embodiment, the first to third anode electrodes AE1 ˜ AE3 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or the like. x), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO) and the like. However, the materials of the first to third anode electrodes AE1-AE3 are not limited thereto. For example, the first to third anode electrodes AE1-AE3 may include titanium nitride.

[0163] In an embodiment, a void VD may be formed in the boundary area BDA. The void VD may cause a discontinuity to be formed in the light emitting structure EMS in the boundary area BDA. For example, the light emitting structure EMS may be at least partially separated (or disconnected) or bent in the boundary area BDA by the void VD.

[0164] The gap VD may be arranged between the first layer L1 of the first to third sub-pixels SP1 to SP3. The gap VD may be arranged between the second layer L2 of the first to third sub-pixels SP1 to SP3. The gap VD may be arranged between the first to third anode electrodes AE1, AE2, AE3. The gap VD may be arranged on the conductive pattern AE'. The gap VD may overlap with the conductive pattern AE' in the third direction DR3. Some or all of the multiple layers included in the light emitting structure EMS may be at least partially separated or bent in the boundary area BDA by the gap VD. For example, at least one charge generation layer included in the light emitting structure EMS may be separated in the boundary area BDA by the gap VD.

[0165] Reference Figure 8 , the thickness TAE of the anode electrode AE ​​in the third direction DR3 may be the same as the thickness TAE' of the conductive pattern AE' in the third direction DR3. According to the embodiment, the conductive pattern AE' is thinner the closer it is to the first layer L1 and the second layer L2, and the portion in contact with the insulating layer INS may be formed relatively thick. However, the thickness variation of the conductive pattern AE' is not necessarily limited thereto, and various changes may be made according to the embodiment.

[0166] The width WL1 of the first layer L1 in the first direction DR1 may be smaller than the width WL2 of the second layer L2 in the first direction DR1. The second layer L2 may completely overlap with the first layer L1. One side of the second layer L2 may protrude more than one side of the first layer L1. The other side of the second layer L2 may protrude more than the other side of the first layer L1. That is, the first layer L1 and the second layer L2 may be formed into a pointed structure. The length WL21 by which the second layer L2 protrudes more than the first layer L1 in the first direction DR1 may be thicker than the thickness TAE of the anode electrode AE ​​in the third direction DR3 or the thickness TAE' of the conductive pattern AE' in the third direction DR3. The thickness TL1 of the first layer L1 in the third direction DR3 may be greater than the sum of the thickness TI of the insulating layer INS in the third direction DR3 and the thickness TAE' of the conductive pattern AE' in the third direction DR3. In the following example, Figure 8 When the first layer L1, the second layer L2, the insulating layer INS and / or the anode electrode AE ​​are formed with such thickness and width, the first to third anode electrodes AE1, AE2, AE3 and the conductive pattern AE' can be easily separated by the tip structure of the first layer L1 and the second layer L2.

[0167] The anode electrode AE ​​and the conductive pattern AE' may include more than two conductive layers. As an example, the anode electrode AE ​​may include a first electrode layer CL1 and a second electrode layer CL2 disposed on the first electrode layer CL1. The conductive pattern AE' may include a first electrode layer CL1' and a second electrode layer CL2' disposed on the first electrode layer CL1'. The first electrode layers CL1 and CL1' may be disposed between the insulating layer INS and the second electrode layers CL2 and CL2'. The second electrode layers CL2 and CL2' may be directly disposed on the first electrode layers CL1 and CL1'.

[0168] The first electrode layers CL1, CL1' may include at least one of silver (Ag), aluminum (Al), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more thereof, but the embodiment is not limited thereto.

[0169] The second electrode layers CL2 and CL2' may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), x), at least one of transparent conductive materials such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc., but the embodiment is not limited thereto.

[0170] Reference Fig. 9 , the anode electrode AE ​​may include a first electrode layer CL1, a second electrode layer CL2 configured on the first electrode layer CL1, and a third electrode layer CL3 configured on the second electrode layer CL2. The conductive pattern AE' may include a first electrode layer CL1', a second electrode layer CL2' configured on the first electrode layer CL1', and a third electrode layer CL3' configured on the second electrode layer CL2'. The first electrode layers CL1 and CL1' may be configured between the insulating layer INS and the second electrode layers CL2 and CL2'. The second electrode layers CL2 and CL2' may be configured between the first electrode layers CL1 and CL1' and the third electrode layers CL3 and CL3'. The second electrode layers CL2 and CL2' may be directly configured on the first electrode layers CL1 and CL1'. The third electrode layers CL3 and CL3' may be directly configured on the second electrode layers CL2 and CL2'.

[0171] The first electrode layers CL1, CL1' may include at least one of silver (Ag), aluminum (Al), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more thereof, but the embodiment is not limited thereto.

[0172] The second electrode layers CL2 and CL2' may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), x ), at least one of transparent conductive materials such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc., but the embodiment is not limited thereto.

[0173] The third electrode layer CL3, CL3' may include at least one of silver (Ag), aluminum (Al), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more substances selected from these, but the embodiment is not limited thereto.

[0174] The first electrode layers CL1 , CL1 ′ and the third electrode layers CL3 , CL3 ′ may include the same material, but are not necessarily limited thereto.

[0175] Refer again Figure 7 , the light emitting structure EMS can be configured on the first to third anode electrodes AE1, AE2, AE3 and the conductive pattern AE'. The light emitting structure EMS can be configured across the first to third sub-pixels SP1~SP3 as a whole. Some or all of the multiple layers included in the light emitting structure EMS can be at least partially separated or bent on the conductive pattern AE'. Some or all of the multiple layers included in the light emitting structure EMS can be at least partially separated or bent in the boundary area BDA through the gap VD. For example, at least one charge generation layer included in the light emitting structure EMS can be separated in the boundary area BDA through the gap VD. Thus, when the display panel DP is operating, the current flowing out from each of the first to third sub-pixels SP1~SP3 to the sub-pixels adjacent thereto through the layers included in the light emitting structure EMS can be reduced. Therefore, the first to third light emitting elements LD1~LD3 can operate with relatively high reliability.

[0176] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be provided in common to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0177] The cathode electrode CE may be connected in the boundary area BDA to be commonly provided to the first to third sub-pixels SP1 ˜ SP3 . The cathode electrode CE may be connected on the conductive pattern AE′ in the boundary area BDA . The cathode electrode CE may be connected on the gap VD in the boundary area BDA .

[0178] The first anode electrode AE1, the portion of the light emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, the portion of the light emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, the portion of the light emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 may constitute a third light emitting element LD3.

[0179] An encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0180] An optical function layer OFL may be configured on the encapsulation layer TFE. In an embodiment, the optical function layer OFL may be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the optical function layer OFL may be manufactured separately and attached to the encapsulation layer TFE through an adhesive layer APL. The adhesive layer APL may also perform a function of protecting the lower layer including the encapsulation layer TFE.

[0181] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may allow light of different wavelength ranges to pass through. For example, the first to third color filters CF1 to CF3 may allow red, green, and blue colors of light to pass through, respectively.

[0182] In an embodiment, the first to third color filters CF1 ˜ CF3 may partially overlap in the boundary area BDA. In another embodiment, the first to third color filters CF1 ˜ CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 ˜ CF3.

[0183] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 may respectively output the light emitted from the first to third light emitting elements LD1 to LD3 in a predetermined path, thereby improving light extraction efficiency.

[0184] Fig.10 It is shown along Figure 6 FIG. 1 is a cross-sectional view of another embodiment of the line II'.

[0185] Reference Fig.10 The first layer L1 and / or the second layer L2 may include an insulating material. As an example, the first layer L1 and / or the second layer L2 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium nitride (ZrO x ), hafnium nitride (HfO x ) or titanium nitride (TiO x) including various types of insulating materials, but not necessarily limited thereto. Thus, when the first layer L1 and / or the second layer L2 are respectively formed of insulating materials, the insulating layer INS for electrically separating the first layer L1 and / or the second layer L2 from the conductive pattern AE' can be omitted (refer to Figure 7 ).

[0186] The first to third anode electrodes AE1, AE2, AE3 (or the first region of the first electrode) may be arranged on the second layer L2. The first to third anode electrodes AE1, AE2, AE3 may be arranged directly on the second layer L2. The conductive pattern AE' (or the second region of the first electrode) may be arranged on the planarization layer PLNL. The conductive pattern AE' may be arranged directly on the planarization layer PLNL. The conductive pattern AE' may be arranged on the same layer as the first layer L1.

[0187] The first to third anode electrodes AE1, AE2, and AE3 may be electrically connected to the first to third reflective electrodes RE1 to RE3 through through holes penetrating the second layer L2, the first layer L1, and / or the planarization layer PLNL, respectively. The first to third anode electrodes AE1, AE2, and AE3 may be electrically connected to the pixel circuit layer PCL through the first to third reflective electrodes RE1 to RE3. The first anode electrode AE1 may be electrically connected to the first reflective electrode RE1 through the first through hole VIA1 penetrating the second layer L2, the first layer L1, and / or the planarization layer PLNL. The second anode electrode AE2 may be electrically connected to the second reflective electrode RE2 through the second through hole VIA2 penetrating the second layer L2, the first layer L1, and / or the planarization layer PLNL. The third anode electrode AE3 may be electrically connected to the third reflective electrode RE3 through the third through hole VIA3 penetrating the second layer L2, the first layer L1, and / or the planarization layer PLNL. The first to third anode electrodes AE1, AE2, and AE3 may be electrically connected to the pixel circuit layer PCL through the first to third reflective electrodes RE1 to RE3, respectively.

[0188] Fig.11 It is shown along Figure 6 A cross-sectional view of yet another embodiment of the line II'.

[0189] Reference Fig.11 , the first layer L1 may include an insulating material. As an example, the first layer L1 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium nitride (ZrO x ), hafnium nitride (HfOx ) or titanium nitride (TiO x ) including various kinds of insulating materials, but not necessarily limited thereto. Thus, in the case where the first layer L1 is formed of an insulating material, the insulating layer INS (refer to Figure 7 ). The first to third anode electrodes AE1, AE2, AE3 (or the first region of the first electrode) may be arranged on the second layer L2. The first to third anode electrodes AE1, AE2, AE3 may be directly arranged on the second layer L2. The conductive pattern AE' (or the second region of the first electrode) may be arranged on the planarization layer PLNL. The conductive pattern AE' may be directly arranged on the planarization layer PLNL. The conductive pattern AE' may be arranged on the same layer as the first layer L1.

[0190] The second layer L2 may include a conductive material. As an example, the second layer L2 includes at least one of titanium (Ti), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and an alloy of two or more of these materials, but the embodiment is not limited thereto. In this way, when the second layer L2 is formed of a conductive material, the second layers L2 of the first to third sub-pixels SP1 to SP3 may be electrically connected to the first to third reflective electrodes RE1 to RE3 through through holes penetrating the first layer L1 and / or the planarization layer PLNL, respectively. The second layers L2 of the first to third sub-pixels SP1 to SP3 may be electrically connected to the pixel circuit layer PCL through the first to third reflective electrodes RE1 to RE3, respectively. The second layer L2 of the first sub-pixel SP1 may be electrically connected to the first reflective electrode RE1 through the first through hole VIA1 penetrating the first layer L1 and / or the planarization layer PLNL. The second layer L2 of the second subpixel SP2 may be electrically connected to the second reflective electrode RE2 via the second through hole VIA2 penetrating the first layer L1 and / or the planarization layer PLNL. The second layer L2 of the third subpixel SP3 may be electrically connected to the third reflective electrode RE3 via the third through hole VIA3 penetrating the first layer L1 and / or the planarization layer PLNL. The second layers L2 of the first to third subpixels SP1-SP3 may be electrically connected to the pixel circuit layer PCL via the first to third reflective electrodes RE1-RE3, respectively.

[0191] The first to third anode electrodes AE1, AE2, AE3 may be electrically connected to the second layer L2, respectively. The first to third anode electrodes AE1, AE2, AE3 may be electrically connected to the pixel circuit layer PCL through the second layer L2 and / or the first to third reflective electrodes RE1-RE3.

[0192] Fig.12 It is shown that the Figure 7A cross-sectional view of an embodiment of a light emitting structure in any one of the first to third light emitting elements.

[0193] Reference Fig.12 The light emitting structure EMS may have a tandem structure in which the first and second light emitting units EU1 and EU2 are stacked. Figure 7 Each of the first to third light emitting elements LD1 to LD3 has substantially the same configuration.

[0194] Each of the first and second light-emitting units EU1 and EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0195] Each of the first and second hole transport units HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and an electron blocking layer as needed. The first and second hole transport units HTU1 and HTU2 may have the same structure or different structures.

[0196] Each of the first and second electron transport units ETU1 and ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first and second electron transport units ETU1 and ETU2 may have the same structure or different structures.

[0197] The connection layer that can be provided in the form of a charge generation layer CGL can be arranged between the first light emitting unit EU1 and the second light emitting unit EU1 and connect them to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, and NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiment is not limited thereto.

[0198] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors from each other. Light emitted from each of the first light-emitting layer EML1 and the second light-emitting layer EML2 may be mixed and recognized as white light. For example, the first light-emitting layer EML1 may generate blue light and the second light-emitting layer EML2 may generate yellow light. In an embodiment, the second light-emitting layer EML2 may include a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light in a stacked structure. The red light and the green light may be mixed to provide yellow light. In this case, an intermediate layer may be further configured between the first and second sub-light-emitting layers, the intermediate layer being configured to perform a function of transporting holes and / or a function of blocking the transport of electrons.

[0199] In another embodiment, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color.

[0200] The light emitting structure EMS may be formed by vacuum evaporation, inkjet printing, etc., but the embodiment is not limited thereto.

[0201] Fig.13 It is shown that the Figure 7 A cross-sectional view of another embodiment of a light emitting structure in any one of the first to third light emitting elements.

[0202] Reference Fig.13 The light emitting structure EMS' may have a series structure in which the first to third light emitting units EU1' to EU3' are stacked. Figure 7 Each of the first to third light emitting elements LD1 to LD3 has substantially the same configuration.

[0203] Each of the first to third light-emitting units EU1'-EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be configured between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be configured between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be configured between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0204] Each of the first to third hole transport units HTU1'~HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first to third hole transport units HTU1'~HTU3' may have the same structure or different structures from each other.

[0205] Each of the first to third electron transport units ETU1'-ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. as needed. The first to third electron transport units ETU1'-ETU3' may have the same structure as each other or different structures from each other.

[0206] The first charge generation layer CGL1' may be disposed between the first light emitting portion EU1' and the second light emitting portion EU2'. The second charge generation layer CGL2' may be disposed between the second light emitting portion EU2' and the third light emitting portion EU3'.

[0207] In an embodiment, the first to third light emitting layers EML1' to EML3' may generate light of different colors from each other. Light emitted from each of the first to third light emitting layers EML1' to EML3' may be mixed and recognized as white light. For example, the first light emitting layer EML1' may generate blue light, the second light emitting layer EML2' may generate green light, and the third light emitting layer EML3' may generate red light.

[0208] In another embodiment, two or more light-emitting layers among the first to third light-emitting layers EML1 ′ to EML3 ′ may generate light of the same color.

[0209] Fig.14 It is shown Figure 5 A plan view of another embodiment of any one of the pixels.

[0210] Reference Fig.14 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′˜ SP3 ′.

[0211] The first sub-pixel SP1' may include a first light emitting area EMA1' and a non-light emitting area NEA' around the first light emitting area EMA1'. The second sub-pixel SP2' may include a second light emitting area EMA2' and a non-light emitting area NEA' around the second light emitting area EMA2'. The third sub-pixel SP3' may include a third light emitting area EMA3' and a non-light emitting area NEA' around the third light emitting area EMA3'.

[0212] The first sub-pixel SP1' and the second sub-pixel SP2' may be arranged in the second direction DR2. The third sub-pixel SP3' may be arranged in the first direction DR1 with respect to each of the first and second sub-pixels SP1' and SP2'.

[0213] The second sub-pixel SP2' may have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' may have a larger area than the second sub-pixel SP2'. Thus, the second light-emitting area EMA2' may have a larger area than the first light-emitting area EMA1', and the third light-emitting area EMA3' may have a larger area than the second light-emitting area EMA2'. However, the embodiment is not limited thereto. For example, the first and second sub-pixels SP1' and SP2' may have substantially the same area as each other, and the third sub-pixel SP3' may have a larger area than each of the first and second sub-pixels SP1' and SP2'. In this way, the areas of the first to third sub-pixels SP1' to SP3' may be variously modified according to the embodiment.

[0214] Fig.15 It is shown Figure 5 A plan view of yet another embodiment of any one of the pixels.

[0215] Reference Fig.15 The first sub-pixel SP1" may include a first light-emitting area EMA1" and a non-light-emitting area NEA" around the first light-emitting area EMA1". The second sub-pixel SP2" may include a second light-emitting area EMA2" and a non-light-emitting area NEA" around the second light-emitting area EMA2". The third sub-pixel SP3" may include a third light-emitting area EMA3" and a non-light-emitting area NEA" around the third light-emitting area EMA3".

[0216] When viewed in the third direction DR3, the first to third sub-pixels SP1"-SP3" may have a polygonal shape. For example, the shapes of the first to third sub-pixels SP1"-SP3" may be as follows: Fig.15 As shown, it is a hexagon.

[0217] When viewed in the third direction DR3, the first to third light emitting regions EMA1 ″~EMA3 ″ may have a circular shape. However, the embodiment is not limited thereto. For example, each of the first to third light emitting regions EMA1 ″~EMA3 ″ may have a polygonal shape.

[0218] The first and third sub-pixels SP1 ″ and SP3 ″ may be arranged in the first direction DR1 . The second sub-pixel SP2 ″ may be arranged in a direction (or a diagonal direction) inclined at an acute angle with respect to the first sub-pixel SP1 ″ with respect to the second direction DR2 .

[0219] Figure 6, Fig.14 as well as Fig.15 The arrangement of the sub-pixels shown is an example, and the embodiment is not limited thereto. Each pixel may include more than two sub-pixels, the sub-pixels may be arranged in various ways, each of the sub-pixels may have various shapes, and each of their light-emitting regions may also have various shapes.

[0220] Fig.16 is a block diagram illustrating an embodiment of a display system.

[0221] Reference Fig.16 The display system 1000 may include a processor 1100 and one or more display devices 1210 , 1220 .

[0222] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system to control them.

[0223] exist Fig.16 It can be shown that the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 through a first channel CH1, and connected to the second display device 1220 through a second channel CH2.

[0224] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 In this case, the first image data IMG1 and the first control signal CTRL1 can be respectively used as Figure 1 The input image data IMG and the control signal CTRL are provided.

[0225] Through the second channel CH2, the processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1In this case, the second image data IMG2 and the second control signal CTRL2 can be respectively used as Figure 1 The input image data IMG and the control signal CTRL are provided.

[0226] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet PC, a smartwatch, a watch phone, a PMP (portable multimedia player), a navigator, and a UMPC (ultra mobile personal computer). The display system 1000 may include at least one of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0227] Fig.17 It is shown Fig.16 A three-dimensional diagram of an application example of a display system.

[0228] Reference Fig.17 , Fig.16 The display system 1000 may be applicable to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that can be worn on the head of a user.

[0229] The head-mounted display device 2000 may include a headband 2100 and a display device storage shell 2200. The headband 2100 may be connected to the display device storage shell 2200. The headband 2100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. It may be that the horizontal band is configured to surround the side of the user's head, and the vertical band is configured to surround the upper part of the user's head. However, the embodiment is not limited thereto. For example, the headband 2100 may also be implemented in the form of a glasses frame, a helmet, etc.

[0230] The display device storage case 2200 can store Fig.16 The first and second display devices 1210 and 1220. The display device storage case 2200 can also store Fig.16 Processor 1100.

[0231] Fig.18 It is shown Fig.17 Figure 1 is a diagram of a head mounted display device worn on a user.

[0232] Reference Fig.18 The head mounted display device 2000 is provided with a first display panel DP1 of a first display device 1210 and a second display panel DP2 of a second display device 1220. The head mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0233] In the display device receiving case 2200, the right eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user. In the display device receiving case 2200, the left eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user.

[0234] The image output from the first display panel DP1 may be displayed in the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract light from the first display panel DP1 toward the right eye of the user. The right eye lens RLNS may perform an optical function for adjusting the viewing and listening distance between the first display panel DP1 and the right eye of the user.

[0235] The image output from the second display panel DP2 may be displayed in the user's left eye through the left eye lens LLNS. The left eye lens LLNS may refract light from the second display panel DP2 toward the user's left eye. The left eye lens LLNS may perform an optical function for adjusting the viewing and listening distance between the second display panel DP2 and the user's left eye.

[0236] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics from each other. In this case, each display panel may output images corresponding to the sub-regions of the multi-channel lens, respectively, and the output images may be displayed to the user through the corresponding sub-regions, respectively.

[0237] Next, a method for manufacturing the display device according to the above-mentioned embodiment will be described.

[0238] Figures 19 to 26 4 is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention according to process steps. Figures 19 to 26 As an illustration Figures 7 to 9 A cross-sectional view of a method for manufacturing a display device is schematically shown for ease of explanation, and detailed markings are omitted.

[0239] Reference Fig.19 as well as Fig. 20 First, a first layer L1 and a second layer L2 are formed on the substrate SUB. The first layer L1 and the second layer L2 can be formed in the first to third light emitting regions EMA1 to EMA3 of the substrate SUB (refer to Figure 6 ).

[0240] The first layer L1 may be formed on the planarization layer PLNL. The first layer L1 may be directly formed on the planarization layer PLNL. The first layers L1 of the first to third sub-pixels SP1 to SP3 may be electrically connected to the first to third reflective electrodes RE1 to RE3 disposed thereunder through the through holes penetrating the planarization layer PLNL, respectively. The first layer L1 of the first sub-pixel SP1 may be electrically connected to the first reflective electrode RE1 through the first through hole VIA1 penetrating the planarization layer PLNL. The first layer L1 of the second sub-pixel SP2 may be electrically connected to the second reflective electrode RE2 through the second through hole VIA2 penetrating the planarization layer PLNL. The first layer L1 of the third sub-pixel SP3 may be electrically connected to the third reflective electrode RE3 through the third through hole VIA3 penetrating the planarization layer PLNL. The first layers L1 of the first to third sub-pixels SP1 to SP3 may be electrically connected to the pixel circuit layer PCL through the first to third reflective electrodes RE1 to RE3, respectively. In an embodiment, the first layer L1 may be formed of a conductive material. As an example, the first layer L1 can be formed by at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and an alloy of two or more substances selected from them, but the embodiment is not limited thereto.

[0241] The second layer L2 may be formed on the first layer L1. The second layer L2 may be directly formed on the first layer L1. The second layer L2 may be formed of a conductive material. As an example, the second layer L2 may be formed of at least one of titanium (Ti), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and an alloy of two or more substances selected therefrom, but the embodiment is not limited thereto.

[0242] The width WL1 of the first layer L1 in the first direction DR1 may be formed smaller than the width WL2 of the second layer L2 in the first direction DR1. The second layer L2 may completely overlap the first layer L1. One side of the second layer L2 may protrude more than one side of the first layer L1. The other side of the second layer L2 may protrude more than the other side of the first layer L1.

[0243] Reference Fig.21 as well as Fig. 22Then, an insulating layer INS is formed on the first layer L1 and the second layer L2. The insulating layer INS may cover the first layer L1 and the second layer L2. The insulating layer INS may be formed by x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium nitride (ZrO x ), hafnium nitride (HfO x ) or titanium nitride (TiO x ) is formed by various types of inorganic insulating materials including, but not necessarily limited to.

[0244] Reference Figure 23 to Figure 25 , and then the first electrodes AE and AE' are formed on the insulating layer INS. The first electrodes AE and AE' can be fully evaporated on the insulating layer INS. The first region of the first electrode, namely the anode electrode AE, and the second region of the first electrode, namely the conductive pattern AE', can be separated by the tip structure of the first layer L1 and the second layer L2. As an example, the first region of the first electrode, namely the anode electrode AE, is formed on the first layer L1 and the second layer L2, and the second region, namely the conductive pattern AE', separated from the first region of the first electrode is formed between the first layer L1 of the first to third sub-pixels SP1 to SP3 or between the second layer L2 of the first to third sub-pixels SP1 to SP3. In this case, a separate etching process for separating the first to third anode electrodes AE1, AE2, and AE3 is not required, so an ultra-high resolution display device can be realized as described above.

[0245] The first to third anode electrodes AE1, AE2, and AE3 may be electrically connected to the second layer L2 through contact holes penetrating the insulating layer INS, respectively. The first anode electrode AE1 may be electrically connected to the second layer L2 of the first sub-pixel SP1 through a contact hole penetrating the insulating layer INS. The second anode electrode AE2 may be electrically connected to the second layer L2 of the second sub-pixel SP2 through a contact hole penetrating the insulating layer INS. The third anode electrode AE3 may be electrically connected to the second layer L2 of the third sub-pixel SP3 through a contact hole penetrating the insulating layer INS.

[0246] Reference Fig.24, the thickness TAE of the anode electrode AE ​​in the third direction DR3 may be the same as the thickness TAE' of the conductive pattern AE' in the third direction DR3. According to the embodiment, the conductive pattern AE' is thinner the closer it is to the first layer L1 and the second layer L2, and the portion in contact with the insulating layer INS may be formed relatively thick. However, the thickness variation of the conductive pattern AE' is not necessarily limited thereto, and various deformations may be performed according to the embodiment.

[0247] The length WL21 by which the second layer L2 protrudes from the first layer L1 in the first direction DR1 may be thicker than the thickness TAE of the anode electrode AE ​​in the third direction DR3 or the thickness TAE' of the conductive pattern AE' in the third direction DR3. The thickness TL1 of the first layer L1 in the third direction DR3 may be greater than the sum of the thickness TI of the insulating layer INS in the third direction DR3 and the thickness TAE of the anode electrode AE ​​in the third direction DR3. The thickness TL1 of the first layer L1 in the third direction DR3 may be greater than the sum of the thickness TI of the insulating layer INS in the third direction DR3 and the thickness TAE' of the conductive pattern AE' in the third direction DR3.

[0248] The anode electrode AE ​​and the conductive pattern AE' may be formed by more than two conductive layers. As an example, the anode electrode AE ​​may include a first electrode layer CL1 and a second electrode layer CL2 formed on the first electrode layer CL1. The conductive pattern AE' may include a first electrode layer CL1' and a second electrode layer CL2' formed on the first electrode layer CL1'. The first electrode layers CL1 and CL1' may be arranged between the insulating layer INS and the second electrode layers CL2 and CL2'. The second electrode layers CL2 and CL2' may be directly formed on the first electrode layers CL1 and CL1'.

[0249] Reference Fig.25 , the anode electrode AE ​​may include a first electrode layer CL1, a second electrode layer CL2 formed on the first electrode layer CL1, and a third electrode layer CL3 formed on the second electrode layer CL2. The conductive pattern AE' may include a first electrode layer CL1', a second electrode layer CL2' formed on the first electrode layer CL1', and a third electrode layer CL3' formed on the second electrode layer CL2'. The first electrode layers CL1 and CL1' may be arranged between the insulating layer INS and the second electrode layers CL2 and CL2'. The second electrode layers CL2 and CL2' may be arranged between the first electrode layers CL1 and CL1' and the third electrode layers CL3 and CL3'. The second electrode layers CL2 and CL2' may be directly formed on the first electrode layers CL1 and CL1'. The third electrode layers CL3 and CL3' may be directly formed on the second electrode layers CL2 and CL2'.

[0250] Reference Fig.26, and then a light-emitting structure EMS is formed on the anode electrode AE ​​and the conductive pattern AE'. The light-emitting structure EMS can be formed as a whole across the first to third sub-pixels SP1 to SP3. Some or all of the multiple layers included in the light-emitting structure EMS can be at least partially separated or bent on the conductive pattern AE'. Some or all of the multiple layers included in the light-emitting structure EMS can be at least partially separated or bent in the boundary area BDA through the gap VD. For example, at least one charge generation layer included in the light-emitting structure EMS can be separated in the boundary area BDA through the gap VD. Thus, when the display panel DP is operating, the current flowing out from each of the first to third sub-pixels SP1 to SP3 to the sub-pixels adjacent thereto through the layers included in the light-emitting structure EMS can be reduced. Therefore, as described above, the first to third light-emitting elements LD1 to LD3 can operate with relatively high reliability.

[0251] Then, a cathode electrode CE, an encapsulation layer TFE, an optical functional layer OFL, an outer coating OC and a cover window CW are sequentially formed on the light-emitting structure EMS, thereby completing Figures 7 to 9 display device.

[0252] Although specific embodiments are described herein, other embodiments and variations can be derived from the above description. Therefore, the concept of the present invention is not limited to such embodiments, but also relates to the attached claims, various obvious variations and equivalents.

Claims

1. A display device, It is characterized in that include: The first layer is arranged in the light emitting area of ​​the substrate; A second layer, configured on the first layer; an insulating layer, disposed on the second layer; A first electrode, disposed on the insulating layer; A light-emitting structure is disposed on the first electrode; as well as A second electrode is disposed on the light-emitting structure. The first electrode includes a first region on the first layer and the second layer and a second region electrically separated from the first region.

2. The display device according to claim 1, It is characterized in that The width of the second layer in the first direction is greater than the width of the first layer in the first direction.

3. The display device according to claim 1, It is characterized in that The length by which the second layer protrudes from the first layer is greater than the thickness of the first electrode.

4. The display device according to claim 1, It is characterized in that The light emitting structure is at least partially separated on the second region of the first electrode.

5. The display device according to claim 1, It is characterized in that The first electrode includes a first electrode layer configured on the insulating layer and a second electrode layer configured on the first electrode layer.

6. The display device according to claim 5, It is characterized in that The first electrode further includes: a third electrode layer, which is configured on the second electrode layer.

7. The display device according to claim 6, It is characterized in that The first electrode layer and the third electrode layer are formed of the same material.

8. The display device according to claim 1, It is characterized in that The thickness of the first layer is greater than the sum of the thickness of the insulating layer and the thickness of the first electrode.

9. The display device according to claim 1, It is characterized in that The insulating layer covers the first layer and the second layer.

10. The display device according to claim 1, It is characterized in that The first region of the first electrode is electrically connected to the second layer through a contact hole penetrating the insulating layer.

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