Display panel and display device

Abstract

The utility model provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate, a transistor layer, a first source-drain metal layer, a second source-drain metal layer and a pixel layer which are sequentially stacked, the display panel comprises circuit areas arranged in an array mode, and the circuit areas are provided with pixel driving circuits for driving sub-pixels. The display panel is provided with a first connecting line and a data signal line, and the circuit area column comprises a plurality of circuit areas which are sequentially arranged in the column direction; the first connecting line comprises first sub-lines which are alternately arranged on the first source-drain metal layer and second sub-lines which are arranged on the second source-drain metal layer in sequence, and the adjacent first sub-lines and second sub-lines are electrically connected through via holes; the display panel further comprises a second connecting line. Wherein at least part of the first connecting lines are electrically connected with the data signal wires through the second connecting lines. The display panel and the display device applying the display panel have the effects of reducing the processing cost and improving the display quality.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display device and a display apparatus. Background Art

[0002] The FIP (Fan-integrated-in-panel) technology can integrate the diagonal traces of the fan-in area in the display area, which can significantly reduce the lower border space of the display panel, achieve an extremely narrow border of the product and improve the visual experience, and has been widely used in the display panel design. In the prior art, the fan-shaped lines are routed with 3 layers of source-drain metal layers, that is, the vertical fan-shaped lines use the third source-drain metal layer, and the horizontal fan-shaped lines use the second source-drain metal layer, but there are problems of low integration and high cost.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Utility Model

[0004] The purpose of the present disclosure is to overcome the above deficiencies of the prior art, and to provide a display panel and a display device applying the display panel, so as to improve the display quality of the display panel and the display device applying the display panel and reduce its processing cost.

[0005] According to one aspect of the present disclosure, a display panel is provided, which includes a substrate, a transistor layer, a first source-drain metal layer, a second source-drain metal layer, and a pixel layer that are sequentially stacked; wherein, the display panel includes circuit areas arranged in an array along the row direction and the column direction, and pixel driving circuits for driving sub-pixels are provided in the circuit areas;

[0006] The display panel is provided with data signal traces corresponding to each column of the circuit areas and extending along the column direction, and first connection lines corresponding to at least some columns of the circuit areas and extending along the column direction are also provided, wherein the columns of the circuit areas include a plurality of the circuit areas arranged in sequence along the column direction;

[0007] The first connection line includes first sub-lines alternately arranged on the first source-drain metal layer and second sub-lines arranged on the second source-drain metal layer, and adjacent first sub-lines and second sub-lines are electrically connected through vias;

[0008] The display panel further includes a second connection line extending along the row direction; wherein, at least some of the first connection lines are electrically connected to the data signal traces through the second connection line.

[0009] According to an embodiment of the present disclosure, the first connection line includes connection leads and initialization voltage auxiliary traces alternately arranged in sequence along the row direction;

[0010] Wherein, the connection leads are electrically connected to the data signal traces through the second connection line;

[0011] The initialization voltage auxiliary traces are used to be electrically connected to the initialization voltage traces located in the first source-drain metal layer or the transistor layer.

[0012] According to an embodiment of the present disclosure, the initialization voltage traces include a first initialization voltage trace for loading a first initialization voltage and extending along the row direction, a second initialization voltage trace for loading a second initialization voltage and extending along the row direction, and a third initialization voltage trace for loading a third initialization voltage and extending along the row direction;

[0013] The initialization voltage auxiliary traces include a first initialization voltage auxiliary trace for being electrically connected to the first initialization voltage trace, a second initialization voltage auxiliary trace for being electrically connected to the second initialization voltage trace, and a third initialization voltage auxiliary trace for being electrically connected to the third initialization voltage trace.

[0014] According to an embodiment of the present disclosure, among the initialization voltage auxiliary traces arranged along the row direction, the first initialization voltage auxiliary trace, the second initialization voltage auxiliary trace, and the third initialization voltage auxiliary trace are arranged in a periodic sequence in turn.

[0015] According to an embodiment of the present disclosure, the second connection line is disposed on the first source-drain metal layer and extends along the row direction;

[0016] The transistor layer includes a first gate layer and a second gate layer stacked in sequence; the second gate layer is provided with a first initialization voltage trace for loading a first initialization voltage, and the first initialization voltage trace is used to reset the gate of the driving transistor of the pixel driving circuit;

[0017] The extending trajectory of the second connection line is the same as that of the adjacent first initialization voltage trace.

[0018] According to an embodiment of the present disclosure, the first connection line is disposed between two adjacent circuit area columns.

[0019] According to an embodiment of the present disclosure, the pixel driving circuit has a storage capacitor;

[0020] The transistor layer includes a first gate layer and a second gate layer stacked in sequence;

[0021] The storage capacitor includes a first electrode plate located in the first gate layer and a second electrode plate located in the second gate layer;

[0022] The orthographic projection of the connection position of the first sub-line and the second sub-line on the substrate overlaps with a part of the orthographic projection of the second electrode plate on the substrate.

[0023] According to an embodiment of the present disclosure, the transistor layer includes a first gate layer and a second gate layer stacked in sequence; the second gate layer is provided with a first initialization voltage trace for loading a first initialization voltage, and the first initialization voltage trace is used to reset the gate of the driving transistor of the pixel driving circuit;

[0024] The first connection line includes a first initialization voltage auxiliary trace connected to the first initialization voltage trace;

[0025] The first source-drain metal layer has a first initialization voltage transfer structure, one end of the first initialization voltage transfer structure is electrically connected to the first initialization voltage auxiliary trace, and the other end is connected to the first initialization voltage trace through a via.

[0026] According to an embodiment of the present disclosure, the pixel driving circuit has a storage capacitor;

[0027] The transistor layer includes a first gate layer and a second gate layer stacked in sequence; the storage capacitor includes a first electrode plate located in the first gate layer and a second electrode plate located in the second gate layer;

[0028] The orthographic projection of the first initialization voltage transfer structure on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate.

[0029] According to an embodiment of the present disclosure, there is a wiring space between the first initialization voltage transfer structure and the first initialization voltage trace and the first sub-line;

[0030] The pixel driving circuit has a data writing transistor;

[0031] The first source-drain metal layer is provided with a data signal transfer structure in the wiring space, one end of the data signal transfer structure is connected to the data signal trace, and the other end is electrically connected to the first pole of the data writing transistor.

[0032] According to an embodiment of the present disclosure, the pixel driving circuit has a node control transistor;

[0033] The display panel is provided with a third initialization voltage trace for loading a third initialization voltage, and the third initialization voltage trace is electrically connected to the first pole of the node control transistor;

[0034] The first initialization voltage transfer structure is disposed between the third initialization voltage trace and the second connection line.

[0035] According to an embodiment of the present disclosure, the transistor layer includes a first gate layer and a second gate layer stacked in sequence; the second gate layer is provided with a second initialization voltage trace for loading a second initialization voltage, and the second initialization voltage trace is used to reset the driving transistor of the pixel driving circuit;

[0036] The first connection line includes a second initialization voltage auxiliary trace connected to the second initialization voltage trace;

[0037] The display panel further includes a power supply voltage trace corresponding to each of the circuit regions; the second initialization voltage auxiliary trace is located between the data signal trace and the power supply voltage trace;

[0038] The first source-drain metal layer has a second initialization voltage transfer structure, the second initialization voltage transfer structure is located between the second initialization voltage auxiliary trace and the power supply voltage trace, and one end of the second initialization voltage transfer structure is electrically connected to the second initialization voltage auxiliary trace through a via, and the other end is electrically connected to the second initialization voltage trace through a via.

[0039] According to an embodiment of the present disclosure, the pixel driving circuit has a driving transistor, a data writing transistor, and a node control transistor; the second pole of the data writing transistor, the first pole of the driving transistor, and the second pole of the node control transistor are electrically connected;

[0040] The display panel is provided with a third initialization voltage trace for loading a third initialization voltage, and the third initialization voltage trace is electrically connected to the first pole of the node control transistor;

[0041] The first connection line includes a third initialization voltage auxiliary trace electrically connected to the third initialization voltage trace;

[0042] The pixel driving circuit has a node control transistor;

[0043] The first source-drain metal layer has a third initialization voltage transfer structure, one end of the third initialization voltage transfer structure is electrically connected to the end of the first sub-line of the third initialization voltage auxiliary trace, and the other end is electrically connected to the third initialization voltage trace.

[0044] According to an embodiment of the present disclosure, the second connection line is disposed adjacent to the third initialization voltage trace;

[0045] The third initialization voltage transfer structure is disposed on a side of the third initialization voltage trace away from the second connection line;

[0046] The projection of one end of the second sub-line of the first connection line on the substrate substrate overlaps with the projection of the third initialization voltage trace on the substrate substrate, and the other end overlaps with the projection of the second connection line on the substrate substrate in the projection on the substrate substrate.

[0047] According to an embodiment of the present disclosure, the initialization voltage auxiliary trace further includes a third sub-line located in the second source-drain metal layer, and the third sub-line and the second sub-line are alternately arranged in sequence and connected to each other to form an integral trace.

[0048] According to another aspect of the present disclosure, a display device is provided, including the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0050] Figure 1 It is a schematic diagram of the distribution and connection relationship of the first connection line and the second connection line in the display panel in an embodiment of the present disclosure.

[0051] Figure 2 It is a schematic diagram of the film layer structure of the display panel in an embodiment of the present disclosure.

[0052] Figure 3 It is a schematic diagram of the pixel driving circuit in an embodiment of the present disclosure.

[0053] Figure 4 It is a schematic diagram of the structure of the low-temperature polycrystalline silicon semiconductor layer in an embodiment of the present disclosure.

[0054] Figure 5 It is a schematic diagram of the structure of the first gate layer in an embodiment of the present disclosure.

[0055] Figure 6 It is a schematic diagram of the structure of the second gate layer in an embodiment of the present disclosure.

[0056] Figure 7In an embodiment of the present disclosure, it is a schematic structural diagram of the first source-drain metal layer.

[0057] Figure 8 In an embodiment of the present disclosure, it is a schematic structural diagram of the first source-drain metal layer.

[0058] Figure 9 In an embodiment of the present disclosure, it is a schematic structural diagram of the first source-drain metal layer.

[0059] Figure 10 In an embodiment of the present disclosure, it is a schematic structural diagram of the first source-drain metal layer.

[0060] Figure 11 In an embodiment of the present disclosure, it is a schematic structural diagram of the second source-drain metal layer.

[0061] Figure 12 In an embodiment of the present disclosure, it is a schematic structural diagram of the second source-drain metal layer.

[0062] Figure 13 In an embodiment of the present disclosure, it is a schematic stacked structural diagram of the second gate layer, the first source-drain metal layer, and the second source-drain metal layer.

[0063] Figure 14 In an embodiment of the present disclosure, it is a schematic structural diagram of the first source-drain metal layer.

[0064] Figure 15 In an embodiment of the present disclosure, it is a schematic structural diagram of the second source-drain metal layer.

[0065] Figure 16 In an embodiment of the present disclosure, it is a schematic structural diagram of the second source-drain metal layer.

[0066] Explanation of the reference numerals: PA, circuit area; VTL, initialization voltage routing; VTL1, first initialization voltage routing; VTL2, second initialization voltage routing; VTL3, third initialization voltage routing; VTLX, initialization voltage auxiliary routing; VTL1X, first initialization voltage auxiliary routing; VTL2X, second initialization voltage auxiliary routing; VTL3X, third initialization voltage auxiliary routing; MA1, first bridge portion; MA2, second bridge portion; MA3, third bridge portion; MA4, fourth bridge portion; MA5, fifth bridge portion; MA6, sixth bridge portion; MA7, seventh bridge portion; MA8, eighth bridge portion; VT1P, first initialization voltage transfer structure; VT2P, second initialization voltage transfer structure Voltage transfer structure; VT3P, third initialization voltage transfer structure; SBT, substrate; DRL, driving layer; TL, transistor layer; BSM, metal light shielding layer; PSCL, low temperature polysilicon semiconductor layer; Buff1, first buffer layer; Buff2, second buffer layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GT1, first gate layer; GT2, second gate layer; ILD, interlayer dielectric layer; SD1, first source and drain metal layer; SD2, second source and drain metal layer; PLN1, first planarization layer; PLN2, second planarization layer; PDL, pixel definition layer; COML, common electrode layer; EL, light emitting function layer; PEL, pixel electrode layer; PIXL, image pixel layer; PIX, sub-pixel; TFE, thin film encapsulation layer; T1, first reset transistor; M1, first polysilicon conductive structure; M2, second polysilicon conductive structure; M3, third polysilicon conductive structure; T2, threshold compensation transistor; M4, fourth polysilicon conductive structure; M5, fifth polysilicon conductive structure; T3, driving transistor; T4, data writing transistor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; T7, electrode reset transistor; T8, node control transistor; CST, storage capacitor; CP1, first electrode plate; CP2, second electrode plate; Vinit, initialization voltage; Vinit1, first initialization voltage; Vinit2, second initialization voltage; Vinit3, the third initialization voltage; RP, the first reset signal; RH, the second reset signal; N1, the first node; N2, the second node; N3, the third node; N4, the fourth node; N5, the fifth node; GN, the first scan signal; Vdata, the data voltage; GP, the second scan signal; VDD, the power supply voltage; VSS, the reference voltage; EM, the enable signal; T1A, the channel region of the first capacitor reset transistor; T2A, the channel region of the threshold compensation transistor; T3A, the channel region of the driving transistor; T4A, the channel region of the data writing transistor; T5A, the channel region of the first light emission control transistor; T6A, the channel region of the second light emission control transistor; T7A, the channel region of the electrode reset transistor;T8A, channel region of the node control transistor; HB1, first upper via region; HB2, second upper via region; HB3, third upper via region; HB4, fourth upper via region; HB5, fifth upper via region; HB6, sixth upper via region; HB7, seventh upper via region; HB8, eighth upper via region; HB9, ninth upper via region; HB10, tenth upper via region; HB11, eleventh upper via region; HB12, twelfth upper via region; HB13, thirteenth upper via region; HB14, fourteenth upper via region; HB15, fifteenth upper via region; HB16, sixteenth upper via region; HB17, seventeenth upper via region; HB18, eighteenth upper via region; HA1, first lower via region; HA2, second lower via region; HA3, third lower via region; HA4, fourth lower via region; HA5, fifth lower via region; HA6, sixth lower via region; HA7, seventh lower via region; HA8, eighth lower via region; HA9, ninth lower via region; HA10, tenth lower via region; HA11, eleventh lower via region; HA12, twelfth lower via region; HA13, thirteenth lower via region; HA14, fourteenth lower via region; HA15, fifteenth lower via region; HA16, sixteenth lower via region; HA17, seventeenth lower via region; HA18, eighteenth lower via region; RPL, first capacitor reset control signal line; RHL, second capacitor reset control signal line; EML, enable signal line; GNL, first scan signal trace; DH, row direction; DV, column direction; DL, data signal trace; LA, first connection line; LA1, first sub-line; LA2, second sub-line; LB, second connection line; LL, connection lead; P1, bulge portion; Detailed implementation manners

[0067] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0068] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions in the examples described in the drawings. It can be understood that if the device of the icon is flipped so that it is upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0069] In an embodiment of the present disclosure, a thin film transistor includes an active layer, a gate insulating layer, and a gate that are stacked. Among them, the active layer is located in the semiconductor layer, and the active layer includes a channel region and a source electrode and a drain electrode that are respectively located on both sides of the channel region. Among them, the channel region maintains semiconductor characteristics, and both the source electrode and the drain electrode are conductorized. In an embodiment of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the current direction during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" sometimes swap with each other, that is, the "source electrode" and the "drain electrode" can swap with each other. In an embodiment of the present disclosure, for any one transistor, one of the "source electrode" and the "drain electrode" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor.

[0070] The structural layer A is located on the side of the structural layer B away from the substrate. It can be understood that the structural layer A is formed on the side of the structural layer B facing away from the substrate. When the structural layer B is a patterned structure, a part of the structure of the structural layer A can also be located at the same physical height as the structural layer B or lower than the physical height of the structural layer B, where the substrate is the height reference.

[0071] It should be noted that the "same layer" in the embodiments of the present invention can refer to the film layers on the same structural layer. For example, the film layers in the same layer can be film layers formed with a specific pattern by the same film formation process. Of course, the film layers with specific patterns can also be at different heights or have different thicknesses.

[0072] In the related art, in order to reduce the space of the lower border of the display panel and achieve an extremely narrow border of the product to improve the visual experience, the FIP technology (integrating the diagonal traces in the fan-shaped area into the display area, that is, connecting the horizontal traces to the corresponding data signal traces, connecting the vertical traces to the end of the horizontal trace far from the data signal trace, and then leading out the vertical traces at the lower border of the display panel) is often used. In the prior art, the FIP technology generally uses three source-drain metal layers for wiring, with the horizontal traces disposed in the second source-drain metal layer and the vertical traces disposed in the third source-drain metal layer. The inventor believes that this embodiment has certain limitations, for example, it will increase the manufacturing cost of the display panel to a certain extent.

[0073] Based on this, the embodiments of the present disclosure provide a kind, see Figure 1 , Figure 2 , the display panel includes a substrate substrate SBT, a transistor layer TL, a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a pixel layer PIXL that are stacked in sequence; wherein, the display panel includes a circuit region PA arranged in an array along a row direction DH and a column direction DV, and a pixel driving circuit for driving sub-pixels is arranged in the circuit region PA; the display panel is provided with data signal traces DL corresponding to each circuit region column VPA one by one and extending along the column direction DV, and a first connection line LA corresponding to at least part of the circuit region columns VPA one by one and extending along the column direction DV is also provided, wherein the circuit region columns VPA include a plurality of circuit regions PA arranged in sequence along the column direction DV; the first connection line LA includes a first sub-line LA1 of the first source-drain metal layer SD1 and a second sub-line LA2 arranged on the second source-drain metal layer SD2 that are alternately arranged in sequence, and adjacent first sub-lines LA1 and second sub-lines LA2 are electrically connected through vias; the display panel further includes a second connection line LB extending along the row direction DH; wherein, at least part of the first connection line LA is electrically connected to the data signal trace DL through the second connection line LB.

[0074] In the embodiments of the present disclosure, part of the first connection line LA is connected to the data signal trace DL through the second connection line LB, so that the connection lines for electrically connecting the display panel and the driving chip can be accumulated at the lower border of the display panel, thereby realizing a reasonable layout of the connection lines for electrical connection between the display panel and the driving chip, which helps to reduce the space of the lower border of the display panel and better realize the narrow border of the display panel; at the same time, the first sub-line LA1 of the first connection line LA is arranged on the first source-drain metal layer SD1, the second sub-line LA2 of the first connection line LA is arranged on the second source-drain metal layer SD2, and the first sub-line LA1 and the second sub-line LA2 are connected through vias, which can reduce the preparation of one layer of source-drain metal layer compared with the prior art, and thus can reduce the processing cost of the display panel.

[0075] In some embodiments of the present disclosure, see Figure 2 , Figure 3 , Figure 5 and Figure 6 , the pixel driving circuit has a storage capacitor CST; the transistor layer TL includes a first gate layer GT1 and a second gate layer GT2 that are stacked in sequence; the storage capacitor CST includes a first electrode plate CP1 located on the first gate layer GT1 and a second electrode plate CP2 located on the second gate layer GT2; the orthographic projection of the connection position of the first sub-line LA1 and the second sub-line LA2 on the substrate substrate SBT partially overlaps with the orthographic projection of the second electrode plate CP2 on the substrate substrate SBT (see Figure 13 ).

[0076] The basic principle of the pixel driving circuit will be described below in conjunction with the equivalent circuit diagram of the pixel driving circuit:

[0077] Figure 3 An equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure is illustrated. It can be understood that the pixel driving circuit in the embodiment of the present disclosure can also be a pixel driving circuit with other structures. When the structure of the pixel driving circuit changes, the structures of the respective film layers exemplified in the present disclosure can also be adjusted adaptively.

[0078] In the embodiment of the present disclosure, the pixel driving circuit can also be 8T1C (8 transistors and 1 storage capacitor), 9T1C (9 transistors and 1 storage capacitor), 10T1C (10 transistors and 1 storage capacitor), etc., and the present embodiment does not make specific limitations thereon.

[0079] See Figure 3 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 and Figure 10 , in some embodiments of the present disclosure, the pixel driving circuit includes a first initialization voltage trace VL1 for loading a first initialization voltage Vinit1, a second initialization voltage trace VL2 for loading a second initialization voltage Vinit2, a third initialization voltage trace VL3 for loading a third initialization voltage Vinit3, a first capacitor reset control signal line RPL for loading a first reset signal RP, a first scan signal trace GNL for loading a first scan signal GN, an enable signal line EML for loading an enable signal EM, a second capacitor reset control signal line RHL for loading a second reset signal RH, a power supply voltage trace VDDL for loading a power supply voltage VDD, a data signal trace DL for loading a data voltage VData, a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, an electrode reset transistor T7, a node control transistor T8, and a storage capacitor CST. The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5.

[0080] In some embodiments of the present disclosure, the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the electrode reset transistor T7, and the node control transistor T8 can all be P-type transistors.

[0081] The first pole of the first reset transistor T1 is electrically connected to the first initialization voltage trace VL1 that loads the first initialization voltage Vinit1. The gate of the first reset transistor T1 is connected to the first capacitive reset control signal line RPL that loads the first reset signal RP. The second pole of the first reset transistor T1 is connected to the first node N1. The first reset transistor T1 is configured to load the first initialization voltage Vinit1 to the first node N1 in response to the first reset signal RP.

[0082] The first pole of the threshold compensation transistor T2 is electrically connected to the third node N3. The second pole of the threshold compensation transistor T2 is electrically connected to the first node N1. The gate of the threshold compensation transistor T2 is connected to the first scan signal trace GNL that loads the first scan signal GN. The threshold compensation transistor T2 is configured to conduct in response to the first scan signal GN.

[0083] The first pole of the driving transistor T3 is connected to the second node N2. The second pole of the driving transistor T3 is connected to the third node N3. The gate of the driving transistor T3 is connected to the first node N1. The driving transistor T3 is configured to output a driving current under the control of the voltage at the first node N1.

[0084] The first pole of the data writing transistor T4 is electrically connected to the data signal trace DL that loads the data voltage VData. The second pole of the data writing transistor T4 is electrically connected to the second node N2. The gate of the data writing transistor T4 is connected to the first scan signal trace GNL that loads the first scan signal GN. The data writing transistor T4 is configured to load the data voltage VData to the second node N2 in response to the first scan signal GN.

[0085] The first pole of the first light emission control transistor T5 is electrically connected to the fifth node N5. The second pole of the first light emission control transistor T5 is connected to the second node N2. The gate of the first light emission control transistor T5 is connected to the enable signal line EML that loads the enable signal EM.

[0086] It should be noted that in some embodiments, the enable signal EM loaded on the gate of the first light emission control transistor T5 and the enable signal EM loaded on the gate of the second light emission control transistor T6 can be set to be turned on asynchronously, that is, the enable signal EM can be first loaded on the gate of the first light emission control transistor T5, and then the enable signal EM is loaded on the gate of the second light emission control transistor T6; or, the enable signal EM is first loaded on the gate of the second light emission control transistor T6, and then the enable signal EM is loaded on the gate of the first light emission control transistor T5.

[0087] The first pole of the second light-emitting control transistor T6 is connected to the third node N3, the second pole of the second light-emitting control transistor T6 is connected to the fourth node N4, and the gate of the second light-emitting control transistor T6 is connected to the enable signal line EML for loading the enable signal EM. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are used to conduct in response to the enable signal EM.

[0088] The first pole of the electrode reset transistor T7 is connected to the second initialization voltage trace VL2 for loading the second initialization voltage Vinit2, the gate of the electrode reset transistor T7 is connected to the second capacitor reset control signal line RHL for loading the second reset signal RH, and the second pole of the electrode reset transistor T7 is connected to the fourth node N4. The electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the second reset signal RH.

[0089] The first pole of the node control transistor T8 is electrically connected to the third initialization voltage trace VL3 for loading the third initialization voltage Vinit3, the gate of the node control transistor T8 is connected to the second capacitor reset control signal line RHL for loading the second reset signal RH, and the second pole of the node control transistor T8 is connected to the second node N2. The node control transistor T8 is used to load the third initialization voltage Vinit3 to the second node N2 in response to the second reset signal RH.

[0090] As an example, in some embodiments, the second reset signal RH loaded on the gate of the electrode reset transistor T7 and the second reset signal RH loaded on the gate of the node control transistor can be set to the same gate signal line; of course, the second reset signal RH loaded on the gate of the electrode reset transistor T7 and the second reset signal RH loaded on the gate of the node control transistor can also be set to different gate signal lines.

[0091] The pixel electrode PE of the light-emitting element is electrically connected to the pixel driving circuit (not specifically shown in the drawings of the present application), and the common electrode is used to load the reference voltage VSS.

[0092] One end of the storage capacitor CST is connected to the first node N1, and the other end is electrically connected to the power supply voltage trace VDDL.

[0093] The display panel in the embodiments of the present disclosure will be described in detail below in conjunction with the structures of the respective film layers in the display panel:

[0094] Figure 2 To illustrate a schematic diagram of the film layer structure of a display panel according to an embodiment of the present disclosure. Refer to Figure 2 , in some embodiments of the present disclosure, the display panel includes a driving layer DRL and a pixel layer PIXL that are sequentially stacked on the substrate SBT;

[0095] Optionally, the substrate substrate SBT can be a substrate substrate SBT made of inorganic materials, or a substrate substrate SBT made of organic materials; of course, it can also be a composite substrate formed by laminating a substrate substrate SBT made of inorganic materials and a substrate substrate SBT made of organic materials. For example, in some embodiments of the present disclosure, the material of the substrate substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass.

[0096] In some other embodiments of the present disclosure, the material of the substrate substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the substrate substrate SBT can also be a flexible substrate substrate. For example, the material of the substrate substrate SBT can include polyimide.

[0097] Optionally, referring to Figure 2 , in the driving layer DRL, any one pixel driving circuit can include a thin film transistor and a storage capacitor CST (not shown in the drawings of this application). Further, the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a double-gate thin film transistor; the material of the active layer of the thin film transistor can be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0098] It can be understood that among the various transistors in the pixel driving circuit, the types of any two transistors can be the same or different. Exemplarily, in some embodiments, in a pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. Another example is that in some other embodiments, in a pixel driving circuit, the material of the active layer of some transistors can be a low-temperature polycrystalline silicon semiconductor material, and the material of the active layer of some transistors can be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polycrystalline silicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polycrystalline silicon transistors and some thin film transistors are metal oxide transistors.

[0099] Optionally, referring to Figure 2 , the driving layer DRL can include a buffer layer laminated on the substrate substrate SBT (for example Figure 2The first buffer layer Buff1 and the second buffer layer Buff2) shown, the metal light-shielding layer BSM disposed between the first buffer layer Buff1 and the substrate SBT, the semiconductor layers in the pixel layer PIXL (such as the low-temperature polysilicon semiconductor layer PSCL and the metal oxide semiconductor layer OSCL), the gate insulating layer (such as Figure 2 the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3 shown), the gate layer (such as Figure 2 the first gate layer GT1, the second gate layer GT2 shown), the interlayer dielectric layer ILD, the source / drain metal layer (such as Figure 2 the first source / drain metal layer SD1 and the second source / drain metal layer SD2 shown), the planarization layer (such as Figure 2 the first planarization layer PLN1, the second planarization layer PLN2 shown), etc. Each thin-film transistor and the storage capacitor CST (not specifically labeled in the drawings of this application) can be formed by film layers such as the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source / drain metal layer; of course, other film layers can also be used. Among them, the positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor. Further, the semiconductor layer can be used to form the active layer of the transistor (including the first pole, the second pole, and the channel region of the transistor), and when necessary, it can also be formed into part of the wiring or the conductive structure by conducting. The first source / drain metal layer SD1 can be used to form the scan signal wiring; the gate layer can be used to form one or more of the gate layer wirings such as the reset control wiring, the light-emitting control wiring, etc., can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plates of the storage capacitor CST. The source / drain metal layer can be used to form the data signal wiring, the driving power supply voltage wiring, etc. of the source / drain metal layer wiring, and can also be used to form part of the electrode plates of the storage capacitor CST.

[0100] Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, such as the metal light-shielding layer BSM located between the semiconductor layer and the substrate SBT. As needed, any one of the above film layers such as the semiconductor layer, the gate layer, the source / drain metal layer, etc. can be multiple layers. For example, the driving layer DRL can include two different semiconductor layers, or include two or three source / drain metal layers, or include two or three gate layers; correspondingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer, the interlayer dielectric layer ILD, the planarization layer, etc.) can be increased or decreased adaptively, or new insulating film layers can be added as needed.

[0101] Optionally, the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EL, and a common electrode layer COML that are sequentially stacked. Among them, the pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings that are set in one-to-one correspondence with the plurality of pixel electrodes PE, and at least a partial area of the corresponding pixel electrode PE is exposed through any one pixel opening. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a partial internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode (the area directly connected to the light-emitting functional layer EL), and further define the light-emitting area and light-emitting area of the sub-pixel. The common electrode layer COML covers the light-emitting functional layer EL as a common electrode. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EL, so that the light-emitting functional layer EL emits light. The portion of the light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML can be used as the light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element serving as a sub-pixel. Among them, one of the pixel electrode PE and the common electrode layer COML serves as the anode of the sub-pixel, and the other serves as the cathode of the sub-pixel.

[0102] In this example, the display panel is an OLED (organic light-emitting diode) display panel. The light-emitting functional layer EL may include an organic light-emitting layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer may include a light-emitting layer host material and a light-emitting layer guest material, and the light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, especially a thermally activated delayed fluorescence material.

[0103] It can be understood that the display panel may also be other types of display panels, such as a QLED display panel, a QD-OLED display panel, or other types of display panels.

[0104] See Figure 2 , the display panel may further include a thin film encapsulation layer TFE. The thin film encapsulation layer TFE may be disposed on the surface of the pixel layer PIXL away from the substrate SBT, and may include an inorganic encapsulation layer and an organic encapsulation layer that are alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the pixel layer PIXL and causing the materials in the pixel layer PIXL to age. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.

[0105] Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer (not specifically shown in this drawing) that are sequentially stacked on the side of the pixel layer PIXL away from the substrate SBT. The first inorganic encapsulation layer covers the display area and extends to the outside of the barrier ribs; the organic encapsulation layer covers the display area and extends to the inside of the barrier ribs; the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the barrier ribs. On the outside of the barrier ribs, the second inorganic encapsulation layer contacts the first inorganic encapsulation layer. In this way, the organic encapsulation layer is enclosed by the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the stress between the first inorganic encapsulation layer and the second inorganic encapsulation layer is balanced. The first inorganic encapsulation layer and the second inorganic encapsulation layer enclose the organic encapsulation layer to isolate the organic encapsulation layer from contact with water and oxygen. Of course, in other embodiments of the present disclosure, the display panel may not be provided with the thin film encapsulation layer TFE, but other methods may be used to encapsulate and protect the pixel layer.

[0106] In some embodiments of the present disclosure, the display panel may further include a touch metal layer (not specifically shown in the drawings of this application), and the touch metal layer may be disposed on the side of the thin film transistor away from the pixel layer PIXL so that the display panel has a touch function.

[0107] In this embodiment, referring to Figure 2 , the driving layer DRL may further include a transistor layer TL, a first source-drain metal layer SD1, and a second source-drain metal layer SD2; the transistor layer TL is a combination of each film layer disposed between the substrate SBT and the first source-drain metal layer SD1, and various thin film transistors required for the pixel driving circuit may be formed therein.

[0108] In some embodiments of the present disclosure, the first connection line LA includes connection leads LL and initialization voltage auxiliary traces VTLX that are alternately arranged in sequence along the row direction DH; among them, the connection leads LL are electrically connected to the data signal traces DL through the second connection line LB. The initialization voltage auxiliary trace VLX is used to be electrically connected to the initialization voltage trace VTL located in the first source-drain metal layer SD1 or the transistor layer TL. In this way, in some circuit regions PA, the connection leads LL are connected to the data signal traces DL through the second connection line LB, which can achieve the purpose of gathering the electrical connection lines with the driving chip at the lower border of the display panel, contributing to the narrow border of the display panel and improving the visual experience of the display panel; in other circuit regions PA, the initialization voltage auxiliary traces VTLX are electrically connected to their corresponding initialization voltage traces VTL, which helps to achieve the gridification of the initialization voltage and can improve the display uniformity of the display panel.

[0109] In some embodiments of the present disclosure, the first connection line LA is disposed between two adjacent circuit region columns VPA.

[0110] In some embodiments, the initialization voltage trace VTL includes a first initialization voltage trace VTL1 for loading a first initialization voltage Vinit1 and extending along the row direction DH, a second initialization voltage trace VTL2 for loading a second initialization voltage Vinit2 and extending along the row direction DH, and a third initialization voltage trace VTL3 for loading a third initialization voltage Vinit3 and extending along the row direction DH; the initialization voltage auxiliary trace VLX includes a first initialization voltage auxiliary trace VL1X for electrically connecting with the first initialization voltage trace VTL1, a second initialization voltage auxiliary trace VL2X for electrically connecting with the second initialization voltage trace VTL2, and a third initialization voltage auxiliary trace VL3X for electrically connecting with the third initialization voltage trace VTL3. In this way, the first initialization voltage Vinit1 loaded on the first initialization voltage trace VTL1 can be loaded on the first initialization voltage auxiliary trace VL1X, so that the first initialization voltage Vinit1 can be gridified, improving the display uniformity of the display panel; the second initialization voltage Vinit2 loaded on the second initialization voltage trace VTL2 can be loaded on the second initialization voltage auxiliary trace VL2X, so that the second initialization voltage Vinit2 can be gridified, improving the display uniformity of the display panel; the third initialization voltage Vinit3 loaded on the third initialization voltage trace VTL3 can be loaded on the third initialization voltage auxiliary trace VL3X, so that the third initialization voltage Vinit3 can be gridified, improving the display uniformity of the display panel.

[0111] In some embodiments of the present disclosure, among the respective initialization voltage auxiliary traces VLX arranged along the row direction DH, the first initialization voltage auxiliary trace VL1X, the second initialization voltage auxiliary trace VL2X, and the third initialization voltage auxiliary trace VL3X are arranged in a periodic order. In this way, a uniform distribution of the initialization voltage auxiliary traces VLX in the display panel is achieved, and further the display uniformity of the display panel can be improved (see Figure 13 ).

[0112] It can be understood that in some embodiments, among the respective initialization voltage auxiliary traces VLX arranged in the row direction DH, it may be that the first initialization voltage auxiliary trace VL1X, the third initialization voltage auxiliary trace VL3X, and the second initialization voltage auxiliary trace VL2X are arranged in a periodic order; or, among the respective initialization voltage auxiliary traces VLX arranged in the row direction DH, the first initialization voltage auxiliary trace VL1X, the third initialization voltage auxiliary trace VL3X, and the second initialization voltage auxiliary trace VL2X are arranged in a periodic order, etc. The present disclosure does not make specific limitations in this regard.

[0113] In some embodiments of the present disclosure, the second connection line LB is disposed on the first source-drain metal layer and extends along the row direction DH; the transistor layer TL includes a first gate layer GT1 and a second gate layer GT2 stacked in sequence; the second gate layer GT2 is provided with a first initialization voltage trace VTL1 for loading a first initialization voltage Vinit1, and the first initialization voltage trace VTL1 is used to reset the gate of the driving transistor T3 of the pixel driving circuit; the extension trajectory of the second connection line LB is the same as that of the adjacent first initialization voltage trace VTL1.

[0114] As an example, the orthographic projection of the second connection line LB on the substrate SBT coincides with the orthographic projection of the first initialization voltage trace VTL1 on the substrate SBT, so that the longitudinal length of the pixel driving circuit can be compressed, providing the possibility of increasing the pixel density of the display panel.

[0115] The driving layer DRL will be described in detail below in combination with the positions of the transistors and the step-by-step conditions of the signal traces in the above 8T1C pixel driving circuit:

[0116] Figure 4 Schematic diagram of a low-temperature polycrystalline silicon semiconductor layer PSCL in an embodiment of the present disclosure is exemplified. Refer to Figure 4 , the active layers and channel regions of the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the electrode reset transistor T7, and the node control transistor T8 are located on the low-temperature polycrystalline silicon semiconductor layer PSCL. Among them, the channel region T4A of the data writing transistor and the channel region T8A of the node control transistor are arranged along the column direction, and the channel region T5A of the first light-emitting control transistor and the channel region T6A of the second light-emitting control transistor are arranged along the row direction. Along the row direction DH, the channel region T3A of the driving transistor is located between the channel region T2A of the threshold compensation transistor and the channel region T4A of the data writing transistor; the channel region T3A of the driving transistor is located between the channel region T5A of the first light-emitting control transistor and the channel region T6A of the second light-emitting control transistor; along the column direction DV, the channel region T7A of the electrode reset transistor and the channel region T3A of the driving transistor are located on both sides of the channel region T5A of the first light-emitting control transistor.

[0117] The low-temperature polysilicon semiconductor layer PSCL is provided with a twelfth lower via region HA12, a second lower via region HA2, a fifth lower via region HA5, a fourteenth lower via region HA14, a seventh lower via region HA7, a third lower via region HA3, an eleventh lower via region HA11, a fourth lower via region HA4, and a ninth lower via region HA9; among them, the twelfth lower via region HA12 is located at a first pole of the first reset transistor T1; the second lower via region HA2 is located at a second pole of the threshold compensation transistor T2; the fifth lower via region HA5 is located at a second pole of the second light-emitting control transistor; the fourteenth lower via region HA14 is located at a first pole of the electrode reset transistor T7; the seventh lower via region HA7 is located at a second pole of the first light-emitting control transistor T5; the third lower via region HA3 is located at a first pole of the first light-emitting control transistor T5; the eleventh lower via region HA11 is located at a first pole of the data writing transistor T4; the fourth lower via region HA4 is located at a second pole of the node control transistor T8; the ninth lower via region HA9 is located at a first pole of the node control transistor T8.

[0118] In some embodiments of the present disclosure, the first reset transistor T1 includes a first polysilicon conductive structure M1, a second polysilicon conductive structure M2, and a third polysilicon conductive structure M3; among them, the first polysilicon conductive structure M1 and the third polysilicon conductive structure M3 are arranged side by side along the column direction DV; the second polysilicon conductive structure M2 is arranged along the row direction DH, and the sides of the first polysilicon conductive structure M1 and the third polysilicon conductive structure M3 away from the driving transistor T3 are electrically connected to each other.

[0119] As an example, the first reset transistor T1 can be a double-gate structure.

[0120] In some embodiments of the present disclosure, the pixel driving circuit includes a threshold compensation transistor T2 and a driving transistor T3; a first pole of the threshold compensation transistor T2 is connected to a second pole of the driving transistor T3; a second pole of the threshold compensation transistor T2 is electrically connected to a gate of the driving transistor T3; a channel region of the threshold compensation transistor T2 is located in the low-temperature polysilicon semiconductor layer PSCL; the threshold compensation transistor T2 includes a fourth polysilicon conductive structure M4 arranged along the row direction DH and a fifth polysilicon conductive structure M5 arranged along the column direction DV; the fourth polysilicon conductive structure M4 is electrically connected to a side of the first polysilicon conductive structure M1 close to the driving transistor T3; the fifth polysilicon conductive structure M5 is electrically connected to a side of the fourth polysilicon conductive structure M4 away from the first polysilicon conductive structure M1.

[0121] As an example, the threshold compensation transistor T2 can be a double-gate structure.

[0122] Figure 5 Schematic diagram of the first gate layer GT1 in the embodiments of the present disclosure is shown inFigure 5 , the first gate layer GT1 is provided with an enable signal line EML, a first capacitor reset control signal line RPL, a second capacitor reset control signal line RHL, a first scan signal trace GNL, and a first electrode plate CP1 of the storage capacitor CST; wherein, the first capacitor reset control signal line RPL extends along the row direction DH and is used to load a first reset signal RP to the first reset transistor T1; the second capacitor reset control signal line RHL extends along the row direction DH and is used to load a second reset signal RH to the node control transistor T8; the enable signal line EML extends along the row direction DH and sequentially overlaps with the channel regions T5A of the first light-emitting control transistor and T6A of the second light-emitting control transistor to multiplex the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6, and the enable signal line EML is used to load an enable signal EM to the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the first electrode plate CP1 of the storage capacitor CST overlaps with the channel region T3A of the driving transistor to multiplex as the gate of the driving transistor T3; the first scan signal trace GNL extends along the row direction DH and can overlap with the channel region T4A of the data writing transistor to multiplex as the gate of the data writing transistor T4; the first scan signal trace GNL is used to load a first scan signal GN to the data writing transistor T4; and at the same time, the first scan signal trace GNL can overlap with the channel region T2A of the threshold compensation transistor to multiplex as the gate of the channel region T2A of the threshold compensation transistor, and is used to load the first scan signal GN to the threshold compensation transistor; the second capacitor reset control signal line RHL extends along the row direction DH to multiplex the gates of the electrode reset transistor T7 and the node control transistor T8, and the second capacitor reset control signal line RHL is used to load the second reset signal RH to the electrode reset transistor T7 and the node control transistor T8. Wherein, the first electrode plate CP1 of the storage capacitor CST has a first lower via region HA1.

[0123] Figure 6 An example of the schematic diagram of the second gate layer GT2 in the embodiments of the present disclosure is shown in Figure 6 , the second gate layer GT2 is provided with a first initialization voltage trace VTL1, a second initialization voltage trace VTL2 extending along the row direction DH, and a second electrode plate CP2 of the storage capacitor CST, wherein the second initialization voltage trace VTL2 has a thirteenth lower via region HA13; the second electrode plate CP2 of the storage capacitor CST has an eighth lower via region HA8; the first initialization voltage trace VTL1 has a fifteenth lower via region HA15.

[0124] In some embodiments of the present disclosure, the second initialization voltage trace VTL2 has a bulged portion P1, and the orthographic projection of the bulged portion P1 on the substrate SBT overlaps with the orthographic projection of the active layer of the first reset transistor T1 on the substrate SBT.

[0125] Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 and Figure 14 schematically illustrate the first source-drain metal layer SD1 in an embodiment of the present disclosure; wherein, Figure 7 is a schematic structural diagram of the first source-drain metal layer corresponding to the first connection lead LL when the first connection line LA is the connection lead LL in a circuit region PA; Figure 8 is a schematic diagram of the first source-drain metal layer corresponding to the first initialization voltage auxiliary trace VTL1X of the first connection line LA in a circuit region PA; Figure 9 is a schematic diagram of the first source-drain metal layer corresponding to the second initialization voltage auxiliary trace VTL2X of the first connection line LA in a circuit region PA; Figure 10 is a schematic diagram of the first source-drain metal layer corresponding to the third initialization voltage auxiliary trace VTL3X of the first connection line LA in a circuit region PA.

[0126] The first source-drain metal layer SD1 has a first bridging portion MA1, a second bridging portion MA2, a third bridging portion MA3, a fourth bridging portion MA4, a fifth bridging portion MA5, a sixth bridging portion MA6, a seventh bridging portion MA7, an eighth bridging portion MA8, and the first source-drain metal layer SD1 further includes a first initialization voltage transfer structure VT1P (see Figure 8 ), a second initialization voltage transfer structure VT2P (see Figure 9 ), a third initialization voltage transfer structure VT3P (see Figure 10 ), and a third initialization voltage trace VTL3.

[0127] A first upper via region HB1 and a second upper via region HB2 are provided on the first bridging portion MA1, wherein the first upper via region HB1 overlaps with a first lower via region HA1 and is connected by a via; the second upper via region HB2 overlaps with a second lower via region HA2 and is connected by a via; in this way, the second pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the first bridging portion MA1.

[0128] A third upper via region HB3 and a fourth upper via region HB4 are provided on the second bridging portion MA2, wherein the third upper via region HB3 overlaps with a third lower via region HA3 and is connected by a via; wherein, the fourth upper via region HB4 overlaps with a fourth lower via region HA4 and is connected by a via; in this way, the second pole of the first light control transistor T5 is electrically connected to the second pole of the node control transistor T8 through the second bridging portion MA2.

[0129] The third bridging portion MA3 is provided with a fifth upper via region HB5 and a sixth upper via region HB6. Among them, the fifth upper via region HB5 overlaps with the fifth lower via region HA5 and is connected through a via. In this way, the signal of the second source-drain metal layer SD2 can be loaded onto the second pole of the second light-emitting control transistor T6 through the third bridging portion MA3.

[0130] The fourth bridging portion MA4 is provided with an eighth upper via region HB8, a seventh lower via region HA7, and a sixteenth lower via region HA16. Among them, the seventh upper via region HB7 overlaps with the seventh lower via region HA7 and is connected through a via. The eighth upper via region HB8 overlaps with the eighth lower via region HA8 and is connected through a via. In this way, the power supply voltage VDD on the second source-drain metal layer SD2 can be loaded onto the first pole of the first light-emitting control transistor and the second electrode plate CP2 of the storage capacitor CST through the fourth bridging portion.

[0131] The fifth bridging portion MA5 is provided with a tenth lower via region HA10 and an eleventh upper via region HB11. Among them, the eleventh upper via region HB11 overlaps with the eleventh lower via region HA11 and is connected through a via. In this way, the data signal loaded by the data signal trace DL can be loaded onto the first pole of the data writing transistor T4 through the fifth bridging portion MA5.

[0132] The sixth bridging portion MA6 is provided with a twelfth upper via region HB12 and a thirteenth upper via region HB13. Among them, the twelfth upper via region HB12 overlaps with the twelfth lower via region HA12 and is connected through a via. The thirteenth upper via region HB13 overlaps with the thirteenth lower via region HA13 and is connected through a via. In this way, the first initialization voltage Vinit1 loaded on the first initialization voltage trace VTL1 is loaded onto the first pole of the first reset transistor T1 through the sixth bridging portion MA6.

[0133] In some embodiments of the present disclosure, the transistor layer TL includes a first gate layer GT1 and a second gate layer GT2 stacked in sequence. The second gate layer GT2 is provided with a first initialization voltage trace VTL1 for loading the first initialization voltage Vinit1. The first initialization voltage trace VTL1 is used to reset the gate of the driving transistor T3 of the pixel driving circuit. The first connection line LA includes a first initialization voltage auxiliary trace VTL1X connected to the first initialization voltage trace VTL1. The first source-drain metal layer SD1 has a first initialization voltage transfer structure VT1P (see Figure 8) One end of the first initialization voltage transfer structure VT1P is electrically connected to the first initialization voltage auxiliary trace VTL1X, and the other end is connected to the first initialization voltage trace VTL1 through a via; the orthographic projection of the first initialization voltage transfer structure VT1P on the substrate SBT overlaps with the orthographic projection of the second electrode plate CP2 on the substrate SBT. In this way, the first initialization voltage Vinit1 loaded on the first initialization voltage trace VTL1 is loaded onto the first initialization voltage auxiliary trace VTL1X through the first initialization voltage transfer structure VT1P, realizing the gridification of the first initialization voltage Vinit1 in sequence, which helps to improve the display uniformity of the display panel.

[0134] In this embodiment, there is a routing space between the first initialization voltage transfer structure VT1P, the first initialization voltage trace VTL1, and the first sub-line LA1; the pixel driving circuit has a data writing transistor T4; a data signal transfer structure DP (the fifth bridging portion MA5) is provided in the routing space in the first source-drain metal layer SD1, one end of the data signal transfer structure DP is connected to the data signal trace DL, and the other end is electrically connected to the first pole of the data writing transistor T4.

[0135] As an example, the first initialization voltage transfer structure VT1P is disposed between the third initialization voltage trace VTL3 and the second connection line LB. Wherein, the first initialization voltage transfer structure VT1P may include a vertical segment L1, an inclined segment L2, and a horizontal segment L3;

[0136] Wherein, one end of the vertical segment L1 is electrically connected to the sixth bridging portion MA6, the inclined segment L2 is electrically connected to the end of the vertical segment L1 far from the sixth bridging portion MA6, one end of the horizontal segment L3 is electrically connected to the inclined segment L2 far from the vertical segment L1, and the other end of the horizontal segment L3 is electrically connected to the first sub-line LA1. It should be noted that in the embodiment of the present disclosure, the horizontal segment L3 may be electrically connected to the middle part of the first sub-line LA1. Of course, in some embodiments, the horizontal segment L3 may also be electrically connected to the end of the first sub-line LA1.

[0137] In some embodiments of the present disclosure, the transistor layer TL includes a first gate layer GT1 and a second gate layer GT2 that are stacked in sequence; the second gate layer GT2 is provided with a second initialization voltage trace VTL2 for loading a second initialization voltage Vinit2, and the second initialization voltage trace VTL2 is used to reset the gate of the driving transistor T3 of the pixel driving circuit; the first connection line LA includes a second initialization voltage auxiliary trace VTL2X connected to the second initialization voltage trace VTL2; the display panel further includes a power supply voltage trace VDDL corresponding to each circuit region; the second initialization voltage auxiliary trace VTL2X is located between the data signal trace DL and the power supply voltage trace VDDL; the first source-drain metal layer SD1 has a second initialization voltage transfer structure VT2P, and the second initialization voltage transfer structure VT2P is located between the second initialization voltage auxiliary trace VTL2X and the power supply voltage trace VDDL, and one end of the second initialization voltage transfer structure VT2P is electrically connected to the second initialization voltage auxiliary trace VTL2X through a via, and the other end is electrically connected to the second initialization voltage trace VTL2 through a via.

[0138] The fifteenth upper via region HB15 and the fourteenth lower via region HA14 (see Figure 9 ) are provided on the seventh bridging portion MA7 (the second initialization voltage transfer structure VT2P); wherein, the fifteenth upper via region HB15 overlaps with the fifteenth lower via region and is connected through a via. In this way, the second initialization voltage Vinit2 loaded on the second initialization voltage trace VTL2 is loaded onto the corresponding trace provided on the second source-drain metal layer SD2 through the seventh bridging portion MA7, and the gridification of the second initialization voltage Vinit2 is realized in sequence, which helps to improve the display uniformity of the display panel.

[0139] In the embodiments of the present disclosure, in the corresponding circuit region PA, even if the gridification setting of the second initialization voltage Vinit2 is not performed, the seventh bridging portion MA7 (the second initialization voltage transfer structure VT2P) can still be provided at the corresponding position, thereby further improving the display uniformity of the display panel.

[0140] In some other embodiments of the present disclosure, in the corresponding circuit region PA, if the gridification setting of the second initialization voltage Vinit2 is not performed, the second initialization voltage transfer structure VT2P may not be provided in the corresponding circuit region PA.

[0141] On the eighth bridging portion MA8 (the first sub-line LA1), a seventeenth lower via region HA17 and an eighteenth lower via region HA18 are provided. In this way, through the eighth bridging portion MA8 (the first sub-line LA1), the meshing of the first initialization voltage Vinit1, the meshing of the second initialization voltage Vinit2, and the meshing of the third initialization voltage Vinit3 can be realized in some circuit regions, and the electrical connection between the first connection line LA located on the first source-drain metal layer SD1 and the second connection line LB located on the second source-drain metal layer SD2 can be realized. Thus, compared with the prior art, the preparation of one layer of the source-drain metal layer can be reduced, and further the cost of preparing the display panel can be reduced.

[0142] On the third initialization voltage trace VTL3, a ninth upper via region HB9 is provided. Among them, the ninth upper via region HB9 overlaps with the ninth lower via region HA9 and is connected through a via. In this way, the third initialization voltage Vinit3 can be loaded to the first pole of the node control transistor T8.

[0143] As an example, the second initialization voltage transfer structure VT2P is provided on the side of the second connection line LB away from the third initialization voltage trace VTL3.

[0144] In some embodiments of the present disclosure, the pixel driving circuit has a driving transistor T3, a data writing transistor T4, and a node control transistor T8; the second pole of the data writing transistor T4, the first pole of the driving transistor T3, and the second pole of the node control transistor T8 are electrically connected; the display panel is provided with a third initialization voltage trace VTL3 for loading the third initialization voltage Vinit3, and the third initialization voltage trace VTL3 is electrically connected to the first pole of the node control transistor T8; the first connection line LA includes a third initialization voltage auxiliary trace VTL3X electrically connected to the third initialization voltage trace VTL3; the first source-drain metal layer SD1 has a third initialization voltage transfer structure VT3P (see Figure 10 ). One end of the third initialization voltage transfer structure VT3P is electrically connected to the end of the first sub-line LA1 of the third initialization voltage auxiliary trace VTL3X, and the other end is electrically connected to the third initialization voltage trace VTL3. Thus, the third initialization voltage Vinit3 loaded on the third initialization voltage trace VTL3 can be loaded to the third initialization voltage auxiliary trace VTL3X through the third initialization voltage transfer structure VT3P to realize the meshing of the third initialization voltage Vinit3, improving the display uniformity of the display panel.

[0145] In this embodiment, the second connecting line LB is arranged adjacent to the third initialization voltage line VTL3; the third initialization voltage transfer structure VT3P is arranged on the side of the third initialization voltage line VTL3 away from the second connecting line LB; the orthographic projection of one end of the second sub-line LA2 of the first connecting line LA on the substrate SBT overlaps with the orthographic projection of the third initialization voltage line VTL3 on the substrate SBT, and the orthographic projection of the other end of the first connecting line LA on the substrate SBT overlaps with the orthographic projection of the second connecting line LB on the substrate SBT.

[0146] In some embodiments of the present disclosure, the third initialization voltage transfer structure VT3P may include a straight segment L4, one end of the straight segment L4 is electrically connected to the end of the second sub-line LA2, and the other end of the straight segment L4 is electrically connected to the third initialization voltage line VTL3, thereby realizing the electrical connection between the third initialization voltage line VTL3 and the first sub-line LA1.

[0147] In the embodiment of the present disclosure, the straight segment L4 is electrically connected to the end of the first sub-line LA1, which can reduce the overlap between the straight segment L4 and the first sub-line LA1 while achieving the electrical connection between the straight segment L4 and the first sub-line LA1, thereby reducing material loss in preparation to a certain extent.

[0148] Figure 11 , Figure 12 and Figure 15 The schematic diagram of the second source-drain metal layer SD2 in the embodiment of the present disclosure is illustrated. Figure 11 Schematic diagram of the second source-drain metal layer SD2 corresponding to a circuit area PA when the first connection line LA is the connection lead LL or the first initialization voltage auxiliary wiring VTL1X or the third initialization voltage auxiliary wiring VTL3X in the circuit area PA; Figure 12 2 is a schematic diagram of a second source-drain metal layer SD2 corresponding to a circuit area PA when the first connection line LA is a second initialization voltage auxiliary wiring line VTL2X in the circuit area PA.

[0149] The second source-drain metal layer SD2 comprises a first conductive portion MB1, a second conductive portion MB2, a power supply voltage line VDDL, a data signal line DL, a first connection line LA, a first initialization voltage auxiliary line VTL1X, a second initialization voltage auxiliary line VTL2X, and a third initialization voltage auxiliary line VTL3X;

[0150] The first conductive part MB1 has a sixth upper via region HB6. Among them, the sixth upper via region HB6 overlaps with the sixth lower via region HA6 and is connected through vias, so as to achieve the purpose of loading a signal to the third bridging part MA3 through the first conductive part MB1. In some embodiments, in adjacent circuit regions PA, since the areas occupied by different sub-pixels are different, the area of the first conductive part MB1 can be adjusted to adapt to different sub-pixels. Therefore, in adjacent circuit regions PA, the sizes of the first conductive part MB1 can be different.

[0151] Among them, the sixteenth upper via region HB16 is provided on the power supply voltage trace VDDL; among them, the sixteenth upper via region HB16 and the sixteenth lower via region HA16 overlap and are connected through vias, so as to achieve the purpose of loading the power supply voltage VDD to the fourth bridging part MA4 through the power supply voltage trace VDDL.

[0152] The tenth upper via region HB10 is provided on the data signal trace DL; among them, the tenth upper via region HB10 and the tenth lower via region HA10 overlap and are connected through vias, so as to achieve the purpose of loading the data signal to the first pole of the data writing transistor T4 through the data signal trace DL via the fifth bridging part MA5.

[0153] The first initialization voltage auxiliary trace VTL1X has a seventeenth upper via region HB17 and an eighteenth upper via region HB18; among them, the seventeenth upper via region HB17 and the seventeenth lower via region HA17 overlap and are connected through vias, so as to achieve the purpose of loading the first initialization voltage Vinit1 to the first initialization voltage auxiliary trace VTL1X, and further achieve the gridification of the first initialization voltage Vinit1.

[0154] The second initialization voltage auxiliary trace VTL2X has a seventeenth upper via region HB17 and an eighteenth upper via region HB18; among them, the seventeenth upper via region HB17 and the seventeenth lower via region HA17 overlap and are connected through vias, so as to achieve the purpose of loading the second initialization voltage Vinit2 to the second initialization voltage auxiliary trace VTL2X, and further achieve the gridification of the second initialization voltage Vinit2.

[0155] The third initialization voltage auxiliary trace VTL3X has a seventeenth upper via region HB17 and an eighteenth upper via region HB18; among them, the seventeenth upper via region HB17 and the seventeenth lower via region HA17 overlap and are connected through vias, so as to achieve the purpose of loading the third initialization voltage Vinit3 to the third initialization voltage auxiliary trace VTL3X, and further achieve the gridification of the third initialization voltage Vinit3.

[0156] The fourteenth upper via region HB14 is provided on the second conductive portion MB2. Among them, the fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14 and is connected through a via, so as to realize that the second initialization voltage Vinit2 loaded on the seventh bridging portion MA7 is transferred to the second sub-line LA2 of the first connection line LA through the second conductive portion MB2, and further realize the meshing of the second initialization voltage Vinit2.

[0157] In the above-described embodiment of the present disclosure, the initialization voltage auxiliary trace VTLX is exemplified by the first connection line LA located in SD1 and the second connection line LB located in the second source-drain metal layer SD2 for illustrative purposes.

[0158] It can be understood that the initialization voltage auxiliary trace VTLX of the embodiment of the present disclosure can also adopt other embodiments.

[0159] For example, in Figure 16 the example, the initialization voltage auxiliary trace VTLX further includes a third sub-line LA3 located in the second source-drain metal layer SD2. The third sub-line LA3 and the second sub-line LA2 are alternately arranged in sequence and connected to form an integral trace.

[0160] In this embodiment, the initialization voltage auxiliary trace VTLX includes a second sub-line LA2 and a third sub-line LA3 located in the second source-drain metal layer SD2, and a first sub-line LA1 located in the first source-drain metal layer SD1. Among them, the second sub-line LA2 and the third sub-line LA3 of the initialization voltage auxiliary trace VTLX are connected to form an entire trace, and the first sub-line LA1 is arranged in parallel with the third sub-line LA3 to reduce the resistance of the initialization voltage auxiliary trace VTLX and further improve the uniform effect on the initialization voltage.

[0161] The embodiment of the present disclosure also provides a display device, which includes any one of the display panels described in the above display panel embodiments. The display device can be a smartphone screen, a smartwatch screen or other types of display devices. Since the display device has any one of the display panels described in the above display panel embodiments, it has the same beneficial effects, and the present disclosure will not repeat them here.

[0162] Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A display panel, comprising a base substrate, a transistor layer, a first source-drain metal layer, a second source-drain metal layer and a pixel layer stacked in sequence; wherein: The display panel comprises a circuit area arranged in an array along a row direction and a column direction, wherein the circuit area is provided with a pixel driving circuit for driving sub-pixels; The display panel is provided with data signal routing lines corresponding to each of the circuit area columns one by one and extending along the column direction, and is also provided with first connection lines corresponding to at least part of the circuit area columns one by one and extending along the column direction, wherein the circuit area columns include a plurality of the circuit areas sequentially arranged along the column direction; The first connecting line includes first sub-lines arranged alternately on the first source-drain metal layer and second sub-lines arranged on the second source-drain metal layer, and the adjacent first sub-lines and second sub-lines are electrically connected through vias; The display panel further includes second connection lines extending along the row direction; wherein at least a portion of the first connection lines are electrically connected to the data signal wiring through the second connection lines.

2. The display panel according to claim 1, wherein: The first connection lines include connection leads and initialization voltage auxiliary lines that are alternately arranged in sequence along the row direction; Wherein, the connecting lead is electrically connected to the data signal wiring through the second connecting wire; The initialization voltage auxiliary wiring is used to be electrically connected to the initialization voltage wiring located in the first source-drain metal layer or the transistor layer.

3. The display panel according to claim 2, wherein: The initialization voltage wiring includes a first initialization voltage wiring for loading a first initialization voltage and extending along the row direction, a second initialization voltage wiring for loading a second initialization voltage and extending along the row direction, and a third initialization voltage wiring for loading a third initialization voltage and extending along the row direction; The initialization voltage auxiliary routing includes a first initialization voltage auxiliary routing for electrically connecting to the first initialization voltage routing, a second initialization voltage auxiliary routing for electrically connecting to the second initialization voltage routing, and a third initialization voltage auxiliary routing for electrically connecting to the third initialization voltage routing.

4. The display panel according to claim 3, wherein: In each of the initialization voltage auxiliary routing lines arranged along the row direction, the first initialization voltage auxiliary routing line, the second initialization voltage auxiliary routing line and the third initialization voltage auxiliary routing line are sequentially arranged in a periodic manner.

5. The display panel according to claim 1, wherein: The second connecting line is disposed on the first source-drain metal layer and extends along the row direction; The transistor layer comprises a first gate layer and a second gate layer which are stacked in sequence; the second gate layer is provided with a first initialization voltage wiring for loading a first initialization voltage, and the first initialization voltage wiring is used to reset the gate of the driving transistor of the pixel driving circuit; An extension track of the second connecting line is consistent with an extension track of the adjacent first initialization voltage wiring line.

6. The display panel according to claim 1, wherein: The first connecting line is arranged between two adjacent circuit area columns.

7. The display panel according to claim 1, wherein: The pixel driving circuit has a storage capacitor; The transistor layer includes a first gate layer and a second gate layer which are stacked in sequence; The storage capacitor comprises a first electrode plate located at the first gate layer and a second electrode plate located at the second gate layer; An orthographic projection of a connection position between the first sub-wire and the second sub-wire on the base substrate partially overlaps with an orthographic projection of the second electrode plate on the base substrate.

8. The display panel according to claim 1, wherein: The transistor layer comprises a first gate layer and a second gate layer which are stacked in sequence; the second gate layer is provided with a first initialization voltage wiring for loading a first initialization voltage, and the first initialization voltage wiring is used to reset the gate of the driving transistor of the pixel driving circuit; The first connection line includes a first initialization voltage auxiliary wiring line connected to the first initialization voltage wiring line; The first source-drain metal layer has a first initialization voltage transfer structure, one end of the first initialization voltage transfer structure is electrically connected to the first initialization voltage auxiliary wiring, and the other end is connected to the first initialization voltage wiring through a via.

9. The display panel according to claim 8, wherein: The pixel driving circuit has a storage capacitor; The transistor layer includes a first gate layer and a second gate layer stacked in sequence; the storage capacitor includes a first electrode plate located at the first gate layer and a second electrode plate located at the second gate layer; The orthographic projection of the first initialization voltage transfer structure on the base substrate overlaps with the orthographic projection of the second electrode plate on the base substrate.

10. The display panel according to claim 8, wherein: There is a wiring space between the first initialization voltage transfer structure, the first initialization voltage wiring and the first sub-line; The pixel driving circuit has a data writing transistor; The first source-drain metal layer is provided with a data signal switching structure in the wiring space, one end of the data signal switching structure is connected to the data signal wiring, and the other end is electrically connected to the first electrode of the data writing transistor.

11. The display panel according to claim 8, wherein: The pixel driving circuit has a node control transistor; The display panel is provided with a third initialization voltage wiring for loading a third initialization voltage, and the third initialization voltage wiring is electrically connected to the first electrode of the node control transistor; The first initialization voltage transfer structure is arranged between the third initialization voltage wiring and the second connection line.

12. The display panel according to claim 1, wherein: The transistor layer comprises a first gate layer and a second gate layer which are stacked in sequence; the second gate layer is provided with a second initialization voltage wiring for loading a second initialization voltage, and the second initialization voltage wiring is used to reset the driving transistor of the pixel driving circuit; The first connection line includes a second initialization voltage auxiliary wiring line connected to the second initialization voltage wiring line; The display panel further includes a power supply voltage wiring arranged corresponding to each of the circuit areas; the second initialization voltage auxiliary wiring is located between the data signal wiring and the power supply voltage wiring; The first source-drain metal layer has a second initialization voltage transfer structure, which is located between the second initialization voltage auxiliary routing and the power supply voltage routing, and one end of the second initialization voltage transfer structure is electrically connected to the second initialization voltage auxiliary routing through a via, and the other end is electrically connected to the second initialization voltage routing through a via.

13. The display panel according to claim 1, wherein: The pixel driving circuit comprises a driving transistor, a data writing transistor and a node control transistor; the second electrode of the data writing transistor, the first electrode of the driving transistor and the second electrode of the node control transistor are electrically connected; The display panel is provided with a third initialization voltage wiring for loading a third initialization voltage, and the third initialization voltage wiring is electrically connected to the first electrode of the node control transistor; The first connection line includes a third initialization voltage auxiliary wiring line electrically connected to the third initialization voltage wiring line; The pixel driving circuit has a node control transistor; The first source-drain metal layer has a third initialization voltage transfer structure, one end of the third initialization voltage transfer structure is electrically connected to the end of the first sub-line of the third initialization voltage auxiliary wiring, and the other end is electrically connected to the third initialization voltage wiring.

14. The display panel according to claim 13, wherein: The second connecting line is arranged adjacent to the third initialization voltage wiring; The third initialization voltage transfer structure is arranged on a side of the third initialization voltage wiring away from the second connection line; One end of the second sub-line of the first connecting line overlaps with the orthographic projection of the third initialization voltage line on the substrate, and the other end overlaps with the orthographic projection of the second connecting line on the substrate.

15. The display panel according to claim 2, wherein: The initialization voltage auxiliary wiring also includes a third sub-line located in the second source-drain metal layer. The third sub-line and the second sub-line are alternately arranged in sequence and connected to each other to form an integral wiring.

16. A display device, wherein: Comprising the display panel as claimed in any one of claims 1 to 15.

Images