Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The uniformity of display brightness in a display area is improved. The display substrate comprises a substrate, a plurality of first area light-emitting elements located in a first display area, a plurality of second area light-emitting elements located in a second display area, a plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of first invalid pixel circuits, a plurality of second invalid pixel circuits and a first power transmission network. The first power transmission network includes a plurality of first transmission lines extending in a first direction and a plurality of second transmission lines extending in a second direction. The second display area comprises a first sub-display area and a second sub-display area. In the first sub-display area, at least one second transmission line is connected with a plurality of first invalid pixel circuits arranged in the second direction, and orthographic projections of the second transmission line and the first invalid pixel circuits on the substrate are overlapped; in the second sub-display area, at least one second transmission line is connected with a plurality of second invalid pixel circuits arranged in the second direction, and orthographic projections of the second transmission line and the second invalid pixel circuits on the substrate are overlapped.

Description

Technical Field

[0001] The utility model relates to, but is not limited to, the field of display technology, and particularly relates to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, lightness, thinness, bendability and low cost. The under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of a display device. Summary of the Utility Model

[0003] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0004] The utility model provides a display substrate and a display device to improve the uniformity of display brightness in a normal display area.

[0005] On the one hand, the present utility model provides a display substrate, comprising: a first display area and a second display area located on at least one side of the first display area; the second display area includes: a first sub-display area located on at least one side of the first display area, and a second sub-display area located on at least one side of the first sub-display area. The display substrate includes: a substrate, a plurality of first area light-emitting elements, a plurality of second area light-emitting elements, a plurality of first type pixel circuits, a plurality of second pixel circuits, and a first power transmission network. The plurality of first area light-emitting elements are disposed on the substrate and located in the first display area. The plurality of second area light-emitting elements, the plurality of first type pixel circuits, and the plurality of second pixel circuits are disposed on the substrate and located in the second display area. The plurality of second pixel circuits and the plurality of first type pixel circuits are arranged at intervals in a first direction; the plurality of first type pixel circuits include: a plurality of first pixel circuits located in the first sub-display area and a plurality of dummy pixel circuits located in the second display area; the plurality of dummy pixel circuits include: a plurality of first dummy pixel circuits located in the first sub-display area and a plurality of second dummy pixel circuits located in the second sub-display area; at least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first area light-emitting element among the plurality of first area light-emitting elements through at least one conductive connection line, and at least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second area light-emitting element among the plurality of second area light-emitting elements. The first power transmission network is disposed on the substrate and located in the second display area, and the first power transmission network includes a plurality of first transmission lines extending in the first direction and a plurality of second transmission lines extending in a second direction; the first direction intersects the second direction. In the first sub-display area, at least one of the plurality of second transmission lines is connected to a plurality of first dummy pixel circuits arranged in the second direction and there is an overlap in the orthographic projection on the substrate; in the second sub-display area, at least one of the plurality of second transmission lines is connected to a plurality of second dummy pixel circuits arranged in the second direction and there is an overlap in the orthographic projection on the substrate.

[0006] In some exemplary embodiments, at least one of the plurality of dummy pixel circuits is connected to a plurality of dummy pixel connection electrodes located in the same conductive layer, and at least some of the dummy pixel connection electrodes connected to the plurality of dummy pixel circuits arranged in sequence in the second direction are connected to form a second transmission line.

[0007] In some exemplary embodiments, a plurality of first dummy pixel circuit groups and a plurality of first pixel circuit groups are provided in the first sub-display area. Each first dummy pixel circuit group includes a plurality of first dummy pixel circuits arranged in sequence along the second direction, and each first pixel circuit group includes a plurality of first pixel circuits arranged in sequence along the second direction. At least one first dummy pixel circuit group among the plurality of first dummy pixel circuit groups is located on a side of at least one first pixel circuit group among the plurality of first pixel circuit groups close to the first display area.

[0008] In some exemplary embodiments, in the first direction and along the direction away from the first display area, the plurality of first pixel circuit groups and the plurality of first dummy pixel circuit groups in the first sub-display area are numbered in sequence. Among them, the numbers of at least some of the first dummy pixel circuit groups among the plurality of first dummy pixel circuit groups conform to an arithmetic progression relationship; or, the numbers of at least some of the first pixel circuit groups among the plurality of first pixel circuit groups conform to an arithmetic progression relationship.

[0009] In some exemplary embodiments, the number of each first pixel circuit group is an even number, and the number of each first dummy pixel circuit group is an odd number; or, the number of each first dummy pixel circuit group is an even number, and the number of each first pixel circuit group is an odd number; or, the numbers of the plurality of first dummy pixel circuit groups conform to the following relationship: 1+(i - 1)×3, where i is an integer greater than 0.

[0010] In some exemplary embodiments, the display substrate further includes: a plurality of data lines and a first peripheral power supply line. The plurality of data lines are provided on the substrate and located in the second display area; at least one of the plurality of data lines is connected to a plurality of dummy pixel circuits arranged along the second direction. The first peripheral power supply line is provided on the substrate and located in the border area, the border area is located on at least one side of the second display area, the first peripheral power supply line extends at least along the first direction and is connected to the first power transmission network; the data lines connected to the plurality of dummy pixel circuits arranged along the second direction are connected to the first power transmission network.

[0011] In some exemplary embodiments, the display substrate further includes: a plurality of first power supply lines, provided on the substrate and located in the second display area, at least one of the plurality of first power supply lines is connected to a plurality of dummy pixel circuits arranged along the second direction. The data lines connected to the plurality of dummy pixel circuits arranged along the second direction are connected to the first peripheral power supply line through the first power supply lines connected to the plurality of dummy pixel circuits.

[0012] In some exemplary embodiments, the first peripheral power line includes: a first peripheral trace and a second peripheral trace connected to each other; the second peripheral trace is located on a side of the first peripheral trace away from the substrate; the first peripheral trace and the first power transmission network are of an integral structure; the second peripheral trace and the plurality of first power lines are of an integral structure.

[0013] In some exemplary embodiments, the plurality of data lines are located on a side of the plurality of first power lines away from the substrate, and the plurality of first power lines are located on a side of the first power transmission network away from the substrate.

[0014] In some exemplary embodiments, in a direction perpendicular to the display substrate, the second display region includes: a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate; the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate, and the third source-drain metal layer is located on a side of the second source-drain metal layer away from the substrate. The first power transmission network is located in the first source-drain metal layer; the plurality of first power lines are located in the second source-drain metal layer; the plurality of data lines are located in the third source-drain metal layer.

[0015] In some exemplary embodiments, in the first direction, every a second pixel circuits arrange n first type pixel circuits, where both a and n are integers greater than 0, and a is greater than n.

[0016] In some exemplary embodiments, a is 4 and n is 1.

[0017] In some exemplary embodiments, the plurality of first region light-emitting elements include: a plurality of first light-emitting elements emitting first color light, a plurality of second light-emitting elements emitting second color light, and a plurality of third light-emitting elements emitting third color light. At least one of the plurality of first pixel circuits is connected to two adjacent first light-emitting elements emitting first color light; at least one of the plurality of first pixel circuits is connected to one second light-emitting element emitting second color light; at least one of the plurality of first pixel circuits is connected to one third light-emitting element emitting third color light.

[0018] In some exemplary embodiments, the plurality of second region light-emitting elements include: a plurality of fourth light-emitting elements that emit first-color light, a plurality of fifth light-emitting elements that emit second-color light, and a plurality of sixth light-emitting elements that emit third-color light. At least one second pixel circuit among the plurality of second pixel circuits is connected to two adjacent fourth light-emitting elements that emit first-color light; at least one second pixel circuit among the plurality of second pixel circuits is connected to one fifth light-emitting element that emits second-color light; and at least one second pixel circuit among the plurality of second pixel circuits is connected to one sixth light-emitting element that emits third-color light.

[0019] In some exemplary embodiments, the first-color light is green light, the second-color light is red light, and the third-color light is blue light.

[0020] On the other hand, the present invention provides a display device, including the display substrate as described above.

[0021] For the display substrate provided by the present invention, the second transmission lines of the first power transmission network are arranged in the regions where the plurality of first invalid pixel circuits in the first sub-display area are located, and the second transmission lines of the first power transmission network are arranged in the regions where the plurality of second invalid pixel circuits in the second sub-display area are located, which can ensure that the first power transmission network is formed in both the first sub-display area and the second sub-display area, thereby reducing the voltage difference of the first power signal between the first sub-display area and the second sub-display area and improving the dark display situation existing in the first sub-display area.

[0022] Other features and advantages of the present invention will be described in the following description, and some of them will become obvious from the description, or be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the structures specifically pointed out in the description and the drawings. Description of the Drawings

[0023] The drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the description. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation to the technical solutions of the present invention.

[0024] Figure 1 It is a schematic diagram of the display substrate of at least one embodiment of the present invention;

[0025] Figure 2 It is a schematic plan view of the arrangement of the light-emitting elements of the display substrate of at least one embodiment of the present invention;

[0026] Figure 3 It is a schematic diagram of an arrangement of the pixel circuits in the second display area of at least one embodiment of the present invention;

[0027] Figure 4 Schematic diagram of the connection between the second pixel circuit and the second region light-emitting element in at least one embodiment of the present utility model;

[0028] Figure 5 Equivalent circuit diagram of the pixel circuit in at least one embodiment of the present utility model;

[0029] Figure 6 Partial cross-sectional schematic diagram of the second display area of the display substrate in at least one embodiment of the present utility model;

[0030] Figure 7A Partial schematic diagram of the semiconductor layer and the first gate metal layer in the second display area of at least one embodiment of the present utility model;

[0031] Figure 7B Partial schematic diagram of the second gate metal layer in the second display area of at least one embodiment of the present utility model;

[0032] Figure 7C Partial schematic diagram of the first source-drain metal layer in the second display area of at least one embodiment of the present utility model;

[0033] Figure 7D is Figure 7C Schematic diagram of the first source-drain metal layer in

[0034] Figure 7E Schematic diagram of the second source-drain metal layer in the second display area of at least one embodiment of the present utility model;

[0035] Figure 7F Schematic diagram of the third source-drain metal layer in the second display area of at least one embodiment of the present utility model;

[0036] Figure 8A Partial schematic diagram of the boundary position between the second display area and the border area of at least one embodiment of the present utility model;

[0037] Figure 8B is Figure 8A Schematic diagram of the first source-drain metal layer in

[0038] Figure 8C is Figure 8A Schematic diagram of the second source-drain metal layer in

[0039] Figure 8D is Figure 8A Schematic diagram of the third source-drain metal layer in

[0040] Figure 9 Another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present utility model;

[0041] Figure 10 Another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present utility model;

[0042] Figure 11 Another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present utility model;

[0043] Figure 12 Another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present utility model;

[0044] Figure 13 Another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present utility model;

[0045] Figure 14 Another layout plan schematic diagram of the light-emitting elements of the display substrate of at least one embodiment of the present utility model;

[0046] Figure 15 Another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present utility model;

[0047] Figure 16 Another layout plan schematic diagram of the light-emitting elements of the display substrate of at least one embodiment of the present utility model;

[0048] Figure 17 Schematic diagram of at least one embodiment of the display device of the present utility model. Detailed implementation manners

[0049] The embodiments of the present utility model will be described in detail below with reference to the accompanying drawings. The present utility model describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be obvious to those of ordinary skill in the art that there can be more embodiments and implementation schemes within the scope of the embodiments described in the present utility model. Although many possible feature combinations are shown in the drawings and discussed in the embodiments, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0050] The present utility model includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present utility model can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown or discussed in the present utility model can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other limitations except those made in accordance with the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of the appended claims.

[0051] In addition, when describing representative embodiments, the specification may have presented a method or process as a particular sequence of steps. However, to the extent that the method or process does not depend on the particular sequence of steps described herein, the method or process should not be limited to the particular sequence of steps described. As will be understood by those of ordinary skill in the art, other sequences of steps are possible. Therefore, the particular sequence of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method or process should not be limited to performing their steps in the order written, as those skilled in the art can readily understand that these orders can vary and still remain within the spirit and scope of the embodiments of the present utility model.

[0052] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present utility model.

[0053] In addition, the terms "first", "second", etc. are only used for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. can explicitly or implicitly include at least one of such features. In the description of the present utility model, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise clearly defined.

[0054] In the present utility model, unless otherwise clearly defined and limited, the terms "installation", "connection", "attachment", "fixation", etc. shall be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or an integral one; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the internal communication between two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the meanings of the above terms in the present utility model can be understood according to the circumstances.

[0055] In the present utility model, "electrical connection" includes the case where the constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit the electrical signals between the constituent elements to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0056] In the present utility model, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first feature and the second feature are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature is at a higher horizontal level than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature is at a lower horizontal level than the second feature.

[0057] In the present utility model, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region or drain electrode) and the source (source electrode terminal, source region or source electrode), and current can flow through the drain, the channel region, and the source. In the present utility model, the channel region refers to the region where the current mainly flows.

[0058] In the present utility model, the first pole may be the drain, the second pole may be the source, or the first pole may be the source and the second pole may be the drain. In the case of using transistors with opposite polarities or when the current direction changes during the operation of the circuit, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in the present utility model, the "source" and "drain" can be interchanged. In addition, the gate can also be referred to as the control pole.

[0059] In the present utility model, "parallel" refers to a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes a state where the angle is more than 85° and less than 95°.

[0060] In the present utility model, shapes such as circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in a strict sense, and can be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There can be some small deformations caused by tolerances, such as chamfers, arc edges and deformations, etc.

[0061] The "light transmittance" in the present utility model refers to the ability of light to pass through a medium, which is the percentage of the luminous flux passing through a transparent or translucent body to its incident luminous flux.

[0062] The "about" and "substantially" in the present utility model mean that the boundaries are not strictly defined, allowing for situations within the process and measurement errors. In the present utility model, "substantially the same" means that the numerical values differ by within 10%.

[0063] In the present utility model, A extending along the B direction means that A can include a main part and a secondary part connected to the main part. The main part is in the shape of a line, a line segment or a strip, and the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. When it is said that "A extends along the B direction" in the present utility model, it always means that "the main part of A extends along the B direction".

[0064] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as notch screens, waterdrop screens, and in-screen hole-digging have emerged one after another. These technologies reduce the area occupied by the camera by digging holes in a local area of the display area and placing the camera below the hole-digging area, thereby increasing the screen-to-body ratio. However, the above-mentioned technologies need to dig out part of the display area, which will cause some areas in the display screen to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and make a true full-screen possible on the premise of ensuring the practicality of the display substrate, the pixel circuit external method or the pixel circuit internal method is usually adopted in the under-screen camera area. The pixel circuit external method means that the pixel circuit connected to the light-emitting element in the under-screen camera area is arranged in the normal display area, and the light transmittance of the under-screen camera area is increased by separately arranging the light-emitting element and the pixel circuit. Since there is no pixel circuit arranged in the under-screen camera area, there is no other light-shielding layer in this area except the anode of the light-emitting element, and a relatively high light transmittance can be achieved.

[0065] The inventor of the present utility model found through observation that there is a phenomenon of dim display in the normal display area near the under-screen camera area. Especially in the low gray-scale display scenario, the dim display near the under-screen camera area is particularly obvious. The inventor of the present utility model further analyzed and found that since the pixel circuit external method is adopted in the under-screen camera area, the external pixel circuits are all arranged in the transition area near the under-screen camera area, resulting in the voltage of the first power signal in the normal display area except the transition area being more uniform than that in the transition area. Thus, the display brightness in the transition area is less than that in the normal display area except the transition area, causing the dim display in the transition area.

[0066] This embodiment provides a display substrate and a display device, which can improve the uniformity of the display brightness in the normal display area.

[0067] This embodiment provides a display substrate, including: a first display area and a second display area located on at least one side of the first display area; the second display area includes: a first sub-display area located on at least one side of the first display area, and a second sub-display area located on at least one side of the first sub-display area. The display substrate includes: a substrate, a plurality of first area light-emitting elements, a plurality of second area light-emitting elements, a plurality of first type pixel circuits, a plurality of second pixel circuits, and a first power transmission network. The plurality of first area light-emitting elements are disposed on the substrate and located in the first display area. The plurality of second area light-emitting elements, the plurality of first type pixel circuits, and the plurality of second pixel circuits are disposed on the substrate and located in the second display area; the plurality of second pixel circuits and the plurality of first type pixel circuits are arranged at intervals in a first direction; the plurality of first type pixel circuits include: a plurality of first pixel circuits located in the first sub-display area and a plurality of invalid pixel circuits located in the second display area; the plurality of invalid pixel circuits include: a plurality of first invalid pixel circuits located in the first sub-display area and a plurality of second invalid pixel circuits located in the second sub-display area. At least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first area light-emitting element among the plurality of first area light-emitting elements through at least one conductive connection line, and at least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second area light-emitting element among the plurality of second area light-emitting elements. The first power transmission network is disposed on the substrate and located in the second display area, and the first power transmission network includes a plurality of first transmission lines extending in the first direction and a plurality of second transmission lines extending in a second direction. Wherein, the first direction intersects the second direction, for example, the first direction can be perpendicular to the second direction. In the first sub-display area, at least one second transmission line among the plurality of second transmission lines is connected to the plurality of first invalid pixel circuits arranged in the second direction and there is an overlap in the orthographic projection on the substrate; in the second sub-display area, at least one second transmission line among the plurality of second transmission lines is connected to the plurality of second invalid pixel circuits arranged in the second direction and there is an overlap in the orthographic projection on the substrate. For example, the orthographic projection of the second transmission line in the first sub-display area on the substrate can be located within the orthographic projection range of the plurality of first invalid pixel circuits arranged in the second direction on the substrate, and the orthographic projection of the second transmission line in the second sub-display area on the substrate can be located within the orthographic projection range of the plurality of second invalid pixel circuits arranged in the second direction on the substrate.

[0068] For the display substrate provided in this embodiment, by arranging the second transmission lines of the first power transmission network in the areas where the plurality of first invalid pixel circuits in the first sub-display area are located, and arranging the second transmission lines of the first power transmission network in the areas where the plurality of second invalid pixel circuits in the second sub-display area are located, it can ensure that the first power transmission network is formed in both the first sub-display area and the second sub-display area, thereby reducing the voltage difference of the first power signal between the first sub-display area and the second sub-display area and improving the situation of dark display in the first sub-display area.

[0069] In some exemplary embodiments, at least one of the plurality of dummy pixel circuits is connected to a plurality of dummy pixel connection electrodes located in the same conductive layer, and at least some of the dummy pixel connection electrodes connected to the plurality of dummy pixel circuits arranged in sequence along the second direction are connected to form a second transmission line. In this example, the region where the dummy pixel circuit is located is used to form the second transmission line, which can ensure the formation of a first power supply transmission network for transmitting the first power signal in the first sub-display area and the second sub-display area, and improve the transmission uniformity of the first power signal in the second display area.

[0070] In some exemplary embodiments, a plurality of first dummy pixel circuit groups and a plurality of first pixel circuit groups are provided in the first sub-display area. Each first dummy pixel circuit group includes a plurality of first dummy pixel circuits arranged in sequence along the second direction, and each first pixel circuit group includes a plurality of first pixel circuits arranged in sequence along the second direction. At least one of the plurality of first dummy pixel circuit groups is located on a side of at least one of the plurality of first pixel circuit groups closer to the first display area. For example, one first pixel circuit group is one first pixel circuit column, and one first dummy pixel circuit group is one first dummy pixel circuit column.

[0071] In some examples, in the first direction and along the direction away from the first display area, the plurality of first pixel circuit groups and the plurality of first dummy pixel circuit groups in the first sub-display area are numbered in sequence; at least some of the numbers of the plurality of first dummy pixel circuit groups conform to an arithmetic progression relationship, or at least some of the numbers of the plurality of first pixel circuit groups conform to an arithmetic progression relationship. For example, the numbers of all the first dummy pixel circuit groups in the first sub-display area conform to an arithmetic progression relationship, or the numbers of all the first pixel circuit groups conform to an arithmetic progression relationship. For example, the number of each first pixel circuit group is an even number, and the number of each first dummy pixel circuit group is an odd number; or the number of each first dummy pixel circuit group is an even number, and the number of each first pixel circuit group is an odd number; or the numbers of the plurality of first dummy pixel circuit groups conform to the following relationship: 1 + (i - 1) × 3, where i is an integer greater than 0. The arrangement of the first dummy pixel circuit and the first pixel circuit in this example can ensure the arrangement of the second transmission line of the first power supply transmission network in the first sub-display area, thereby reducing the voltage drop of the first power signal in the first sub-display area, improving the transmission uniformity of the first power signal in the second display area, and further improving the dark display situation in the first sub-display area.

[0072] The following uses some examples to illustrate the solution of this embodiment.

[0073] Figure 1Schematic diagram of a display substrate according to at least one embodiment of the present utility model. In some examples, the display substrate may include: a display area AA, and a border area BB surrounding the periphery of the display area AA. For example, the border area BB may include: a first border area B1, a second border area B2, a third border area B3, and a fourth border area B4 located around the display area AA. The first border area B1 and the second border area B2 may be located on opposite sides of the display area AA along the second direction D2, and the third border area B3 and the fourth border area B4 may be located on opposite sides of the display area AA along the first direction D1. Among them, the first direction D1 intersects with the second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2. In some examples, the first border area B1 may be the upper border of the display substrate, the second border area B2 may be the lower border of the display substrate, the third border area B3 may be the left border of the display substrate, and the fourth border area B4 may be the right border of the display substrate.

[0074] In some examples, the display area AA may include: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the first display area A1 may be located at the exact middle position at the top of the display area AA, and the second display area A2 may surround the first display area A1 on all sides. However, this embodiment is not limited thereto. For example, the first display area A1 may be located at the upper left corner or the upper right corner of the display area AA or other positions, and the second display area A2 may surround at least one side of the first display area A1.

[0075] In some examples, as Figure 1 shown, the display area AA may be rectangular, such as a rounded rectangle. The first display area A1 may be circular or oval. However, this embodiment is not limited thereto. For example, the first display area A1 may be rectangular, semi-circular, pentagonal or other shapes.

[0076] In some examples, the first display area A1 may be a transmissive display area, also known as an under-screen camera (FDC, Full Display with Camera) area, configured to perform image display and transmit light; the second display area A2 may be called a normal display area, configured to perform image display. For example, the orthographic projection of a sensor (such as a camera, an infrared sensor, etc., hardware) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as Figure 1 shown, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited thereto. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0077] In some examples, such as Figure 1 shown, the pixel density of the first display area A1 can be less than or equal to the pixel density of the second display area A2. For example, the pixel density of the first display area A1 can be equal to the pixel density of the second display area A2. In some examples, the ratio of the resolution of the first display area A1 to the resolution of the second display area A2 can be approximately 0.8 to 1.2. Or, the resolution of the second display area A2 and the resolution of the first display area A1 can be substantially the same. This embodiment does not limit this.

[0078] In some examples, the display substrate can at least include: a plurality of first area light-emitting elements 31 located in the first display area A1, a plurality of second area light-emitting elements 32 located in the second display area A2, and a plurality of pixel circuits. The plurality of pixel circuits located in the second display area A2 can include: a plurality of first type pixel circuits and a plurality of second pixel circuits 42. The plurality of first type pixel circuits can include: a plurality of first pixel circuits 41 and a plurality of dummy pixel circuits.

[0079] In some examples, at least one first pixel circuit 41 among the plurality of first pixel circuits 41 can be electrically connected to at least one first area light-emitting element 31 among the plurality of first area light-emitting elements 31 through a conductive connection line 51. The first pixel circuit 41 can be configured to provide a driving signal to the connected first area light-emitting element 31 to drive the corresponding first area light-emitting element 31 to emit light. For example, the plurality of first pixel circuits 41 and the plurality of first area light-emitting elements 31 can have a one-to-one driving relationship, or can have a one-to-many driving relationship. Since the first area light-emitting element 31 and the first pixel circuit 41 are located in different areas, the orthographic projection of at least one first pixel circuit 41 on the substrate and the orthographic projection of at least one first area light-emitting element 31 on the substrate may not have an overlapping part.

[0080] In some examples, at least one second pixel circuit 42 among the plurality of second pixel circuits 42 can be electrically connected to at least one second light-emitting element 32 among the plurality of second area light-emitting elements 32, and the orthographic projection of at least one second pixel circuit 42 on the substrate and the orthographic projection of at least one second area light-emitting element 32 on the substrate can at least partially overlap. The second pixel circuit 42 can be configured to provide a driving signal to the connected second area light-emitting element 32 to drive the corresponding second area light-emitting element 32 to emit light. For example, the plurality of second pixel circuits 42 and the plurality of second area light-emitting elements 32 can have a one-to-one driving relationship, or can have a one-to-many driving relationship.

[0081] Figure 2 It is a schematic plan view of the arrangement of the light-emitting elements of the display substrate according to at least one embodiment of the present invention. In some examples, such as Figure 1and Figure 2 As shown in Figure 2 , the first display area A1 of the display substrate may include a plurality of first area light-emitting elements 31. The plurality of first area light-emitting elements 31 may include: a plurality of first light-emitting elements 31a and 31d that emit first-color light, a plurality of second light-emitting elements 31b that emit second-color light, and a plurality of third light-emitting elements 31c that emit third-color light. The second display area A2 of the display substrate may include a plurality of second area light-emitting elements 32. The plurality of second area light-emitting elements 32 may include: a plurality of fourth light-emitting elements 32a and 32d that emit first-color light, a plurality of fifth light-emitting elements 32b that emit second-color light, and a plurality of sixth light-emitting elements 32c that emit third-color light. In some examples, the first-color light may be green light, the second-color light may be red light, and the third-color light may be blue light. However, this embodiment is not limited thereto.

[0082] In some examples, a pixel unit in the first display area A1 may include four first area light-emitting elements (for example, including two first light-emitting elements 31a and 31d, one second light-emitting element 31b, and one third light-emitting element 31c). The two first light-emitting elements 31a and 31d, one second light-emitting element 31b, and one third light-emitting element 31c may be arranged in a diamond shape to form an RGBG pixel arrangement. For example, the second light-emitting element 31b and the third light-emitting element 31c may be spaced apart in the same row along the first direction D1 and spaced apart in the same column along the second direction D2; the first light-emitting elements 31a and 31d may be arranged in sequence in the same row along the first direction D1 and arranged in sequence in the same column along the second direction D2. The row where the second light-emitting element 31b and the third light-emitting element 31c are located is spaced apart from the row where the first light-emitting elements 31a and 31d are located, and the column where the second light-emitting element 31b and the third light-emitting element 31c are located is spaced apart from the column where the first light-emitting elements 31a and 31d are located. The arrangement of the fourth light-emitting elements 32a and 32d, the fifth light-emitting elements 32b, and the sixth light-emitting elements 32c in the second display area A2 may be the same as the arrangement of the first light-emitting elements 31a and 31d, the second light-emitting element 31b, and the third light-emitting element 31c in the first display area A1, so it will not be described herein again.

[0083] In some examples, two adjacent first light-emitting elements 31a and 31d arranged along the first direction D1 within the first display area A1 can be connected to each other. For example, the anodes of two adjacent first light-emitting elements 31a and 31d arranged along the first direction D1 can be connected to each other. In this example, the first pixel circuit within the second display area A2 and the first light-emitting elements within the first display area A1 can have a one-to-two driving relationship. In other words, one first pixel circuit within the second display area A2 can be configured to drive two first light-emitting elements within the first display area A1 (such as one first light-emitting element 31a and one first light-emitting element 31d). The first pixel circuit within the second display area A2 and the second light-emitting element 31b within the first display area A1 can have a one-to-one driving relationship, and the first pixel circuit within the second display area A2 and the third light-emitting element 31c within the first display area A1 can have a one-to-one driving relationship. The second pixel circuit within the second display area A2 and the second area light-emitting elements can have a one-to-one driving relationship.

[0084] In some examples, each light-emitting element of the display area can include: an anode, an organic light-emitting layer, and a cathode that are sequentially stacked. In this example, the light-emitting area of the light-emitting element refers to the stacked area of the anode, the organic light-emitting layer, and the cathode of the light-emitting element, that is, the connection area of the anode exposed by the pixel opening of the pixel definition layer with the organic light-emitting layer and the cathode.

[0085] In some examples, the area of the light-emitting area of a single first area light-emitting element 31 can be smaller than the area of the light-emitting area of a single second area light-emitting element 32 that emits the same color of light. Among them, the area of the light-emitting area of the first light-emitting element 31a (or 31d) can be smaller than the area of the light-emitting area of the fourth light-emitting element 32a (or 32d). The area of the light-emitting area of the second light-emitting element 31b can be smaller than the area of the light-emitting area of the fifth light-emitting element 32b. The area of the light-emitting area of the third light-emitting element 31c can be smaller than the area of the light-emitting area of the sixth light-emitting element 32c. For example, the orthographic projection of a single second area light-emitting element 32 on the substrate can be a quadrilateral or a pentagon, and the orthographic projection of a single first area light-emitting element 31 on the substrate can be a circle or an ellipse. In this example, by reducing the area of the light-emitting area of the first area light-emitting element, the light transmittance of the first display area can be improved, and the diffraction situation can be improved.

[0086] Figure 3 It is a schematic layout diagram of the pixel circuit of the second display area in at least one embodiment of the present utility model. Figure 4 It is a schematic connection diagram of the second pixel circuit and the second area light-emitting elements of the second display area in at least one embodiment of the present utility model.

[0087] In some examples, such as Figure 1 and Figure 3As shown, the second display area A2 of the display substrate may include: a first sub-display area (which may also be referred to as a transition area) A21 and a second sub-display area (which may also be referred to as a non-transition area) A22. The first sub-display area A21 may be located on at least one side outside the first display area A1 (for example, one side; or, both the left and right sides; or, all around, that is, including both the upper and lower sides and the left and right sides). The first sub-display area A21 may be connected to the first display area A1, and the second sub-display area A22 may be located on at least one side of the first sub-display area A21, for example, it may surround the first sub-display area A21 all around.

[0088] In some examples, the multiple pixel circuits in the second display area include: multiple first pixel circuits 41 located in the first sub-display area A21, multiple first dummy pixel circuits 43a located in the first sub-display area A21, multiple second dummy pixel circuits 43b located in the second sub-display area A22, and multiple second pixel circuits 42 located in the second display area A2.

[0089] In some examples, the multiple first pixel circuits 41 in the first sub-display area A21 may be arranged at intervals between the multiple second pixel circuits 42, and the multiple first dummy pixel circuits 43a may be arranged at intervals between the multiple second pixel circuits 42; the multiple second dummy pixel circuits 43b in the second sub-display area A22 may be arranged at intervals between the multiple second pixel circuits 42. For example, between two adjacent first pixel circuits 41 in the first direction D1, multiple second pixel circuits 42 may be arranged, between two adjacent first dummy pixel circuits 43a in the first direction D1, multiple second pixel circuits 42 may be arranged, and between two adjacent second dummy pixel circuits 43b in the first direction D1, multiple second pixel circuits 42 may be arranged. In this example, by providing multiple dummy pixel circuits (including multiple first dummy pixel circuits 43a and multiple second dummy pixel circuits 43b) in the second display area A2, it is beneficial to improve the uniformity of the components of multiple film layers in the etching process. For example, the dummy pixel circuit may have a structure substantially the same as that of the first pixel circuit in its row or column, except that it is not electrically connected to any light-emitting element.

[0090] In some examples, at least one first pixel circuit 41 in the first sub-display area A21 can be electrically connected to at least one first area light-emitting element 31 through a conductive connection line 51, and is configured to drive the at least one first area light-emitting element 31 to emit light. For example, two adjacent first area light-emitting elements 31 that emit the first color light (such as green G) in the first display area A1 can be driven by the same first pixel circuit 41, a single first area light-emitting element 31 that emits the second color light (such as red R) in the first display area A1 can be driven by a first pixel circuit 41, and a single first area light-emitting element 31 that emits the third color light (such as blue B) in the first display area A1 can be driven by a first pixel circuit 41. In some examples, the first pixel circuit that drives the first area light-emitting element 31 that emits the first color light can be located on the side of the first pixel circuits that drive the first area light-emitting elements 31 that emit the second and third color lights and is closer to the first display area A1. In some examples, the conductive connection line 51 can be prepared from a transparent conductive material to improve the light transmittance of the display substrate. For example, multiple conductive connection lines 51 can be arranged in at least one transparent conductive layer.

[0091] In some examples, as Figure 4 shown, a second pixel circuit 42 in the second display area A2 can be connected to the anode of a second area light-emitting element 32 (such as anodes 320a, 320b, 320c, or 320d). The orthographic projection of the anode of the second area light-emitting element 32 on the substrate and the orthographic projection of the connected second pixel circuit 42 on the substrate can partially overlap.

[0092] In some examples, since the second display area A2 is provided with not only the second pixel circuit 42 electrically connected to the second area light-emitting element 32 but also the first pixel circuit 41 electrically connected to the first area light-emitting element 31, the number of pixel circuits in the second display area A2 is greater than the number of second area light-emitting elements 32. In some examples, an area for arranging additional pixel circuits (i.e., the first type of pixel circuits, including the first pixel circuit 41, the first dummy pixel circuit 43a, and the second dummy pixel circuit 43b) can be obtained by reducing the size of the second pixel circuit 42 in the first direction D1. For example, the size of the pixel circuit in the first direction D1 can be smaller than the size of the second area light-emitting element in the first direction D1.

[0093] In this example, multiple pixel circuits in the second display area A2 can be arranged in an array along a first direction D1 and a second direction D2. The original a pixel circuit columns can be compressed along the first direction D1 to create a layout space for an additional pixel circuit column, and the space occupied by the a pixel circuit columns before compression and the a + 1 pixel circuit columns after compression can be the same. Here, a can be an integer greater than 1. In some examples, a can be equal to 4. That is, along the first direction D1, a first pixel circuit column or an invalid pixel circuit column can be arranged every four second pixel circuit columns. However, this embodiment is not limited thereto. For example, a can be equal to 2 or 3.

[0094] In other examples, the original b pixel circuit rows can be compressed along the second direction D2 to create a layout space for an additional pixel circuit row, and the space occupied by the b pixel circuit rows before compression and the b + 1 pixel circuit rows after compression is the same. Here, b can be an integer greater than 1. Alternatively, an area for arranging additional pixel circuits can be obtained by reducing the size of the second pixel circuits in the first direction D1 and the second direction D2.

[0095] In this example, a pixel circuit group can be a pixel circuit column. A pixel circuit row can include multiple pixel circuits arranged in sequence along the first direction D1, and the multiple pixel circuits in a pixel circuit row can all be connected to the same gate line. A pixel circuit column can include multiple pixel circuits arranged in sequence along the second direction D2.

[0096] In some examples, in the second display area A2, multiple second pixel circuit columns 420, multiple first pixel circuit columns 410, and multiple invalid pixel circuit columns (for example, including multiple first invalid pixel circuit columns 430a and multiple second invalid pixel circuit columns 430b) can be arranged at intervals along the first direction D1. Each second pixel circuit column 420 includes multiple second pixel circuits 42 arranged in sequence along the second direction D2; each first pixel circuit column 410 includes multiple first pixel circuits 41 arranged in sequence along the second direction D2, each first invalid pixel circuit column 430a includes multiple first invalid pixel circuits 43a arranged in sequence along the second direction D2, and each second invalid pixel circuit column 430b includes multiple second invalid pixel circuits 43b arranged in sequence along the second direction D2. For example, a first pixel circuit column 410, or a first invalid pixel circuit column 430a, or a second invalid pixel circuit column 430b can be arranged at an interval of four second pixel circuit columns 420. In the first sub-display area A21, multiple first invalid pixel circuit columns 430a, multiple first pixel circuit columns 410, and multiple second pixel circuit columns 420 can be arranged at intervals.

[0097] In some examples, such as Figure 3As shown, within the first sub-display area A21, along the first direction D1 away from the first display area A1, the multiple first pixel circuit columns 410 and the multiple first dummy pixel circuit columns 430a inserted in the multiple second pixel circuit columns 420 can be numbered. Among them, the numbers of the multiple first dummy pixel circuit columns 430a can conform to an arithmetic progression relationship. For example, among the multiple first pixel circuit columns 410 and the multiple first dummy pixel circuit columns 430a in the first sub-display area A21, the numbers of the multiple first dummy pixel circuit columns 430a can satisfy the following relationship: 1+(i - 1)×3, where i is an integer greater than 0. For instance, along the first direction D1 away from the first display area A1, the 1st column, the 4th column, and the 7th column inserted in the multiple second pixel circuit columns 420 are all first dummy pixel circuit columns 430a, and the 2nd column, the 3rd column, the 5th column, and the 6th column inserted in the multiple second pixel circuit columns 420 are all first pixel circuit columns 410. Within the second sub-display area A22, the multiple pixel circuit columns inserted in the multiple second pixel circuit columns 420 are all second dummy pixel circuit columns 430b.

[0098] In some examples, the second display area A2 can be provided with a first power transmission network, and the first power transmission network can include: multiple first transmission lines extending along the first direction D1 and multiple second transmission lines extending along the second direction D2. The multiple first dummy pixel circuit columns 430a in the first sub-display area A21 can be connected to the multiple second transmission lines, and the multiple second dummy pixel circuit columns 430b in the second sub-display area A22 can be connected to the multiple second transmission lines. For example, one first dummy pixel circuit column 430a is connected to one second transmission line, and one second dummy pixel circuit column 430b is connected to one second transmission line. Within the first sub-display area A21, the orthographic projection of the second transmission line on the substrate overlaps with the orthographic projection of the connected first dummy pixel circuit column 430a on the substrate; within the second sub-display area A22, the orthographic projection of the second transmission line on the substrate overlaps with the orthographic projection of the connected second dummy pixel circuit column 430b on the substrate. For example, within the first sub-display area A21, the orthographic projection of the second transmission line on the substrate can be located within the orthographic projection range of the connected first dummy pixel circuit column 430a on the substrate; within the second sub-display area A22, the orthographic projection of the second transmission line on the substrate can be located within the orthographic projection range of the connected second dummy pixel circuit column 430b on the substrate.

[0099] In this example, at least one first dummy pixel circuit column 430a is used in the first sub-display area A21 to set a second transmission line, and at least one second dummy pixel circuit column 430b is used in the second sub-display area A22 to set a second transmission line, so that a first power transmission network is formed in the second display area, which can reduce the voltage difference of the first power signal between the first sub-display area and the second sub-display area, improve the transmission uniformity of the first power signal in the second display area, and thus improve the phenomenon of dim display in the first sub-display area.

[0100] Figure 5 It is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present invention. The pixel circuit of this exemplary embodiment will be described by taking the 7T1C structure as an example. In some examples, as Figure 5 shown, the pixel circuit of this example may include a first transistor (which may also be referred to as a first reset transistor) T1, a second transistor (which may also be referred to as a threshold compensation transistor) T2, a third transistor (which may also be referred to as a driving transistor) T3, a fourth transistor (which may also be referred to as a data writing transistor) T4, a fifth transistor (which may also be referred to as a first light emission control transistor) T5, a sixth transistor (which may also be referred to as a second light emission control transistor) T6, a seventh transistor (which may also be referred to as a second reset transistor) T7, and a storage capacitor Cst. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0101] In some examples, as Figure 5 shown, the display substrate may include: a scan line GL, a data line DL, a first power supply line PL1, a second power supply line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power supply line PL1 may be configured to provide a constant first power signal VDD to the pixel circuit, the second power supply line PL2 may be configured to provide a constant second power signal VSS to the cathode of the light-emitting element EL, and the first power signal VDD is greater than the second power signal VSS. The scan line GL may be configured to provide a scan signal SCAN to the pixel circuit, the data line DL may be configured to provide a data signal DATA to the pixel circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the pixel circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, the second reset control line RST2 connected to the k-th row of pixel circuits and the first reset control line RST1 connected to the (k + 1)-th row of pixel circuits may be an integrated structure. Wherein, n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, and a narrow bezel design of the display substrate can be achieved.

[0102] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first power supply signal VDD and the second power supply signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be set to provide the first initial signal.

[0103] In some examples, as Figure 5 shown, the third transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first power supply signal VDD, and the second power supply signal VSS. The gate of the fourth transistor T4 is electrically connected to the scan line GL, the first pole of the fourth transistor T4 is electrically connected to the data line DL, and the second pole of the fourth transistor T4 is electrically connected to the first pole of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GL, the second pole of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the first pole of the second transistor T2 is electrically connected to the second pole of the driving transistor T3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first pole of the fifth transistor T5 is electrically connected to the first power supply line PL1, and the second pole of the fifth transistor T5 is electrically connected to the first pole of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first pole of the sixth transistor T6 is electrically connected to the second pole of the third transistor T3, and the second pole of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first pole of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0104] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2. The second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3. The third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6. The fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0105] The working process of the Figure 5 schematic pixel circuit will be described below. Taking the Figure 5 example that the multiple transistors included in the shown pixel circuit are all P-type transistors. In some examples, during a frame display period, the working process of the pixel circuit may include: a first stage, a second stage, and a third stage.

[0106] The first stage is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, which turns on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, which turns off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The light-emitting element EL does not emit light during this stage.

[0107] The second stage is called the data writing stage or the threshold compensation stage. The scan signal SCAN provided by the scan line GL is a low-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the emission control signal EM provided by the emission control line EML are both high-level signals, and the data line DL outputs the data signal DATA. In this stage, since the first electrode of the storage capacitor Cst is at a low level, the third transistor T3 is turned on. The scan signal SCAN being a low-level signal turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage Vdata output by the data line DL to be provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The conduction of the seventh transistor T7 causes the second initial signal provided by the second initial signal line INIT2 to be provided to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL, clearing the pre-stored voltage inside it, completing the initialization, and ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 being a high-level signal turns off the first transistor T1. The emission control signal EM provided by the emission control line EML being a high-level signal turns off the fifth transistor T5 and the sixth transistor T6.

[0108] The third stage is called the light-emitting stage. The emission control signal EM provided by the emission control line EML is a low-level signal, and the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The emission control signal EM provided by the emission control line EML being a low-level signal turns on the fifth transistor T5 and the sixth transistor T6, and the first power supply signal VDD output by the first power supply line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting element EL to emit light.

[0109] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0110] I = K × (Vgs - Vth) 2= K × [(VDD - Vdata + |Vth|) - Vth] 2 = K × [VDD - Vdata] 2 。

[0111] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first power signal output by the first power supply line PL1.

[0112] It can be seen from the above formula that the current flowing through the light-emitting element EL is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can preferably compensate for the threshold voltage of the third transistor T3.

[0113] Figure 6 This is a partial cross-sectional schematic diagram of the second display area of the display substrate according to at least one embodiment of the present invention. Figure 6 The structure of one second-region light-emitting element and one second pixel circuit in the second display area is taken as an example for illustration. In this example, it is assumed that the types of multiple transistors in the pixel circuit are the same. For example, multiple transistors in the pixel circuit can all be made of low-temperature polycrystalline silicon thin-film transistors or all be made of oxide thin-film transistors. In other examples, multiple transistors in the pixel circuit can be made of low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors.

[0114] In some examples, as Figure 6 shown, in the direction perpendicular to the display substrate, the second display area of the display substrate may include: a substrate 10, and a circuit structure layer 11, a conductive connection layer 12, a light-emitting structure layer 13, and a packaging structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 11 in the second display area may at least include: multiple first pixel circuits, multiple second pixel circuits, and multiple dummy pixel circuits. Each pixel circuit may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 in the second display area may at least include: multiple second-region light-emitting elements.

[0115] In some examples, Figure 6Taking a thin-film transistor 21 and a capacitor 22 included in the second pixel circuit as an example for illustration. In some examples, the circuit structure layer 11 of the second display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer provided on the substrate 10. A first gate insulating layer 101 may be provided between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 may be provided between the second gate metal layer and the first source-drain metal layer, a passivation layer 104 and a first planarization layer 105 may be provided between the first source-drain metal layer and the second source-drain metal layer, a second planarization layer 106 may be provided between the second source-drain metal layer and the third source-drain metal layer, and a third planarization layer 107 may be provided on the side of the third source-drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 may be inorganic insulating layers, and the first planarization layer 105, the second planarization layer 106, and the third planarization layer 107 may be organic insulating layers. However, this embodiment does not limit this. In some other examples, a buffer layer may further be provided on the side of the semiconductor layer close to the substrate. The buffer layer may prevent harmful substances in the substrate from invading the interior of the display substrate, and may also increase the adhesion of the film layers in the display substrate to the substrate. In some other examples, a bottom shielding metal layer (BSM, Bottom Shielding Metal) may be provided on the side of the buffer layer close to the substrate. The bottom shielding metal layer may be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid the influence of external light on the performance of the thin-film transistor. In some other examples, the passivation layer between the first source-drain metal layer and the second source-drain metal layer may be omitted, and only the first planarization layer may be provided between the first source-drain metal layer and the second source-drain metal layer. In some other examples, the circuit structure layer may omit the third source-drain metal layer, or the circuit structure layer may further include a fourth source-drain metal layer on the side of the third source-drain metal layer away from the substrate.

[0116] In some examples, as Figure 6 shown, the conductive connection layer 12 may include: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer sequentially provided along the direction of the substrate 10. A fourth planarization layer 108 may be provided between the first conductive connection layer and the second conductive connection layer, a fifth planarization layer 109 may be provided between the second conductive connection layer and the third conductive connection layer, and a sixth planarization layer 110 may be provided on the side of the third conductive connection layer away from the substrate 10. Among them, the fourth planarization layer 108, the fifth planarization layer 109, and the sixth planarization layer 110 may be organic insulating layers. In some examples, the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer may be made of a transparent conductive material, for example, may include indium tin oxide (ITO).

[0117] In some examples, such as Figure 6As shown, the semiconductor layer of the second display region may at least include: the active layer 210 of the thin film transistor 21. The active layer 210 of the thin film transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may at least include: the gate 213 of the thin film transistor 21, and the first electrode plate 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin film transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10. The second gate metal layer may at least include: the second electrode plate 222 of the capacitor 22. The orthographic projection of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may coincide. The first source-drain metal layer may at least include: the source electrode 211 and the drain electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may be provided with a plurality of vias in the display region (for example, including a first pixel via and a second pixel via). The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a part of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a part of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may at least include: a first transfer electrode 231. The first transfer electrode 231 may be electrically connected to the drain electrode 212 of the thin film transistor 21 of the pixel circuit through a third pixel via opened by the passivation layer 104 and the first planarization layer 105. The third source-drain metal layer may at least include: a second transfer electrode 232. The second transfer electrode 232 may be connected to the first transfer electrode 231 through a fourth pixel via opened by the second planarization layer 106. The first conductive connection layer may at least include: a third transfer electrode 233. The third transfer electrode 233 may be connected to the second transfer electrode 232 through a fifth pixel via opened by the third planarization layer 107. The second conductive connection layer may at least include: a fourth transfer electrode 234. The fourth transfer electrode 234 may be connected to the third transfer electrode 233 through a sixth pixel via opened by the fourth planarization layer 108. The third conductive connection layer may at least include: a fifth transfer electrode 235. The fifth transfer electrode 235 may be connected to the fourth transfer electrode 234 through a seventh pixel via opened by the fifth planarization layer 109. In some examples, the orthographic projections of the fifth pixel via, the sixth pixel via, and the seventh pixel via on the substrate may be rectangular or circular.For example, the orthographic projections of the seventh pixel via and the fifth pixel via on the substrate may overlap, and the orthographic projection of the sixth pixel via on the substrate and the orthographic projection of the seventh pixel via on the substrate may have no overlap. This example can implement the electrical connection between the pixel circuit and the light-emitting element through the second source-drain metal layer, the third source-drain metal layer, and three conductive connection layers. However, this embodiment is not limited thereto. In other examples, the number of conductive connection layers may be one, two, or more.

[0118] In some examples, the orthographic projections of the third transfer electrode 233, the fourth transfer electrode 234, and the fifth transfer electrode 235 on the substrate may be rectangular. The orthographic projections of the third transfer electrode 233, the fourth transfer electrode 234, and the fifth transfer electrode 235 on the substrate may overlap, and may partially overlap with the orthographic projection of the second transfer electrode 232 on the substrate.

[0119] In some examples, as Figure 6 shown, the light-emitting structure layer 13 in the display area may include: a pixel definition layer 304 and a plurality of light-emitting elements (for example, including a plurality of second-region light-emitting elements located in the second display region A2 and a plurality of first-region light-emitting elements located in the first display region A1). For example, each light-emitting element may include: a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. For example, the first electrode 301 of the second-region light-emitting element located in the second display region A2 may be disposed on the fifth flat layer 110 and electrically connected to the fifth transfer electrode 235 through an eighth pixel via formed in the fifth flat layer 110. The pixel definition layer 304 is disposed on the first electrode 301 and the fifth flat layer 110. The pixel definition layer 304 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a part of the surface of a corresponding first electrode 301. At least a part of the organic light-emitting layer 302 may be disposed in one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation column layer may also be disposed on the side of the pixel definition layer 304 away from the substrate 10, and the isolation column layer may include a plurality of isolation columns (PS).

[0120] In some examples, the organic light-emitting layer 302 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Driven by the voltages of the first electrode 301 and the second electrode 303, light can be emitted according to the required gray scale by utilizing the light-emitting characteristics of the organic material.

[0121] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be fabricated by a single process (a single evaporation process or a single inkjet printing process), and isolation may be achieved by means of surface step differences formed by the film layers or by surface treatment, etc. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer may be prepared by evaporation using a fine metal mask (FMM, Fine Metal Mask) or an open mask, or by an inkjet process.

[0122] In some examples, as Figure 6 shown, the encapsulation structure layer 14 may include a stacked first encapsulation layer 1401, a second encapsulation layer 1402, and a third encapsulation layer 1403. Among them, the first encapsulation layer 1401 and the third encapsulation layer 1403 may adopt inorganic materials, the second encapsulation layer 1402 may adopt an organic material, and the second encapsulation layer 1402 may be disposed between the first encapsulation layer 1401 and the third encapsulation layer 1403 to ensure that external moisture cannot enter the light-emitting element. However, this embodiment is not limited thereto. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0123] The circuit structure layer of the second display area will be illustrated by way of example below. Figures 7A to 7FTaking two rows (for example, the k-th row and the (k + 1)-th row) and five columns (for example, the f-th column to the (f + 4)-th column) of pixel circuits in the first sub-display area of the second display area as an example for illustration. Among them, the pixel circuits in the f-th column, the (f + 1)-th column, the (f + 2)-th column, and the (f + 3)-th column are all second pixel circuit columns, and the pixel circuit in the (f + 4)-th column can be a first invalid pixel circuit column. Wherein, both f and k are integers greater than 0. For example, the equivalent circuit diagram of the second pixel circuit can be as Figure 5 shown, and may include a first transistor T21, a second transistor T22, a third transistor T23, a fourth transistor T24, a fifth transistor T25, a sixth transistor T26, a seventh transistor T27, and a storage capacitor C1; the first invalid pixel circuit may include: a first transistor T31, a second transistor T32, a third transistor T33, a fourth transistor T34, a fifth transistor T35, a sixth transistor T36, a seventh transistor T37, and a storage capacitor C2.

[0124] Figure 7A is a partial schematic diagram of the semiconductor layer and the first gate metal layer in the second display area of at least one embodiment of the present invention. In some examples, as Figure 7A shown, the semiconductor layer in the second display area may include: active layers of multiple transistors of multiple second pixel circuits (for example, active layers including the first transistor T21 to the seventh transistor T27), and active layers of multiple transistors of multiple first invalid pixel circuits (for example, active layers including the first transistor T31 to the seventh transistor T37). The active layers of the first transistor T21 to the seventh transistor T27 of a single second pixel circuit may be an integrally connected structure, and the active layers of the first transistor T31 to the seventh transistor T37 of a single first invalid pixel circuit may be an integrally connected structure.

[0125] In some examples, as Figure 7A shown, the first gate metal layer in the second display area may include: gates of multiple transistors of multiple second pixel circuits (for example, gates including the first transistor T21 to the seventh transistor T27), gates of multiple transistors of the first invalid pixel circuit (for example, gates including the first transistor T31 to the seventh transistor T37), multiple scan lines (for example, including scan lines GL(k), GL(k + 1)), multiple first reset control lines (for example, including first reset control lines RST1(k), RST1(k + 1), RST1(k + 2)), and multiple light emission control lines (for example, including light emission control lines EML(k), EML(k + 1)). The multiple scan lines, the multiple first reset control lines, and the multiple light emission control lines may all extend along the first direction D1, for example, may be a broken line extending along the first direction D1.

[0126] In some examples, as Figure 7AAs shown, the first reset control line RST1(k + 1) connected to the pixel circuit of the (k + 1)-th row can be used as the second reset control line connected to the pixel circuit of the k-th row. The scan line GL(k) can be an integrated structure connected to the gates of the second transistor T22 and the fourth transistor T24 of the second pixel circuit located in the k-th row, the gates of the second transistor T32 and the fourth transistor T34 of the first dummy pixel circuit. The first reset control line RST1(k) can be an integrated structure connected to the gates of the first transistor T21 of the second pixel circuit located in the k-th row and the gates of the first transistor T31 of the first dummy pixel circuit. The emission control line EML(k) can be an integrated structure connected to the gates of the fifth transistor T25 and the sixth transistor T26 of the second pixel circuit located in the k-th row, the gates of the fifth transistor T35 and the sixth transistor T36 of the first dummy pixel circuit. The gate of the third transistor T23 of the second pixel circuit can simultaneously serve as the first electrode of the storage capacitor of the second pixel circuit, and the gate of the third transistor T33 of the first dummy pixel circuit can simultaneously serve as the first electrode of the storage capacitor of the first dummy pixel circuit.

[0127] Figure 7B It is a partial schematic diagram of the second gate metal layer of the second display area of at least one embodiment of the present invention. In some examples, as Figure 7B shown, the second gate metal layer of the second display area may include: a plurality of first initial signal lines (for example, including first initial signal lines INIT1(k), INIT1(k + 1), INIT1(k + 2)), a plurality of second initial signal lines (for example, including second initial signal lines INIT2(k), INIT2(k - 1), INIT2(k + 1)), the second electrodes of the storage capacitors C1 of a plurality of second pixel circuits, and the second electrodes of the storage capacitors C2 of a plurality of first dummy pixel circuits. The second plates of the storage capacitors C1 of a plurality of second pixel circuits located in the same row and the second plates of the storage capacitors C2 of a plurality of first dummy pixel circuits can be an integrated structure connected to each other. The plurality of first initial signal lines and the plurality of second initial signal lines may extend along the first direction D1, for example, may be a broken line extending along the first direction D1.

[0128] Figure 7C It is a partial schematic diagram of the first source-drain metal layer of the second display area of at least one embodiment of the present invention. Figure 7D is Figure 7C the schematic diagram of the first source-drain metal layer in Figure 7C and Figure 7DAs shown, the first source-drain metal layer in the second display area may include: multiple pixel connection electrodes (such as including the first pixel connection electrode 401 to the sixth pixel connection electrode 406), multiple dummy pixel connection electrodes (such as including the first dummy pixel connection electrode 411 to the sixth dummy pixel connection electrode 416), multiple first transmission lines 551, and multiple auxiliary routing segments 54.

[0129] In some examples, the first transmission line 551 may be located between adjacent rows of pixel circuits (such as the k-th row and the (k + 1)-th row of pixel circuits) and extend along the first direction D1. The multiple auxiliary routing segments 54 may be arranged at intervals along the first direction D1 and extend along the first direction D1. The multiple auxiliary routing segments 54 may be located between adjacent rows of pixel circuits (such as the (k + 1)-th row of pixel circuits and the (k + 2)-th row of pixel circuits). Along the second direction D2, the first transmission line 551 and the multiple auxiliary routing segments 54 may be arranged at intervals. By providing the multiple auxiliary routing segments 54 in this example, it can contribute to the electrostatic discharge in the second display area.

[0130] In some examples, the active layer of the first transistor T21 in the second pixel circuit located in the k-th row may be connected to the first initial signal line INIT1(k) through the first pixel connection electrode 401. The gate of the third transistor T23 may be connected to the active layer of the second transistor T22 through the second pixel connection electrode 402. The active layer of the fourth transistor T24 may be connected to the fourth pixel connection electrode 404. The active layer of the fifth transistor T25 may be connected to the second electrode of the storage capacitor C1 through the third pixel connection electrode 403. The active layer of the sixth transistor T26 may be connected to the fifth pixel connection electrode 405. The active layer of the seventh transistor T27 may be connected to the second initial signal line INIT2(k) through the sixth pixel connection electrode 406.

[0131] In some examples, the active layer of the first transistor T31 in the first dummy pixel circuit located in the k-th row may be connected to the first initial signal line INIT1(k) through the first dummy pixel connection electrode 411. The gate of the third transistor T33 may be connected to the active layer of the second transistor T32 through the second dummy pixel connection electrode 412. The active layer of the fourth transistor T34 may be connected to the fourth dummy pixel connection electrode 414. The active layer of the fifth transistor T35 may be connected to the second electrode of the storage capacitor C2 through the third dummy pixel connection electrode 413. The active layer of the sixth transistor T36 may be connected to the fifth dummy pixel connection electrode 415. The active layer of the seventh transistor T37 may be connected to the second initial signal line INIT2(k) through the sixth dummy pixel connection electrode 416.

[0132] In some examples, the orthographic projections of the first pixel connection electrode 401 and the first dummy pixel connection electrode 411 on the substrate may be substantially rectangular rings. The orthographic projections of the second pixel connection electrode 402 and the second dummy pixel connection electrode 412 on the substrate may be substantially in a broken line shape extending along the second direction D2. The orthographic projections of the third pixel connection electrode 403 and the third dummy pixel connection electrode 413 on the substrate may be substantially in a strip shape extending along the second direction D2. The orthographic projections of the fourth pixel connection electrode 404 and the fourth dummy pixel connection electrode 414 on the substrate may be substantially rectangular. The orthographic projections of the fifth pixel connection electrode 405 and the fifth dummy pixel connection electrode 415 on the substrate may be substantially rectangular. The orthographic projections of the sixth pixel connection electrode 406 and the sixth dummy pixel connection electrode 416 on the substrate may be substantially in a dumbbell shape extending along the second direction D2. By setting the shapes of the plurality of dummy pixel connection electrodes to be substantially the same as the shapes of the plurality of pixel connection electrodes in this example, it is beneficial to improve the uniformity of the first source-drain metal layer in the etching process.

[0133] In some examples, the first dummy pixel connection electrode 411, the second dummy pixel connection electrode 412, and the third dummy pixel connection electrode 413 may be connected in sequence. The plurality of dummy pixel connection electrodes of the plurality of first dummy pixel circuits arranged along the second direction D2 (such as including the first dummy pixel connection electrode 411, the second dummy pixel connection electrode 412, and the third dummy pixel connection electrode 413) may be connected in sequence to form a second transmission line 552. The second transmission line 552 is connected to the first transmission line 551 to form a first power transmission network 55 in the first sub-display area. In the second sub-display area, the structure of the second dummy pixel circuit is similar to the structure of the first dummy pixel circuit, and the plurality of dummy pixel connection electrodes connected to the second dummy pixel circuit may be connected to form a second transmission line to form a first power transmission network 55 in the second sub-display area.

[0134] Figure 7E It is a schematic diagram of the second source-drain metal layer in the second display area of at least one embodiment of the present invention. In some examples, as Figure 7EAs shown, the second source-drain metal layer of the second display area may include: multiple first power supply lines (such as including first power supply lines PL1(f) to PL1(f + 4)), and multiple transfer electrodes (such as including a first transfer electrode 231, a sixth transfer electrode 236, a seventh transfer electrode 237, and an eighth transfer electrode 238). The multiple first power supply lines may extend along the second direction D2, for example, may be a broken line extending along the second direction D2. For example, the first power supply line PL1(f + 3) may be connected to the third pixel connection electrode 403 to connect to the active layer of the fifth transistor and the second electrode of the storage capacitor of the second pixel circuit; the first power supply line PL1(f + 4) may be connected to the third dummy pixel connection electrode 413 to connect to the second transmission line 552 of the first power transmission network 55.

[0135] In some examples, the sixth transfer electrode 236 may be connected to the fourth pixel connection electrode 404 to connect to the active layer of the fourth transistor of the second pixel circuit. The seventh transfer electrode 237 may be connected to the fourth dummy pixel connection electrode 414 to connect to the active layer of the fourth transistor of the first dummy pixel circuit. The first transfer electrode 231 may be connected to the fifth pixel connection electrode 405 to connect to the active layer of the sixth transistor of the second pixel circuit. The eighth transfer electrode 238 may be connected to the fifth dummy pixel connection electrode 415 to connect to the active layer of the sixth transistor of the first dummy pixel circuit.

[0136] Figure 7F Schematic diagram of the third source-drain metal layer of the second display area of at least one embodiment of the present invention. In some examples, as Figure 7F shown, the third source-drain metal layer of the second display area may include: multiple second power supply lines PL2, multiple data lines (such as including data lines DL(f) to DL(f + 4)), and multiple transfer electrodes (such as including a second transfer electrode 232 and a ninth transfer electrode 239). The multiple second power supply lines PL2 and the multiple data lines may extend along the second direction D2 and be arranged at intervals along the first direction D1. The second power supply line PL2 may be configured to be connected to the cathode of the light-emitting element in the second area. For example, the data line DL(f + 3) may be connected to the sixth transfer electrode 236 to connect to the second pixel circuit, and is configured to provide a data signal to the second pixel circuit. The data line DL(f + 4) may be connected to the seventh transfer electrode 237 to connect to the first dummy pixel circuit. Since the first dummy pixel circuit is not used to drive the light-emitting element, the data line (such as data line DL(f + 4)) connected to the first dummy pixel circuit may be configured to receive the first power signal to further improve the transmission uniformity of the first power signal in the second display area.

[0137] In some examples, the second transfer electrode 232 may be connected to the first transfer electrode 231, so as to achieve electrical connection with the second pixel circuit. The ninth transfer electrode 239 may be connected to the eighth transfer electrode 238, so as to achieve electrical connection with the first dummy pixel circuit. In this example, the second transfer electrode 232 may be connected to the anode of the second region light-emitting element, to achieve electrical connection between the second pixel circuit and the second region light-emitting element; the ninth transfer electrode 239 is not connected to the second region light-emitting element and the first region light-emitting element.

[0138] Figure 8A It is a partial schematic view of the junction position between the second display area and the border area in at least one embodiment of the present invention. Figure 8A Schematically shows the junction position between the second display area A2 and the first border area B1. Figure 8A Taking the structures of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer as examples for illustration, the structures of the remaining film layers are omitted. Figure 8A Taking the partial film layers of the pixel circuits in two rows and nine columns (for example, the f-th column to the f + 8-th column) in the second display area A2 as an example for illustration. Figure 8B is Figure 8A a schematic view of the first source-drain metal layer in Figure 8C is Figure 8A a schematic view of the second source-drain metal layer in Figure 8D is Figure 8A a schematic view of the third source-drain metal layer in

[0139] In some examples, as Figures 8A to 8D shown, the first border area B1 may be provided with a first peripheral power line 61 and a second peripheral power line 62. The first peripheral power line 61 and the second peripheral power line 62 may at least extend along the first direction D1. The second peripheral power line 62 may be located on the side of the first peripheral power line 61 away from the second display area A2. The second peripheral power line 62 may be located in the first source-drain metal layer. The first peripheral power line 61 may include: a first peripheral trace 611 and a second peripheral trace 612 that are connected to each other. The second peripheral trace 612 may be located in the second source-drain metal layer, and the first peripheral trace 611 may be located in the first source-drain metal layer. For example, the orthographic projection of the second peripheral trace 612 on the substrate may cover the orthographic projection of the first peripheral trace 611 on the substrate.

[0140] In some examples, as Figure 8B shown, the second transmission line 552 of the first power transmission network 55 located in the first source-drain metal layer may extend to the first border area B1 and be connected to the first peripheral trace 611 of the first peripheral power line 61. For example, the first power transmission network 55 and the first peripheral trace 611 are of an integral structure.

[0141] In some examples, such as Figure 8C shown, the pixel circuit in the (f + 4)-th column is a first invalid pixel circuit column, and the pixel circuits in the columns from the f-th column to the (f + 3)-th column and from the (f + 5)-th column to the (f + 8)-th column are second pixel circuit columns. The first power supply line PL1(f + 4) connected to the first invalid pixel circuit column and the first power supply lines connected to the multiple second pixel circuit columns can extend to the first border area B1 and are both connected to the second peripheral trace 612 of the first peripheral power supply line 61. For example, the second peripheral trace 612 and the multiple first power supply lines can be an integral structure.

[0142] In some examples, such as Figure 8A and Figure 8D shown, the second power supply line PL2 connected to the multiple second pixel circuit columns can extend to the first border area B1 and is electrically connected to the second peripheral power supply line 62 located in the second source-drain metal layer. The second power supply line PL2(f + 4) and the data line DL(f + 4) connected to the first invalid pixel circuit column (for example, the pixel circuit in the (f + 4)-th column) are an interconnected integral structure and extend to the first border area B1 and are connected to the first power supply line PL1(f + 4) located in the second source-drain metal layer, so as to achieve electrical connection with the first peripheral power supply line 61.

[0143] In this example, the first transmission line is formed in the first sub-display area by using the invalid pixel connection electrode connected to the first invalid pixel circuit column, ensuring the formation of the first power supply transmission network in the first sub-display area; moreover, the data line connected to the first invalid pixel circuit column is connected to the first peripheral power supply line and the first power supply line, which can further improve the transmission uniformity of the first power supply signal. The structure of the second invalid pixel circuit in the second sub-display area is similar to that of the first invalid pixel circuit in the first sub-display area, so it will not be elaborated here.

[0144] Figure 9 It is another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present invention. In some examples, such as Figure 9As shown, in the first sub-display area A21, along the first direction D1 away from the first display area A1, the multiple first pixel circuit columns 410 and the multiple first dummy pixel circuit columns 430a inserted in the multiple second pixel circuit columns 420 are numbered. Among them, the numbers of the multiple first dummy pixel circuit columns 430a may conform to an arithmetic progression relationship. For example, among the multiple first pixel circuit columns 410 and the multiple first dummy pixel circuit columns 430a in the first sub-display area A21, the numbers of the multiple first pixel circuit columns 410 satisfy the following relationship: 1+(i - 1)×3, where i is an integer greater than 0. For example, the 1st column, the 4th column, and the 7th column inserted in the second pixel circuit column 420 are all first pixel circuit columns 410, and the 2nd column, the 3rd column, the 5th column, and the 6th column inserted in the second pixel circuit column 420 are all first dummy pixel circuit columns 430a. For the remaining descriptions of the display substrate of this example, reference may be made to the descriptions of the foregoing embodiments, so they will not be elaborated herein.

[0145] Figure 10 Another layout diagram of the pixel circuit in the second display area according to at least one embodiment of the present invention. In some examples, as Figure 10 As shown, in the first sub-display area A21, along the first direction D1 away from the first display area A1, the multiple first pixel circuit columns 410 and the multiple first dummy pixel circuit columns 430a inserted in the multiple second pixel circuit columns 420 are numbered. Among them, the numbers of the multiple first dummy pixel circuit columns 430a may conform to an arithmetic progression relationship. For example, the numbers of the multiple first dummy pixel circuit columns 430a are odd numbers, and the numbers of the multiple first pixel circuit columns 410 are even numbers. For example, the 1st column, the 3rd column, and the 5th column inserted in the second pixel circuit column 420 are all first dummy pixel circuit columns 430a, and the 2nd column, the 4th column, and the 6th column inserted in the second pixel circuit column 420 are all first pixel circuit columns 410. For the remaining descriptions of the display substrate of this example, reference may be made to the descriptions of the foregoing embodiments, so they will not be elaborated herein.

[0146] Figure 11 Another layout diagram of the pixel circuit in the second display area according to at least one embodiment of the present invention. In some examples, as Figure 11As shown, within the first sub-display area A21, along the first direction D1 away from the first display area A1, numbers are assigned to a plurality of first pixel circuit columns 410 and a plurality of first dummy pixel circuit columns 430a inserted in a plurality of second pixel circuit columns 420. Among them, the numbers of the plurality of first dummy pixel circuit columns 430a may conform to an arithmetic progression relationship. For example, the numbers of the plurality of first dummy pixel circuit columns 430a are even numbers, and the numbers of the plurality of first pixel circuit columns 410 are odd numbers. For instance, the 1st column, 3rd column, and 5th column inserted in the second pixel circuit column 420 are all first pixel circuit columns 410, and the 2nd column, 4th column, and 6th column inserted in the second pixel circuit column 420 are all first dummy pixel circuit columns 430a. For the remaining descriptions of the display substrate in this example, reference may be made to the descriptions of the foregoing embodiments, and thus they will not be elaborated herein.

[0147] Figure 12 Another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present invention. In some examples, as Figure 12 shown, within the first sub-display area A21, a plurality of first dummy pixel circuit columns 430a are located on the side of a plurality of first pixel circuit columns 410 closer to the first display area A1. For example, a dozen first dummy pixel circuit columns 430a may be provided on the side of a plurality of first pixel circuit columns 410 closer to the first display area A1. By centrally arranging the plurality of first pixel circuit columns 410, the ratio between the maximum length and the minimum length of the conductive connection lines can be reduced. For the remaining descriptions of the display substrate in this example, reference may be made to the descriptions of the foregoing embodiments, and thus they will not be elaborated herein.

[0148] Figure 13 Another layout schematic diagram of the pixel circuit in the second display area of at least one embodiment of the present invention. In some examples, as Figure 13 shown, within the first sub-display area A21, two first dummy pixel circuit columns 430a and four first pixel circuit columns 410 may be arranged at intervals. Two first dummy pixel circuit columns 430a are provided every four first pixel circuit columns 410, and four second pixel circuit columns 420 are provided between adjacent first pixel circuit columns 410, four second pixel circuit columns 420 are provided between adjacent first dummy pixel circuit columns 430a, and four second pixel circuit columns 420 are provided between an adjacent first pixel circuit column 410 and a first dummy pixel circuit column 430a. For the remaining descriptions of the display substrate in this example, reference may be made to the descriptions of the foregoing embodiments, and thus they will not be elaborated herein.

[0149] In some other examples, the arrangement manners of the first dummy pixel circuit columns and the first pixel circuit columns in the first sub-display area in the above embodiments can be combined with each other. For example, in the first sub-display area close to the first display area, multiple first dummy pixel circuit columns can be arranged, and in the remaining area of the first sub-display area, multiple first dummy pixel circuit columns and multiple first pixel circuit columns can be arranged alternately, for example, arranged at intervals according to an arithmetic data column relationship.

[0150] Figure 14 Another schematic plan view of the arrangement of the light-emitting elements of the display substrate according to at least one embodiment of the present invention. In some examples, as Figure 14 shown, two adjacent first light-emitting elements 31a and 31d arranged along the first direction D1 in the first display area A1 can be connected to each other. For example, the anodes of two adjacent first light-emitting elements 31a and 31d arranged along the first direction D1 can be connected to each other. Two adjacent fourth light-emitting elements 32a and 32d arranged along the first direction D1 in the second display area A2 can be connected to each other. For example, the anodes of two adjacent fourth light-emitting elements 32a and 32d arranged along the first direction D1 can be connected to each other.

[0151] In this example, the first pixel circuit in the second display area A2 and the first light-emitting element in the first display area A1 can have a one-to-two driving relationship, and the second pixel circuit in the second display area A2 and the fourth light-emitting element can have a one-to-two driving relationship. In other words, one first pixel circuit in the second display area A2 can be configured to drive two first light-emitting elements in the first display area A1 (for example, one first light-emitting element 31a and one first light-emitting element 31d), and one second pixel circuit in the second display area A2 can be configured to drive two fourth light-emitting elements in the second display area A2 (for example, one fourth light-emitting element 32a and one fourth light-emitting element 32d). For the remaining description of the display substrate in this example, reference can be made to the description of the foregoing embodiments, so it will not be repeated here.

[0152] Figure 15 Another schematic arrangement diagram of the pixel circuit in the second display area according to at least one embodiment of the present invention. In some examples, based on Figure 14 the driving relationship between the pixel circuit and the light-emitting element shown, as Figure 15 shown, in the first sub-display area A21 of the second display area, in the first direction D1, two first-type pixel circuit columns can be arranged every three second pixel circuit columns; in the second sub-display area A22, in the first direction D1, two second dummy pixel circuit columns 430b can be arranged every three second pixel circuit columns.

[0153] In some examples, as Figure 15As shown, the two first-type pixel circuit columns provided with an interval of three second pixel circuit columns 420 in the first sub-display area A21 include the following two combinations. The first combination is two first pixel circuit columns 410 arranged along the first direction D1; the second combination is one first dummy pixel circuit column 430a and one first pixel circuit column 410 arranged along the direction away from the first display area A1 in the first direction D1. The first combination and the second combination are alternately arranged along the first direction D1. In some other examples, the arrangement manners of the first combination and the second combination may satisfy the aforementioned arithmetic progression relationship. In some other examples, the two first-type pixel circuit columns provided with an interval of three second pixel circuit columns 420 in the first sub-display area A21 include the following three combinations; the first combination is two first pixel circuit columns 410 arranged along the first direction D1; the second combination is one first dummy pixel circuit column 430a and one first pixel circuit column 410 arranged along the direction away from the first display area A1 in the first direction D1; the third combination is two first dummy pixel circuit columns 430a arranged along the first direction D1; the first combination, the second combination and the third combination may be alternately arranged along the first direction D1. This embodiment does not limit this. Other descriptions of the display substrate of this example may refer to the descriptions of the foregoing embodiments, so they will not be elaborated here.

[0154] Figure 16 It is another schematic plan view of the arrangement of the light-emitting elements of the display substrate according to at least one embodiment of the present invention. In some examples, as Figure 16 shown, two adjacent first light-emitting elements 31a and 31d arranged along the second direction D2 in the first display area A1 may be connected to each other; two adjacent second light-emitting elements 31b arranged diagonally in the first display area A1 may be connected to each other, and two adjacent third light-emitting elements 31c arranged diagonally in the first display area A1 may be connected to each other.

[0155] In this example, the first pixel circuit in the second display area A2 and the first light-emitting element in the first display area A1 may have a one-to-two driving relationship, the first pixel circuit in the second display area A2 and the second light-emitting element in the first display area A1 may have a one-to-two driving relationship, and the first pixel circuit in the second display area A2 and the third light-emitting element in the first display area A1 may have a one-to-two driving relationship. Based on the driving relationship between the pixel circuit and the light-emitting element of this example, compared with the previous embodiments, the number of the first pixel circuit columns in the second display area can be reduced, which is beneficial to reducing the length of the conductive connection lines and improving the display defect situation in the first display area caused by the length of the conductive connection lines. The arrangement manners of the first pixel circuit columns and the first dummy pixel circuit columns of this example may refer to the descriptions of the foregoing embodiments, so they will not be elaborated here.

[0156] Figure 17Schematic diagram of a display device according to at least one embodiment of the present utility model. As Figure 17 shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 can be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 and the first display area A1 can at least partially overlap. For example, the orthographic projection of the sensor 92 on the display substrate 91 can be located within the range of the first display area A1. In some examples, the sensor 92 can be a camera or an infrared sensor.

[0157] In some examples, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a product with an image (including static images or dynamic images, where the dynamic image can be a video) display function. For example, the display device can be: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable video camera, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device in departments such as e-government, banking, hospitals, and power), a monitor, etc. Another example is that the display device can also be a microdisplay, any product such as a VR device or an AR device containing a microdisplay.

[0158] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", or "some examples" means that the features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0159] Although the disclosed embodiments of the present utility model are as above, the content described is only an embodiment for facilitating the understanding of the present utility model and is not used to limit the present utility model. Any person skilled in the art within the scope of the present utility model can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present utility model. However, the patent protection scope of the present utility model shall still be defined by the appended claims.

Claims

1. A display substrate, characterized in that: include: A first display area and a second display area located at at least one side of the first display area; the second display area includes: a first sub-display area located at at least one side of the first display area, and a second sub-display area located at at least one side of the first sub-display area; The display substrate comprises: substrate; A plurality of first-region light-emitting elements are disposed on the substrate and located in the first display area; A plurality of second-region light-emitting elements, a plurality of first-type pixel circuits, and a plurality of second pixel circuits are arranged on the substrate and located in the second display area; the plurality of second pixel circuits and the plurality of first-type pixel circuits are arranged at intervals along a first direction; the plurality of first-type pixel circuits include: a plurality of first pixel circuits located in the first sub-display area and a plurality of invalid pixel circuits located in the second display area; the plurality of invalid pixel circuits include: a plurality of first invalid pixel circuits located in the first sub-display area and a plurality of second invalid pixel circuits located in the second sub-display area; at least one first pixel circuit among the plurality of first pixel circuits is connected to at least one first-region light-emitting element among the plurality of first-region light-emitting elements through at least one conductive connecting line, and at least one second pixel circuit among the plurality of second pixel circuits is connected to at least one second-region light-emitting element among the plurality of second-region light-emitting elements; a first power transmission network, disposed on the substrate and located in the second display area, the first power transmission network comprising a plurality of first transmission lines extending along a first direction and a plurality of second transmission lines extending along a second direction; the first direction intersects the second direction; In the first sub-display area, at least one of the plurality of second transmission lines is connected to a plurality of first invalid pixel circuits arranged along the second direction and overlaps with the orthographic projection of the substrate; in the second sub-display area, at least one of the plurality of second transmission lines is connected to a plurality of second invalid pixel circuits arranged along the second direction and overlaps with the orthographic projection of the substrate.

2. The display substrate according to claim 1, characterized in that: At least one of the multiple invalid pixel circuits is connected to a plurality of invalid pixel connection electrodes located on the same conductive layer, and at least some of the multiple invalid pixel connection electrodes connected to the multiple invalid pixel circuits arranged sequentially along the second direction are connected to form a second transmission line.

3. The display substrate according to claim 1, characterized in that: A plurality of first invalid pixel circuit groups and a plurality of first pixel circuit groups are arranged in the first sub-display area, each of the first invalid pixel circuit groups includes a plurality of first invalid pixel circuits sequentially arranged along the second direction, and each of the first pixel circuit groups includes a plurality of first pixel circuits sequentially arranged along the second direction; At least one first invalid pixel circuit group among the plurality of first invalid pixel circuit groups is located at a side of at least one first pixel circuit group among the plurality of first pixel circuit groups close to the first display area.

4. The display substrate according to claim 3, characterized in that: In the first direction and in a direction away from the first display area, sequentially numbering the plurality of first pixel circuit groups and the plurality of first invalid pixel circuit groups in the first sub-display area; The numbers of at least some of the first invalid pixel circuit groups among the plurality of first invalid pixel circuit groups conform to an arithmetic progression relationship; Alternatively, the numbers of at least some of the plurality of first pixel circuit groups conform to an arithmetic progression.

5. The display substrate according to claim 4, characterized in that: Each first pixel circuit group is numbered as an even number, and each first invalid pixel circuit group is numbered as an odd number; or, each first invalid pixel circuit group is numbered as an even number, and each first pixel circuit group is numbered as an odd number; or, the numbers of the multiple first invalid pixel circuit groups conform to the following relationship: 1+(i-1)×3, where i is an integer greater than 0.

6. The display substrate according to claim 1, characterized in that: The display substrate further comprises: A plurality of data lines are arranged on the substrate and located in the second display area; at least one data line among the plurality of data lines is connected to a plurality of invalid pixel circuits arranged along the second direction; A first peripheral power line is arranged on the substrate and located in a frame area, the frame area is located on at least one side of the second display area, the first peripheral power line extends at least along the first direction and is connected to the first power transmission network; the data lines connected to the multiple invalid pixel circuits arranged along the second direction are connected to the first power transmission network.

7. The display substrate according to claim 6, characterized in that: The display substrate further comprises: A plurality of first power lines are arranged on the substrate and located in the second display area, and at least one first power line among the plurality of first power lines is connected to a plurality of invalid pixel circuits arranged along the second direction; The data lines connected to the multiple invalid pixel circuits arranged along the second direction are connected to the first peripheral power lines through the first power lines connected to the multiple invalid pixel circuits.

8. The display substrate according to claim 7, characterized in that: The first peripheral power line includes: a first peripheral routing and a second peripheral routing that are connected to each other; the second peripheral routing is located on a side of the first peripheral routing away from the substrate; the first peripheral routing and the first power transmission network are an integrated structure; the second peripheral routing and the multiple first power lines are an integrated structure.

9. The display substrate according to claim 7, characterized in that: The plurality of data lines are located on a side of the plurality of first power lines away from the substrate, and the plurality of first power lines are located on a side of the first power transmission network away from the substrate.

10. The display substrate according to claim 9, characterized in that: In a direction perpendicular to the display substrate, the second display area includes: a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate; the second source-drain metal layer is located on a side of the first source-drain metal layer away from the substrate, and the third source-drain metal layer is located on a side of the second source-drain metal layer away from the substrate; The first power transmission network is located in the first source-drain metal layer; The plurality of first power lines are located in the second source-drain metal layer; The plurality of data lines are located in the third source-drain metal layer.

11. The display substrate according to any one of claims 1 to 10, characterized in that: In the first direction, n first-type pixel circuits are arranged every a second pixel circuits, wherein a and n are both integers greater than 0, and a is greater than n.

12. The display substrate according to claim 11, characterized in that: a is 4 and n is 1.

13. The display substrate according to claim 1, characterized in that: The plurality of first region light emitting elements include: a plurality of first light emitting elements emitting first color light, a plurality of second light emitting elements emitting second color light, and a plurality of third light emitting elements emitting third color light; At least one of the multiple first pixel circuits is connected to two adjacent first light-emitting elements that emit first color light; at least one of the multiple first pixel circuits is connected to a second light-emitting element that emits second color light; and at least one of the multiple first pixel circuits is connected to a third light-emitting element that emits third color light.

14. The display substrate according to claim 13, characterized in that: The plurality of second region light emitting elements include: a plurality of fourth light emitting elements emitting first color light, a plurality of fifth light emitting elements emitting second color light, and a plurality of sixth light emitting elements emitting third color light; At least one of the multiple second pixel circuits is connected to two adjacent fourth light-emitting elements that emit the first color light; at least one of the multiple second pixel circuits is connected to a fifth light-emitting element that emits the second color light; and at least one of the multiple second pixel circuits is connected to a sixth light-emitting element that emits the third color light.

15. The display substrate according to claim 13 or 14, characterized in that: The first color light is green light, the second color light is red light, and the third color light is blue light.

16. A display device, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 15.

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