Display panel and display device

Abstract

The utility model discloses a display panel and a display device, relates to the technical field of display, and aims to improve the burn type dark spot defect of the display panel and improve the yield. Every two adjacent sub-pixels of the display panel form a pixel group; the pixel driving circuit comprises a specified transistor, the signal line comprises a specified signal line, and the specified transistor is coupled with the specified signal line; the display panel comprises a first active layer, a specified gate metal layer and a first source-drain metal layer; the first active layer includes an active layer first pole pattern specifying a transistor; the specified gate metal layer comprises a specified signal line pattern; the first source-drain metal layer comprises a specified signal line bridging pattern, and an active layer first pole pattern of a specified transistor of one sub-pixel in the pixel group is connected with an active layer first pole pattern of a specified transistor of another sub-pixel; the specified signal line bridging pattern is located in an area where one sub-pixel is located, and the specified signal line bridging pattern is connected with a first pole pattern of an active layer of a specified transistor of one sub-pixel and is also connected with a specified signal line pattern.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the rapid development of modern electronic information technologies, the display industry has also been continuously progressing, and display products are being applied in a wider range of fields.

[0003] For example, OLED (Organic Light-Emitting Diode) display products have gradually occupied an important position in the market due to their advantages such as being thin, light, high in brightness, low in power consumption, good in flexibility, and fast in response. OLED display products enable more users to enjoy a wonderful visual sensory experience. At the same time, users also put forward higher requirements for OLED display products; however, the screen dark spots of OLED display products greatly affect the user experience effect. Summary of the Utility Model

[0004] Some embodiments of this application solve the technical problem of how to reduce the probability of the occurrence of burn-type dark spots in a display panel, improve the burn-type dark spot defect of the display panel, and increase the manufacturing yield.

[0005] On the one hand, a display panel is provided. The display panel includes a plurality of sub-pixels, and the plurality of sub-pixels are arranged in multiple rows along a first direction. Two adjacent sub-pixels in a row of sub-pixels form a pixel group; one of the plurality of sub-pixels includes a pixel driving circuit, the pixel driving circuit is coupled to at least one signal line, the pixel driving circuit includes a specified transistor, at least one signal line includes a specified signal line, and the specified transistor is coupled to the specified signal line; the display panel includes a substrate, a first active layer disposed on one side of the substrate, a specified gate metal layer disposed on the side of the first active layer away from the substrate, and a first source-drain metal layer disposed on the side of the specified gate metal layer away from the substrate; the first active layer includes an active layer pattern of the specified transistor, and the active layer pattern of the specified transistor includes an active layer first pole pattern. In a pixel group, the active layer first pole pattern of the specified transistor of one sub-pixel is connected to the active layer first pole pattern of the specified transistor of another sub-pixel; the specified gate metal layer includes a specified signal line pattern of the specified signal line; the first source-drain metal layer includes a specified signal line bridging pattern. In a pixel group, the specified signal line bridging pattern is located within the area of one sub-pixel, the specified signal line bridging pattern is connected to the active layer first pole pattern of the specified transistor of one of the sub-pixels, and is also connected to the specified signal line pattern.

[0006] The beneficial effects of some embodiments of the present application are as follows: A specified signal line bridging pattern is provided in a sub-pixel of a pixel group, and the specified signal line bridging pattern connects the first pole pattern of the active layer of a specified transistor in one sub-pixel and the specified signal line pattern; Since the first pole patterns of the active layers of the specified transistors in two sub-pixels of a pixel group are connected, it is thus possible to achieve that the first pole patterns of the active layers of the specified transistors in two sub-pixels of a pixel group can both be connected to the specified signal line pattern through the specified signal line bridging pattern, without affecting the operation of the pixel driving circuit; This setting reduces the specified signal line bridging pattern in one sub-pixel of the pixel group, that is, reduces the number of specified signal line bridging patterns, thereby reducing the overlap between the specified signal line bridging pattern and other signal line patterns, and reducing the probability of short circuit due to the overlap between the specified signal line bridging pattern and other signal line patterns from the source, thus reducing the probability of occurrence of burned dark dots, greatly improving the burned dark dot defect of the display panel, improving the manufacturing yield, and significantly improving the Y-line defect caused by burning, and significantly reducing the market-end risk caused by burning of the pixel driving circuit.

[0007] In some embodiments, in a pixel group, the first pole pattern of the active layer of a specified transistor in one sub-pixel is connected to the first pole pattern of the active layer of a specified transistor in another sub-pixel at a specified connection point, and the specified signal line bridging pattern is connected to the specified connection point.

[0008] In some embodiments, in a pixel group, the active layer patterns of the specified transistors in two sub-pixels are mirror-symmetrical, and the specified connection point is located on the mirror symmetry axis of the active layer patterns of the specified transistors in the two sub-pixels; The specified signal line pattern extends in a first direction and passes through the regions where the two sub-pixels are located.

[0009] In some embodiments, the width of the specified signal line bridging pattern is greater than a set width.

[0010] In some embodiments, the pixel driving circuit further includes other transistors in addition to the specified transistor; The first active layer further includes the active layer patterns of the other transistors; The active layer patterns of the other transistors include active layer channel patterns; The active layer pattern of the specified transistor includes an active layer channel pattern, and the aspect ratio of the active layer channel pattern of the specified transistor is greater than the aspect ratio of the active layer channel pattern of the other transistors.

[0011] In some embodiments, the designated transistor includes a third reset transistor, the designated signal line includes a third initialization signal line, and the third reset transistor is coupled to the third initialization signal line; the first active layer includes an active layer pattern of the third reset transistor, and the active layer pattern of the third reset transistor includes an active layer first pole pattern; the designated gate metal layer includes a third initialization signal line pattern of the third initialization signal line; the designated signal line bridging pattern includes a third initialization signal line bridging pattern, and the first source-drain metal layer includes the third initialization signal line bridging pattern.

[0012] In some embodiments, the signal line further includes a first initialization signal line; the designated gate metal layer further includes a first initialization signal line pattern of the first initialization signal line; the first initialization signal line pattern extends along a first direction and passes through regions where two sub-pixels in a pixel group are located; the third initialization signal line bridging pattern overlaps with the first initialization signal line pattern.

[0013] In some embodiments, the pixel driving circuit further includes a compensation transistor, the signal line further includes a first power supply signal line; the display panel further includes a second active layer disposed between the first active layer and the designated gate metal layer, and a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate; the second active layer includes an active layer pattern of the compensation transistor; the second source-drain metal layer includes a first power supply signal line pattern of the first power supply signal line, the first power supply signal line pattern includes a block pattern, and a positive projection of the active layer pattern of the compensation transistor on the substrate is located within a positive projection of the block pattern of the first power supply signal line pattern on the substrate.

[0014] In some embodiments, the first power supply signal line pattern further includes a strip pattern connected to the block pattern, and the width of the strip pattern is 3.5um - 5um.

[0015] In some embodiments, the pixel driving circuit further includes a driving transistor, the first active layer includes an active layer pattern of the driving transistor; the display panel further includes a bottom metal layer disposed on a side of the first active layer close to the substrate; the bottom metal layer includes a bottom metal protection pattern, and a positive projection of the active layer pattern of the driving transistor on the substrate is located within a positive projection of the bottom metal protection pattern on the substrate; the bottom metal protection pattern is connected to the first power supply signal line pattern of the second source-drain metal layer.

[0016] In some embodiments, the display panel further includes an anode layer disposed on a side of the second source-drain metal layer away from the substrate; the anode layer includes a first anode and a second anode, the first anode is connected to a pixel driving circuit of one sub-pixel in the pixel group, and the second anode is connected to a pixel driving circuit of another sub-pixel in the pixel group; the first anode is disposed above the block pattern of the first power supply signal line pattern, and a ratio of an overlapping area between the first anode and the block pattern to an area of the first anode is greater than a set threshold.

[0017] In some embodiments, the substrate includes at least two layers of flexible substrates and at least two layers of buffer layers.

[0018] On the other hand, a display device is provided, including a display panel as described in any of the above embodiments.

[0019] The above display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be elaborated herein. Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present application.

[0021] Figure 1 A plan view of a display panel for some embodiments;

[0022] Figure 2 A cross-sectional view of a display panel for some embodiments;

[0023] Figure 3 A pixel driving circuit diagram for some embodiments;

[0024] Figure 4 A plan view of the film stack of a display panel for some embodiments;

[0025] Figure 5 A plan view of the film stack of another display panel for some embodiments;

[0026] Figure 6 A plan view of the film stack of yet another display panel for some embodiments;

[0027] Figure 7 A plan view of the film stack of yet another display panel for some embodiments;

[0028] Figure 8 A plan view of the film stack of yet another display panel for some embodiments;

[0029] Figure 9 A plan view of the film stack of yet another display panel for some embodiments;

[0030] Figure 10 A plan view of the film stack of yet another display panel for some embodiments;

[0031] Figure 11 Membrane layer stack floor plan of another display panel for some embodiments;

[0032] Figure 12 Membrane layer stack floor plan of another display panel for some embodiments;

[0033] Figure 13 Membrane layer stack floor plan of another display panel for some embodiments;

[0034] Figure 14 Membrane layer stack floor plan of another display panel for some embodiments;

[0035] Figure 15 Membrane layer stack floor plan of another display panel for some embodiments;

[0036] Figure 16 Membrane layer stack floor plan of another display panel for some embodiments;

[0037] Figure 17 For Figure 16 Membrane layer stack cross-sectional view;

[0038] Figure 18 Membrane layer stack floor plan of another display panel for some embodiments;

[0039] Figure 19 For Figure 18 Membrane layer stack cross-sectional view;

[0040] Figure 20 Membrane layer stack floor plan of another display panel for some embodiments;

[0041] Figure 21 For Figure 20 Membrane layer stack cross-sectional view;

[0042] Figure 22 Membrane layer stack floor plan of another display panel for some embodiments;

[0043] Figure 23 For Figure 22 Membrane layer stack cross-sectional view;

[0044] Figure 24 Membrane layer stack floor plan of another display panel for some embodiments;

[0045] Figure 25 For Figure 24 Membrane layer stack cross-sectional view;

[0046] Figure 26 Membrane layer stack floor plan of another display panel for some embodiments;

[0047] Figure 27 is Figure 26 a cross-sectional view of a film stack;

[0048] Figure 28 is a plan view of a film stack of another display panel of some embodiments;

[0049] Figure 29 is Figure 28 a cross-sectional view of a film stack;

[0050] Figure 30 is a plan view of a film stack of another display panel of some embodiments;

[0051] Figure 31 is Figure 30 a cross-sectional view of a film stack;

[0052] Figure 32 is Figure 30 a cross-sectional view along the A-A section line;

[0053] Figure 33 is Figure 30 a cross-sectional view along the B-B section line;

[0054] Figure 34 is a plan view of a film stack of another display panel of some embodiments;

[0055] Figure 35 is Figure 34 a cross-sectional view of a film stack;

[0056] Figure 36 is a plan view of a film stack of another display panel of some embodiments;

[0057] Figure 37 is Figure 36 a cross-sectional view of a film stack;

[0058] Figure 38 is a plan view of a film stack of another display panel of some embodiments;

[0059] Figure 39 is Figure 38 a cross-sectional view of a film stack;

[0060] Figure 40 is a plan view of a film stack of another display panel of some embodiments;

[0061] Figure 41 is Figure 40 a cross-sectional view of a film stack;

[0062] Figure 42 is a plan view of a film stack of another display panel of some embodiments;

[0063] Figure 43 is Figure 42 a cross-sectional view of a film stack;

[0064] Figure 44 is a plan view of a film stack of another display panel of some embodiments;

[0065] Figure 45 is a plan view of a film stack of another display panel of some embodiments;

[0066] Figure 46 is a cross-sectional view of a stack of substrates of some embodiments;

[0067] Figure 47 is a plan view of a display device of some embodiments. Detailed implementation manners

[0068] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0069] Unless otherwise required by the context, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any suitable manner.

[0070] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0071] In the description of some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, in the description of some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other. Again, in the description of some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0072] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0073] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0074] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0075] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0076] With the development of display technology, there are various types of display panels. For example, the display panel can be an Organic Light-Emitting Diode (OLED) display panel, a Micro Organic Light-Emitting Diode (Micro OLED) display panel, a Quantum Dot Light Emitting Diodes (QLED) display panel, a Mini Light-Emitting Diode (Mini LED) display panel, or a Micro Light-Emitting Diode (Micro LED) display panel, etc. Some embodiments of this application will be described by taking the OLED display panel as an example.

[0077] OLED belongs to a current-type organic light-emitting device, and it is a phenomenon of luminescence caused by the injection and recombination of carriers. The luminescence intensity is proportional to the injected current. Under the action of an electric field in the OLED, the holes generated by the anode and the electrons generated by the cathode will move, and are respectively injected into the hole transport layer and the electron transport layer, and migrate to the light-emitting layer. When the two meet in the light-emitting layer, energy excitons are generated, which can excite the luminescent molecules to finally generate visible light. The luminescent molecules generate the three primary colors of red, green, and blue (RGB three primary colors) according to their different formulations, constituting the basic colors. The OLED display panel 1000 made of OLED has the advantages of high brightness, high efficiency, wide viewing angle, self-luminescence, all-solid state, ultra-thin and ultra-light, simple manufacturing process, fast response speed, full-color display, and good mechanical processing performance, etc., and has been more and more widely used in display products such as mobile phones, tablets, computers, and TVs. With the application of the OLED display panel 1000 in display products such as mobile phones, computers, and tablets, the requirements for the display effect of the OLED display panel 1000 are getting higher and higher.

[0078] In order to achieve a better display effect, the pixel driving circuit 10 for driving the OLED to emit light in the OLED display panel 1000 has been continuously optimized. However, the increasingly complex and dense pixel driving circuit 10 also brings many problems, such as pixel defects such as non-extinguishing points (bright points) and / or non-light-emitting points (dark points) in the OLED display panel 1000.

[0079] For example, in a full-color, red, green, and blue lighting display screen, it can be seen that the sub-pixels in a certain area do not emit light, presenting non-light-emitting points (dark points) in each lighting display screen.

[0080] The following introduces the specific settings of the display panel 1000.

[0081] In some embodiments, as Figure 1 shown, the display panel 1000 includes a plurality of sub-pixels P, and a sub-pixel P includes a pixel driving circuit 10 and an element 20 to be driven coupled to the pixel driving circuit 10. In some examples, as Figure 3 shown, the pixel driving circuit 10 includes a first transistor T1 (first reset transistor), a second transistor T2 (compensation transistor), a third transistor T3 (driving transistor), a fourth transistor T4 (writing transistor), a fifth transistor T5 (first light-emitting control transistor), a sixth transistor T6 (second light-emitting control transistor), a seventh transistor T7 (second reset transistor), and a coupling capacitor Cst. In some examples, the pixel driving circuit 10 further includes an eighth transistor T8 (third reset transistor).

[0082] The first transistor T1 is a P-type transistor. A first pole T11 of the first transistor T1 is coupled to a first initialization signal line Vinit1. A gate T13 of the first transistor T1 is coupled to a first reset signal line Reset1. A second pole T12 of the first transistor T1 is coupled to a third node N3.

[0083] The second transistor T2 is an N-type transistor. A first pole T21 of the second transistor T2 is coupled to a first node N1. A first gate T23 of the second transistor T2 is coupled to a first gate signal line Gate1. A second gate T24 of the second transistor T2 is coupled to a second gate signal line Gate2. A second pole T22 of the second transistor T2 is coupled to the third node N3.

[0084] The third transistor T3 is a P-type transistor. A first pole T31 of the third transistor T3 is coupled to a second node N2. A gate T33 of the third transistor T3 is coupled to the first node N1. A second pole T32 of the third transistor T3 is coupled to the third node N3.

[0085] The fourth transistor T4 is a P-type transistor. A first pole T41 of the fourth transistor T4 is coupled to a data signal line Data. A gate T43 of the fourth transistor T4 is coupled to a third gate signal line Gate3. A second pole T42 of the fourth transistor T4 is coupled to the second node N2.

[0086] The fifth transistor T5 is a P-type transistor. A first pole T51 of the fifth transistor T5 is coupled to a first power supply signal line VDD. A gate T53 of the fifth transistor T5 is coupled to a light-emitting control signal line EM. A second pole T52 of the fifth transistor T5 is coupled to the second node N2.

[0087] The sixth transistor T6 is a P-type transistor. The first pole T61 of the sixth transistor T6 is coupled to the third node N3. The gate T63 of the sixth transistor T6 is coupled to the emission control signal line EM. The second pole T62 of the sixth transistor T6 is coupled to the fourth node N4.

[0088] The seventh transistor T7 is a P-type transistor. The first pole T71 of the seventh transistor T7 is coupled to the second initialization signal line Vinit2. The gate T73 of the seventh transistor T7 is coupled to the second reset signal line Reset2. The second pole T72 of the seventh transistor T7 is coupled to the fourth node N4.

[0089] The eighth transistor T8 is a P-type transistor. The first pole T81 of the eighth transistor T8 is coupled to the third initialization signal line Vinit3. The gate T83 of the eighth transistor T8 is coupled to the second reset signal line Reset2. The second pole T82 of the eighth transistor T8 is coupled to the second node N2.

[0090] The first electrode plate Cst1 of the coupling capacitor Cst is coupled to the first power supply signal line VDD. The second electrode plate Cst2 of the coupling capacitor Cst is coupled to the first node N1.

[0091] The first end 21 of the element 20 to be driven is coupled to the fourth node N4 to realize the coupling of the element 20 to be driven and the pixel driving circuit 10. The second end 22 of the element 20 to be driven is coupled to the second power supply signal line VSS.

[0092] The following introduces the specific film layer settings of the pixel driving circuit 10 as shown in Figure 3 the following in some embodiments in the display panel 1000.

[0093] In some embodiments, as Figure 1 shown, the display panel 1000 includes a display area AA and a peripheral area BB located on at least one side of the display area AA. The display area AA is provided with a plurality of sub-pixels P. One sub-pixel P includes a pixel driving circuit 10 and an element 20 to be driven coupled to the pixel driving circuit 10.

[0094] Exemplarily, as Figure 1As shown, the display panel 1000 includes a plurality of sub-pixels P. The sub-pixel P is the smallest unit for the display panel 1000 to display an image. Each sub-pixel P can display a single color, such as red (R), green (G), or blue (B). The plurality of sub-pixels P can be arranged in an array. For example, the plurality of sub-pixels P are arranged in multiple rows along the first direction X and in multiple columns along the second direction Y. Each sub-pixel P includes a device to be driven 20 and a pixel driving circuit 10 for driving the device to be driven 20 to emit light. The pixel driving circuit 10 can be formed by electrically connecting a plurality of transistors and at least one capacitor. In each sub-pixel P, the device to be driven 20 is electrically connected to the corresponding pixel driving circuit 10 below. Specifically, the anode of the device to be driven 20 is electrically connected to the corresponding pixel driving circuit 10. In this way, the first power signal input into the display panel 1000 is transmitted to the anode of the device to be driven 20 through the pixel driving circuit 10. At the same time, the second power signal is transmitted to the cathode of the device to be driven 20, so that an electric field is formed between the anode and the cathode of the device to be driven 20, causing the device to be driven 20 to emit light.

[0095] In some embodiments, as Figure 2 shown, the display panel 1000 may include, for example, a substrate 100, a driving circuit layer 200, a driving element layer 300, and a packaging layer 400 that are sequentially stacked. The substrate 100 provides a bearing basis for other film layer structures of the display panel 1000, that is, other film layer structures in the display panel 1000, such as the driving circuit layer 200, the driving element layer 300, and the packaging layer 400, are fabricated on the substrate 100. The substrate 100 can be a rigid substrate, and the material of the rigid substrate can be, for example, rigid materials such as glass materials, quartz materials, and sapphire materials. The substrate 100 can also be a flexible substrate, and the material of the flexible substrate can be, for example, flexible materials such as polyimide (PI) or saturated polyester (PET). The driving circuit layer 200 is used to arrange the pixel driving circuit 10. The driving element layer 300 is used to arrange the device to be driven 20, and the device to be driven 20 is, for example, a light-emitting device. The packaging layer 400 is used to protect the display panel 1000 and prevent moisture in the air from entering the interior of the display panel 1000 and damaging the display panel 1000.

[0096] In some embodiments, the driving circuit layer 200 of the display panel 1000 includes a first active layer 201, a first gate insulating layer 202, a first gate metal layer 203, a second gate insulating layer 204, a second gate metal layer 205, a first interlayer dielectric layer 206, a second active layer 207, a third gate insulating layer 208, a third gate metal layer 209, a second interlayer dielectric layer 210, a first source-drain metal layer 211, a passivation layer 212, a first planarization layer 213, a second source-drain metal layer 214, and a second planarization layer 215, which are sequentially stacked; the driving element layer 300 of the display panel 1000 includes an anode layer 301, a pixel defining layer 302, a light-emitting layer 303, and a cathode layer 304, which are sequentially arranged.

[0097] Taking the structure included in a pixel driving circuit 10 as an example, the patterns of the respective film layers of the display panel 1000 will be described below.

[0098] Exemplarily, as Figure 4 、 Figure 16 shown, and with reference to Figure 2 、 Figure 3 、 Figure 17 shown, the driving circuit layer 200 of the display panel 1000 includes a first active layer 201, and the first active layer 201 is disposed on one side of the substrate 100, for example, above. The first active layer 201 includes the active layer patterns of a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0099] Among them, as Figure 4As shown, the active layer pattern 2011 of the first transistor T1 includes an active layer first pole pattern 2011-1, an active layer channel pattern 2011-3, and an active layer second pole pattern 2011-2 that are sequentially connected; the active layer pattern 2013 of the third transistor T3 includes an active layer first pole pattern 2013-1, an active layer channel pattern 2013-3, and an active layer second pole pattern 2013-2 that are sequentially connected; the active layer pattern 2014 of the fourth transistor T4 includes an active layer first pole pattern 2014-1, an active layer channel pattern 2014-3, and an active layer second pole pattern 2014-2 that are sequentially connected; the active layer pattern 2015 of the fifth transistor T5 includes an active layer first pole pattern 2015-1, an active layer channel pattern 2015-3, and an active layer second pole pattern 2015-2 that are sequentially connected; the active layer pattern 2016 of the sixth transistor T6 includes an active layer first pole pattern 2016-1, an active layer channel pattern 2016-3, and an active layer second pole pattern 2016-2 that are sequentially connected; the active layer pattern 2017 of the seventh transistor T7 includes an active layer first pole pattern 2017-1, an active layer channel pattern 2017-3, and an active layer second pole pattern 2017-2 that are sequentially connected; the active layer pattern 2018 of the eighth transistor T8 includes an active layer first pole pattern 2018-1, an active layer channel pattern 2018-3, and an active layer second pole pattern 2018-2 that are sequentially connected.

[0100] Exemplarily, as Figure 5 , Figure 18 shown, and referring to Figure 19 shown, the driving circuit layer 200 of the display panel 1000 further includes a first gate metal layer 203, and the first gate metal layer 203 is disposed on a side of the first active layer 201 away from the substrate 100. The first gate metal layer 203 includes a first reset signal line pattern 2031 extending along the first direction X, a second reset signal line pattern 2032 extending along the first direction X, a light emission control signal line pattern 2033 extending along the first direction X, a third gate signal line pattern 2034 extending along the first direction X, and a gate pattern 2035 of the third transistor T3.

[0101] Among them, as Figure 5 shown, the first reset signal line pattern 2031 overlaps with the active layer channel pattern 2011-3 of the first transistor T1 in a direction perpendicular to the substrate 100, and a portion of the first reset signal line pattern 2031 that overlaps with the active layer channel pattern 2011-3 of the first transistor T1 serves as the gate pattern 2031-1 of the first transistor T1.

[0102] Among them, as Figure 5As shown, the second reset signal line pattern 2032 overlaps with the active layer channel pattern 2017-3 of the seventh transistor T7 and the active layer channel pattern 2018-3 of the eighth transistor T8 in a direction perpendicular to the substrate 100. The overlapping portion of the second reset signal line pattern 2032 with the active layer channel pattern 2017-3 of the seventh transistor T7 serves as the gate pattern 2032-1 of the seventh transistor T7; the overlapping portion of the second reset signal line pattern 2032 with the active layer channel pattern 2018-3 of the eighth transistor T8 serves as the gate pattern 2032-2 of the eighth transistor T8.

[0103] Among them, as Figure 5 shown, the light emission control signal line pattern 2033 overlaps with the active layer channel pattern 2015-3 of the fifth transistor T5 and the active layer channel pattern 2016-3 of the sixth transistor T6 in a direction perpendicular to the substrate 100. The overlapping portion of the light emission control signal line pattern 2033 with the active layer channel pattern 2015-3 of the fifth transistor T5 serves as the gate T53 pattern 2033-2 of the fifth transistor T5; the overlapping portion of the light emission control signal line pattern 2033 with the active layer channel pattern 2016-3 of the sixth transistor T6 serves as the gate T63 pattern 2033-1 of the sixth transistor T6.

[0104] Among them, as Figure 5 shown, the third gate signal line pattern 2034 overlaps with the active layer channel pattern 2014-3 of the fourth transistor T4 in a direction perpendicular to the substrate 100. The overlapping portion of the third gate signal line pattern 2034 with the active layer channel pattern 2014-3 of the fourth transistor T4 serves as the gate pattern 2034-1 of the fourth transistor T4.

[0105] Among them, as Figure 5 shown, the gate pattern 2035 of the third transistor T3 overlaps with the active layer channel pattern 2013-3 of the third transistor T3 in a direction perpendicular to the substrate 100.

[0106] It should be noted that the overlap mentioned in some examples means that, in a direction perpendicular to the substrate 100, a partial pattern of one film layer is disposed opposite to a partial pattern of another film layer. The opposite setting can be interpreted as that the orthographic projection of a partial pattern of one film layer on the substrate 100 overlaps with the orthographic projection of a partial pattern of another film layer on the substrate 100, and the opposite-setting portion is the overlapping portion. There may be some other film layers, such as an insulating layer, etc., between the partial pattern of one film layer and the partial pattern of another film layer.

[0107] Exemplarily, as Figure 6 、 Figure 20 shown, and with reference to Figure 21As shown, the driving circuit layer 200 of the display panel 1000 further includes a second gate metal layer 205, and the second gate metal layer 205 is disposed on a side of the first gate metal layer 203 away from the substrate 100. The second gate metal layer 205 includes a first plate pattern 2052 of the coupling capacitor Cst and a first gate signal line pattern 2051 extending along the first direction X. Among them, the first plate pattern 2052 of the coupling capacitor Cst is disposed opposite to the gate pattern 2035 of the third transistor T3, and the gate pattern 2035 of the third transistor T3 can serve as the second plate pattern of the coupling capacitor Cst.

[0108] It should be noted that the opposite setting can be interpreted as that the positive projection of a partial pattern of one film layer on the substrate 100 overlaps with the positive projection of a partial pattern of another film layer on the substrate 100, and there may be some other film layers, such as an insulating layer, etc., between the partial pattern of one film layer and the partial pattern of another film layer.

[0109] Exemplarily, as Figure 7 、 Figure 22 shown, and referring to Figure 23 shown, the driving circuit layer 200 of the display panel 1000 further includes a second active layer 207, and the second active layer 207 is disposed on a side of the second gate metal layer 205 away from the substrate 100. The second active layer 207 includes an active layer pattern 2071 of the second transistor T2, and the active layer pattern 2071 of the second transistor T2 includes a first active layer pole pattern 2071-1, an active layer channel pattern 2071-3, and a second active layer pole pattern 2071-2 that are connected in sequence.

[0110] Among them, as Figure 7 shown, the active layer channel pattern 2071-3 of the second transistor T2 overlaps with the first gate signal line pattern 2051 of the second gate metal layer 205 in a direction perpendicular to the substrate 100, and a portion of the first gate signal line pattern 2051 that overlaps with the active layer channel pattern 2071-3 of the second transistor T2 serves as the first gate pattern 2051-1 of the second transistor T2.

[0111] Exemplarily, as Figure 8 、 Figure 24 shown, and referring to Figure 25 shown, the driving circuit layer 200 of the display panel 1000 further includes a third gate metal layer 209, and the third gate metal layer 209 is disposed on a side of the second active layer 207 away from the substrate 100. The third gate metal layer 209 includes a first initialization signal line pattern 2092 extending along the first direction X, a second initialization signal line pattern 2091 extending along the first direction X, a third initialization signal line pattern 2093 extending along the first direction X, and a second gate signal line pattern 2094 extending along the first direction X.

[0112] Among them, as Figure 8 shown, the first initialization signal line pattern 2092 is correspondingly arranged with the second reset signal line pattern 2032; the second initialization signal line pattern 2091 is correspondingly arranged with the first reset signal line pattern 2031; the third initialization signal line pattern 2093 is correspondingly arranged with the light emission control signal line pattern 2033; the second gate signal line pattern 2094 is correspondingly arranged with the first gate signal line pattern 2051. The active layer channel pattern 2071-3 of the second transistor T2 overlaps with the second gate signal line pattern 2094 in a direction perpendicular to the substrate 100, and the overlapping portion of the second gate signal line pattern 2094 and the active layer channel pattern 2071-3 of the second transistor T2 serves as the second gate pattern 2094-1 of the second transistor T2.

[0113] Exemplarily, as Figure 9 , Figure 26 , Figure 28 shown, and referring to Figure 27 , Figure 29 shown, the driving circuit layer 200 of the display panel 1000 further includes a second interlayer dielectric layer 210. A via hole process is performed on the second interlayer dielectric layer 210 to respectively form via holes 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, via holes 2102 penetrating through the third gate insulating layer 208 and the second interlayer dielectric layer 210, via holes 2103 penetrating through the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, via holes 2104 penetrating through the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, and via holes 2105 penetrating through the second interlayer dielectric layer 210.

[0114] Exemplarily, as Figure 10 , Figure 30 shown, and referring to Figure 31 , Figure 32 , Figure 33 shown, the driving circuit layer 200 of the display panel 1000 further includes a first source-drain metal layer 211, and the first source-drain metal layer 211 is disposed on a side of the second interlayer dielectric layer 210 away from the substrate 100.

[0115] Among them, as Figure 10 shown, and in combination with Figure 4 , Figure 9As shown, the first source / drain metal layer 211 includes a first pole pattern 2111-1 and a second pole pattern 2111-2 of the first transistor T1. The first pole pattern 2111-1 of the first transistor T1 is connected to the first pole pattern 2011-1 of the active layer of the first transistor T1 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. And the first pole pattern 2111-1 of the first transistor T1 is connected to the first initialization signal line pattern 2092 through a via 2105 that penetrates the second interlayer dielectric layer 210. The second pole pattern 2111-2 of the first transistor T1 is connected to the second pole pattern 2011-2 of the active layer of the first transistor T1 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0116] Among them, as Figure 10 shown, and in combination with Figure 4 、 Figure 9 shown, the first source / drain metal layer 211 includes a first pole pattern 2112-1 and a second pole pattern 2112-2 of the second transistor T2. The first pole pattern 2112-1 of the second transistor T2 is connected to the first pole pattern 2071-1 of the active layer of the second transistor T2 through a via 2102 that penetrates the third gate insulating layer 208 and the second interlayer dielectric layer 210. And the first pole pattern 2112-1 of the second transistor T2 is connected to the gate pattern 2035 of the third transistor T3 through a via 2104 that penetrates the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second pole pattern 2112-2 of the second transistor T2 is connected to the second pole pattern 2071-2 of the active layer of the second transistor T2 through a via 2102 that penetrates the third gate insulating layer 208 and the second interlayer dielectric layer 210. The second pole pattern 2112-2 of the second transistor T2 is connected to the second pole pattern 2111-2 of the first transistor T1.

[0117] Among them, as Figure 10 shown, and in combination with Figure 4 、 Figure 9As shown, the first source / drain metal layer 211 includes a first pole pattern 2113-1 and a second pole pattern 2113-2 of the third transistor T3. The first pole pattern 2113-1 of the third transistor T3 is connected to the first pole pattern 2013-1 of the active layer of the third transistor T3 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second pole pattern 2113-2 of the third transistor T3 is connected to the second pole pattern 2013-2 of the active layer of the third transistor T3 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second pole pattern 2113-2 of the third transistor T3 is connected to the second pole pattern 2112-2 of the second transistor T2.

[0118] Among them, as Figure 10 shown, and combined with Figure 4 , Figure 9 shown, the first source / drain metal layer 211 includes a first pole pattern 2114-1 and a second pole pattern 2114-2 of the fourth transistor T4. The first pole pattern 2114-1 of the fourth transistor T4 is connected to the first pole pattern 2014-1 of the active layer of the fourth transistor T4 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second pole pattern 2114-2 of the fourth transistor T4 is connected to the second pole pattern 2014-2 of the active layer of the fourth transistor T4 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second pole pattern 2114-2 of the fourth transistor T4 is connected to the first pole pattern 2113-1 of the third transistor T3.

[0119] Among them, as Figure 10 shown, and combined with Figure 4 , Figure 9As shown, the first source-drain metal layer 211 includes a first pole pattern 2115-1 and a second pole pattern 2115-2 of the fifth transistor T5; the first pole pattern 2115-1 of the fifth transistor T5 is connected to the first pole pattern 2015-1 of the active layer of the fifth transistor T5 through a via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; the second pole pattern 2115-2 of the fifth transistor T5 is connected to the second pole pattern 2015-2 of the active layer of the fifth transistor T5 through a via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210; the second pole pattern 2115-2 of the fifth transistor T5 is connected to the second pole pattern 2114-2 of the fourth transistor T4.

[0120] Among them, as Figure 10 shown, and in combination with Figure 4 、 Figure 9 shown, the first source-drain metal layer 211 includes a first pole pattern 2116-1 and a second pole pattern 2116-2 of the sixth transistor T6; the first pole pattern 2116-1 of the sixth transistor T6 is connected to the first pole pattern 2016-1 of the active layer of the sixth transistor T6 through a via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210, and the first pole pattern 2116-1 of the sixth transistor T6 is connected to the second pole pattern 2113-2 of the third transistor T3; the second pole pattern 2116-2 of the sixth transistor T6 is connected to the second pole pattern 2016-2 of the active layer of the sixth transistor T6 through a via 2101 penetrating through the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0121] Among them, as Figure 10 shown, and in combination with Figure 4 、 Figure 9As shown, the first source / drain metal layer 211 includes a first pole pattern 2117-1 and a second pole pattern 2117-2 of the seventh transistor T7. The first pole pattern 2117-1 of the seventh transistor T7 is connected to the first pole pattern 2017-1 of the active layer of the seventh transistor T7 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The first pole pattern 2117-1 of the seventh transistor T7 is connected to the second initialization signal line pattern 2091 through a via 2105 that penetrates the second interlayer dielectric layer 210. The second pole pattern 2117-2 of the seventh transistor T7 is connected to the second pole pattern 2017-2 of the active layer of the seventh transistor T7 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second pole pattern 2117-2 of the seventh transistor T7 is connected to the second pole pattern 2116-2 of the sixth transistor T6.

[0122] Among them, as Figure 10 shown, and in combination with Figure 4 、 Figure 9 shown, the first source / drain metal layer 211 includes a first pole pattern 2118-1 and a second pole pattern 2118-2 of the eighth transistor T8. The first pole pattern 2118-1 of the eighth transistor T8 is connected to the first pole pattern 2018-1 of the active layer of the eighth transistor T8 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second pole pattern 2118-2 of the eighth transistor T8 is connected to the second pole pattern 2018-2 of the active layer of the eighth transistor T8 through a via 2101 that penetrates the first gate insulating layer 202, the second gate insulating layer 204, the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210. The second pole pattern 2118-2 of the eighth transistor T8 is connected to the second pole pattern 2115-2 of the fifth transistor T5.

[0123] Among them, as Figure 10 shown, and in combination with Figure 9 shown, the first source / drain metal layer 211 includes a first power supply signal line bridging pattern 2119. The first power supply signal line bridging pattern 2119 is connected to the first pole pattern 2115-1 of the fifth transistor T5, and the first power supply signal line bridging pattern 2119 is connected to the first plate pattern 2052 of the coupling capacitor Cst through a via 2103 that penetrates the first interlayer dielectric layer 206, the third gate insulating layer 208, and the second interlayer dielectric layer 210.

[0124] Among them, asFigure 10 as shown in and in combination with Figure 9 As shown in Figure 9 , the first source-drain metal layer 211 includes a third initialization signal line bridging pattern 21110; the first pole pattern 2118-1 of the eighth transistor T8 is connected to the third initialization signal line bridging pattern 21110, and the third initialization signal line bridging pattern 21110 is connected to the third initialization signal line pattern 2093 through a via 2105 penetrating the second interlayer dielectric layer 210.

[0125] Among them, as Figure 10 shown in and in combination with Figure 9 As shown in Figure 9 , the first source-drain metal layer 211 includes a vertical third initialization signal line pattern 21111 extending along the second direction Y; the vertical third initialization signal line pattern 21111 is connected to the third initialization signal line pattern 2093 through a via 2105 penetrating the second interlayer dielectric layer 210.

[0126] It should be noted that the connection of a pattern of a certain film layer to another pattern can be regarded as these two patterns being the same pattern. For example, the connection of the first pole pattern 2118-1 of the eighth transistor T8 on the first source-drain metal layer 211 to the third initialization signal line bridging pattern 21110 can be understood as the first pole pattern 2118-1 of the eighth transistor T8 on the first source-drain metal layer 211 and the third initialization signal line bridging pattern 21110 being the same pattern.

[0127] Exemplarily, as Figure 11 、 Figure 34 shown in and with reference to Figure 35 As shown in Figure 35 , the driving circuit layer 200 of the display panel 1000 further includes a passivation layer 212 and a first planarization layer 213, and a via 2131 penetrating the passivation layer 212 and the first planarization layer 213 is formed by performing a drilling process on the first planarization layer 213.

[0128] Exemplarily, as Figure 12 、 Figure 36 shown in and with reference to Figure 37 As shown in Figure 37 , the driving circuit layer 200 of the display panel 1000 further includes a second source-drain metal layer 214, and the second source-drain metal layer 214 is disposed on a side of the first source-drain metal layer 211 away from the substrate 100. The second source-drain metal layer 214 includes a data signal line pattern 2143 extending along the second direction Y, a first power supply signal line pattern 2141 extending along the second direction Y, and an anode tab pattern 2142.

[0129] Among them, as Figure 12 shown in and in combination with Figure 10 、 Figure 11As shown, the data signal line pattern 2143 is connected to the first pole pattern 2114-1 of the fourth transistor T4 through the via 2131 that penetrates the passivation layer 212 and the first planarization layer 213; the first power supply signal line pattern 2141 is connected to the first power supply signal line bridging pattern 2119 through the via 2131 that penetrates the passivation layer 212 and the first planarization layer 213; the anode lead pattern 2142 is connected to the second pole pattern 2116-2 of the sixth transistor T6 through the via 2131 that penetrates the passivation layer 212 and the first planarization layer 213.

[0130] Exemplarily, as Figure 13 、 Figure 40 shown, and referring to FIG. Figure 38 、 Figure 39 、 42 shown, the driving element layer 300 of the display panel 1000 includes an anode layer 301; the anode layer 301 includes a plurality of anode patterns 3010, and one anode pattern 3010 is connected to one anode lead pattern 2142 through a via that penetrates the second planarization layer 215.

[0131] Exemplarily, as Figure 14 、 Figure 42 shown, and referring to Figure 43 shown, the driving element layer 300 of the display panel 1000 further includes a pixel defining layer 302; the pixel defining layer 302 includes a plurality of openings 3021, and one opening 3021 exposes one anode pattern 3010.

[0132] Exemplarily, the driving element layer 300 of the display panel 1000 further includes a light emitting layer 303, and the light emitting layer 303 includes a plurality of light emitting patterns, and one light emitting pattern is located within one opening 3021.

[0133] Exemplarily, the driving element layer 300 of the display panel 1000 further includes a cathode layer 304, and the cathode layer 304 is entirely laid on the side of the light emitting layer 303 away from the substrate 100.

[0134] Through the above settings, the pixel driving circuit 10 as Figure 3 shown can be implemented in the display panel 1000.

[0135] It should be noted that the film layer arrangement of the display panel 1000 is not limited to including the film layers described above. In some embodiments, multiple insulating layers may be included between adjacent metal layers; in other embodiments, one or more of the above metal layers may be deleted, or one or more metal layers may be added; in still other embodiments, as Figure 43As shown, the driving element layer 300 of the display panel 1000 may further include spacers 305 disposed on the side of the pixel defining layer 302 away from the substrate 100. The arrangement of the film layers of the display panel 1000 can be designed according to specific circumstances, and the present application does not limit this here.

[0136] When the display panel 1000 does not display an image, it is required that the element to be driven 20 in the sub-pixel P of the display panel 1000 stops working, that is, the pixel driving circuit 10 in the sub-pixel P of the display panel 1000 is disconnected, and no current passes through the element to be driven 20 coupled to the pixel driving circuit 10. The conduction or disconnection of the pixel driving circuit 10 is controlled by the conduction or cut-off of a transistor. However, a transistor, such as a P-type transistor, may have a leakage current in the cut-off state, that is, there is still current passing through the transistor in the cut-off state; when the passing leakage current is large enough to enable the element to be driven 20 of the sub-pixel P to work, the sub-pixel P of the display panel 1000 will be lit, forming a non-extinguishing point (bright point) on the display panel 1000.

[0137] Exemplarily, as Figure 3 shown, when the display panel 1000 does not display an image, that is, when the pixel driving circuit 10 is in the non-light-emitting stage, the second transistor T2 and the sixth transistor T6 are cut off, the first node N1 is at a high voltage level, and the fourth node N4 is at a low voltage level. When the leakage currents of the second transistor T2 and the sixth transistor T6 are too large, current will flow through the element to be driven 20, causing the element to be driven 20 to start working, and the sub-pixel P is lit, forming a bright point on the display panel 1000; or when the leakage currents of the fifth transistor T5, the third transistor T3, and the sixth transistor T6 are too large, current will flow through the element to be driven 20, causing the element to be driven 20 to start working, and the sub-pixel P is lit, forming a non-extinguishing point (bright point) on the display panel 1000.

[0138] In some embodiments, in order to avoid the bright point defect of the display panel 1000 when it does not display an image, an electrical aging process (Aging process) can be used to reduce the leakage current of the transistor, for example, reduce the leakage current of the P-type transistor, so that the leakage current is not large enough to enable the element to be driven 20 of the sub-pixel P to work, eliminate the bright point defect caused by the too high leakage current of the transistor, and improve the stability of the transistor.

[0139] Exemplarily, the principle of the Aging process for reducing the leakage current of transistors is as follows: In the display panel 1000, the active layer, gate metal layer, and source-drain metal layer of the display panel 1000 are combined to form a transistor, such as a P-type transistor. The active layer includes an active layer source, an active layer channel region, and an active layer drain; the gate metal layer includes a gate, which is correspondingly arranged with the active layer channel region; the source-drain metal layer includes a source and a drain, the source is connected to the active layer source, and the drain is connected to the active layer drain. A negative voltage is applied to the drain of the transistor, such as a P-type transistor, and a positive voltage is applied to the gate, so that the electrons at the drain of the transistor are captured by the gate of the gate metal layer. Therefore, holes are induced in the active layer channel region to form a structure similar to a lightly doped drain (LDD), thereby reducing the gate-drain electric field and reducing the leakage current of the transistor.

[0140] Exemplarily, the Aging process can be used to reduce the leakage current of the P-type transistor in the pixel driving circuit 10 as shown in Figure 3 Figure. The specific Aging process layout is shown in Table 1.

[0141] Pattern Vgh / Vgh-N Vgl / Vgl-N Vdd Vss Vint1 Vint2 Vinit3 Vdata Time 1 T1 / T7-1 15 -7 7 7 -15 -15 4 4 15s 2 T4 / T8-1 15 -12 -8 10 -4 -4 12 12 15s 3 T3-1 7 -15 -3 -20 -15 -15 7 7 15s 4 T1 / T7-2 15 -7 5 5 -20 -20 0 0 15s 5 T4 / T8-2 15 -12 -10 10 -4 -4 12 12 15s 6 T6 12 -10 12 -8 -8 -8 12 12 15s 7 T3-2 7 -17 0 -20 -15 -15 7 7 15s 8 T3-3 7 -17 3 -22 -15 -15 7 7 15s 9 L-G 8.5 -7 4.6 -3 -4 -3 7.4 8.5 / 2.7 / 8.5 3min 10 L-B 8.5 -7 4.6 -3 -4 -3 7.4 8.5 / 8.5 / 0.1 7min

[0142] Table 1

[0143] As shown in Table 1, where Pattern represents the process layout, Vgh / Vgh-N represents the voltage of the high-voltage signal, Vgl / Vgl-N represents the voltage of the low-voltage signal, Vdd represents the voltage of the first power supply signal, Vss represents the voltage of the second power supply signal, Vint1 represents the voltage of the first initialization signal, Vint2 represents the voltage of the second initialization signal, Vint3 represents the voltage of the third initialization signal, Vdata represents the voltage of the data signal, and Time represents the time used for the Aging process.

[0144] Specifically, the row corresponding to No. 1 in Table 1 indicates that the first Aging process is performed on the first transistor T1 and the seventh transistor T7 respectively; the voltage Vgh / Vgh-N of the high-voltage signal applied to the gates T13 of the first transistor T1 and T73 of the seventh transistor T7 is 15V; the voltage Vgl / Vgl-N of the low-voltage signal applied to the drains of the first transistor T1 and the seventh transistor T7 is -7V; the voltage Vdd of the first power supply signal is 7V; the voltage Vss of the second power supply signal is 7V; the voltage Vint1 of the first initialization signal is -15V; the voltage Vint2 of the second initialization signal is -15V; the voltage Vint3 of the third initialization signal is 4V; the voltage Vdata of the data signal is 4V; and the time Time used for the Aging process is 15s.

[0145] The meanings represented by the rows where the serial numbers 2 to 10 are located in Table 1 are the same as those represented by the row where the serial number 1 is located, and will not be elaborated here.

[0146] For the relevant P-type transistors in the pixel driving circuit 10 as Figure 3 shown, after performing the Aging process, the leakage current that appears in the pixel driving circuit 10 as Figure 3 shown is greatly reduced, the probability of bright spot defects when the display panel 1000 does not display an image is reduced, and the stability of the pixel driving circuit 10 as Figure 3 shown is improved. At the same time, when performing a display image detection on the display panel 1000, the inventor of the present disclosure found that non-emitting points (dark spots) appeared on the display panel 1000 when displaying an image. When observing the position where the non-emitting points (dark spots) appeared on the display panel 1000 using an optical microscope, it can be clearly seen that the pixels at the positions where the non-emitting points (dark spots) appeared were significantly burned, resulting in burned-type dark spots on the display panel 1000.

[0147] Regarding the reason for the formation of the burned-type dark spots, the inventor of the present disclosure found through research that: the reason for the pixels to be burned is likely that there is a short circuit in the signal lines of the pixel driving circuit 10, resulting in the pixels of the display panel 1000 being burned and burned-type dark spots appearing.

[0148] The inventor of the present disclosure analyzed the signal lines of each film layer in the driving circuit layer 200 of the display panel 1000. After analysis, as Figure 3 shown, and in combination with Figure 10 shown, the first pole T81 of the eighth transistor T8 is coupled to the third initialization signal line Vinit3; in the design of the driving circuit layer 200 of the display panel 1000, the third gate metal layer 209 includes a first initialization signal line pattern 2092 extending along the first direction X and a third initialization signal line pattern 2093 extending along the first direction X, and the first source-drain metal layer 211 includes a first pole pattern 2118-1 of the eighth transistor T8 and a third initialization signal line bridging pattern 21110; the first pole pattern 2118-1 of the eighth transistor T8 is connected to the third initialization signal line bridging pattern 21110, and the third initialization signal line bridging pattern 21110 is connected to the third initialization signal line pattern 2093 through a via 2105 penetrating the second interlayer dielectric layer 210, thereby realizing the coupling of the first pole T81 of the eighth transistor T8 to the third initialization signal line Vinit3.

[0149] However, the third initialization signal line bridging pattern 21110 overlaps with the first initialization signal line pattern 2092, and there is only one second interlayer dielectric layer 210 between the first source-drain metal layer 211 where the third initialization signal line bridging pattern 21110 is located and the third gate metal layer 209 where the first initialization signal line pattern 2092 is located. If there are small particles or dust during the preparation of the second interlayer dielectric layer 210 of the display panel 1000, the small particles or dust will pierce through the second interlayer dielectric layer 210. For example, it pierces through the second interlayer dielectric layer 210 at the overlapping position of the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092, or the small particles or dust prevent the originally deposited second interlayer dielectric layer 210 from being successfully deposited, resulting in the second interlayer dielectric layer 210 not taking effect. When magnetron sputtering the first source-drain metal layer 211, the material of the first source-drain metal layer 211 will enter the gaps of the small particles or dust, making the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092 conductive or directly connected, thus causing a short circuit between the first initialization signal line Vinit1 and the third initialization signal line Vinit3. According to the FIB diagram, it can be further determined that there are small particles or dust PT at the overlapping position of the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092, resulting in a short circuit between the first initialization signal line Vinit1 and the third initialization signal line Vinit3.

[0150] As can be seen from Table 1, when performing the Aging process on the P-type transistor in the pixel driving circuit 10 as Figure 3 shown, the voltage difference between the voltage Vint1 of the first initialization signal and the voltage Vint3 of the third initialization signal can reach 22V. When the first initialization signal line Vinit1 and the third initialization signal line Vinit3 of the display panel 1000 are short-circuited, during the Aging process of the display panel 1000, the voltage difference between the voltage Vint1 of the first initialization signal and the voltage Vint3 of the third initialization signal is relatively large. For example, when it is 22V, it will cause the signal lines and pixels of the display panel 1000 to be burned, resulting in burn-type dark spots, and further greatly reducing the manufacturing yield of the display panel 1000.

[0151] To avoid burn-type dark spots, in some embodiments, a display panel 1000 is provided, as Figure 1 shown. The display panel 1000 includes a plurality of sub-pixels P, and the plurality of sub-pixels P are arranged in multiple rows along the first direction X. Two adjacent sub-pixels P in one row of sub-pixels P form a pixel group PP; one sub-pixel P includes a pixel driving circuit 10, and the pixel driving circuit 10 is coupled to at least one signal line 30.

[0152] As Figure 3As shown, the pixel driving circuit 10 includes a specified transistor 11, and at least one signal line 30 includes a specified signal line 31, and the specified transistor 11 is coupled to the specified signal line 31; wherein, the specified transistor 11 is one of the multiple transistors included in the pixel driving circuit 10, the specified signal line 31 is one of the multiple signal lines 30 connected to the pixel driving circuit 10, and the specified signal line 31 is connected to the specified transistor 11.

[0153] Taking the structure included in two adjacent sub-pixels P (i.e., a pixel group PP) along the first direction X as an example, the patterns of each film layer of the display panel 1000 will be introduced.

[0154] As Figure 2 shown, the display panel 1000 includes a substrate 100 and a driving circuit layer 200 disposed on one side of the substrate 100, and the pixel driving circuit 10 is disposed on the driving circuit layer 200. As Figure 15 shown, the driving circuit layer 200 includes a first active layer 201 disposed on one side of the substrate 100, a specified gate metal layer 2001 disposed on the side of the first active layer 201 away from the substrate 100, and a first source-drain metal layer 211 disposed on the side of the specified gate metal layer 2001 away from the substrate 100; the first active layer 201 includes an active layer pattern 2010 of the specified transistor 11, and the active layer pattern 2010 of the specified transistor 11 includes an active layer first pole pattern 2010-1. In a pixel group PP, the active layer first pole pattern 2010-1 of the specified transistor 11 of one sub-pixel P is connected to the active layer first pole pattern 2010-1' of the specified transistor 11 of another sub-pixel P'; the specified gate metal layer 2001 includes a specified signal line pattern 20010 of the specified signal line 31; the first source-drain metal layer 211 includes a specified signal line bridging pattern 2110. In a pixel group PP, the specified signal line bridging pattern 2110 is located within the area of one sub-pixel P, the specified signal line bridging pattern 2110 is connected to the active layer first pole pattern 2010-1 of the specified transistor 11 of one of the sub-pixels P, and is also connected to the specified signal line pattern 20010.

[0155] Exemplarily, as Figure 1 shown, two adjacent sub-pixels P in a row of sub-pixels P can be used as a pixel group PP. The display panel 1000 includes multiple pixel groups PP, and the pixel group PP is the smallest repeating unit of the display panel 1000, that is, the settings of each film layer of the multiple pixel groups PP in the display panel 1000 are the same.

[0156] Exemplarily, as Figure 1 shown, the pixel driving circuit 10 is coupled to the signal lines in the display panel 1000, as Figure 3As shown, the pixel driving circuit 10 includes a designated transistor 11, and the signal line includes a designated signal line 31, and the designated transistor 11 is coupled to the designated signal line 31.

[0157] It should be noted that the number of the designated transistors 11 is not limited herein. There may be only one designated transistor 11, or there may be multiple ones. The number of the designated signal lines 31 is not limited herein. There may be only one designated signal line 31, or there may be multiple ones. When there is only one designated transistor 11 and one designated signal line 31, the designated transistor 11 is coupled to the designated signal line 31. When there are multiple designated transistors 11 and multiple designated signal lines 31, one designated transistor 11 is coupled to one designated signal line 31.

[0158] Exemplarily, as Figure 2 shown, the display panel 1000 includes a substrate 100 and a driving circuit layer 200 disposed on one side of the substrate 100. The driving circuit layer 200 is a general term for the film layer where the pixel driving circuits 10 of all the sub-pixels P in the display panel 1000 are located, that is, the pixel driving circuit 10 is disposed in the driving circuit layer 200.

[0159] Exemplarily, as Figure 15 shown, the driving circuit layer 200 includes a first active layer 201 disposed on one side of the substrate 100, a designated gate metal layer 2001 disposed on the side of the first active layer 201 away from the substrate 100, and a first source-drain metal layer 211 disposed on the side of the designated gate metal layer 2001 away from the substrate 100. An insulating layer is disposed between the first active layer 201 and the designated gate metal layer 2001, and an insulating layer is disposed between the designated gate metal layer 2001 and the first source-drain metal layer 211.

[0160] Exemplarily, as Figure 15 shown, the first active layer 201 includes an active layer pattern 2010 of the designated transistor 11. The active layer pattern 2010 of the designated transistor 11 includes an active layer first pole pattern 2010-1, an active layer channel pattern 2010-3, and an active layer second pole pattern 2010-2 that are connected in sequence. The active layer first pole pattern 2010-1 of the designated transistor 11 of one sub-pixel P in a pixel group PP is connected to the active layer first pole pattern 2010-1' of the designated transistor 11 of another sub-pixel P'.

[0161] It should be noted that when there are multiple designated transistors 11 in the pixel driving circuit 10, the first pole patterns 2010-1 of the active layers of the designated transistors 11 corresponding to two sub-pixels P in a pixel group PP are connected. Specifically, for example, a sub-pixel P includes three designated transistors 11, namely a first designated transistor, a second designated transistor, and a third designated transistor; in a pixel group PP, the first pole pattern 2010-1 of the active layer of the first designated transistor of a sub-pixel P is connected to the first pole pattern 2010-1' of the active layer of the first designated transistor of another sub-pixel P', the first pole pattern 2010-1 of the active layer of the second designated transistor of a sub-pixel P is connected to the first pole pattern 2010-1' of the active layer of the second designated transistor of another sub-pixel P', and the first pole pattern 2010-1 of the active layer of the third designated transistor of a sub-pixel P is connected to the first pole pattern 2010-1' of the active layer of the third designated transistor of another sub-pixel P'.

[0162] Exemplarily, as Figure 15 shown, the designated gate metal layer 2001 includes a designated signal line pattern 20010 of the designated signal line 31.

[0163] Exemplarily, as Figure 15 shown, the first source-drain metal layer 211 includes a designated signal line bridging pattern 2110; in a pixel group PP, the designated signal line bridging pattern 2110 is located within the area of one sub-pixel P. It can be understood that the area of another sub-pixel P' does not include the designated signal line bridging pattern 2110, that is, among the two sub-pixels P of a pixel group PP, only one sub-pixel P includes the designated signal line bridging pattern 2110; the designated signal line bridging pattern 2110 is connected to the first pole pattern 2010-1 of the active layer of the designated transistor 11 of one sub-pixel P through a via hole penetrating the insulating layer between the first source-drain metal layer 211 and the first active layer 201; and the designated signal line bridging pattern 2110 is also connected to the designated signal line pattern 20010 through a via hole penetrating the insulating layer between the first source-drain metal layer 211 and the designated gate metal layer 2001.

[0164] It should be noted that the number of specified signal line bridging patterns 2110 in the area where a sub-pixel P is located is not limited herein. There may be only one specified signal line bridging pattern 2110, or there may be multiple ones. When there is only one active layer first pole pattern 2010-1 of the specified transistor 11 and only one specified signal line pattern 20010, there is also only one specified signal line bridging pattern 2110. When there are multiple active layer first pole patterns 2010-1 of the specified transistor 11 and multiple specified signal line patterns 20010, there may also be multiple specified signal line bridging patterns 2110. The active layer first pole pattern 2010-1, the specified signal line pattern 20010, and the specified signal line bridging pattern 2110 of the specified transistor 11 correspond to each other. Specifically, for example, a sub-pixel P includes two specified transistors 11, namely a first specified transistor and a second specified transistor, that is, a sub-pixel P includes an active layer first pole pattern of the first specified transistor and an active layer first pole pattern of the second specified transistor. A sub-pixel P includes two specified signal line patterns 20010, namely a first specified signal line pattern and a second specified signal line pattern. A sub-pixel P includes two specified signal line bridging patterns 2110, namely a first specified signal line bridging pattern and a second specified signal line bridging pattern. The first specified signal line bridging pattern of a sub-pixel P is respectively connected to the active layer first pole pattern of the first specified transistor and the first specified signal line pattern, and the second specified signal line bridging pattern of a sub-pixel P is respectively connected to the active layer first pole pattern of the second specified transistor and the second specified signal line pattern.

[0165] Although among the two sub-pixels P of a pixel group PP, the specified signal line bridging pattern 2110 is only provided in one of the sub-pixels P, and the specified signal line bridging pattern 2110 is connected to the active layer first pole pattern 2010-1 of the specified transistor 11 in one of the sub-pixels P through a via hole penetrating the insulating layer between the first source-drain metal layer 211 and the first active layer 201, so that the signal transmitted by the specified signal line pattern 20010 is transmitted to the active layer first pole pattern 2010-1 of the specified transistor 11 in one of the sub-pixels P through the specified signal line bridging pattern 2110; however, since the active layer first pole pattern 2010-1 of the specified transistor 11 in one of the sub-pixels P in a pixel group PP is connected to the active layer first pole pattern 2010-1' of the specified transistor 11 in another sub-pixel P', therefore, while the signal transmitted by the specified signal line pattern 20010 is transmitted to the active layer first pole pattern 2010-1 of the specified transistor 11 in one of the sub-pixels P through the specified signal line bridging pattern 2110, the signal transmitted by the specified signal line pattern 20010 will also be transmitted to the active layer first pole pattern 2010-1' of the specified transistor 11 in another sub-pixel P' through the specified signal line bridging pattern 2110, so as to enable the active layer first pole patterns 2010-1 of the specified transistors 11 in the two sub-pixels P of a pixel group PP to both receive the signal transmitted by the specified signal line pattern 20010.

[0166] Therefore, the specified signal line bridging pattern 2110 is provided in one of the sub-pixels P of a pixel group PP, and the specified signal line bridging pattern 2110 is connected to the active layer first pole pattern 2010-1 of the specified transistor 11 in one of the sub-pixels P and the specified signal line pattern 20010; since the active layer first pole patterns 2010-1 of the specified transistors 11 in the two sub-pixels P of a pixel group PP are connected, it can be realized that the active layer first pole patterns 2010-1 of the specified transistors 11 in the two sub-pixels P of a pixel group PP can both be connected to the specified signal line pattern 20010 through the specified signal line bridging pattern 2110, without affecting the operation of the pixel driving circuit 10; this setting reduces the specified signal line bridging pattern 2110 in one of the sub-pixels P in the pixel group PP, that is, reduces the number of the specified signal line bridging patterns 2110, thereby reducing the overlap between the specified signal line bridging pattern 2110 and other signal line patterns, reducing the probability of short circuit caused by the overlap between the specified signal line bridging pattern 2110 and other signal line patterns from the source, thereby reducing the probability of occurrence of burn-type dark dots, greatly improving the burn-type dark dot defect of the display panel 1000, improving the manufacturing yield, and significantly improving the Y-line defect caused by burning, and significantly reducing the market-end risk caused by the burning of the pixel driving circuit 10.

[0167] In some embodiments, such as Figure 15As shown, in a pixel group PP, the first pole pattern 2010-1 of the active layer of the designated transistor 11 of one sub-pixel P is connected to the first pole pattern 2010-1' of the active layer of the designated transistor 11 of another sub-pixel P' at the designated connection point 1, and the designated signal line bridging pattern 2110 is connected to the designated connection point 1.

[0168] Exemplarily, the designated connection point 1 can be set at a position where its orthographic projection on the substrate 100 is closer to the orthographic projection of the designated signal line pattern 20010 on the substrate 100; such a setting is beneficial to reducing the length of the designated signal line bridging pattern 2110, reducing the probability of defects occurring during the preparation process of the designated signal line bridging pattern 2110, and at the same time reducing the impedance of the designated signal line bridging pattern 2110.

[0169] In some embodiments, as Figure 15 shown, in a pixel group PP, the active layer patterns 2010 of the designated transistors 11 of two sub-pixels P are mirror-symmetrical, and the designated connection point 1 is located on the mirror symmetry axis 2 of the active layer patterns 2010 of the designated transistors 11 of the two sub-pixels P; the designated signal line pattern 20010 extends along the first direction X and passes through the regions where the two sub-pixels P are located.

[0170] Exemplarily, as Figure 15 shown, the active layer patterns 2010 of the designated transistors 11 of two sub-pixels P in a pixel group PP are mirror-symmetrical, and the designated connection point 1 is set on the mirror symmetry axis 2 of the active layer patterns 2010 of the designated transistors 11 of the two sub-pixels P, that is, the sizes and shapes of the first pole patterns 2010-1 of the active layers of the designated transistors 11 of the two sub-pixels P are the same, and the lengths of the transmission paths from the designated connection point 1 to the first pole patterns 2010-1 of the active layers of the designated transistors 11 of the two sub-pixels P are the same, which can ensure that the first pole patterns 2010-1 of the active layers of the designated transistors 11 of the two sub-pixels P in a pixel group PP receive the signals transmitted by the designated signal line pattern 20010 simultaneously, and the losses of the received signals are consistent, enabling synchronous transmission and ensuring the uniformity of the sub-pixels P in the display panel 1000.

[0171] In some embodiments, as Figure 15 shown, the width of the designated signal line bridging pattern 2110 is greater than the set width.

[0172] Exemplarily, as Figure 15As shown, when the specified signal line bridging pattern 2110 is set in one sub-pixel P of a pixel group PP, compared with setting the specified signal line bridging pattern 2110 in each sub-pixel P, since one specified signal line bridging pattern 2110 is reduced, the impedance of the specified signal line bridging pattern 2110 increases, resulting in an increase in the write impedance of the specified signal line 31.

[0173] In some embodiments, the specified signal line bridging pattern 2110 is set in each sub-pixel P, and the width of the specified signal line bridging pattern 2110 can be, for example, the set width of 1.8 um. In order to reduce Figure 15 the impedance of the specified signal line bridging pattern 2110 when the specified signal line bridging pattern 2110 is set in one sub-pixel P of a pixel group PP as shown, the width of the specified signal line bridging pattern 2110 can be set to 1.8 um to 3 um, such as 2 um, 2.1 um, 2.2 um, 2.3 um, 2.4 um, 2.5 um, 2.6 um, 2.7 um, 2.8 um, 2.9 um, 3 um, so as to compensate for the write ability of the specified signal line 31.

[0174] It should be noted that the "set width" refers to the width of the specified signal line bridging pattern 2110 when the specified signal line bridging pattern 2110 is set in each sub-pixel P. The above-mentioned "set width of 1.8 um" is only an exemplary width, and the set width is not necessarily 1.8 um. The "set width" can be set according to the actual product process, and the present disclosure does not make a setting.

[0175] In some embodiments, as Figure 15 shown, the pixel driving circuit 10 further includes other transistors in addition to the specified transistor 11; the first active layer 201 further includes the active layer patterns of other transistors; the active layer patterns of other transistors include active layer channel patterns; the active layer pattern 2010 of the specified transistor 11 includes an active layer channel pattern 2010-3, and the aspect ratio of the active layer channel pattern 2010-3 of the specified transistor 11 is greater than the aspect ratio of the active layer channel patterns of other transistors.

[0176] Exemplarily, as Figure 15 shown, when the specified signal line bridging pattern 2110 is set in one sub-pixel P of a pixel group PP, compared with setting the specified signal line bridging pattern 2110 in each sub-pixel P, the impedance of the specified signal line bridging pattern 2110 increases, resulting in an increase in the write impedance of the specified signal line 31; the write ability of the specified signal line 31 can be compensated by increasing the aspect ratio of the active layer channel pattern 2010-3 of the specified transistor 11.

[0177] Exemplarily, a specified signal line bridging pattern 2110 is provided in each sub-pixel P. For example, the aspect ratios of the active layer channel patterns of the transistors in the sub-pixel P may be the same, and for example, the aspect ratios may all be 2 / 4; in order to compensate for Figure 15 the writing ability of the specified signal line 31 when the specified signal line bridging pattern 2110 is provided in one of the sub-pixels P of a pixel group PP as shown, the aspect ratio of the active layer channel pattern 2010-3 of the specified transistor 11 can be increased, while the aspect ratios of the active layer channel patterns of other transistors remain unchanged; for example, the aspect ratio of the active layer channel pattern 2010-3 of the specified transistor 11 can be 2.4 / 4.

[0178] In some embodiments, the display panel 1000 includes a plurality of sub-pixels P. One sub-pixel P includes a pixel driving circuit 10 as shown in Figure 3 ; a plurality of sub-pixels P are arranged in multiple rows along the first direction X. Two adjacent sub-pixels P in one row of sub-pixels P form a pixel group PP. Except for the difference in the setting of the first active layer 201 and the first source-drain metal layer 211 between the two sub-pixels in a pixel group PP, the other film layer settings are the same as those of one sub-pixel described above. For the film layer settings of the two sub-pixels in a pixel group PP, see Figures 15 to 43 and will not be elaborated here.

[0179] In some embodiments, as shown in Figure 3 , the specified transistor 11 includes a third reset transistor, that is, the eighth transistor T8, and the specified signal line 31 includes a third initialization signal line Vinit3. The third reset transistor, that is, the eighth transistor T8 is coupled to the third initialization signal line Vinit3; as shown in Figure 30 , the first active layer 201 includes an active layer pattern 2018 of the third reset transistor, that is, the eighth transistor T8. The active layer pattern 2018 of the third reset transistor, that is, the eighth transistor T8 includes an active layer first pole pattern 2018-1; the specified gate metal layer 2001 includes a third initialization signal line pattern 2093 of the third initialization signal line Vinit3; the specified signal line bridging pattern 2110 includes a third initialization signal line bridging pattern 21110, and the first source-drain metal layer 211 includes the third initialization signal line bridging pattern 21110.

[0180] Exemplarily, as shown in Figure 16As shown, the first active layer 201 includes the active layer pattern 2018 of the eighth transistor T8. The active layer pattern 2018 of the eighth transistor T8 includes a first active layer pole pattern 2018-1, an active layer channel pattern 2018-3, and a second active layer pole pattern 2018-2 that are connected in sequence. The first active layer pole pattern 2018-1 of the eighth transistor T8 of a sub-pixel P in a pixel group PP is connected to the first active layer pole pattern 2018-1' of the eighth transistor T8 of another sub-pixel P'.

[0181] Exemplarily, as Figure 24 shown, the designated gate metal layer 2001 can be, for example, the third gate metal layer 209. The designated gate metal layer 2001, such as the third gate metal layer 209, includes the third initialization signal line pattern 2093 of the third initialization signal line Vinit3.

[0182] Exemplarily, as Figure 30 shown, the designated signal line bridging pattern 2110 includes the third initialization signal line bridging pattern 21110. The first source-drain metal layer 211 includes the third initialization signal line bridging pattern 21110. In a pixel group PP, the third initialization signal line bridging pattern 21110 is located within the area of a sub-pixel P. It can be understood that the area of another sub-pixel P' does not include the third initialization signal line bridging pattern 21110. That is to say, among the two sub-pixels P of a pixel group PP, only one sub-pixel P includes the third initialization signal line bridging pattern 21110; the third initialization signal line bridging pattern 21110 is connected to the first active layer pole pattern 2018-1 of the eighth transistor T8 of one of the sub-pixels P through a via hole that penetrates the insulating layer between the first source-drain metal layer 211 and the first active layer 201; and the third initialization signal line bridging pattern 21110 is also connected to the third initialization signal line pattern 2093 through a via hole that penetrates the insulating layer between the first source-drain metal layer 211 and the designated gate metal layer 2001.

[0183] In some embodiments, as Figure 3 shown, the signal line further includes the first initialization signal line Vinit1; as Figure 24 shown, the designated gate metal layer 2001, such as the third gate metal layer 209, further includes the first initialization signal line pattern 2092 of the first initialization signal line Vinit1; the first initialization signal line pattern 2092 extends along the first direction X and passes through the areas of the two sub-pixels P in a pixel group PP; as Figure 30 shown, the third initialization signal line bridging pattern 21110 overlaps with the first initialization signal line pattern 2092.

[0184] Exemplarily, as Figure 30As shown, when the third initialization signal line bridging pattern 21110 is connected to the first pole pattern 2018-1 of the active layer of the eighth transistor T8 of one of the sub-pixels P and is also connected to the third initialization signal line pattern 2093, although the third initialization signal line bridging pattern 21110 will overlap with the first initialization signal line pattern 2092, only one sub-pixel P in a pixel group PP is provided with the third initialization signal line bridging pattern 21110, reducing the third initialization signal line bridging pattern 21110 of one sub-pixel P in the pixel group PP, that is, reducing the number of the third initialization signal line bridging patterns 21110, thereby reducing the overlap between the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092, reducing the probability of short circuit caused by the overlap between the third initialization signal line bridging pattern 21110 and the first initialization signal line pattern 2092 from the source, thereby reducing the probability of occurrence of burning-type dark spots, greatly improving the burning-type dark spot defect of the display panel 1000, improving the manufacturing yield, and significantly improving the Y-line defect caused by burning, and significantly reducing the market-end risk caused by the burning of the pixel driving circuit 10.

[0185] In some embodiments, as Figure 44 shown and with reference to Figure 10 , the width of the third initialization signal line bridging pattern 21110 is greater than the set width.

[0186] Exemplarily, as Figure 44 shown, in a pixel group PP, two sub-pixels P share one third initialization signal line bridging pattern 21110, and the initialization signal transmitted by the third initialization signal line Vinit3 reaches the eighth transistors T8 of the two sub-pixels P through one third initialization signal line bridging pattern 21110. At this time, the impedance of the third initialization signal line bridging pattern 21110 is increased compared with the impedance when the initialization signal transmitted by the third initialization signal line Vinit3 in some previous embodiments reaches the eighth transistors T8 of the two sub-pixels P through two third initialization signal line bridging patterns 21110, thereby causing an increase in the write impedance of the third initialization signal line Vinit3.

[0187] Exemplarily, as Figure 44 shown, in order to reduce the impedance of the third initialization signal line bridging pattern 21110 when the third initialization signal line bridging pattern 21110 is provided in one of the sub-pixels P of a pixel group PP, the width of the third initialization signal line bridging pattern 21110 can be greater than the width of other patterns on the first source-drain metal layer 211, and other patterns can be, for example, the first power supply signal line bridging pattern 2119, the first pole pattern 2112-1 of the second transistor T2, etc.

[0188] Exemplarily, as Figure 10A third initialization signal line bridging pattern 21110 is provided in each of the sub-pixels P shown. The width of the third initialization signal line bridging pattern 21110 can be, for example, 1.8 um. In order to reduce Figure 44 the impedance of the third initialization signal line bridging pattern 21110 when the third initialization signal line bridging pattern 21110 is provided in one of the sub-pixels P of a pixel group PP as shown, the width of the third initialization signal line bridging pattern 21110 can be set to, for example, 1.8 um to 3 um, such as 2 um, 2.1 um, 2.2 um, 2.3 um, 2.4 um, 2.5 um, 2.6 um, 2.7 um, 2.8 um, 2.9 um, 3 um, so as to compensate for the writing ability of the third initialization signal line Vinit3.

[0189] In some embodiments, as Figure 45 shown, and with reference to Figure 3 shown, the first active layer 201 further includes active layer patterns of a first transistor T1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The active layer patterns of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 all include active layer channel patterns; the active layer pattern 2018 of the eighth transistor T8 includes an active layer channel pattern 2018-3. In some examples, the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than the aspect ratio of the active layer channel pattern of the first transistor T1; in some examples, the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than the aspect ratio of the active layer channel pattern of the seventh transistor T7; in other examples, the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 is greater than the aspect ratios of the active layer channel patterns of the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0190] Exemplarily, the first transistor T1 is a first reset transistor, the second transistor T2 is a compensation transistor, the third transistor T3 is a driving transistor, the fourth transistor T4 is a writing transistor, the fifth transistor T5 is a first light-emitting control transistor, the sixth transistor T6 is a second light-emitting control transistor, the seventh transistor T7 is a second reset transistor, and the eighth transistor T8 is a third reset transistor.

[0191] The aspect ratio of a transistor is the ratio of the width to the length of the conductive channel of the transistor. The larger the aspect ratio, the larger the on-state current value Id passing through the transistor when the transistor is turned on. That is, the aspect ratio is proportional to the on-state current value Id. The aspect ratio of a transistor reflects the on-state ability of the transistor, that is, the signal writing ability.

[0192] Exemplarily, as Figure 10 shown, the aspect ratios of the active layer channel patterns of the transistors in the sub-pixel P may be the same, and the aspect ratios may be 2 / 4; in order to compensate for the writing ability of the third initialization signal line Vinit3 when the third initialization signal line bridging pattern 21110 is provided in one of the sub-pixels P of a pixel group PP as Figure 45 shown, the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 may be increased so that the signal writing ability of the eighth transistor T8 is enhanced, while the aspect ratios of the active layer channel patterns of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 remain unchanged; the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 may be 2.4 / 4, for example.

[0193] The first transistor T1, the eighth transistor T8, and the seventh transistor T7 are all reset transistors and all implement the reset function. By setting the aspect ratio of the active layer channel pattern 2018-3 of the eighth transistor T8 to be greater than the aspect ratio of the active layer channel pattern of the first transistor T1 and greater than the aspect ratio of the active layer channel pattern of the seventh transistor T7, and improving the signal writing ability of the eighth transistor T8, the writing abilities of the initialization signals of the three reset transistors can be ensured to be consistent, the uniformity of the corresponding node potentials of the pixel driving circuit can be improved, and the influence of the setting of the third initialization signal line bridging pattern 21110 on the reset function of the eighth transistor T8 can be avoided.

[0194] In some embodiments, as Figure 3 shown, the pixel driving circuit 10 further includes a compensation transistor, that is, the second transistor T2, and the signal line further includes a first power supply signal line VDD; as Figure 36 shown, the driving circuit layer 200 of the display panel 1000 further includes a second active layer 207 provided between the first active layer 201 and a specified gate metal layer 2001, such as the third gate metal layer 209, and a second source-drain metal layer 214 provided on the side of the first source-drain metal layer 211 away from the substrate 100; as Figure 22 shown, the second active layer 207 includes a compensation transistor, that is, the active layer pattern 2071 of the second transistor T2; as Figure 36 shown, the second source-drain metal layer 214 includes a first power supply signal line pattern 2141 of the first power supply signal line VDD. The first power supply signal line pattern 2141 includes a block pattern 2141-1, and the orthographic projection of the active layer pattern 2071 of the compensation transistor, that is, the second transistor T2, on the substrate 100 is located within the orthographic projection of the block pattern 2141-1 of the first power supply signal line pattern 2141 on the substrate 100.

[0195] Exemplarily, as Figure 36As shown, the positive projection of the active layer pattern 2071 of the second transistor T2 on the substrate 100 is located within the positive projection of the block pattern 2141-1 of the first power supply signal line pattern 2141 on the substrate 100. That is to say, the area of the block pattern 2141-1 of the first power supply signal line pattern 2141 is larger than the area of the active layer pattern 2071 of the second transistor T2, and the block pattern 2141-1 of the first power supply signal line pattern 2141 is located above the active layer pattern 2071 of the second transistor T2 and can cover the active layer pattern 2071 of the second transistor T2 in the direction perpendicular to the substrate 100. The block pattern 2141-1 of the first power supply signal line pattern 2141 can be used to block the light entering the display panel 1000 from nature for the active layer pattern 2071 of the second transistor T2, preventing the properties of the material of the active layer pattern 2071 of the second transistor T2 from changing under the influence of natural light and affecting the performance of the display panel 1000.

[0196] In some embodiments, as Figure 36 shown, the first power supply signal line pattern 2141 further includes a strip pattern 2141-2 connected to the block pattern 2141-1, and the width of the strip pattern 2141-2 is 3.5um to 5um.

[0197] Exemplarily, the strip pattern 2141-2 of the first power supply signal line pattern 2141 is mainly used to transmit the first power supply signal. In order to reduce the impedance of the strip pattern 2141-2, the width of the strip pattern 2141-2 can be set to 3.5um to 5um, such as 3.5um, 3.6um, 3.7um, 3.8um, 3.9um, 4um, 4.1um, 4.2um, 4.3um, 4.4um, 4.5um, 4.6um, 4.7um, 4.8um, 4.9um, 5um.

[0198] Exemplarily, as Figure 36 shown, the strip pattern 2141-2 can be set to two, and the two strip patterns 2141-2 are respectively connected to the block pattern 2141-1, and the strip patterns 2141-2 are symmetric. This setting can ensure simultaneous power supply, which is beneficial to improving the flatness of the display panel 1000 and reducing color deviation.

[0199] In some embodiments, as Figure 3 shown, the pixel driving circuit 10 further includes a driving transistor, that is, the third transistor T3. As Figure 16 shown, the first active layer 201 includes a driving transistor, that is, the active layer pattern 2013 of the third transistor T3; as Figure 17As shown, the driving circuit layer 200 of the display panel 1000 further includes a bottom metal layer 219 disposed on the side of the first active layer 201 close to the substrate 100; the bottom metal layer 219 includes a bottom metal protection pattern 2191, and the active layer pattern 2013 of the driving transistor, i.e., the third transistor T3, is located within the orthographic projection of the bottom metal protection pattern 2191 on the substrate 100; the bottom metal protection pattern 2191 is connected to the first power signal line pattern 2141 of the second source-drain metal layer 214.

[0200] Exemplarily, as Figure 16 shown, the active layer pattern 2013 of the third transistor T3 includes a first pole pattern 2013-1 of the active layer, an active layer channel pattern 2013-3, and a second pole pattern 2013-2 connected in sequence; as Figure 17 shown, the orthographic projection of the active layer pattern 2013 of the third transistor T3 on the substrate 100 is located within the orthographic projection of the bottom metal protection pattern 2191 on the substrate 100. That is to say, the bottom metal protection pattern 2191 is located below the active layer pattern of the third transistor T3 and can cover the active layer pattern of the third transistor T3 in the direction perpendicular to the substrate 100, and the bottom metal protection pattern 2191 is connected to the first power signal line pattern 2141 of the second source-drain metal layer 214. This setting can protect the third transistor T3 and prevent impurities in the lower layer from moving up to affect the performance of the third transistor T3. At the same time, the bottom metal protection pattern 2191 is connected to the first power signal line pattern 2141. For example, the bottom metal protection pattern 2191 and the first power signal line pattern 2141 are connected through vias in the peripheral area BB of the display panel 1000. After the signal is turned on, the bottom metal protection pattern 2191 and the active layer pattern of the third transistor T3 form a balanced electric field, making the channel electric field of the active layer channel pattern of the third transistor T3 more stable and not easily interfered by the electric field at the bottom of the display panel 1000.

[0201] In some embodiments, as Figure 42 shown, the display panel 1000 further includes an anode layer 301 disposed on the side of the second source-drain metal layer 214 away from the substrate 100; the anode layer 301 includes a first anode 3011 and a second anode 3012. The first anode 3011 is connected to the pixel driving circuit 10 of a sub-pixel P in the pixel group PP, and the second anode 3012 is connected to the pixel driving circuit 10 of another sub-pixel P' in the pixel group PP; the first anode 3011 is disposed above the block pattern 2141-1 of the first power signal line pattern 2141, and the overlapping area between the first anode 3011 and the block pattern 2141-1 accounts for a ratio greater than a set threshold of the area of the first anode 3011.

[0202] Exemplarily, the first anode 3011 is disposed above the block pattern 2141-1 of the first power signal line pattern 2141. The overlapping area between the first anode 3011 and the block pattern 2141-1 accounts for a ratio greater than a set threshold of the area of the first anode 3011. The set threshold is, for example, 60%. This can ensure the flatness of the first anode 3011, improve the uniformity of the sub-pixels P of the display panel 1000, and improve the manufacturing yield of the display panel 1000.

[0203] It should be noted that the "set threshold" can be set according to the actual product process, and the present disclosure does not make a setting. The above-mentioned "set threshold is, for example, 60%" is only an exemplary value, and the set threshold is not necessarily 60%.

[0204] In some embodiments, as Figure 46 shown, the substrate 100 includes at least two layers of flexible substrates 101 and at least two layers of buffer layers 102.

[0205] Exemplarily, when manufacturing the display panel 1000, a glass carrier is usually disposed below the substrate 100.

[0206] Exemplarily, the material of the buffer layer 102 can be, for example, silicon nitride and / or silicon oxide. The silicon nitride material has good denseness, which can prevent metal ions of the glass carrier below the substrate 100 from diffusing into the active layer region; the silicon oxide material has good insulation, which can avoid the influence of static electricity outside the display panel 1000 on the pixel driving circuit 10 inside the display panel 1000; and the silicon oxide material has good heat insulation, which can reduce the heat conduction rate and help form larger crystal grains; it plays a role in absorbing heat during the subsequent laser lift-off of the glass carrier and blocks the penetration of heat to the film layer on the substrate 100; at the same time, when the substrate 100 includes at least two layers of flexible substrates 101 and at least two layers of buffer layers 102, it can better protect the bottom of the display panel 1000 and reduce the influence of small particles or small dust, preventing small particles or small dust from entering the display panel 1000 from below.

[0207] On the other hand, a display device 10000 is provided, as Figure 47 shown, including the display panel 1000 described in any of the above embodiments.

[0208] Exemplarily, the display device 10000 can display images, for example, it can display static images or dynamic images, etc.

[0209] Exemplarily, the display device 10000 may be (but is not limited to) a mobile phone, a wireless device, a personal digital assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automotive display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a building structure, a packaging, and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc.

[0210] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0211] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, thinking of variations or substitutions, should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that: The method comprises a plurality of sub-pixels, wherein the plurality of sub-pixels are arranged into a plurality of rows along a first direction, and two adjacent sub-pixels in a row of the sub-pixels are regarded as a pixel group; a sub-pixel in the plurality of sub-pixels comprises a pixel driving circuit, the pixel driving circuit is coupled to at least one signal line, the pixel driving circuit comprises a designated transistor, the at least one signal line comprises a designated signal line, and the designated transistor is coupled to the designated signal line; The display panel comprises: substrate; A first active layer disposed on one side of the substrate, the first active layer comprising an active layer pattern of the designated transistor, the active layer pattern of the designated transistor comprising an active layer first electrode pattern; in one pixel group, the active layer first electrode pattern of the designated transistor of one sub-pixel is connected to the active layer first electrode pattern of the designated transistor of another sub-pixel; A designated gate metal layer is disposed on a side of the first active layer away from the substrate, the designated gate metal layer includes a designated signal line pattern of the designated signal line; A first source-drain metal layer is arranged on the side of the designated gate metal layer away from the substrate, and the first source-drain metal layer includes a designated signal line bridge pattern; in one of the pixel groups, the designated signal line bridge pattern is located in the area where one of the sub-pixels is located, and the designated signal line bridge pattern is connected to the first electrode pattern of the active layer of the designated transistor of one of the sub-pixels, and is also connected to the designated signal line pattern.

2. The display panel according to claim 1, characterized in that: In one of the pixel groups, the active layer first electrode pattern of the designated transistor of one sub-pixel and the active layer first electrode pattern of the designated transistor of another sub-pixel are connected to a designated connection point, and the designated signal line bridge pattern is connected to the designated connection point.

3. The display panel according to claim 2, characterized in that: In one of the pixel groups, the active layer patterns of the designated transistors of the two sub-pixels are mirror-symmetrical, and the designated connection point is located on the mirror-symmetrical axis of the active layer pattern of the designated transistors of the two sub-pixels; the designated signal line pattern extends along the first direction and passes through the areas where the two sub-pixels are located.

4. The display panel according to any one of claims 1 to 3, characterized in that: The width of the designated signal line bridge pattern is greater than a set width.

5. The display panel according to any one of claims 1 to 3, characterized in that: The pixel driving circuit further includes other transistors except the designated transistor; The first active layer further includes an active layer pattern of the other transistors; the active layer pattern of the other transistors includes an active layer channel pattern; The active layer pattern of the designated transistor includes an active layer channel pattern, and a width-to-length ratio of the active layer channel pattern of the designated transistor is greater than a width-to-length ratio of the active layer channel pattern of the other transistors.

6. The display panel according to any one of claims 1 to 3, characterized in that: The designated transistor includes a third reset transistor, the designated signal line includes a third initialization signal line, and the third reset transistor is coupled to the third initialization signal line; The first active layer includes an active layer pattern of the third reset transistor, and the active layer pattern of the third reset transistor includes an active layer first electrode pattern; The designated gate metal layer includes a third initialization signal line pattern of the third initialization signal line; The designated signal line bridge pattern includes a third initialization signal line bridge pattern, and the first source-drain metal layer includes the third initialization signal line bridge pattern.

7. The display panel according to claim 6, characterized in that: The signal line also includes a first initialization signal line; The designated gate metal layer further includes a first initialization signal line pattern of the first initialization signal line; the first initialization signal line pattern extends along the first direction and passes through an area where two sub-pixels in one pixel group are located; The third initialization signal line bridge pattern overlaps with the first initialization signal line pattern.

8. The display panel according to claim 6, characterized in that: The pixel driving circuit further includes a compensation transistor, the signal line further includes a first power signal line; and the display panel further includes: a second active layer disposed between the first active layer and the designated gate metal layer; the second active layer comprising an active layer pattern of the compensation transistor; A second source-drain metal layer is arranged on a side of the first source-drain metal layer away from the substrate; the second source-drain metal layer includes a first power signal line pattern of the first power signal line, the first power signal line pattern includes a block pattern, and the orthographic projection of the active layer pattern of the compensation transistor on the substrate is located within the orthographic projection of the block pattern of the first power signal line pattern on the substrate.

9. The display panel according to claim 8, characterized in that: The first power signal line pattern further includes a stripe pattern connected to the block pattern, and the width of the stripe pattern is 3.5 um to 5 um.

10. The display panel according to claim 8 or 9, characterized in that: The pixel driving circuit further includes a driving transistor, and the first active layer includes an active layer pattern of the driving transistor; The display panel further includes: A bottom metal layer is arranged on the side of the first active layer close to the substrate; the bottom metal layer includes a bottom metal protection pattern, and the orthographic projection of the active layer pattern of the driving transistor on the substrate is located within the orthographic projection of the bottom metal protection pattern on the substrate; the bottom metal protection pattern is connected to the first power signal line pattern of the second source and drain metal layer.

11. The display panel according to claim 8 or 9, characterized in that: The display panel further includes: an anode layer disposed on a side of the second source-drain metal layer away from the substrate; The anode layer includes a first anode and a second anode, the first anode is connected to the pixel driving circuit of one of the sub-pixels in the pixel group, and the second anode is connected to the pixel driving circuit of another sub-pixel in the pixel group; The first anode is disposed above the block pattern of the first power signal line pattern, and a ratio of an overlapping area of ​​the first anode and the block pattern to an area of ​​the first anode is greater than a set threshold.

12. The display panel according to any one of claims 1 to 3, characterized in that: The substrate includes at least two flexible base layers and at least two buffer layers.

13. A display device, characterized in that: It comprises the display panel as claimed in any one of claims 1 to 12.

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