Display panel and display device
By setting a virtual shift register in the display panel of the folded product and processing the start control signal, the problem of display differences at the fold is solved, and the uniformity of display brightness and the improvement of display effect is achieved.
Patent Information
- Application Number
- CN202422116636.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-08-29
AI Technical Summary
When the full screen of the folded product is displayed, obvious differences are easily formed at the folding point, such as black lines or brightness differences, resulting in poor display.
A display panel is designed, including at least two sets of gate driving circuits and a plurality of pixels. By setting a virtual shift register before the first stage shift register of the second gate driving circuit group, the start control signal transmitted by the external driving chip is processed to ensure that the signal waveforms received by all shift registers are consistent.
Effectively reduce or prevent waveform differences caused by different driving signal sources of GOA at the connection between groups, avoid obvious differences in pixel brightness, ensure uniform display brightness at folded positions, and reduce poor display problems caused by display differences.
Smart Images
Figure CN223038585U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art
[0002] With the rapid development of movable products (such as mobile phones, smart tablets, etc.), various forms of products have emerged on the market, among which folding products are becoming increasingly popular. For folding products, full-screen display is required when unfolded, and partial display is required after folding. In order to save power consumption in the folded state, generally, the GOA (Gate Driver on Array) is grouped with the folding position as the boundary.
[0003] However, for the folding products with grouped control, when in full-screen display, obvious differences often occur at the folding position, such as forming black lines or causing obvious brightness differences, etc., thus resulting in poor display. Summary of the Utility Model
[0004] In view of this, the present application provides a display panel and a display device to solve or partially solve the above problems.
[0005] Based on the above object, in a first aspect, the present application provides a display panel, including: at least two groups of gate driving circuits and a plurality of pixels arranged in an array;
[0006] The gate driving circuit includes: a first gate driving circuit group and a second gate driving circuit group, and the first gate driving circuit group and the second gate driving circuit group are arranged in sequence along a first direction;
[0007] The first gate driving circuit group and the second gate driving circuit group are used to respond to a start control signal of an external driving chip to control the display of the plurality of pixels; both the first gate driving circuit group and the second gate driving circuit group include multiple stages of shift registers;
[0008] The multiple stages of shift registers are connected to the plurality of pixels, and the multiple stages of shift registers are cascaded;
[0009] The second gate driving circuit group further includes at least one stage of virtual shift register; the virtual shift register is connected to the external driving chip and is connected to the first-stage shift register of the second gate driving circuit group;
[0010] The virtual shift register responds to the start control signal of the external driving chip to provide a cascading signal to the first-stage shift register of the second gate driving circuit group.
[0011] In some exemplary embodiments, the second gate driving circuit group includes two - stage or three - stage virtual shift registers, wherein the two - stage or three - stage virtual shift registers are connected in cascade.
[0012] In some exemplary embodiments, the output signal line of the virtual shift register is connected to the compensation line.
[0013] In some exemplary embodiments, the compensation line extends in a first direction.
[0014] In some exemplary embodiments, the orthographic projection of the compensation line on the substrate of the display panel is located between the orthographic projection of the second gate driving circuit group on the substrate and the orthographic projection of the display area of the display panel on the substrate.
[0015] In some exemplary embodiments, it further includes: a plurality of first reset signal lines and a plurality of first initial signal lines, and at least one pixel is respectively connected to the first reset signal line and the first initial signal line;
[0016] At least one pixel includes: a pixel driving circuit, and the pixel driving circuit of at least one pixel includes: a first reset transistor, and the first reset transistor is respectively connected to the first reset signal line and the first initial signal line connected to the pixel where it is located;
[0017] The output control signal line of at least one - stage shift register is connected to the first reset signal line connected to at least one row of pixel driving circuits.
[0018] In some exemplary embodiments, it further includes: a plurality of first scan signal lines, and at least one pixel is connected to the first scan signal line;
[0019] At least one pixel includes: a pixel driving circuit, and the pixel driving circuit of at least one pixel includes: a compensation transistor, and the compensation transistor is connected to the first scan signal line connected to the pixel where it is located;
[0020] The output control signal line of at least one - stage shift register is connected to the first scan signal line connected to at least one row of pixel driving circuits.
[0021] In some exemplary embodiments, it further includes: a plurality of second scan signal lines and a plurality of data signal lines, and at least one pixel is respectively connected to the second scan signal line and the data signal line;
[0022] At least one pixel includes: a pixel driving circuit, and the pixel driving circuit of at least one pixel includes: a data writing transistor, and the data writing transistor is respectively connected to the second scan signal line and the data signal line connected to the pixel where it is located;
[0023] The output control signal line of at least one - stage shift register is connected to the second scan signal line connected to at least one row of pixel driving circuits.
[0024] In some exemplary embodiments, it further includes: a plurality of light - emitting control signal lines, and at least one pixel is connected to the light - emitting control signal lines;
[0025] At least one pixel includes: a pixel driving circuit, and the pixel driving circuit of at least one pixel includes: a light - emitting transistor, and the light - emitting transistor is connected to the light - emitting control signal line connected to the pixel where it is located;
[0026] The output control signal line of at least one - stage shift register is connected to the light - emitting control signal line connected to at least one row of pixel driving circuits.
[0027] Based on the same concept, in a second aspect, the present application further provides a display device, including the display panel described in the first aspect above.
[0028] As can be seen from the above, a display panel and a display device provided by the present application. The display panel includes at least two groups of gate driving circuits and a plurality of pixels arranged in an array. The gate driving circuits include a first gate driving circuit group and a second gate driving circuit group, and the first gate driving circuit group and the second gate driving circuit group are arranged in sequence along a first direction. The first gate driving circuit group and the second gate driving circuit group are configured to respond to a start control signal of an external driving chip to control the display of the plurality of pixels. Both the first gate driving circuit group and the second gate driving circuit group include multiple stages of shift registers. The multiple stages of shift registers are connected to the plurality of pixels, and the shift registers are cascaded. The second gate driving circuit group further includes at least one stage of virtual shift register. The virtual shift register is connected to the external driving chip and is connected to the first stage of the shift register of the second gate driving circuit group. The virtual shift register responds to the start control signal of the external driving chip and provides a cascade signal to the first stage of the shift register of the second gate driving circuit group. By setting a virtual shift register before the first stage of the shift register of the second gate driving circuit group, the start control signal transmitted from the external driving chip is first processed by the virtual shift register and then transmitted to the shift register in the form of a cascade signal. In specific applications, for a solution such as a folding screen with at least two groups of gate driving circuits arranged in the first direction, the shift registers of the second gate driving circuit group at the folding position also receive the cascade signal transmitted from the virtual shift register, rather than the start control signal directly obtained from the external driving chip. This reduces or even prevents the waveform difference of the GOA at the junction between groups caused by different signal sources for driving, and reduces or even prevents the problem of obvious difference in pixel brightness caused thereby, ensuring uniform display brightness at the folding position and reducing or even solving the problem of poor display caused by display difference. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.
[0030] Figure 1 FIG. is a schematic structural diagram of a driving control circuit of an exemplary display panel provided by an embodiment of the present application.
[0031] Figure 2 FIG. is a schematic diagram of the brightness difference of an exemplary display panel provided by an embodiment of the present application.
[0032] Figure 3Schematic diagram of the structure of another exemplary driving control circuit for a display panel provided by an embodiment of the present application.
[0033] Figure 4 Schematic diagram of the structure of another exemplary equivalent pixel driving circuit for a display panel provided by an embodiment of the present application.
[0034] Figure 5 Schematic diagram of the structure of another exemplary driving control circuit for a display panel provided by an embodiment of the present application.
[0035] Figure 6 Schematic diagram of the structure of another exemplary driving control circuit for a display panel provided by an embodiment of the present application. Detailed implementation manners
[0036] In order to make the objectives, technical solutions and advantages of the present utility model clearer and more understandable, the present utility model will be further described in detail below with reference to specific embodiments and the accompanying drawings.
[0037] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meanings understood by those of ordinary skill in the field to which the present application belongs. The "first", "second" and similar terms used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements, objects or method steps appearing before this term cover the elements, objects or method steps listed after this term and their equivalents, without excluding other elements, objects or method steps. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative position relationships, and when the absolute positions of the objects being described change, the relative position relationships may also change accordingly.
[0038] As described in the background technology section, with the rise of foldable smart devices such as foldable mobile phones in the market, more and more attention has been paid to the display effect of foldable screens. In some embodiments, for image display, the corresponding circuit of the image display of the non-foldable screen is directly moved to the foldable screen for use, and the foldable processing is performed only in the folded position. For folding display, the display state before and after folding will change. For example, full-screen display is required when not folded, and only partial display is required after folding. For smart devices that directly apply the corresponding gate drive circuit of the image display of the non-foldable screen, the part that does not need to be displayed can be written to a black screen by controlling Data writing, so as to complete the partial display function in disguise. However, although such a design can achieve partial display, since the GOA and pixels (Pixel) of the non-displayed part are working normally, the power consumption of the IC (Integrated Circuit, driver chip) is no different from that of the full-screen display, and power consumption cannot be saved. Among them, it should be noted that in some embodiments, the gate drive circuit can be a GOA circuit, that is, the gate drive circuit is directly integrated in the array substrate of the display panel. The following embodiments are all described by taking the gate drive circuit as a GOA circuit as an example. Afterwards, in some embodiments, the gate drive circuit may include at least two cascaded shift registers, such as Figure 1 As shown, the gate driving circuit is represented by 110, and 113 is a shift register. In every two adjacent shift registers, the signal input end of the next-stage shift register 113 is electrically connected to the shift output end of the previous-stage shift register 113, and the signal input end of the first-stage shift register 113 is electrically connected to the start signal line STV.
[0039] Thus, in other embodiments, in order to save power consumption in the folded state, for a foldable smart device, the driving circuit of the pixels of the display panel can be controlled by multiple groups of GOAs, which can be based on the folded position (such as Figure 1 The dotted line position shown is the folded position) is used as the boundary to group the circuits. The specific driving circuits can be as follows: Figure 1 As shown, the dotted line is the folded position, above the dotted line is a group of gate drive circuits, which obtain the initial signal through the first start signal line STV1 (STV is Start of Vertical Blanking, input signal terminal or start signal terminal); below is a group of gate drive circuits, which obtain the initial signal through the second start signal line STV2. That is, the GOA is separated at the folded position, and each group of GOA introduces the STV signal to control each part separately.
[0040] However, another problem is found in the above embodiment when it is used, that is, when the full screen is displayed, there is often a more obvious difference in the partition position, such as Figure 2As shown, a black line or the like may be formed, resulting in poor display. When analyzing the defective products, it is found that for the drive circuit design of the folding products, generally, the gate drive circuits are grouped with the folding position as the boundary. For example, Figure 1 As shown, above the folding position is a group of gate drive circuits, which are provided with a start signal through the first start signal line STV1. Below the folding position is a group of gate drive circuits, which are provided with a start signal through the second start signal line STV2. Here, it is assumed that each group of gate drive circuits includes N - stage shift registers cascaded. Then, for a folding product with at least two groups of gate drive circuits arranged in one column, there are at least 2N - stage shift registers in one column, and the folding position is between the two groups, that is, between the N - th stage shift register and the (N + 1)-th stage shift register. Furthermore, the first N - stage shift registers use the signal from the first start signal line STV1, and starting from the (N + 1)-th stage, the second start signal line STV2 is introduced. At this time, for the N - th stage shift register, since it is above the folding position, the output signal of the previous - stage shift register, that is, the cascaded signal, is connected to it. For the (N + 1)-th stage shift register, since it is connected to the second start signal line STV2, and this signal is directly provided by the external drive chip IC, the signal waveforms of the N - th stage shift register and the (N + 1)-th stage shift register are inconsistent, such as the rising edge, falling edge, amplitude of high and low levels, etc. Eventually, it affects the working state of the pixel circuit in the AA area, resulting in differences in brightness (black lines) in the AA area. It can be seen that the reason for this difference is that the output signal waveform of the (N + 1)-th stage shift register directly connected to STV2 is different from the output signal of the N - th stage shift register, thereby affecting the working state of each TFT (Thin Film Transistor) in the pixel circuit and ultimately affecting the pixel current.
[0041] Combined with the above - mentioned actual situation, the embodiment of the present application provides a display panel. By setting a virtual shift register before the first - stage shift register of the second gate drive circuit group, the start control signal transmitted from the external drive chip is first processed by the virtual shift register and then transmitted to the shift register in the form of a cascaded signal. In this way, in specific applications, for a solution such as a folding screen with at least two groups of gate drive circuits arranged in the first direction, the shift registers of the second gate drive circuit group at the folding position also obtain the cascaded signal transmitted from the virtual shift register, rather than the start control signal directly obtained from the external drive chip. Thus, the waveform difference of the GOA at the junction between groups caused by different signal sources of driving is reduced or even prevented, and the problem of obvious difference in pixel brightness caused thereby is reduced or even prevented, ensuring uniform display brightness at the folding position and reducing or even solving the problem of poor display caused by display differences.
[0042] Figure 3 The figure shows a partial structural schematic diagram of a driving circuit of another display panel provided by an embodiment of the present application.
[0043] As Figure 3 shown, the display panel of the embodiment of the present application includes: at least two groups of gate driving circuits 110 and a plurality of pixels 120 arranged in an array; the gate driving circuit 110 includes: a first gate driving circuit group 111 and a second gate driving circuit group 112, and the first gate driving circuit group 111 and the second gate driving circuit group 112 are arranged in sequence along the first direction X; the first gate driving circuit group 111 and the second gate driving circuit group 112 are used to respond to a start control signal of an external driving chip to perform display control on the plurality of pixels 120; both the first gate driving circuit group 111 and the second gate driving circuit group 112 include multiple stages of shift registers 113; the multiple stages of shift registers 113 are connected to the plurality of pixels 120, and the multiple stages of shift registers 113 are cascaded; the second gate driving circuit group 112 further includes at least one stage of virtual shift register 114; the virtual shift register 114 is connected to the external driving chip and is connected to the first-stage shift register 113 of the second gate driving circuit group 112; the virtual shift register 114 responds to the start control signal of the external driving chip to provide a cascading signal to the first-stage shift register 113 of the second gate driving circuit group 112.
[0044] In this embodiment, the gate driving circuit 110 is mainly used to respond to a start control signal STV of an external driving chip IC to perform display control on a plurality of pixels 120. The shift register 113 mainly plays a control role in the gate driving circuit 110, and thus the gate driving circuit 110 may include multiple stages of shift registers. In a more specific scenario, the plurality of pixels 120 may be arranged in an array, and thus the number of stages of shift registers 113 corresponding to the number of rows of pixels 120 is set, and one stage of shift register 113 controls one row of pixels 120. Then, for the multiple stages of shift registers 113, adjacent shift registers 113 may be connected in a cascading manner.
[0045] Afterwards, according to the analysis of the foregoing embodiments, it can be seen that the defect of the display difference is due to the fact that in the adjacent different groups of gate driving circuits, at the folding position, the previous stage shift register 113 belongs to the first gate driving circuit group 111, and the source of the start signal input to this stage shift register 113 is the shift register 113 of the previous stage of this shift register 113, that is, the cascade signal; while the subsequent stage shift register 113 belongs to the second gate driving circuit group 112, that is, the first stage shift register 113 in the second gate driving circuit group 112, and the source of its input start control signal is directly obtained from the external driving chip IC through the second start signal line STV2. This results in a slight difference between the start control signal of the subsequent stage shift register 113 and the start control signal of the previous stage shift register 113 at the folding position (before and after the dash line in the figure). For example, there may be differences in the rising edge, falling edge, and amplitude of the high and low levels, which causes the working states of the TFTs to be inconsistent. Finally, when presented on the pixels, an obvious brightness difference is formed.
[0046] Furthermore, in order to make the output waveforms have no difference, in the display panel solution with multiple groups of gate driving circuits 110, the multiple groups of gate driving circuits 110 arranged in the same direction can be further divided. Among them, the first group of gate driving circuits is the first gate driving circuit group 111, and the subsequent ones are the second gate driving circuit groups 112. Furthermore, the second gate driving circuit group 112 is at least one group, and can also be multiple groups. Among them, the first gate driving circuit group 111 and the second gate driving circuit group 112 can be arranged in the above order along the first direction. Here, the first direction can be the longitudinal direction of the multiple pixels 120 arranged in an array, or the length direction of the display panel in the normal use state (the direction where the longer side of the display panel is located), etc. Furthermore, the transverse direction or the width direction can be the second direction. In Figures 1 to 6 such figures, the first direction is the X direction, and the second direction is the Y direction.
[0047] For the second gate driving circuit group 112, at least one stage of virtual shift register 114 can be set before the multi-stage shift register 113 for pixel control. In this way, the source of the starting control signal of the shift register 113 in the second gate driving circuit group 112 is the previous-stage shift register (whether it is the previous-stage shift register 113 or the virtual shift register 114). Here, the virtual shift register 114 is mainly connected to the external driving chip IC and is also connected to the first-stage shift register 113 in the second gate driving circuit group 112. Its main function is to receive the initial control signal transmitted from the external driving chip IC, act on it, and finally transmit it to the first-stage shift register 113 in the second gate driving circuit group 112 in the form of a cascaded signal. From this, it can be seen that the virtual shift register 114 does not have a corresponding row or several rows of pixels 120, and it is not connected to the pixels 120, but is only used for the processing of the initial control signal.
[0048] Thus, in the specific scenario of the aforementioned folding product, at the folding position, whether it is the Nth-stage shift register 113 (belonging to the previous group of gate driving circuit groups) or the (N + 1)th-stage shift register 113 (belonging to the subsequent group of gate driving circuit groups), the source of its starting control signal is the shift register (whether it is the shift register 113 or the virtual shift register 114). Thus, the difference in the starting control signals of the two is reduced or even eliminated, and finally, this brightness difference can be significantly eliminated. That is, in specific applications, several stages of virtual shift registers 114 (which can be called Dummy GOA) are added before the first-stage shift register 113 of the second gate driving circuit group 112 controlled by the second starting signal line STV2. The outputs of this part of the virtual shift registers 114 are not connected to the display area (AA area), but are directly connected to the next-stage shift register 113.
[0049] In some other more specific scenarios, the same setting can also be made for the display panel with only one group of gate driving circuits 110 according to needs, that is, at least one stage of virtual shift register 114 can also be set before the first-stage shift register 113 of this group of gate driving circuits 110.
[0050] Furthermore, as Figure 3The upper and lower groups of gate driving circuit groups shown above, the upper group is the first gate driving circuit group 111, and the lower group is the second gate driving circuit group 112. In some embodiments, both of these two groups of gate driving circuit groups can be provided with virtual shift registers 114, or only the second gate driving circuit group 112 can be provided with a virtual shift register 114. Among them, for the solution where only the second gate driving circuit group 112 is provided, although the first-stage shift register 113 of the first gate driving circuit group 111 is still directly connected to the external driving chip IC and receives the signal of the first start signal line STV1, since there is no other shift register 113 on it for comparison, there will be no difference. Of course, in some other embodiments, for the first gate driving circuit group 111, at least one stage of virtual shift register 114 can also be provided before the first-stage shift register 113, so that the initial control signals received by all the shift registers 113 in all groups of gate driving circuits are cascaded signals obtained through the conversion of other shift registers, and thus the waveforms of the signals received by all the shift registers 114 tend to be consistent.
[0051] After that, for the virtual shift register 114, since its core function is to provide a qualified cascaded signal for the corresponding shift register 113, the structure of the virtual shift register 114 can be based on the shift register 113, or even the same as the shift register 113, so that its main difference from the shift register 113 is only that it is not connected to the pixel 120.
[0052] In some embodiments, only one stage of virtual shift register 114 can be provided, and it has already produced a relatively obvious effect on solving the brightness difference. However, when only one stage is provided, there are still small differences in the output signal waveforms, which are mainly due to the fact that the virtual shift register 114 is not actually connected to the pixel 120, resulting in a certain difference in the load (Loading) from the shift register 113, and also due to less driving. Therefore, in some scenarios, multiple stages of virtual shift registers 114 can be provided to act on the initial control signal multiple times by using the multiple stages of virtual shift registers 114, so that the cascaded signal obtained by the finally connected first-stage shift register 113 is as close as possible to the control signal waveform of the last-stage shift register 113 of the first gate driving circuit group 111 (in some other embodiments, it may also be the last-stage shift register 113 of the previous group of the second gate driving circuit group 112). More specifically, that is to say, after passing through multiple stages of virtual shift registers 114, the signal waveform of the output cascaded signal gradually tends to be consistent with the output / input signal waveform of the last-stage shift register 113 of the previous group.
[0053] In a more specific scenario, the multi-stage virtual shift register 114 can be set to two or three stages. Of course, more stages of the virtual shift register 114 can also be set according to the specific scenario. After that, for the virtual shift register 114 set to multiple stages, the multiple-stage virtual shift registers 114 can be connected in cascade.
[0054] In a more specific embodiment, as Figure 3 shown, the shift register 113 can be connected to the pixels 120 in the same row through the output control signal line 115, and signal transmission is carried out through the output control signal line 115. Similarly, for at least one stage of the virtual shift register 114, the last stage of the virtual shift register 114 can be connected to the first-stage shift register 113 by using the output signal line 116. Further, as Figure 3 shown, in order to enable the virtual shift register 114 to further simulate the effect of accessing the pixels 120, further load (Loading) compensation can be performed on the output of the virtual shift register 114. Here, a compensation line 117 can be separately set, and the compensation line 117 is connected to the output signal line 116 to extend the cascaded signal output by the virtual shift register 114, so that the cascaded signal needs to pass through the compensation line 117 before reaching the first-stage shift register 113 of the second gate driving circuit group 112. By compensating in this way, the load of the cascaded signal output by the virtual shift register 114 is made consistent with the load of the cascaded signals output by other shift registers 113, and further ensures that the control signal STV of the shift register 113 at the partition position remains the same as that in the normal area, avoiding brightness differences in the display area (AA area) due to this difference. That is, in some embodiments, the output signal line 116 of the virtual shift register 114 is connected to the compensation line 117.
[0055] In some embodiments, the compensation line 117 can be set in any suitable manner. In some more specific scenarios, as Figure 3 shown, the compensation line 117 can be extended and set along the first direction X. And for the setting position of the compensation line 117, it can be specifically between the second gate driving circuit group 112 and the display area (AA area) of the display panel. Since the display area mainly uses the pixels 120 for display, then in the example as Figure 3 shown, the compensation line 117 can be located between the second gate driving circuit group 112 and the pixels 120. More specifically, a reference plane can be set to define the setting position of the compensation line 117. Here, the substrate of the display panel can be used as a reference. Furthermore, the setting position of the compensation line 117 can be: the orthographic projection of the compensation line 117 on the substrate of the display panel is located between the orthographic projection of the second gate driving circuit group 112 on the substrate and the orthographic projection of the display area of the display panel on the substrate.
[0056] In some embodiments, as Figure 3 shown, the first gate driving circuit 110 and at least one group of second gate driving circuits 120 arranged in the same column are connected to a clock signal line CLK for obtaining a clock signal during operation by using the clock signal line CLK.
[0057] In some embodiments, the pixel 120 is generally driven for display by a corresponding pixel driving circuit, that is, one pixel 120 may include a corresponding pixel driving circuit. As Figure 4 shown, it is a schematic structural diagram of an equivalent pixel driving circuit of a display panel pixel. It can be seen that this circuit is a schematic diagram of an 8T1C circuit, where the control electrodes of different transistors (transistors T1 to T8) are connected to their respective control terminals. In a more specific scenario, the control of the shift register 113 can be subdivided into control through multiple control terminals. Taking the Figure 4 8T1C circuit shown as an example, it can be subdivided into five control terminals, namely Reset_H, Reset_P, Gate_N, Gate_P, and EM. Furthermore, the form of the control circuit corresponding to this pixel circuit can be as Figure 5 shown, where the HSTV line corresponds to Reset_H, the PSTV line corresponds to Reset_P, the NSTV line corresponds to Gate_N, the GSTV line corresponds to Gate_P, and the ESTV line corresponds to EM. Furthermore, in some embodiments, the first gate driving circuit group 111 and at least one group of second gate driving circuit groups 112 are provided with at least one column; wherein, each column is used to control at least one transistor in the pixel driving circuits of multiple pixels 120.
[0058] Furthermore, for a display panel including the first gate driving circuit group 111 and at least one group of second gate driving circuit groups 112 such as a folding screen, due to the brightness difference problem clarified in the foregoing embodiments, here it is possible to detect more specifically for different control terminals respectively. Specifically, according to the actual power consumption test, the introduction of HSTV2 by HSTV has little impact on the power consumption. At the same time, because the shift register control corresponding to Reset_H controls the transistor T7 (specifically defined as the second reset transistor T7) for voltage reset of the pixel, at low gray levels, there are differences in Reset_H, resulting in differences in the reset voltage controlled by the second reset transistor T7. The impact of this voltage difference on the brightness is particularly obvious at low gray levels. Therefore, for the partition design scheme, as Figure 5As shown, in some embodiments, the column of gate driving circuits 110 corresponding to Reset_H may not adopt a partitioned design. That is, only the other four groups of gate driving circuits 110 may be partitioned at the partition position, divided into a first gate driving circuit group 111 and at least one second gate driving circuit group 112. Reset_H does not introduce HSTV2, and the first-level shift register 113 at the partition position is directly controlled by the output of the previous-level shift register 113, so that the brightness difference in the display area (AA area) caused by the difference in Reset_H can be avoided. That is to say, for the gate driving circuit 110 corresponding to this transistor, only one group is set, and it only includes a multi-stage shift register 113, without including a virtual shift register 114. After that, for the other column gate driving circuits 110 corresponding to other lines, they can be grouped as Figure 5 shown, grouped (that is, at least two groups of gate driving circuits are set in the same column), and at the same time, virtual shift registers 114 may not be set for the second and subsequent gate driving circuits in the same column. And in order to further improve the effect, virtual shift registers 114 may also be set for the second and subsequent gate driving circuits in the same column. Further, for the gate driving circuits corresponding to other lines, they may also adopt the same setting as the gate driving circuit of Reset_H (that is, not partitioned), so as to improve the display effect. As long as not all of them adopt such a setting, the power consumption can be reduced accordingly on the basis of the first embodiment, achieving a certain power consumption reduction effect. Furthermore, for the gate driving circuit that is not grouped, the transistors it controls, taking Figure 4 as an example, may only correspond to the T7 and T8 transistors corresponding to Reset_H (mainly for controlling the T7 transistor), or may correspond to multiple of the T1 to T8 transistors.
[0059] More specifically, in some embodiments, such as Figure 4 and Figure 5As shown, the display panel may further include a first reset signal line Reset_P and a plurality of first initialization signal lines Vinit1, and at least one pixel 120 is respectively connected to the first reset signal line Reset_P and the first initialization signal line Vinit1; at least one pixel 120 includes: a pixel driving circuit, and the pixel driving circuit of at least one pixel 120 includes: a first reset transistor T1, and the first reset transistor T1 is respectively connected to the first reset signal line Reset_P and the first initialization signal line Vinit1 connected to the pixel 120 where it is located; the output control signal line 115 of at least one stage of shift register 113 is connected to the first reset signal line Reset_P connected to at least one row of pixel driving circuits. That is, the solution of grouping the gate driving circuit 110 as described in the foregoing embodiments and setting the virtual shift register 114 in the second and subsequent groups of gate driving circuits may be set in the control circuit of the first reset transistor T1. That is, it may be set in a column of gate driving circuits connected to the PSTV line.
[0060] In other embodiments, as Figure 4 and Figure 5 shown, the display panel may further include a plurality of first scan signal lines Gate_N, and at least one pixel 120 is connected to the first scan signal line Gate_N; at least one pixel 120 includes: a pixel driving circuit, and the pixel driving circuit of at least one pixel 120 includes: a compensation transistor T2, and the compensation transistor T2 is connected to the first scan signal line Gate_N connected to the pixel 120 where it is located; the output control signal line 115 of at least one stage of shift register 113 is connected to the first scan signal line Gate_N connected to at least one row of pixel driving circuits. That is, the solution of grouping the gate driving circuit 110 as described in the foregoing embodiments and setting the virtual shift register 114 in the second and subsequent groups of gate driving circuits may also be set in the control circuit of the compensation transistor T2. That is, it may be set in a column of gate driving circuits connected to the NSTV line.
[0061] In other embodiments, as Figure 4 and Figure 5As shown, the display panel may further include a plurality of second scan signal lines Gate_P and a plurality of data signal lines Data, and at least one pixel 120 is respectively connected to the second scan signal line Gate_P and the data signal line Data; at least one pixel 120 includes: a pixel driving circuit, and the pixel driving circuit of at least one pixel 120 includes: a data writing transistor T4, and the data writing transistor T4 is respectively connected to the second scan signal line Gate_P and the data signal line Data connected to the pixel 120 where it is located; the output control signal line 115 of at least one stage of shift register 113 is connected to the second scan signal line Gate_P connected to at least one row of pixel driving circuits. That is, the solution of grouping the gate driving circuit 110 as described in the foregoing embodiment and setting the virtual shift register 114 in the second and subsequent groups of gate driving circuits can also be set in the control circuit of the data writing transistor T4. That is, it can be set in a column of gate driving circuits connected to the GSTV line.
[0062] In some other embodiments, as Figure 4 and Figure 5 shown, the display panel may further include a plurality of light emission control signal lines EM, and at least one pixel 120 is connected to the light emission control signal line EM; at least one pixel 120 includes: a pixel driving circuit, and the pixel driving circuit of at least one pixel 120 includes: light emitting transistors (T5 and T6), and the light emitting transistors (T5 and T6) are connected to the light emission control signal line EM connected to the pixel 120 where they are located; the output control signal line 115 of at least one stage of shift register 113 is connected to the light emission control signal line EM connected to at least one row of pixel driving circuits. That is, the solution of grouping the gate driving circuit 110 as described in the foregoing embodiment and setting the virtual shift register 114 in the second and subsequent groups of gate driving circuits can also be set in the control circuit of the light emitting transistors (T5 and T6). That is, it can be set in a column of gate driving circuits connected to the ESTV line.
[0063] Finally, in some other embodiments, according to the description of the previous embodiment, it can be seen that the brightness difference is mainly caused by the difference in the output of the second reset transistor T7 of the pixel circuit controlled by the first stage of the shift register 113 of the second gate driving circuit 112 controlled by the second start signal line STV2 at the grouping position. Furthermore, as Figure 6 shown, the input of the second reset transistor T7 of the pixels 120 in the same row controlled by this stage of the shift register 113 can be controlled separately. For example, as Figure 4 shown, the input Vinit2 of the second reset transistor T7 is controlled separately, such as being controlled by Vinit2_1. That is, in order to compensate for the difference, as Figure 6As shown, by introducing the Vinit2_1 signal to separately control the second reset transistor T7 of the pixel 120 at the partition position, the brightness of the partition position can be controlled by the separately set Vinit2_1 signal, compensating for the problem of brightness difference caused by reset difference, thereby solving the problems of brightness difference and dark line defect.
[0064] As can be seen from the above embodiments, a display panel provided by an embodiment of the present application includes: at least two groups of gate driving circuits and a plurality of pixels arranged in an array; the gate driving circuits include: a first gate driving circuit group and a second gate driving circuit group, and the first gate driving circuit group and the second gate driving circuit group are arranged in sequence along a first direction; the first gate driving circuit group and the second gate driving circuit group are used to respond to a start control signal of an external driving chip to perform display control on the plurality of pixels; both the first gate driving circuit group and the second gate driving circuit group include multiple stages of shift registers; the multiple stages of shift registers are connected to the plurality of pixels, and the multiple stages of shift registers are cascaded; the second gate driving circuit group further includes at least one stage of virtual shift register; the virtual shift register is connected to the external driving chip and is connected to the first stage of shift register of the second gate driving circuit group; the virtual shift register responds to the start control signal of the external driving chip to provide a cascade signal to the first stage of shift register of the second gate driving circuit group. By setting a virtual shift register before the first stage of shift register of the second gate driving circuit group in the present application, the start control signal transmitted from the external driving chip is first processed by the virtual shift register and then transmitted to the shift register in the form of a cascade signal. In this way, in specific applications, for a solution such as a folding screen with at least two groups of gate driving circuits arranged in the first direction, the shift registers of the second gate driving circuit group at the folding position also obtain the cascade signal transmitted from the virtual shift register, rather than the start control signal directly obtained from the external driving chip, thereby reducing or even preventing the waveform difference of the GOA at the connection between groups caused by different signal sources for driving, and reducing or even preventing the problem of obvious difference in pixel brightness caused thereby, ensuring uniform display brightness at the folding position, and reducing or even solving the display defect problem caused by display difference.
[0065] Based on the same concept, the present application further provides a display device including the display panel described in any of the foregoing embodiments.
[0066] The display device of the above embodiment is used to apply the corresponding display panel in the foregoing embodiment and has the beneficial effects of the embodiment of the corresponding display panel, which will not be elaborated herein.
[0067] It is understandable that the display device is a product with an image display function, and generally it is driven by multiple driving circuits. For example, it can be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable video camera, a viewfinder, a navigator, a vehicle, a large-area wall, a household appliance, an information query device (such as a business query device and a monitor in departments such as e-government, banks, hospitals, and power).
[0068] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, and they are not provided in detail for the sake of brevity.
[0069] In addition, for the sake of simplicity of description and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. In addition, the device may be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (that is, these details should be completely within the understanding of those skilled in the art). In the case where specific details (such as circuits) are set forth to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with variations of these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.
[0070] Although the present application has been described in connection with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) can be used in the embodiments discussed.
[0071] The embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application shall be included within the protection scope of the present application.
Claims
1. A display panel, characterized in that: include: At least two groups of gate driving circuits and a plurality of pixels arranged in an array; The gate driving circuit comprises: a first gate driving circuit group and a second gate driving circuit group, wherein the first gate driving circuit group and the second gate driving circuit group are sequentially arranged along a first direction; The first gate driving circuit group and the second gate driving circuit group are used to respond to the start control signal of the external driving chip to perform display control on the plurality of pixels; the first gate driving circuit group and the second gate driving circuit group both include a multi-stage shift register; The multi-stage shift register is connected to the plurality of pixels, and the multi-stage shift registers are cascade-connected; The second gate drive circuit group further includes at least one stage of virtual shift register; the virtual shift register is connected to the external drive chip and is connected to the first stage shift register of the second gate drive circuit group; The virtual shift register provides a cascade signal to the first stage shift register of the second gate driving circuit group in response to a start control signal of the external driving chip.
2. The display panel according to claim 1, characterized in that: The second gate driving circuit group includes two or three stages of virtual shift registers, wherein the two or three stages of virtual shift registers are cascade-connected.
3. The display panel according to claim 1 or 2, characterized in that: The output signal line of the virtual shift register is connected to the compensation line.
4. The display panel according to claim 3, characterized in that: The compensation line extends along a first direction.
5. The display panel according to claim 3, characterized in that: The orthographic projection of the compensation line on the base substrate of the display panel is located between the orthographic projection of the second gate driving circuit group on the base substrate and the orthographic projection of the display area of the display panel on the base substrate.
6. The display panel according to claim 1, characterized in that: Also includes: A plurality of first reset signal lines and a plurality of first initial signal lines, at least one pixel being connected to each of the first reset signal lines and the first initial signal lines; At least one pixel comprises: a pixel driving circuit, wherein the pixel driving circuit of at least one pixel comprises: a first reset transistor, wherein the first reset transistor is respectively connected to a first reset signal line and a first initial signal line connected to the pixel; The output control signal line of at least one stage of the shift register is connected to the first reset signal line connected to at least one row of pixel driving circuits.
7. The display panel according to claim 1, characterized in that: Also includes: A plurality of first scanning signal lines, at least one pixel being connected to the first scanning signal line; At least one pixel comprises: a pixel driving circuit, and the pixel driving circuit of at least one pixel comprises: a compensation transistor, and the compensation transistor is connected to a first scanning signal line connected to the pixel; The output control signal line of at least one stage of the shift register is connected to the first scanning signal line connected to at least one row of pixel driving circuits.
8. The display panel according to claim 1, characterized in that: Also includes: A plurality of second scanning signal lines and a plurality of data signal lines, at least one pixel being connected to the second scanning signal line and the data signal line respectively; At least one pixel comprises: a pixel driving circuit, and the pixel driving circuit of at least one pixel comprises: a data writing transistor, wherein the data writing transistor is respectively connected to a second scanning signal line and a data signal line connected to the pixel; The output control signal line of at least one stage of the shift register is connected to the second scanning signal line connected to at least one row of pixel driving circuits.
9. The display panel according to claim 1, characterized in that: Also includes: A plurality of light emitting control signal lines, at least one pixel being connected to the light emitting control signal line; At least one pixel comprises: a pixel driving circuit, and the pixel driving circuit of at least one pixel comprises: a light emitting transistor, and the light emitting transistor is connected to a light emitting control signal line connected to the pixel; The output control signal line of at least one stage of the shift register is connected to the light emitting control signal line connected to at least one row of pixel driving circuits.
10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.