Solar cell and photovoltaic module

Abstract

The utility model discloses a solar cell and a photovoltaic module. The solar cell includes: a silicon substrate; the semiconductor layer is arranged on the surface of the silicon substrate; the first passivation layer is arranged on the side, away from the silicon substrate, of the semiconductor layer; the transparent conductive layer is made of a transparent conductive compound and comprises a first transparent conductive sub-layer and a second transparent conductive sub-layer, the first transparent conductive sub-layer is arranged on the surface, deviating from the silicon substrate, of the semiconductor layer, and the first transparent conductive sub-layer is filled in a hollow-out area which is not covered by the graphical area of the first passivation layer, and the second transparent conductive sub-layer is arranged on the surface, deviating from the silicon substrate, of the semiconductor layer. The second transparent conductive sub-layer covers the first transparent conductive sub-layer and the surface, deviating from the silicon substrate, of the first passivation layer, and the width of the second transparent conductive sub-layer is 150-400 [mu] m; and the copper grid line is arranged on one surface, deviating from the semiconductor layer, of the transparent conductive layer, and the width of the copper grid line is 5-100 microns.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Copper is a common material for making solar cell grid lines. In solar cells, a barrier layer is generally set to isolate the copper grid lines from the polysilicon layer to prevent the copper grid lines from directly contacting the polysilicon layer to cause diffusion and adverse reactions, thereby causing leakage problems.

[0003] At present, aluminum, its alloys, nickel and other metal materials are generally used as barrier layers. Due to the large comprehensive tolerance of the film opening process and the printing mask for the identification of the reference points, this problem seriously restricts the accuracy of copper grid line production, especially when producing copper grid lines with a width of 100μm and below, the difficulty is significantly increased. Summary of the invention

[0004] In order to achieve the above-mentioned purpose, the present invention discloses a solar cell and a photovoltaic module, in which the accuracy and efficiency of copper grid lines in the solar cell are significantly improved, which is conducive to providing copper grid lines with high reliability and a width of 100μm or less, thereby improving the refinement of the copper grid lines.

[0005] In a first aspect, an embodiment of the present invention provides a solar cell.

[0006] A solar cell comprising:

[0007] Silicon substrate;

[0008] A semiconductor layer, wherein the semiconductor layer is disposed on a surface of the silicon substrate;

[0009] A patterned first passivation layer, wherein the first passivation layer is disposed on a side of the semiconductor layer away from the silicon substrate;

[0010] A transparent conductive layer, wherein the material of the transparent conductive layer is a transparent conductive compound, and the transparent conductive layer includes a first transparent conductive sublayer and a second transparent conductive sublayer, wherein the first transparent conductive sublayer is disposed on a surface of the semiconductor layer away from the silicon substrate, and the first transparent conductive sublayer is filled in a hollow area not covered by a patterned area of ​​the first passivation layer, and the second transparent conductive sublayer covers the first transparent conductive sublayer and a surface of the first passivation layer away from the silicon substrate, and the width of the second transparent conductive sublayer is 150 μm to 400 μm;

[0011] The copper grid line is arranged on a side of the transparent conductive layer away from the semiconductor layer, and the width of the copper grid line is 5 μm to 100 μm.

[0012] As an alternative embodiment, in the embodiments of the present invention, the width of the copper gate line is 5 μm to 20 μm.

[0013] As an alternative embodiment, in the embodiments of the present invention, the light transmittance of the transparent conductive layer is greater than or equal to 85%, and the sheet resistance is 50 Ω / sq to 200 Ω / sq; and / or, the transparent conductive compound is one or a combination of indium tin oxide, indium titanium oxide, indium zinc oxide, aluminum zinc oxide, niobium aluminum oxide, lanthanum aluminate, and tin fluoride oxide.

[0014] As an alternative embodiment, in the embodiments of the present invention, the thickness of the second transparent electron-conducting layer is 50 nm to 200 nm.

[0015] As an alternative embodiment, in the embodiments of the present invention, the solar cell is a passivated contact solar cell. The semiconductor layer includes a P-type semiconductor layer disposed on the first surface of the silicon substrate and an N-type semiconductor layer disposed on the second surface of the silicon substrate. One of the first surface and the second surface is the light-receiving surface, and the other is the backlight surface;

[0016] A first dielectric layer is disposed between the silicon substrate and the P-type semiconductor layer, and a second dielectric layer is disposed between the silicon substrate and the N-type semiconductor layer. The thicknesses of the first dielectric layer and the second dielectric layer are 0.8 nm to 2.5 nm;

[0017] The first passivation layer and the transparent conductive layer are simultaneously disposed on the sides of the P-type semiconductor layer and the N-type semiconductor layer facing away from the silicon substrate, and the second transparent electron-conducting layer entirely or partially covers the surfaces of the first transparent electron-conducting layer and the first passivation layer facing away from the silicon substrate.

[0018] As an alternative embodiment, in the embodiments of the present invention, the solar cell is a back-contact solar cell. The semiconductor layer includes a P-type semiconductor layer and an N-type semiconductor layer arranged in a finger-crossed manner, and the transparent conductive layers on the surfaces of the P-type semiconductor layer and the N-type semiconductor layer are insulated from each other.

[0019] As an alternative embodiment, in the embodiments of the present invention, a first dielectric layer is disposed between the silicon substrate and the P-type semiconductor layer, and a second dielectric layer is disposed between the silicon substrate and the N-type semiconductor layer. The first dielectric layer and the second dielectric layer are insulated from each other.

[0020] As an alternative embodiment, in the embodiments of the present invention, the thickness of the copper gate line is 10 μm to 25 μm.

[0021] As an alternative embodiment, in the embodiments of the present invention, the width of the hollowed-out area is 10 μm to 40 μm; and / or, the height of the hollowed-out area is 0.05 μm to 0.5 μm.

[0022] As an alternative embodiment, in the embodiments of the present invention, a protective layer is provided on the surface of the copper grid line, and the thickness of the protective layer is 0.1 μm to 3.0 μm.

[0023] As an alternative embodiment, in the embodiments of the present invention, the material of the protective layer is one or a combination of tin, tin alloy, silver, and silver alloy.

[0024] As an alternative embodiment, in the embodiments of the present invention, the semiconductor layer is a doped polysilicon layer; and / or, the first passivation layer includes a stacked silicon oxide layer and a silicon nitride layer, the thickness of the silicon oxide layer is 25 nm to 35 nm, and the thickness of the silicon nitride layer is 40 nm to 70 nm; and / or, the silicon substrate is a P-type silicon wafer or an N-type silicon wafer.

[0025] In a second aspect, embodiments of the present invention provide a photovoltaic module.

[0026] A photovoltaic module includes a solar cell as mentioned in the first aspect.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] In the present invention, a transparent conductive layer composed of a transparent conductive compound is used as a barrier layer to isolate the copper grid line and the semiconductor layer through the transparent conductive layer. The risk of copper elements in the copper grid line transferring to the semiconductor layer by thermal migration or electromigration is lower. Therefore, it can better reduce the possibility of leakage of the solar cell. Moreover, in this application, the width of the second transparent conductive sub-layer is set between 150 μm and 400 μm. This width setting can better shield the recognition tolerance brought by the pattern recognition device during the printing mask process, which enables the width of the copper grid line not to be set above 100 μm to obtain a better contact effect among the doped polysilicon layer, the transparent conductive layer, and the copper grid line. Also, because the transparent conductive layer has a higher transparency compared with common barrier layer materials (such as nickel or aluminum, etc.), it is beneficial for light to pass through. Setting the width of the copper grid line to 5 μm to 100 μm can reduce the shading area caused by the copper grid line and improve the light utilization rate in the solar cell. Description of the Drawings

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0030] Figure 1 is a schematic structural diagram of a solar cell disclosed in an embodiment of the present invention;

[0031] Figure 2 is a schematic structural diagram of a solar cell including a second transparent conductive electron layer disclosed in an embodiment of the present invention;

[0032] Figure 3 is another schematic structural diagram of a solar cell including a second transparent conductive electron layer disclosed in an embodiment of the present invention.

[0033] Reference numerals: 1, silicon substrate; 211, first dielectric sublayer; 212, second dielectric sublayer; 22, semiconductor layer; 221, N-type semiconductor layer; 222, P-type semiconductor layer; 3, first passivation layer; 31, first passivation sublayer; 32, second passivation sublayer; 4, transparent conductive layer; 41, first transparent conductive electron layer; 42, second transparent conductive electron layer; 5, copper grid line; 51, negative electrode copper grid line; 52, positive electrode copper grid line; 6, second passivation layer. Detailed implementation manners

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0035] In the present invention, terms such as "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit that the indicated device, element or component must have a specific orientation, or be constructed and operated in a specific orientation.

[0036] Moreover, in addition to being able to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0037] In addition, terms such as "installed", "set", "provided with", "connected", and "linked" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there can be internal communication between two devices, components, or parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] In addition, terms such as "first", "second", etc. are mainly used to distinguish different devices, components, or parts (the specific types and structures may be the same or different), and do not indicate or imply the relative importance and quantity of the indicated devices, components, or parts. Unless otherwise specified, the meaning of "a plurality" is two or more.

[0039] When preparing a back-contact solar cell or a passivated-contact solar cell, the surface of the silicon wafer includes a doped polysilicon layer and a passivation layer arranged in a stack. Generally, it is necessary to perform a film-opening treatment on the passivation layer to expose the underlying doped polysilicon layer, so that the subsequently prepared grid lines form an ohmic contact with the doped polysilicon layer. When the grid line material is mainly made of copper, it is usually necessary to first deposit a metal material such as aluminum and its alloy, nickel, etc. as a barrier layer, deposit a seed layer on the barrier layer, then form a patterned mask layer on the surface of the seed layer through a printing mask, and then deposit a copper layer in the electroplating area to be electroplated without the mask layer covering through an electrochemical deposition method. Finally, the mask layer, the seed layer and the barrier layer under the mask layer are removed by chemical reagents, thus completing the preparation of the copper grid lines.

[0040] During the above film-opening treatment and printing mask, it is necessary to use a patterning device (such as a ccd image sensor) to identify the same reference point to determine the relevant operation positions. Currently, the pattern recognition tolerance of the patterning device is between 15 μm and 30 μm. The film-opening treatment and printing mask together require two identifications of the reference point, and the combined tolerance of these two reference point identifications is likely to exceed 50 μm. Currently, the width of the hollowed-out area formed by the film-opening treatment is generally set to be between 10 μm and 40 μm. Due to the large recognition tolerance of the patterning device, in order to ensure a better contact between the barrier layer, the copper grid lines and the doped polysilicon layer, so that the doped polysilicon layer, the barrier layer and the copper grid lines are connected and form a good conductive effect. Related technologies usually set the width of the copper grid lines to be above 100 μm to effectively shield the above recognition tolerance, and the width of the barrier layer is usually set to be the same as that of the copper grid lines to avoid further increasing the light-shielding area. However, the currently produced grid lines still have a large light-shielding area and high costs, which is not conducive to further improving the performance and efficiency of solar cells.

[0041] To overcome this technical problem, the present invention provides a solar cell and a photovoltaic module.

[0042] The technical solution of the present invention will be further described below in conjunction with embodiments and drawings.

[0043] Referring to Figure 1 , in a first aspect, an embodiment of the present invention provides a solar cell.

[0044] A solar cell includes:

[0045] A silicon substrate 1;

[0046] A semiconductor layer 22, which is disposed on the surface of the silicon substrate 1;

[0047] A patterned first passivation layer 3, which is disposed on the side of the semiconductor layer 22 away from the silicon substrate 1;

[0048] A transparent conductive layer 4, the material of the transparent conductive layer 4 is a transparent conductive compound. The transparent conductive layer 4 includes a first transparent conductive sub-layer 41 and a second transparent conductive sub-layer 42. The first transparent conductive sub-layer 41 is disposed on the surface of the semiconductor layer 22 away from the silicon substrate 1, and the first transparent conductive sub-layer 41 fills the hollow area not covered by the patterned area of the first passivation layer 3. The second transparent conductive sub-layer 42 covers the first transparent conductive sub-layer 41 and the surface of the first passivation layer 3 away from the silicon substrate 1, and the width of the second transparent conductive sub-layer 42 is 150 μm to 400 μm;

[0049] Copper grid lines 5, which are disposed on the side of the transparent conductive layer 4 away from the semiconductor layer 22, and the width of the copper grid lines 5 is 5 μm to 100 μm.

[0050] In the present invention, the transparent conductive layer 4 composed of a transparent conductive compound is used as a barrier layer. The copper grid lines 5 and the semiconductor layer 22 are isolated by the transparent conductive layer 4, and the risk of copper elements in the copper grid lines 5 transferring to the semiconductor layer 22 through thermal migration or electromigration is lower. Therefore, the possibility of solar cell leakage can be better reduced. Moreover, in this application, the width of the second transparent conductive sub-layer 42 is set between 150 μm and 400 μm. This width setting can better shield the recognition tolerance brought by the recognition reference points of the patterning equipment during the printing mask process, which enables the width of the copper grid lines 5 not to be set above 100 μm, and a better contact effect can also be obtained between the doped polysilicon layer, the transparent conductive layer 4, and the copper grid lines 5. Also, because the transparent conductive compound used in the transparent conductive layer 4 has higher transparency compared with common barrier layer materials (such as nickel or aluminum, etc.), which is beneficial to light transmission. Setting the width of the copper grid lines 5 to 5 μm to 100 μm can reduce the light-shielding area brought by the copper grid lines 5 and improve the light utilization rate of the solar cell.

[0051] Exemplarily, the width of the second transparent conductive electron layer 42 can be 150 μm, 170 μm, 200 μm, 230 μm, 250 μm, 300 μm, 350 μm, 400 μm, etc.

[0052] The minimum width of the copper grid line 5 is 5 μm, which not only significantly reduces the light shielding area and optimizes the light utilization rate, but also ensures the stability and reliability of the overall performance of the solar cell in actual production. Exemplarily, the width of the copper grid line 5 can be 5 μm, 8 μm, 10 μm, 15 μm, 25 μm, 35 μm, 5 μm, 5 μm, 5 μm, 5 μm, 100 μm. Preferably, the width of the copper grid line is 5 μm to 20 μm.

[0053] In some embodiments, the light transmittance of the transparent conductive layer 4 is greater than or equal to 85%, and the sheet resistance is 50 Ω / sq to 200 Ω / sq; and / or, the transparent conductive compound is one or a combination of indium tin oxide, indium titanium oxide, indium zinc oxide, aluminum zinc oxide, niobium aluminum oxide, lanthanum aluminate, and tin fluoride oxide.

[0054] The light transmittance of the transparent conductive layer 4 being greater than or equal to 85% is more conducive to light transmission, improving the light utilization rate of the solar cell, and thus enhancing the energy conversion efficiency of the solar cell. The sheet resistance of the transparent conductive layer 4 being between 50 Ω / sq and 200 Ω / sq can more effectively transport carriers and improve the energy conversion efficiency of the solar cell.

[0055] Preferably, the thickness of the second transparent conductive electron layer 42 is 50 nm to 200 nm.

[0056] Setting the thickness of the second transparent conductive electron layer 42 within a specific range can better enhance the blocking ability of the transparent conductive layer 4 to copper elements. Exemplarily, the thickness of the second transparent conductive electron layer 42 can be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, etc.

[0057] Refer to Figure 2 and Figure 3 , in some embodiments, as Figure 2 and Figure 3 shown, the solar cell is a passivated contact solar cell, and the semiconductor layer includes a P-type semiconductor layer 221 disposed on the first surface of the silicon substrate 1 and an N-type semiconductor layer 222 disposed on the second surface of the silicon substrate 1. One of the first surface and the second surface is the light-receiving surface, and the other is the backlight surface;

[0058] A first dielectric layer 211 is provided between the silicon substrate 1 and the P-type semiconductor layer 221, and a second dielectric layer 212 is provided between the silicon substrate 1 and the N-type semiconductor layer 222. The thickness of the first dielectric layer 211 and the second dielectric layer 212 is 0.8 nm to 2.5 nm;

[0059] The first passivation layer 3 includes a first passivation sub-layer 31 and a second passivation sub-layer 32. The first passivation sub-layer 31 is located on the side where the light-receiving surface of the silicon substrate 1 is located, and the second passivation sub-layer 32 is located on the side where the backlight surface of the silicon substrate 1 is located;

[0060] There are two transparent conductive film layers 4, which are correspondingly arranged on the sides of the P-type semiconductor layer 221 and the N-type semiconductor layer 222 away from the silicon substrate 1. The second transparent conductive sub-layer 42 entirely or partially covers the surface of the first transparent conductive sub-layer 41 and the first passivation layer 3 away from the silicon substrate 1.

[0061] The passivated contact solar cell is a TOPCon cell. As Figure 2 shown, the second transparent conductive sub-layer 42 entirely covers the surface of the first transparent conductive sub-layer 41 and the first passivation layer 3 away from the silicon substrate 1, or as Figure 3 shown, the second transparent conductive sub-layer 42 partially covers the surface of the first transparent conductive sub-layer 41 and the first passivation layer 3 away from the silicon substrate 1. Compared with the case where the second transparent conductive sub-layer 42 entirely covers the surface of the first transparent conductive sub-layer 41 and the first passivation layer 3 away from the silicon substrate 1, when the second transparent conductive sub-layer 42 only partially covers the surface of the first transparent conductive sub-layer 41 and the first passivation layer 3 away from the silicon substrate 1, the light loss caused by the absorption of part of the light by the second transparent conductive sub-layer 42 can be reduced, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0062] The materials of the first dielectric layer 211 and the second dielectric layer 212 may include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide. Specifically, the first dielectric layer 211 and the second dielectric layer 212 may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation performance, can minimize the recombination loss of minority carriers on the surface of the silicon substrate 1, and is a film with excellent durability for subsequent high-temperature processes. The thickness of the first dielectric layer 211 and the second dielectric layer 212 is 0.8 nm to 2.5 nm. Exemplarily, the first dielectric layer 211 and the second dielectric layer 212 may be 0.8 nm, 1 nm, 1.2 nm, 1.5 nm, 2 nm, 2.5 nm, etc.

[0063] Preferably, the P-type semiconductor layer 221 may be a boron-doped polycrystalline silicon layer, and the N-type semiconductor layer 222 may be a phosphorus-doped polycrystalline silicon layer.

[0064] Further, the first passivation sub-layer 31 includes a first aluminum oxide layer and a first composite silicon nitride layer that are sequentially stacked on the surface of the semiconductor layer 22. The thickness of the first aluminum oxide layer is 5 nm to 15 nm, and the thickness of the first composite silicon nitride layer is 60 nm to 90 nm. The second passivation sub-layer 32 is a second aluminum oxide layer and a second composite silicon nitride layer that are sequentially stacked on the surface of the semiconductor layer 22. The thickness of the second aluminum oxide layer is 5 nm to 15 nm, and the thickness of the second composite silicon nitride layer is 80 nm to 100 nm.

[0065] Preferably, the first composite silicon nitride layer can be a first silicon oxide layer and a first silicon nitride layer that are sequentially stacked on the first aluminum oxide layer, and the thickness ratio of the first silicon oxide layer to the first silicon nitride layer is 1:2 to 3. The first composite silicon nitride layer can also be a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer that are sequentially stacked on the first aluminum oxide layer, and the thickness ratio of the first silicon oxide layer, the first silicon nitride layer, and the second silicon oxide layer is 1:4 to 6:1.

[0066] Preferably, the second composite silicon nitride layer can be a third silicon oxide layer and a second silicon nitride layer that are sequentially stacked on the second aluminum oxide layer, and the thickness ratio of the third silicon oxide layer to the second silicon nitride layer is 1:2 to 3. The first composite silicon nitride layer can also be a third silicon oxide layer, a second silicon nitride layer, and a fourth silicon oxide layer that are sequentially stacked on the second aluminum oxide layer, and the thickness ratio of the third silicon oxide layer, the second silicon nitride layer, and the fourth silicon oxide layer is 1:4 to 6:1.

[0067] In some embodiments, the solar cell is a back-contact solar cell. The semiconductor layer 22 includes a P-type semiconductor layer 221 and an N-type semiconductor layer 222 that are arranged in a finger-crossed manner. The transparent conductive layers 4 on the surfaces of the P-type semiconductor layer 221 and the N-type semiconductor layer 222 are insulated from each other.

[0068] The back-contact solar cell is a BC cell. As Figure 1 shown, since the P-type semiconductor layer 221 and the N-type semiconductor layer 222 in the BC cell are arranged in a finger-crossed manner, the transparent conductive layers 4 on the P-type semiconductor layer 221 and the N-type semiconductor layer 222 are insulated from each other, which can better avoid the leakage phenomenon of the back-contact solar cell.

[0069] Preferably, the P-type semiconductor layer 221 can be a boron-doped polysilicon layer, and the N-type semiconductor layer 222 can be a phosphorus-doped polysilicon layer.

[0070] Further preferably, the P-type semiconductor layer 221, the N-type semiconductor layer 222, the transparent conductive layer 4, and the copper gate line 5 are disposed on the side where the backlight surface of the silicon substrate 1 is located. The light-receiving surface of the silicon substrate 1 further includes a second passivation layer 6. The second passivation layer 6 may be a silicon oxide layer and a silicon nitride layer stacked in sequence on the light-receiving surface of the silicon substrate 1. Preferably, the thickness of the silicon oxide layer is 25 nm to 35 nm, and the thickness of the silicon nitride layer is 40 nm to 70 nm.

[0071] In some embodiments, a first dielectric layer 211 is disposed between the silicon substrate 1 and the P-type semiconductor layer 221, and a second dielectric layer 212 is disposed between the silicon substrate 1 and the N-type semiconductor layer 222. The first dielectric layer 211 and the second dielectric layer 212 are insulated from each other, and the thickness of the first dielectric layer 211 and the second dielectric layer 212 is 0.8 nm to 2.5 nm.

[0072] The materials of the first dielectric layer 211 and the second dielectric layer 212 may include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the first dielectric layer 211 and the second dielectric layer 212 may be composed of a silicon oxide layer containing silicon oxide.

[0073] Exemplarily, the thicknesses of the first dielectric layer 211 and the second dielectric layer 212 may both be 0.8 nm, 1 nm, 1.2 nm, 1.5 nm, 2 nm, 2.5 nm, etc.

[0074] Further, the P-type semiconductor layer 221 may be a doped polysilicon layer doped with boron elements. The N-type semiconductor layer 222 may be a doped polysilicon layer doped with phosphorus elements. The passivation contact structures formed by the combination of the first dielectric layer 211 and the P-type semiconductor layer 221 or the combination of the second dielectric layer 212 and the N-type semiconductor layer 222 can both prevent minority carriers from passing through and reduce the recombination loss of minority carriers.

[0075] In some embodiments, the first passivation layer 3 includes an aluminum oxide layer and a composite silicon nitride layer. The thickness of the aluminum oxide layer is 5 nm to 15 nm, and the thickness of the composite silicon nitride layer is 60 nm to 90 nm. Further, the composite silicon nitride layer may be a silicon oxide layer and a silicon nitride layer stacked in sequence on the aluminum oxide layer, and the thickness ratio of the first silicon oxide layer to the first silicon nitride layer is 1:2 to 3. The first composite silicon nitride layer may also be a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer stacked in sequence on the aluminum oxide layer, and the thickness ratio of the first silicon oxide layer, the first silicon nitride layer, and the second silicon oxide layer is 1:4 to 6:1.

[0076] In some embodiments, the thickness of the copper gate line 5 is 10 μm to 25 μm.

[0077] When the thickness of the copper grid line 5 is within the above range, it is beneficial to maintain a low material cost of the copper grid line 5 and a low power loss, thereby better improving the photoelectric conversion efficiency of the solar cell. If the thickness of the copper grid line 5 is too thick, not only will the material cost of the copper grid line 5 increase, but also the possibility of side leakage or detachment will increase, thus reducing the reliability of the copper grid line 5. If it is too thin, it cannot provide sufficient current collection ability, which is not conducive to further improving the photoelectric conversion efficiency of the solar cell.

[0078] Exemplarily, the thickness of the copper grid line 5 can be 10μm, 12μm, 14μm, 16μm, 18μm, 20μm, 22μm, 24μm, 25μm, etc.

[0079] In some embodiments, the width of the hollowed-out area is 10μm to 40μm; and / or, the height of the hollowed-out area is 0.05μm to 0.5μm.

[0080] By setting the hollowed-out area, the semiconductor layer 22 is exposed and contacts the subsequently prepared transparent conductive layer 4, thereby better collecting current. The height of the hollowed-out area can change with the thickness of the first passivation layer 3 and the semiconductor layer 22, and the height of the hollowed-out area is not less than the thickness of the first passivation layer 3 to ensure that the first passivation layer 3 in the hollowed-out area is completely removed and the semiconductor layer 22 is fully exposed. Exemplarily, the width of the hollowed-out area can be 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, etc. The height of the hollowed-out area can be 0.05μm, 0.1μm, 0.15μm, 0.25μm, 0.3μm, 0.35μm, 0.4μm, 0.45μm, 0.5μm, etc.

[0081] In some embodiments, a protective layer is provided on the surface of the copper grid line 5, and the thickness of the protective layer is 0.1μm to 3.0μm.

[0082] The protective layer can not only protect the copper grid line 5, prevent the copper grid line 5 from being oxidized due to environmental factors, and extend the service life of the solar cell, but also provide good solderability, enabling the photovoltaic solder tape to be firmly welded on the grid line.

[0083] In some embodiments, the material of the protective layer is one or a combination of tin, tin alloy, silver, and silver alloy.

[0084] The above materials are all commonly used protective layer materials. Among them, tin has a lower cost compared to other metals such as silver. Using tin or its alloy can reduce the overall cost of the solar cell.

[0085] In some embodiments, the semiconductor layer 22 is a doped polycrystalline silicon layer.

[0086] The semiconductor layer 22 can be a doped polysilicon layer doped with phosphorus or boron. The combination of the dielectric layer 21 and the doped polysilicon layer can prevent minority carriers from passing through and reduce the recombination loss of minority carriers.

[0087] In some embodiments, the silicon substrate 1 is a P-type silicon wafer or an N-type silicon wafer.

[0088] Taking the back-contact solar cell as an example, the manufacturing method of the back-contact solar cell includes the following steps:

[0089] Providing an N-type silicon wafer: The backlight surface of the N-type silicon wafer has a semiconductor layer 22 and a first passivation layer 3. Among them, the semiconductor layer 22 includes an interdigitated boron-doped polysilicon layer and a phosphorus-doped polysilicon layer, and the first passivation layer 3 covers the surfaces of the semiconductor layer 22 and the N-type silicon wafer;

[0090] Film opening treatment: Use laser film opening to remove part of the first passivation layer 3 to form a hollowed-out area, and then remove the laser ablation residue by cleaning, or directly use wet etching for patterning. The etching depth of the wet etching is determined by the thickness of the first passivation layer 3 and the thickness of the semiconductor layer 22; In the embodiment of the present invention, laser film opening is used to remove part of the first passivation layer 3. The width of the hollowed-out area is 10 μm to 40 μm, and the height is 0.05 μm to 0.5 μm, obtaining a patterned first passivation layer 3; Further, in the embodiment of the present invention, the width of the hollowed-out area is 25 μm and the height is 0.2 μm;

[0091] Depositing a transparent conductive layer 4: Prepare a first transparent conductive layer 41 and a second transparent conductive layer 42 by physical vapor deposition. The first transparent conductive layer 41 is respectively disposed on the surfaces of the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer facing away from the silicon substrate 1, and the first transparent conductive layer 41 fills the hollowed-out area not covered by the first passivation layer 3. The second transparent conductive layer 42 covers the first transparent conductive layer 41 and the silicon wafer surface, and the thickness is 50 nm to 200 nm; In the embodiment of the present invention, the thickness of the second transparent conductive layer 42 is 100 nm;

[0092] Preparing a seed layer: Prepare a seed layer on the side of the second transparent conductive layer 42 facing away from the silicon wafer by magnetron sputtering, and the thickness is 50 nm to 300 nm; In the embodiment of the present invention, the material of the seed layer is Cu and the thickness is 150 nm;

[0093] Printing a first mask layer: Select any one of the negative wet films of the acrylic resin system, epoxy resin system or polyester resin system with a reaction wavelength of 365 nm to 405 nm as the first mask layer material, and use screen printing to pattern the first mask layer, and the thickness is 5 μm to 30 μm; In the embodiment of the present invention, the thickness of the first mask layer is 20 μm;

[0094] Fabrication of copper grid lines 5: The copper grid lines 5 are deposited by electroplating, and the electroplated and reduced copper atoms are deposited on the seed layer area not covered by the mask layer, obtaining copper grid lines 5 with a width of 5 μm to 100 μm and a thickness of 10 μm to 25 μm. Among them, the copper grid lines 5 correspondingly arranged on the boron-doped polysilicon layer are the positive electrode copper grid lines 52, and the copper grid lines 5 correspondingly arranged on the phosphorus-doped polysilicon layer are the negative electrode copper grid lines 51; in the embodiment of the present invention, the width of the copper grid lines 5 is 5 μm and the thickness is 15 μm;

[0095] Fabrication of the protective layer: A tin layer is prepared by electroplating, and the electroplated and reduced tin atoms are deposited on the surface of the copper grid lines 5 as the protective layer of the copper grid lines 5, playing a role in protection and welding. The thickness of the protective layer is 0.1 μm to 3.0 μm; in the embodiment of the present invention, the thickness of the protective layer is 1 μm;

[0096] Removal of the first mask layer: Patterning is carried out by wet etching, and the etching solution can be any one of the citric acid with hydrogen peroxide system, phosphoric acid with hydrogen peroxide system, and sulfuric acid with hydrogen peroxide system; in the embodiment of the present invention, the first mask layer is removed by using a nitric acid solution with a mass concentration of 2% and a hydrochloric acid solution with a mass concentration of 9%;

[0097] Removal of the seed layer under the first mask layer: Treatment is carried out by wet etching, and the etching solution is a citric acid solution with a mass concentration of 3% to 10%, a hydrogen peroxide solution with a mass concentration of 3% to 7%, and a phosphoric acid solution with a mass concentration of 1% to 5%; in the embodiment of the present invention, the first mask layer is removed by using 5% citric acid, a hydrogen peroxide solution with a mass concentration of 5%, and a phosphoric acid solution with a mass concentration of 3%;

[0098] Printing the second mask layer: Any one of the negative wet films of the acrylic resin system, epoxy resin system, or polyester resin system with a reaction wavelength of 365 nm to 405 nm is selected as the second mask layer material, and the patterned second mask layer is screen-printed on the surface of the second transparent conductive electron layer 42, so that the second mask layer completely covers the positive electrode copper grid lines 52 and the negative electrode copper grid lines 51 respectively, and the second mask layer covering the positive electrode copper grid lines 52 and the second mask layer covering the negative electrode copper grid lines 51 do not contact each other;

[0099] Removal of the second transparent conductive electron layer 42: Patterning is carried out by wet etching method, and the etching solution can be the oxalic acid with hydrochloric acid system, nitric acid with hydrochloric acid system, or ferric chloride with hydrochloric acid system. In the embodiment of the present invention, a nitric acid solution with a mass concentration of 2% and a hydrochloric acid solution with a mass concentration of 9% are selected as the etching solution;

[0100] Removal of the second mask layer: The second mask layer is removed by using a KOH solution or NaOH solution with a mass concentration of 3% to 8%. In the embodiment of the present invention, the second mask layer is removed by using a KOH solution with a mass concentration of 5%.

[0101] In a second aspect, an embodiment of the present invention provides a photovoltaic module.

[0102] A photovoltaic module includes a solar cell as mentioned in the first aspect.

[0103] The solar cell and the photovoltaic module disclosed in the embodiments of the present invention have been introduced in detail above. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only for helping to understand the solar cell and the photovoltaic module of the present invention and its core idea. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation on the present invention.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; A semiconductor layer, wherein the semiconductor layer is disposed on a surface of the silicon substrate; A patterned first passivation layer, wherein the first passivation layer is disposed on a side of the semiconductor layer away from the silicon substrate; A transparent conductive layer, wherein the material of the transparent conductive layer is a transparent conductive compound, and the transparent conductive layer includes a first transparent conductive sublayer and a second transparent conductive sublayer, wherein the first transparent conductive sublayer is disposed on a surface of the semiconductor layer away from the silicon substrate, and the first transparent conductive sublayer is filled in a hollow area not covered by a patterned area of ​​the first passivation layer, and the second transparent conductive sublayer covers the first transparent conductive sublayer and a surface of the first passivation layer away from the silicon substrate, and the width of the second transparent conductive sublayer is 150 μm to 400 μm; The copper grid line is arranged on a side of the transparent conductive layer away from the semiconductor layer, and the width of the copper grid line is 5 μm to 100 μm.

2. The solar cell according to claim 1, characterized in that: The copper grid line has a width of 5 μm to 20 μm.

3. The solar cell according to claim 1, characterized in that: The light transmittance of the transparent conductive layer is greater than or equal to 85%, and the square resistance is 50Ω / □ to 200Ω / □; and / or the transparent conductive compound is one or more combinations of tin-doped indium oxide, titanium-doped indium oxide, zinc-doped indium oxide, zinc aluminum oxide, aluminum-doped niobium oxide, lanthanum aluminate and fluorine-doped tin oxide.

4. The solar cell according to claim 1, characterized in that: The thickness of the second transparent conductive sublayer is 50 nm to 200 nm.

5. The solar cell according to any one of claims 1 to 4, characterized in that: The solar cell is a passivated contact solar cell, the semiconductor layer comprises a P-type semiconductor layer arranged on the first surface of the silicon substrate and an N-type semiconductor layer arranged on the second surface of the silicon substrate, one of the first surface and the second surface is a light-receiving surface, and the other surface is a backlight surface; A first dielectric layer is disposed between the silicon substrate and the P-type semiconductor layer, and a second dielectric layer is disposed between the silicon substrate and the N-type semiconductor layer, wherein the thickness of the first dielectric layer and the second dielectric layer is 0.8 nm to 2.5 nm; The first passivation layer and the transparent conductive layer are simultaneously arranged on the side of the P-type semiconductor layer and the N-type semiconductor layer away from the silicon substrate, and the second transparent conductive sublayer completely or partially covers the surface of the first transparent conductive sublayer and the first passivation layer away from the silicon substrate.

6. The solar cell according to any one of claims 1 to 4, characterized in that: The solar cell is a back-contact solar cell, the semiconductor layer includes a P-type semiconductor layer and an N-type semiconductor layer arranged in a cross-finger manner, and the transparent conductive layer on the surface of the P-type semiconductor layer and the transparent conductive layer on the surface of the N-type semiconductor layer are insulated from each other.

7. The solar cell according to claim 6, characterized in that: A first dielectric layer is arranged between the silicon substrate and the P-type semiconductor layer, a second dielectric layer is arranged between the silicon substrate and the N-type semiconductor layer, and the first dielectric layer and the second dielectric layer are insulated from each other.

8. The solar cell according to claim 1, characterized in that: The copper grid line has a thickness of 10 μm to 25 μm.

9. The solar cell according to claim 1, characterized in that: The width of the hollow area is 10 μm to 40 μm; and / or the height of the hollow area is 0.05 μm to 0.5 μm.

10. The solar cell according to claim 1, characterized in that: A protective layer is provided on the surface of the copper grid line, and the thickness of the protective layer is 0.1 μm to 3.0 μm.

11. The solar cell according to claim 10, characterized in that: The material of the protective layer is one or a combination of tin, tin alloy, silver and silver alloy.

12. The solar cell according to claim 1, characterized in that: The semiconductor layer is a doped polysilicon layer; and / or, the first passivation layer includes a stacked silicon oxide layer and a silicon nitride layer, the thickness of the silicon oxide layer is 25nm to 35nm, and the thickness of the silicon nitride layer is 40nm to 70nm; and / or, the silicon substrate is a P-type silicon wafer or an N-type silicon wafer.

13. A photovoltaic module, characterized in that: Comprising the solar cell as described in any one of claims 1-12.

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