Display device

Abstract

A display device includes: a substrate having a pixel electrode; a light emitting element disposed on the pixel electrode and including a first semiconductor layer, an active layer, and a second semiconductor layer; an anti-step cover layer surrounding the light emitting element in a plan view; a common electrode disposed on the light emitting element and the step prevention cover layer; and an anti-oxidation layer provided on a portion of the common electrode that does not overlap the light-emitting element in the thickness direction. The common electrode includes a first portion disposed on the light emitting element and a second portion disposed between the anti-oxidation layer and the step-preventing capping layer, and a material forming the first portion is an oxide of a material forming the second portion.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0097890, filed on July 27, 2023, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device. Background art

[0004] As the information society develops, the demand for display devices for displaying images increases in various forms. The display device may be a flat panel display device such as a liquid crystal display, a field emission display, or a light - emitting display. The light - emitting display device may include an organic light - emitting display device including an organic light - emitting diode element as a light - emitting element or an inorganic light - emitting display device including an inorganic semiconductor element as a light - emitting element or a micro - light - emitting diode element (or micro - LED element) as a light - emitting element.

[0005] Recently, a head - mounted display including a light - emitting display device has been developed. A head - mounted display (HMD) is a glasses - type monitor device for virtual reality (VR) or augmented reality that is worn in the form of glasses or a helmet and focuses on a distance close to the user's eyes.

[0006] A high - resolution micro - light - emitting diode display panel including micro - light - emitting diode elements is applied to a head - mounted display. In order to prevent the light emitted from a micro - light - emitting diode element and the light emitted from another adjacent micro - light - emitting diode element from mixing, a reflective layer surrounding the micro - light - emitting diode element may be provided. However, a mask process and an etching process are required to form the reflective layer surrounding the micro - light - emitting diode element. Summary of the utility model

[0007] Aspects and features of embodiments of the present disclosure provide a display device capable of blocking and reflecting side light using a common electrode and a method of manufacturing the same.

[0008] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an embodiment, a display device may include: a substrate having a pixel electrode; a light-emitting element disposed on the pixel electrode and including a first semiconductor layer, an active layer, and a second semiconductor layer; an anti-step coverage layer surrounding the light-emitting element in a plan view; a common electrode disposed on the light-emitting element and the anti-step coverage layer; and an anti-oxidation layer disposed on a portion of the common electrode that does not overlap with the light-emitting element in a thickness direction. The common electrode may include a first portion disposed on the light-emitting element and a second portion disposed between the anti-oxidation layer and the anti-step coverage layer, and a material forming the first portion may be an oxide of a material forming the second portion.

[0010] The first portion may include InSnO x , and the second portion may include InSn, or the first portion may include InZnO x , and the second portion may include InZn.

[0011] The second portion may extend from the first portion and surround a side surface of the light-emitting element.

[0012] The second portion may have a ramp structure having a curvature.

[0013] The anti-oxidation layer may have a ramp structure having a curvature, and the anti-step coverage layer may have a ramp structure having a curvature.

[0014] The second portion, the anti-oxidation layer, and the anti-step coverage layer may have a convex shape on a side surface of the light-emitting element.

[0015] An upper surface of the second portion may be in contact with the anti-oxidation layer, and a lower surface of the second portion may be in contact with the anti-step coverage layer.

[0016] An amount of In in the second portion may be about 90 wt%.

[0017] An upper surface of the second semiconductor layer and the first portion may have an uneven pattern.

[0018] The anti-oxidation layer and the anti-step coverage layer may include an insulating material including one of an organic material, an inorganic material, and an organic-inorganic hybrid material.

[0019] According to an embodiment, a method of manufacturing a display device may include: bonding a first substrate and a second substrate by fusion bonding a connection electrode layer disposed between the first substrate having a pixel electrode and the second substrate having a semiconductor material layer; forming a plurality of light-emitting elements by removing the second substrate and etching the semiconductor material layer; forming an anti-step coverage layer surrounding the plurality of light-emitting elements in a plan view; depositing a common electrode material layer on the plurality of light-emitting elements and the anti-step coverage layer; forming an anti-oxidation layer on a portion of the common electrode material layer that does not overlap with the plurality of light-emitting elements in a thickness direction; and forming a common electrode by oxidizing a portion of the common electrode material layer disposed on the plurality of light-emitting elements.

[0020] The common electrode material layer may include In:Sn = 90:10 Wt% or In:Zn = 90:10 Wt%.

[0021] Forming the anti-step coverage layer may include: spreading a material for preventing step coverage over an entire area of the first substrate on which the plurality of light-emitting elements are disposed; covering the plurality of light-emitting elements with the material for preventing step coverage; and etching the material for preventing step coverage disposed on an upper surface of the plurality of light-emitting elements after forming a ramp structure having a convex curvature on sides of the plurality of light-emitting elements to expose the upper surfaces of the plurality of light-emitting elements.

[0022] Forming the anti-oxidation layer may include: spreading a material for preventing oxidation over an entire area of the first substrate on which the common electrode material layer is deposited; covering the plurality of light-emitting elements with the material for preventing oxidation; and etching the material for preventing oxidation disposed on an upper surface of the plurality of light-emitting elements after forming a ramp structure having a convex curvature on sides of the plurality of light-emitting elements to expose the upper surfaces of the plurality of light-emitting elements.

[0023] The anti-oxidation layer and the anti-step coverage layer may include an insulating material including one of an organic material, an inorganic material, and an organic-inorganic hybrid material.

[0024] Forming the common electrode may include oxidizing the common electrode material layer disposed on the upper surfaces of the plurality of light-emitting elements by oxygen plasma treatment.

[0025] The plurality of light-emitting elements may include a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked, and the common electrode may be in contact with an upper surface of the second semiconductor layer.

[0026] The second substrate may be a patterned sapphire substrate (PSS) having a concavo-convex pattern.

[0027] The upper surface of the second semiconductor layer may have a concavo-convex pattern.

[0028] The portion of the common electrode formed on the upper surfaces of the plurality of light-emitting elements may have an uneven pattern.

[0029] According to an embodiment of the display device and a manufacturing method thereof, the side light can be reflected by only the common electrode without a side reflection film that requires a separate masking process for the light-emitting elements.

[0030] However, the effects of the present disclosure are not limited to the effects mentioned above, and various other effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic perspective view of a display device according to an embodiment.

[0032] Figure 2 schematically shows Figure 1 a plan view of the display panel of region A.

[0033] Figure 3 is a schematic cross-sectional view of the display panel taken along Figure 2 A-A' of.

[0034] Figure 4 is a schematic cross-sectional view of the display panel taken along Figure 2 B-B' of.

[0035] Figure 5 is according to an embodiment of Figure 4 a schematic enlarged cross-sectional view of the light-emitting element of.

[0036] Figure 6 is a schematic enlarged cross-sectional view of the light-emitting element showing the traveling direction of light in the light-emitting element according to an embodiment Figure 4 of.

[0037] Figure 7 is a graph showing the transparency according to wavelength of the upper portion of the common electrode formed according to an embodiment.

[0038] Figure 8 is a schematic cross-sectional view of the display panel taken along Figure 2 B-B' of.

[0039] Figure 9 is according to an embodiment of Figure 8 a schematic enlarged cross-sectional view of the light-emitting element of.

[0040] Figure 10 is a schematic enlarged cross-sectional view of the light-emitting element showing the traveling direction of light in the light-emitting element according to an embodiment Figure 8 of.

[0041] Figures 11 to 19 is a schematic cross-sectional view showing a method of manufacturing a display device according to an embodiment.

[0042] Figures 20 to 28 is a schematic cross-sectional view showing a method of manufacturing a display device according to another embodiment. DETAILED DESCRIPTION

[0043] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as being limited. Throughout the present disclosure, like reference numerals denote like components. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

[0044] To describe the embodiments of the present disclosure, some of the parts not relevant to the description may not be provided.

[0045] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or an intervening layer may also be present. In contrast, when an element is referred to as being "directly on" another element, no intervening element may be present.

[0046] In addition, the phrase "in a plan view" means when the object part is observed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object part is observed from the side. The terms "overlap" or "overlapped" mean that a first object can be above or below a second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" may include laminating, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. The expression "not overlapping" may include meanings such as "spaced apart from", "separated from", or "offset from", as well as any other suitable equivalents as would be appreciated and understood by those of ordinary skill in the art. The terms "face" and "facing" may mean that a first object can be directly or indirectly opposite a second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object may be understood to be indirectly opposite each other, but still face each other.

[0047] For ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device shown in the drawings is turned over, a device positioned "below" or "beneath" another device may be positioned "above" the other device. Thus, the illustrative term "below" can include both the lower and upper positions. The device may also be oriented in other directions, and thus the spatial relative terms may be interpreted differently depending on the orientation.

[0048] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "electrically connected" or "electrically coupled" to the other element with one or more intervening elements interposed therebetween. Additionally, when an element is referred to as being "in contact" or "contacted" with another element, etc., the element may be "electrically in contact" or "physically in contact" with the other element; or "indirectly in contact" or "directly in contact" with the other element. It will also be understood that when the terms "comprises", "comprising", "has", "have", "having", "includes", and / or "including" are used, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0049] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or for convenience in their description and illustration. For example, without departing from the teachings herein, when discussing a "first element" in a description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner.

[0050] In view of the measurements discussed and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the term "about" or "approximate" as used herein includes the stated value and means within an acceptable deviation range of the particular value determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0051] In the description and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or". In the description and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0052] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined in this specification.

[0053] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a schematic perspective view of a display device according to an embodiment. Figure 2 is schematically shown Figure 1 a plan view of a display panel of region A.

[0055] In Figure 1 and Figure 2 , a display device according to an embodiment is described as a micro light-emitting diode display (or mini-LED display) including a micro light-emitting diode (or mini-LED) as a light-emitting element, but the present disclosure is not limited thereto.

[0056] Although Figure 1 and Figure 2 a display device according to an embodiment is described as an LED on Si (LEDoS) having a light-emitting diode element disposed on a semiconductor circuit board formed using a semiconductor process, it should be noted that the present disclosure is not limited thereto.

[0057] Furthermore, in Figure 1 and Figure 2In this case, the first direction DR1 refers to the horizontal direction of the display panel 100, the second direction DR2 refers to the vertical direction of the display panel 100, and the third direction DR3 refers to the thickness direction of the display panel 100. "Left", "right", "top", and "bottom" refer to the directions when observing the display panel 100 from a plane (e.g., in a plan view). For example, "right" refers to one side of the first direction DR1, "left" refers to the other side of the first direction DR1, "top" refers to one side of the second direction DR2, and "bottom" refers to the other side of the second direction DR2. In addition, "up" refers to the first side of the third direction DR3, and "down" refers to the second side of the third direction DR3.

[0058] Reference Figure 1 and Figure 2 , according to an embodiment, the display device may include a display panel 100, and the display panel 100 includes a display area DA and a non-display area NDA.

[0059] The display panel 100 may have a rectangular shape with a long side in the first direction DR1 and a short side in the second direction DR2 in a plan view. However, the planar shape of the display panel 100 is not limited thereto, and the display panel 100 may have a polygon, a circle, an ellipse, or an atypical planar shape other than a rectangle.

[0060] The display area DA may be an area for displaying an image, and the non-display area NDA may be an area for not displaying an image. The planar shape of the display area DA may follow the planar shape of the display panel 100. In Figure 1 this case, the planar shape of the display area DA is rectangular. The display area DA may be provided in the central area of the display panel 100. The non-display area NDA may be provided adjacent to the display area DA. The non-display area NDA may be provided to surround the display area DA in a plan view.

[0061] The display area DA of the display panel 100 may include a plurality of pixels PX. The pixel PX may be the smallest light-emitting unit capable of displaying white light.

[0062] Each of the pixels PX may include a plurality of light-emitting regions EA1, EA2, and EA3 that emit light. In an embodiment of the present disclosure, each of the pixels PX may include three light-emitting regions EA1, EA2, and EA3, but the present disclosure is not limited thereto. For example, each of the pixels PX may include four light-emitting regions.

[0063] Each of the first light-emitting regions EA1 may be a region that emits first light. Each of the first light-emitting regions EA1 may output the first light output from the light-emitting element LE as it is. The first light may be light in a blue wavelength band. The blue wavelength band may be in the range of approximately 370 nm to approximately 460 nm, but the present disclosure is not limited thereto.

[0064] Each of the second light-emitting regions EA2 may be a region that emits second light. Each of the second light-emitting regions EA2 may convert a part of the first light emitted from the light-emitting element LE into second light and output the second light. The second light may be light in a green wavelength band. The green wavelength band may be in the range of approximately 480 nm to approximately 560 nm, but the present disclosure is not limited thereto.

[0065] Each of the third light-emitting regions EA3 may be a region that emits third light. Each of the third light-emitting regions EA3 may convert a part of the first light emitted from the light-emitting element LE into third light and output the third light. The third light may be light in a red wavelength band. The red wavelength band may be in the range of approximately 600 nm to approximately 750 nm, but the present disclosure is not limited thereto.

[0066] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be alternately arranged in the first direction DR1. For example, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be arranged in the order of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 in the first direction DR1.

[0067] The first light-emitting region EA1 may be arranged in the second direction DR2. The second light-emitting region EA2 may be arranged in the second direction DR2. The third light-emitting region EA3 may be arranged in the second direction DR2.

[0068] In addition to the light-emitting element LE that emits the first light, each of the light-emitting regions EA1, EA2, and EA3 may further include at least one of a wavelength conversion layer and a color filter.

[0069] The wavelength conversion layer may be disposed on two or more of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. For example, the wavelength conversion layer may be disposed in the second light-emitting region EA2 and the third light-emitting region EA3. The wavelength conversion layer may include wavelength conversion particles. The wavelength conversion particles may convert light in the blue wavelength band into light in another wavelength band (e.g., light in the yellow wavelength band). The wavelength conversion particles may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. The quantum dots may include group-IV nanocrystals, II-VI compound nanocrystals, III-V compound nanocrystals, IV-VI nanocrystals, or combinations thereof.

[0070] The quantum dots may include a core and a shell coating the core. The core is not limited thereto.

[0071] The wavelength conversion layer may further include a scatterer for scattering the light of the light-emitting element LE in a random direction. The scatterer may include metal oxide particles or organic particles. For example, the metal oxide may be titanium oxide (TiO2), zirconium oxide (ZrO2), silicon dioxide (SiO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2). In addition, the organic particles may include an acrylic resin or a polyurethane resin. The scatterer may have a diameter in the range of several nanometers to several tens of nanometers.

[0072] A plurality of color filters may be arranged to overlap with the plurality of pixel circuit units and the wavelength conversion layer in a plan view. The color filters may transmit only specific light. For example, the color filters may include a first color filter, a second color filter, and a third color filter. The first color filter may be disposed in the first light-emitting region EA1, the second color filter may be disposed in the second light-emitting region EA2, and the third color filter may be disposed in the third light-emitting region EA3.

[0073] Each of the first color filters may transmit first light and absorb or block second light and third light. For example, each of the first color filters may transmit light in the blue wavelength band and absorb or block light in the green wavelength band and the red wavelength band. Accordingly, each of the first color filters may transmit the first light emitted from the light-emitting element LE. For example, the first light emitted from the light-emitting element LE in the first light-emitting region EA1 may not be converted by a separate wavelength conversion layer and may pass through the first color filter. Accordingly, each of the first light-emitting regions EA1 may emit the first light.

[0074] Each of the second color filters may be disposed on the wavelength conversion layer in the second light-emitting region EA2. Each of the second color filters may transmit the second light and absorb or block the first light and the third light. For example, each of the second color filters may transmit light in the green wavelength band and absorb or block light in the blue wavelength band and the red wavelength band. Thus, each of the second color filters may absorb or block the first light that is not converted by the wavelength conversion layer among the first light emitted from the light-emitting element LE. In addition, each of the second color filters may transmit the second light corresponding to the green wavelength band among the fourth light converted by the wavelength conversion layer, and absorb or block the third light corresponding to the blue wavelength band. Thus, each of the second light-emitting regions EA2 may emit the second light.

[0075] Each of the third color filters may be disposed on the wavelength conversion layer in the third light-emitting region EA3. Each of the third color filters may transmit the third light and absorb or block the first light and the second light. For example, each of the third color filters may transmit light in the red wavelength band and absorb or block light in the blue wavelength band and the green wavelength band. Thus, each of the third color filters may absorb or block the first light that is not converted by the wavelength conversion layer among the first light emitted from the light-emitting element LE. In addition, each of the third color filters may transmit the third light corresponding to the red wavelength band among the fourth light converted by the wavelength conversion layer, and absorb or block the second light corresponding to the green wavelength band. Thus, each of the third light-emitting regions EA3 may emit the third light.

[0076] In another embodiment, a light-transmissive layer may be formed instead of the wavelength conversion layer in one of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. The light-transmissive layer may be disposed on the common electrode ( Figure 3 and Figure 4 CE) in each of the first light-emitting regions EA1. The light-transmissive layer may overlap with the light-emitting element LE in the third direction DR3 in each of the first light-emitting regions EA1. The light-transmissive layer may include a light-transmissive organic material. For example, the light-transmissive layer may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0077] In another embodiment, each of the light-emitting regions EA1, EA2, and EA3 may include a light-emitting element LE that sequentially emits the first light, the second light, and the third light. For example, the first light-emitting region EA1 may include a light-emitting element LE that emits the first light, the second light-emitting region EA2 may include a light-emitting element LE that emits the second light, and the third light-emitting region EA3 may include a light-emitting element LE that emits the third light, and the wavelength conversion layer and / or the color filter may be omitted.

[0078] The non-display area NDA may include a first common voltage supply area CVA1, a second common voltage supply area CVA2, a first pad unit PDA1, a second pad unit PDA2, and a peripheral area PHA.

[0079] The first common voltage supply area CVA1 may be disposed between the first pad unit PDA1 and the display area DA. The second common voltage supply area CVA2 may be disposed between the second pad unit PDA2 and the display area DA. Each of the first common voltage supply area CVA1 and the second common voltage supply area CVA2 may include a plurality of common connection electrodes CCE connected to a common electrode ( Figure 3 and Figure 4 CE) of the light-emitting element LE. The common voltage may be supplied to each of the light-emitting elements LE through the common connection electrodes CCE.

[0080] The common connection electrodes CCE of the first common voltage supply area CVA1 may be electrically connected to one of the first pads PD1 of the first pad unit PDA1. For example, the common connection electrodes CCE of the first common voltage supply area CVA1 may receive the common voltage from one of the first pads PD1 of the first pad unit PDA1.

[0081] The common connection electrodes CCE of the second common voltage supply area CVA2 may be electrically connected to one of the second pads of the second pad unit PDA2. For example, the common connection electrodes CCE of the second common voltage supply area CVA2 may receive the common voltage from one of the second pads of the second pad unit PDA2.

[0082] The first pad unit PDA1 may be disposed on the top side of the display panel 100. The first pad unit PDA1 may include a first pad PD1 connected to an external circuit board.

[0083] The second pad unit PDA2 may be disposed on the bottom side of the display panel 100. The second pad unit PDA2 may include a second pad connected to an external circuit board. In an embodiment, the second pad unit PDA2 may be omitted.

[0084] The peripheral area PHA may be an area excluding the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad unit PDA1, and the second pad unit PDA2 from the non-display area NDA. The peripheral area PHA may surround the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad unit PDA1, the second pad unit PDA2, and the display area DA.

[0085] Figure 3 is according to an embodiment along Figure 2A schematic cross-sectional view of the display panel taken along A-A'. Figure 4 is a schematic cross-sectional view of the display panel taken along Figure 2 B-B' according to an embodiment. Figure 5 is according to an embodiment of Figure 4 A schematic enlarged cross-sectional view of the light-emitting element.

[0086] Referring to Figures 3 to 5 , the display panel 100 may include a semiconductor circuit board 110 and a light-emitting element layer 120.

[0087] The semiconductor circuit board 110 may include a first substrate SUB1, a plurality of pixel circuit units PXC, pixel electrodes 111, first pads PD1, a first common connection electrode CCE1 of a common connection electrode CCE, and a planarization insulating layer INS1.

[0088] The first substrate SUB1 may be a silicon wafer substrate. The first substrate SUB1 may be made of single-crystalline silicon.

[0089] Each of the pixel circuit units PXC may be disposed on the first substrate SUB1. Each of the pixel circuit units PXC may include a complementary metal oxide semiconductor (CMOS) circuit formed using a semiconductor process. Each of the pixel circuit units PXC may include at least one transistor formed through a semiconductor process. In addition, each of the pixel circuit units PXC may further include at least one capacitor formed through a semiconductor process.

[0090] The pixel circuit units PXC may be disposed in the display area DA. Each of the pixel circuit units PXC may be connected to a corresponding pixel electrode 111. For example, the pixel circuit units PXC and the pixel electrodes 111 may be connected in a one-to-one correspondence. Each of the pixel circuit units PXC may apply a pixel voltage or an anode voltage to the pixel electrode 111.

[0091] Each of the pixel electrodes 111 may be disposed on a corresponding pixel circuit unit PXC. Each of the pixel electrodes 111 may be an exposed electrode exposed from the pixel circuit unit PXC. For example, each of the pixel electrodes 111 may protrude from the upper surface of the pixel circuit unit PXC. Each of the pixel electrodes 111 and the pixel circuit unit PXC may be integral with each other. Each of the pixel electrodes 111 may receive a pixel voltage or an anode voltage from the pixel circuit unit PXC. The pixel electrodes 111 may include aluminum (Al).

[0092] Each of the first pad PD1 and the first common connection electrode CCE1 may be an exposed electrode exposed from the first substrate SUB1. The first pad PD1, the first common connection electrode CCE1, and the pixel electrode 111 may include the same material. For example, the first pad PD1 and the first common connection electrode CCE1 may include aluminum (Al).

[0093] Since the second pad of the second pad unit PDA2 may be substantially the same as the first pad PD1 described above, its description is omitted. Figure 3 Since the second pad of the second pad unit PDA2 may be substantially the same as the first pad PD1 described above, its description is omitted.

[0094] The planarization insulating layer INS1 may be provided on the first substrate SUB1 on which the pixel electrode 111, the first pad PD1, and the first common connection electrode CCE1 are not provided. The upper surface of the planarization insulating layer INS1, the upper surface of each of the pixel electrodes 111, the upper surface of each of the first pads PD1, and the upper surface of each of the first common connection electrodes CCE1 may be continuously flat (e.g., coplanar with each other). In another embodiment, the planarization insulating layer INS1 may cover the pixel electrode 111, the first pad PD1, and the first common connection electrode CCE1, and at least a part of each of the pixel electrode 111, the first pad PD1, and the first common connection electrode CCE1 may be exposed through a contact hole penetrating the planarization insulating layer INS1 and not covered by the planarization insulating layer INS1. The planarization insulating layer INS1 may be formed of an inorganic material such as silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO x )).

[0095] The light-emitting element layer 120 may include light-emitting regions EA1, EA2, and EA3 and may be a layer that emits light. The light-emitting element layer 120 may include a connection electrode 112, a pad connection electrode PDE, a second common connection electrode CCE2 that connects to the common connection electrode CCE, a light-emitting element LE, an anti-step coverage layer NCP1, a common electrode CE, and an anti-oxidation layer NCP2.

[0096] Each of the connection electrodes 112 may be provided on a corresponding pixel electrode 111. For example, the connection electrodes 112 may be connected to the pixel electrodes 111 in a one-to-one correspondence. The connection electrodes 112 may be used as bonding metals for bonding the pixel electrodes 111 and the light-emitting elements LE in the manufacturing process. For example, the connection electrodes 112 may include at least one of gold (Au), copper (Cu), aluminum (Al), and tin (Sn). In an embodiment, the connection electrode 112 may include a first layer containing one of gold (Au), copper (Cu), aluminum (Al), and tin (Sn) and a second layer containing another of gold (Au), copper (Cu), aluminum (Al), and tin (Sn), and the second layer may be provided on the first layer.

[0097] The pad connection electrode PDE may be disposed on the first pad PD1, and the second common connection electrode CCE2 may be disposed on the first common connection electrode CCE1. The pad connection electrode PDE may contact the upper surface of the first pad PD1, and the second common connection electrode CCE2 may contact the upper surface of the first common connection electrode CCE1. The pad connection electrode PDE, the second common connection electrode CCE2, and the connection electrode 112 may include the same material. For example, each of the pad connection electrode PDE and the second common connection electrode CCE2 may include at least one of gold (Au), copper (Cu), aluminum (Al), and tin (Sn). In the case where each of the connection electrodes 112 includes a first layer and a second layer, each of the pad connection electrode PDE and the second common connection electrode CCE2 may include a first layer and a second layer.

[0098] The pad connection electrode PDE may be connected to the pad CPD of the circuit board CB through a conductive connection member such as a wiring WR. For example, the first pad PD1, the pad connection electrode PDE, the wiring WR, and the pad CPD of the circuit board CB may be electrically connected to each other.

[0099] The semiconductor circuit board 110 and the circuit board CB may be disposed on the base substrate BSUB. The semiconductor circuit board 110 and the circuit board CB may be attached to the upper surface of the base substrate BSUB using an adhesive such as a pressure-sensitive adhesive.

[0100] The circuit board CB may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), a flexible printed circuit (FPC), or a flexible film such as a chip on film (COF).

[0101] Each of the light-emitting elements LE may be disposed on the connection electrode 112. The light-emitting element LE may be a vertical light-emitting diode element extending in the third direction DR3. For example, the length of the light-emitting element LE in the third direction DR3 may be greater than the length of the light-emitting element LE in the horizontal direction. The length in the horizontal direction is the length in the first direction DR1 or the length in the second direction DR2. For example, the length of the light-emitting element LE in the third direction DR3 may be in the range of approximately 1 μm to approximately 5 μm.

[0102] The light-emitting element LE may be a micro light-emitting diode element or a nano light-emitting diode element. As Figure 5As shown, the light-emitting element LE may include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2 stacked in a third direction DR3. The first semiconductor layer SEM1, the electron blocking layer EBL, the active layer MQW, the superlattice layer SLT, and the second semiconductor layer SEM2 may be sequentially stacked in the third direction DR3.

[0103] The first semiconductor layer SEM1 may be disposed on the connection electrode 112. The first semiconductor layer SEM1 may be doped with a first conductive type dopant such as Mg, Zn, Ca, Se, or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The thickness Tsem1 of the first semiconductor layer SEM1 may be in a range of approximately 30 to approximately 200 nm.

[0104] The electron blocking layer EBL may be disposed on the first semiconductor layer SEM1. The electron blocking layer EBL may be a layer for suppressing or preventing too many electrons from flowing into the active layer MQW. For example, the electron blocking layer EBL may be p-AlGaN doped with p-type Mg. The thickness Tebl of the electron blocking layer EBL may be in a range of approximately 10 nm to approximately 50 nm. In an embodiment, the electron blocking layer EBL may be omitted.

[0105] The active layer MQW may be disposed on the electron blocking layer EBL. The active layer MQW may emit light by combining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light having a center wavelength in a range of approximately 450 nm to approximately 495 nm, for example, light in the blue wavelength band, but the present disclosure is not limited thereto.

[0106] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. In the case where the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. The well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but the present disclosure is not limited thereto. The thickness of the well layer may be in a range of approximately 1 to approximately 4 nm, and the thickness of the barrier layer may be in a range of approximately 3 to approximately 10 nm. In this case, the thickness Tmqw of the active layer MQW may be the sum of the thickness of the well layer and the thickness of the barrier layer.

[0107] In another embodiment, the active layer MQW may have a structure in which a semiconductor material having a high bandgap energy and a semiconductor material having a low bandgap energy are alternately stacked with each other, and may include group III to group V semiconductor materials according to the wavelength range of the emitted light. In an embodiment, the light emitted from the active layer MQW is not limited to the first light (light in the blue wavelength band) and may emit the second light (light in the green wavelength band) or the third light (light in the red wavelength band).

[0108] The superlattice layer SLT may be disposed on the active layer MQW. The superlattice layer SLT may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer SLT may be formed of InGaN or GaN. The thickness Tslt of the superlattice layer SLT may be in the range of approximately 50 to approximately 200 nm. In an embodiment, the superlattice layer SLT may be omitted.

[0109] The second semiconductor layer SEM2 may be disposed on the superlattice layer SLT. The second semiconductor layer SEM2 may be doped with a second conductivity type dopant such as Si, Ge, or Sn. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness Tsem2 of the second semiconductor layer SEM2 may be in the range of approximately 500 nm to approximately 1 μm.

[0110] The upper surface of the second semiconductor layer SEM2 may contact (e.g., directly contact) the common electrode CE to be described below.

[0111] The common electrode CE may be disposed on the upper surface of each light-emitting element LE and on the upper surface of the anti-step coverage layer NCP1 where the light-emitting element LE is not disposed. The common electrode CE may be disposed on the entire surface of the pixel PX. The common electrode CE may completely cover each of the light-emitting elements LE.

[0112] The common electrode CE may include a first portion CE-1 disposed on the upper surface of each of the light-emitting elements LE and a second portion CE-2 disposed on the upper surface of the planarization insulating layer INS1 that does not overlap with the light-emitting elements LE. The first portion CE-1 and the second portion CE-2 may be integral with each other. The second portion CE-2 may extend from the first portion CE-1 and may be integrally formed.

[0113] The first portion CE-1 may include a transparent conductive oxide. The first portion CE-1 may include an oxide of the material constituting the second portion CE-2. For example, the first portion CE-1 may include InSnO x or InZnO x .

[0114] The second part CE-2 can extend from the first part CE-1 toward the planarized insulating layer INS1 on which the light-emitting element LE is not provided. The second part CE-2 can surround the side surface of the light-emitting element LE. The second part CE-2 can have a ramp structure with a curvature. The second part CE-2 can have a convex shape toward the side surface of the light-emitting element LE.

[0115] The second part CE-2 can include a conductive material having a relatively high reflectivity. The second part CE-2 and the first part CE-1 can include the same material. For example, when the first part CE-1 includes InSnO x , the second part CE-2 can include InSn. The second part CE-2 can be made of a material with In:Sn = 90:10 wt%. When the first part CE-1 includes InZnO x , the second part CE-2 can include InZn. The second part CE-2 can be made of a material with In:Zn = 90:10 wt%.

[0116] The first part CE-1 can include a material formed by oxidizing the material included in the second part CE-2. The first part CE-1 can have a higher transparency than the second part CE-2, and the second part CE-2 can have a higher reflectivity than the first part CE-1.

[0117] The anti-step coverage layer NCP1 can be provided between the second part CE-2 and the light-emitting element LE.

[0118] Step coverage refers to the coverage state of the film at the step portion on the surface of the semiconductor element thin film, and step coverage may affect (e.g., directly affect) the disconnection defect of the wiring and cause the deterioration of the quality.

[0119] For example, when the common electrode CE is formed along the upper surface and the side surface of the light-emitting element LE, a step difference may occur at the corner portion of the upper surface of the light-emitting element LE. Therefore, the anti-step coverage layer NCP1 can be provided on the side surface of the light-emitting element LE to form the common electrode CE that smoothly extends from the upper surface of the light-emitting element LE to the side surface, thereby preventing the above-mentioned step coverage.

[0120] The anti-step coverage layer NCP1 can surround the side surface of the light-emitting element LE. The anti-step coverage layer NCP1 can have a convex shape toward the side surface of the light-emitting element LE. The anti-step coverage layer NCP1 can contact (e.g., directly contact) the side surface of the light-emitting element LE. In addition, the anti-step coverage layer NCP1 can contact (e.g., directly contact) the second part CE-2 of the common electrode CE.

[0121] The anti-step coverage layer NCP1 may have a slope structure having a curvature formed in a downward diagonal direction from the corner where the upper surface and the side surface of the light-emitting element LE intersect.

[0122] Therefore, the second portion CE-2 provided on the anti-step coverage layer NCP1 may also be formed as a slope structure having a curvature. In this way, the common electrode CE can be stably supported, and the occurrence of a step difference can be prevented.

[0123] The anti-step coverage layer NCP1 may be formed of one of an organic material, an inorganic material, and an organic-inorganic hybrid material.

[0124] The inorganic material may include, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO x ). The organic material may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The organic-inorganic hybrid material may be a material having the properties of an organic material and an inorganic material by physically or chemically bonding an organic material and an inorganic material.

[0125] For example, the organic-inorganic hybrid material may be prepared by a sol-gel method, a low-temperature method, a melt intercalation method, and a self-assembly method for manufacturing an organic-inorganic composite film using electrostatic force.

[0126] The anti-oxidation layer NCP2 may be provided on the common electrode CE that does not overlap the upper surface of the light-emitting element LE in the third direction DR3.

[0127] The anti-oxidation layer NCP2 may surround the side surface of the light-emitting element LE. The anti-oxidation layer NCP2 may have a convex shape facing the side surface of the light-emitting element LE. The anti-oxidation layer NCP2 may contact (e.g., directly contact) the upper surface of the second portion CE-2 of the common electrode CE.

[0128] The anti-oxidation layer NCP2 may have a slope structure having a curvature formed in a downward diagonal direction from the corner where the first portion CE-1 and the second portion CE-2 of the common electrode CE intersect.

[0129] The anti-oxidation layer NCP2 may be formed of one of an organic material, an inorganic material, and an organic-inorganic hybrid material.

[0130] The inorganic material may include, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO x)). The organic material may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The organic-inorganic hybrid material may be a material having the properties of an organic material and an inorganic material by physically or chemically bonding the organic material and the inorganic material.

[0131] The non-display area NDA may include a first common voltage supply area CVA1, a second common voltage supply area CVA2, a first pad unit PDA1, and a second pad unit PDA2.

[0132] The first common voltage supply area CVA1 may be disposed between the first pad unit PDA1 and the display area DA. The second common voltage supply area CVA2 may be disposed between the second pad unit PDA2 and the display area DA. Each of the first common voltage supply area CVA1 and the second common voltage supply area CVA2 may include a plurality of common connection electrodes CCE connected to the common electrode CE. As a result, the common voltage may be provided to the common electrode CE through the common connection electrodes CCE. The common connection electrodes CCE of the first common voltage supply area CVA1 may be electrically connected to one of the first pads PD1 of the first pad unit PDA1. The common connection electrodes CCE of the second common voltage supply area CVA2 may be electrically connected to one of the second pads of the second pad unit PDA2.

[0133] The first pad unit PDA1 may be disposed adjacent to the top side of the display panel 100. The first pad unit PDA1 may include a first pad PD1 connected to an external circuit board CB.

[0134] The second pad unit PDA2 may be disposed adjacent to the bottom side of the display panel 100. The second pad unit PDA2 may include a second pad connected to the external circuit board CB. In an embodiment, the second pad unit PDA2 may be omitted.

[0135] Figure 6 is a schematic enlarged cross-sectional view of a light-emitting element showing the traveling direction of light in the light-emitting element according to an embodiment Figure 4 of the light-emitting element. Figure 7 is a graph showing the transparency according to wavelength of the upper part of the common electrode formed according to an embodiment.

[0136] As Figure 6 shown, the common electrode CE may include a first portion CE-1 disposed above the light-emitting element LE and a second portion CE-2 surrounding the side surface of the light-emitting element LE.

[0137] The first part CE-1 and the second part CE-2 can be integrally formed, but the first part CE-1 can be made of an oxide of the material constituting the second part CE-2. For example, the first part CE-1 can be made of InSnO x and the second part CE-2 can be made of InSn (In:Sn = 90:10 Wt%). In another example, the first part CE-1 can be made of InZnO x and the second part CE-2 can be made of InZn (In:Zn = 90:10 Wt%).

[0138] Therefore, the first part CE-1 and the second part CE-2 can have different physical properties. The first part CE-1 can have a higher transmittance than the second part CE-2, and the second part CE-2 can have a higher reflectance than the first part CE-1.

[0139] Therefore, the light emitted from the active layer MQW to the side of the light-emitting element LE can be reflected by the second part CE-2 of the common electrode CE and advance to the upper surface of the light-emitting element LE. The light transmitted to the upper surface of the light-emitting element LE can pass through the first part CE-1 with little loss.

[0140] Reference Figure 7 , in the case where the first part CE-1 of the common electrode CE according to the embodiment is formed of InSnO x and has thickness, the transmittance according to the wavelength is shown. In Figure 7 the graph of, A1 shown as a solid line represents the permeability of the first part CE-1 in an oxygen environment, and A2 shown as a dotted line represents the permeability of the first part CE-1 under anoxic conditions.

[0141] It can be seen that the transmittance of the first part CE-1 in an oxygen environment is similar to that of a conventional common electrode. For example, it can be seen that the transmittance of the first part CE-1 at a wavelength of 550 nm is about 84%.

[0142] When the first part CE-1 of the common electrode CE is formed of InSnO x and the thickness is , the sheet resistance is about 22.0 Ω and the resistivity is about 275 μΩ-cm, which is equivalent to the sheet resistance of a conventional common electrode.

[0143] Here, the conventional common electrode refers to ITO (indium tin oxide; InSnO x ) or IZO (indium zinc oxide; InZnO x ).

[0144] Figure 8is a schematic cross-sectional view of a display panel taken along Figure 2 B-B' of Figure 9 according to an embodiment. Figure 8 is a schematic enlarged cross-sectional view of a light-emitting element of Figure 10 according to an embodiment. Figure 8 is a schematic enlarged cross-sectional view of a light-emitting element showing the traveling direction of light in the light-emitting element of

[0145] Referring to Figures 8 to 10 the difference between the display panel 100 shown and Figures 4 to 6 the display panel 100 of

[0146] is only that the upper surface of the light-emitting element LE and the first portion CE-1 of the common electrode CE provided on the upper surface of the light-emitting element LE have a concavo-convex pattern CNP. Therefore, the description will focus on these differences.

[0147] Each of the concavo-convex patterns CNP may have a convex portion and a concave portion as a whole. The cross-sectional shape of the concavo-convex pattern CNP may be hemispherical or triangular, but the present disclosure is not limited thereto.

[0148] In the thickness direction, the concave portion of the first concavo-convex pattern CNP1 may be arranged to correspond to the concave portion of the second concavo-convex pattern CNP2, and the convex portion of the first concavo-convex pattern CNP1 may be arranged to correspond to the convex portion of the second concavo-convex pattern CNP2.

[0149] Referring to Figure 10 , the light emitted from the active layer MQW to the side surface of the light-emitting element LE may be reflected by the second portion CE-2 of the common electrode CE and advance to the upper surface of the light-emitting element LE. The light advancing to the upper surface of the light-emitting element LE may pass through the first portion CE-1 with very little loss.

[0150] Figures 11 to 19 is a schematic cross-sectional view showing a method of manufacturing a display device according to an embodiment. Figures 11 to 19is a schematic cross-sectional view showing a method of manufacturing a display device according to an embodiment and corresponds to the cross-sectional view of the display panel shown in Figure 4 The cross-sectional view of the display panel shown in

[0151] As shown in Figure 11 and Figure 12 As shown in, a first connection electrode layer 112L_1 may be formed on the pixel electrode 111 and the planarization insulating layer INS1 of the first substrate SUB1, and a second connection electrode layer 112L_2 may be formed on the light-emitting material layer LEML of the second substrate SUB2.

[0152] For example, a planarization insulating layer INS1 may be formed on the first substrate SUB1 on which the pixel electrode 111 is not provided. The upper surface of the planarization insulating layer INS1 and the upper surface of each of the pixel electrodes 111 may be flatly connected (e.g., coplanar with each other). For example, the height difference between the upper surface of the first substrate SUB1 and the upper surface of the pixel electrode 111 may be eliminated by the planarization insulating layer INS1. The planarization insulating layer INS1 may be formed of an inorganic material such as silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO x )

[0153] The first connection electrode layer 112L_1 may be deposited on the pixel electrode 111 and the planarization insulating layer INS1. The first connection electrode layer 112L_1 may include gold (Au), copper (Cu), aluminum (Al), or tin (Sn).

[0154] A buffer layer BF may be formed on the surface of the second substrate SUB2. The second substrate SUB2 may be a silicon substrate or a sapphire substrate. The buffer layer BF may be formed of an inorganic layer such as a silicon oxide layer (SiO2), an aluminum oxide layer (Al2O3), or a hafnium oxide layer (HfO x )

[0155] The light-emitting material layer LEML may be provided on the buffer layer BF. The light-emitting material layer LEML may include a first semiconductor material layer LEMD and a second semiconductor material layer LEMU. The second semiconductor material layer LEMU may be provided on the buffer layer BF, and the first semiconductor material layer LEMD may be provided on the second semiconductor material layer LEMU. The thickness of the second semiconductor material layer LEMU may be greater than the thickness of the first semiconductor material layer LEMD.

[0156] As shown in Figure 5As shown, the first semiconductor material layer LEMD may include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2. The second semiconductor material layer LEMU may be a semiconductor layer that is not doped with a dopant, for example, an undoped semiconductor layer. For example, the second semiconductor material layer LEMU may be undoped GaN that is not doped with a dopant.

[0157] A second connection electrode layer 112L_2 may be deposited on the first semiconductor material layer LEMD. The second connection electrode layer 112L_2 may include gold (Au), copper (Cu), aluminum (Al), or tin (Sn).

[0158] Thereafter, the first connection electrode layer 112L_1 and the second connection electrode layer 112L_2 may be joined, and the second substrate SUB2 may be removed.

[0159] The first connection electrode layer 112L_1 of the first substrate SUB1 and the second connection electrode layer 112L_2 of the second substrate SUB2 may be brought into contact. The connection electrode layer 112L may be formed by melting and joining the first connection electrode layer 112L_1 and the second connection electrode layer 112L_2 at a certain temperature (e.g., a predetermined temperature). For example, the connection electrode layer 112L may be disposed between the pixel electrode 111 of the first substrate SUB1 and the light-emitting material layer LEML of the second substrate SUB2 and serve as a bonding metal layer to bond the pixel electrode 111 of the first substrate SUB1 and the light-emitting material layer LEML of the second substrate SUB2.

[0160] The second substrate SUB2 and the buffer layer BF may be removed by a polishing process such as a chemical mechanical polishing (CMP) process and / or an etching process. In addition, the second semiconductor material layer LEMU of the light-emitting material layer LEML may be removed by a polishing process such as a CMP process.

[0161] Reference Figure 13 , a light-emitting element LE may be formed by etching the light-emitting material layer LEML and the connection electrode layer 112L.

[0162] To this end, a mask pattern (not shown) may be formed on the light-emitting material layer LEML.

[0163] A mask pattern may be formed on the upper surface of the light-emitting material layer LEML. The upper surface of the light-emitting material layer LEML may be the upper surface of the first semiconductor material layer LEMD exposed by removing the second substrate SUB2, the buffer layer BF, and the second semiconductor material layer LEMU. The mask pattern may be disposed in the region where the light-emitting element LE is to be formed. The mask pattern may overlap with the pixel electrode 111 in the third direction DR3. The thickness of the mask pattern may be in the range of approximately 0.01 to approximately 1 μm.

[0164] The light-emitting element LE may be formed by etching the light-emitting material layer LEML and the connection electrode layer 112L according to the mask pattern, and the mask pattern may be removed.

[0165] The mask pattern may not be etched by the first etching material for etching the light-emitting material layer LEML and the second etching material for etching the connection electrode layer 112L. As a result, the light-emitting material layer LEML and the connection electrode layer 112L in the region where the mask pattern is disposed may not be etched. Therefore, the connection electrode 112 and the light-emitting element LE may be formed on the upper surface of each of the pixel electrodes 111. Remove the mask pattern.

[0166] Reference Figure 14 and Figure 15 , an anti-step coverage layer NCP1 may be formed on the side surface of the light-emitting element LE. The anti-step coverage layer NCP1 may have a ramp structure with a curvature. The anti-step coverage layer NCP1 may be formed protruding with respect to the light-emitting element LE.

[0167] As Figure 14 shown, a material for preventing step coverage may be deposited on the entire surface of the substrate to cover the light-emitting element LE. The material for preventing step coverage may include, for example, one of an inorganic material, an organic material, and an organic-inorganic hybrid material. The inorganic material may include, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO x ). The organic material may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The organic-inorganic hybrid material may be a material having the properties of an organic material and an inorganic material by physically bonding or chemically bonding an organic material and an inorganic material.

[0168] A large voltage difference can be formed in the third direction DR3 without the need for a separate mask, and the material for preventing step coverage can be etched by an etching material. The etching material can be moved in the third direction DR3 (e.g., from top to bottom) by voltage control, and the material for preventing step coverage can be etched to form an anti-step coverage layer NCP1. As a result, the material for preventing step coverage provided on the horizontal plane defined by the first direction DR1 and the second direction DR2 can be removed quickly, while the material for preventing step coverage provided on the vertical plane defined by the third direction DR3 can be removed slowly. Therefore, etching can continue until all the material for preventing step coverage on the light-emitting element LE is removed. When all the material for preventing step coverage on the light-emitting element LE has been removed, the etching can be stopped. Thus, an anti-step coverage layer NCP1 having a ramp structure with a curvature can be formed on the side surface of the light-emitting element LE. The anti-step coverage layer NCP1 does not overlap with the light-emitting element LE in the third direction DR3.

[0169] Reference Figures 16 to 19 , a common electrode CE can be formed on the upper surface of the light-emitting element LE and the upper surface of the anti-step coverage layer NCP1, and the common electrode CE formed on the upper surface of the light-emitting element LE can be formed of an oxide of the forming material of the common electrode CE formed on the upper surface of the anti-step coverage layer NCP1.

[0170] For example, a common electrode material layer CEL can be deposited on the upper surface of the light-emitting element LE and the upper surface of the anti-step coverage layer NCP1.

[0171] For example, a common electrode material layer CEL can be deposited on the upper surface of the light-emitting element LE and the upper surface of the anti-step coverage layer NCP1 by a method such as sputtering.

[0172] The common electrode material layer CEL can include InSn or InZn.

[0173] For example, the common electrode material layer CEL can include In:Sn = 90:10 wt%. In another example, the common electrode material layer CEL can include In:Zn = 90:10 wt%.

[0174] Subsequently, reference Figure 17 , a material for preventing oxidation can be deposited over the entire first substrate SUB1 to cover the entire common electrode material layer CEL. The material for preventing oxidation can include, for example, one of an inorganic material, an organic material, and an organic-inorganic hybrid material. The inorganic material can include, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO x)。The organic material may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The organic-inorganic hybrid material may be a material having the properties of an organic material and an inorganic material by physically or chemically bonding the organic material and the inorganic material.

[0175] As Figure 18 shown, a large voltage difference can be formed in the third direction DR3 without the need for a separate mask, and the material for preventing oxidation can be etched by an etching material. The anti-oxidation layer NCP2 can be formed by etching the material for preventing oxidation while moving (e.g., from top to bottom) the etching material in the third direction DR3 by voltage control. Thus, the material for preventing oxidation provided on the horizontal plane defined by the first direction DR1 and the second direction DR2 can be quickly removed, while the material for preventing oxidation provided on the vertical plane defined by the third direction DR3 can be slowly removed. Therefore, etching can be continued until all the materials for preventing oxidation provided on the light-emitting element LE are removed. When all the materials for preventing step coverage on the light-emitting element LE are removed, the etching can be stopped. As a result, the anti-oxidation layer NCP2 having a ramp structure with a curvature can be formed on the side surface of the light-emitting element LE. The anti-oxidation layer NCP2 can prevent oxidation of the common electrode CE protected by the anti-oxidation layer NCP2 in the oxidation process to be described below with reference to Figure 19 .

[0176] Reference Figure 19 , an oxygen plasma treatment can be performed while exposing the common electrode CE on the light-emitting element LE. The exposed common electrode CE on the light-emitting element LE can be easily oxidized. On the other hand, the common electrode CE provided on the side surface of the light-emitting element LE, which does not overlap with the light-emitting element LE and is surrounded by the anti-oxidation layer NCP2, can be prevented from being oxidized. Therefore, the common electrode CE on the light-emitting element LE can become InSnO x , and the InSnO x is an oxide of InSn of the common electrode CE that does not overlap with the light-emitting element LE in the third direction DR3.

[0177] InSnO x may have higher transparency and lower reflectivity than InSn.

[0178] Figures 20 to 28 is a schematic cross-sectional view showing a method of manufacturing a display device according to another embodiment. Figures 20 to 28 is a schematic cross-sectional view showing a method of manufacturing a display device according to an embodiment, corresponding to the cross-sectional view of the display panel shown in Figure 8 .

[0179] Reference Figures 20 to 28 The manufacturing method of the display device according to another embodiment is different from the manufacturing method of the display device described in the reference Figures 11 to 19 in that the second substrate is a patterned sapphire substrate (PSS). Therefore, the description will focus on these differences.

[0180] As Figure 20 and Figure 21 shown in, a first connection electrode layer 112L_1 can be formed on the pixel electrode 111 and the planarization insulating layer INS1 of the first substrate SUB1, and a second connection electrode layer 112L_2 can be formed on the first semiconductor material layer LEMD of the second substrate SUB2.

[0181] For example, a planarization insulating layer INS1 can be formed on the first substrate SUB1 on which the pixel electrode 111 is not provided. The upper surface of the planarization insulating layer INS1 and the upper surface of each of the pixel electrodes 111 can be flatly connected (e.g., coplanar with each other). For example, the height difference between the upper surface of the first substrate SUB1 and the upper surface of the pixel electrode 111 can be eliminated by the planarization insulating layer INS1. The planarization insulating layer INS1 can be formed of an inorganic material such as silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO x ).

[0182] The first connection electrode layer 112L_1 can be deposited on the pixel electrode 111 and the planarization insulating layer INS1. The first connection electrode layer 112L_1 can include gold (Au), copper (Cu), aluminum (Al), or tin (Sn).

[0183] The second substrate SUB2 can be a patterned sapphire substrate (PSS).

[0184] The second substrate SUB2 can be a silicon substrate or a sapphire substrate. The second substrate SUB2 can be a patterned sapphire substrate (PSS).

[0185] The second substrate SUB2 can have a concavo-convex pattern CNP. The cross-section of the concavo-convex pattern CNP can be circular, and the overall shape of the concavo-convex pattern CNP can be circular, hemispherical, or conical. Thus, the concavo-convex pattern CNP of the PSS can be formed on the upper surface of the PSS in a form of bilateral symmetry or omnidirectional symmetry with respect to the center of the pattern, and the light extraction efficiency can be increased by reflecting the light incident within a specific angular range.

[0186] However, the width of the upper surface of the second substrate SUB2 exposed between adjacent concavo-convex patterns CNP can vary due to positioning, and the distance between adjacent concavo-convex patterns CNP can vary according to the position.

[0187] A semiconductor material layer LEMD can be formed on a second substrate SUB2. As Figure 9 shown, the semiconductor material layer LEMD can include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2. The second semiconductor layer SEM2 can include a concavo-convex pattern CNP corresponding to the concavo-convex pattern CNP of the second substrate SUB2.

[0188] A second connection electrode layer 112L_2 can be deposited on the semiconductor material layer LEMD. The second connection electrode layer 112L_2 can include gold (Au), copper (Cu), aluminum (Al), or tin (Sn).

[0189] Thereafter, the first connection electrode layer 112L_1 and the second connection electrode layer 112L_2 can be joined, and the second substrate SUB2 can be removed.

[0190] Reference Figure 22 , a light-emitting element LE can be formed by etching the semiconductor material layer LEMD and the connection electrode layer 112L. Since the etching of the semiconductor material layer LEMD and the connection electrode layer 112L has been described with reference to Figure 13 , an overlapping description will be omitted. However, the difference from the light-emitting element LE described with reference to Figure 13 is that the upper surface of the formed light-emitting element LE has a concavo-convex pattern CNP.

[0191] As Figure 23 and Figure 24 shown, an anti-step coverage layer NCP1 can be formed on the side surface of the light-emitting element LE. Since the method of forming the anti-step coverage layer NCP1 has been described with reference to Figure 14 and Figure 15 , a detailed description thereof will be omitted.

[0192] Reference Figures 25 to 28 , a common electrode CE can be formed on the upper surface of the light-emitting element LE and the upper surface of the anti-step coverage layer NCP1, but the common electrode CE formed on the upper surface of the light-emitting element LE can be formed of an oxide of the forming material of the common electrode CE formed on the upper surface of the anti-step coverage layer NCP1. Since the method of forming the common electrode CE has been described with reference to Figures 16 to 19 , a detailed description thereof will be omitted. However, the difference from Figures 16 to 19 is that the upper surface of the common electrode CE has a concavo-convex pattern.

[0193] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and variations. Therefore, the above-described embodiments of the present disclosure can be implemented alone or in combination with each other.

[0194] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but are intended to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, characterized in that: include: A substrate having a pixel electrode; A light emitting element, disposed on the pixel electrode and comprising a first semiconductor layer, an active layer and a second semiconductor layer; an anti-step covering layer surrounding the light emitting element in a plan view; A common electrode, disposed on the light emitting element and the anti-step covering layer; as well as an anti-oxidation layer, disposed on a portion of the common electrode that does not overlap with the light emitting element in a thickness direction, The common electrode includes a first portion disposed on the light emitting element and a second portion disposed between the anti-oxidation layer and the anti-step covering layer, and The material forming the first portion is an oxide of the material forming the second portion.

2. The display device according to claim 1, characterized in that The first part includes InSnO x , and the second portion comprises InSn, or The first part includes InZnO x , and the second part includes InZn.

3. The display device according to claim 2, characterized in that: The second portion extends from the first portion and surrounds a side surface of the light emitting element.

4. The display device according to claim 3, characterized in that: The second portion has a slope structure having a curvature.

5. The display device according to claim 4, characterized in that: The anti-oxidation layer has the slope structure having the curvature, and The anti-step covering layer has the slope structure having the curvature.

6. The display device according to claim 4, characterized in that: The second portion, the oxidation preventing layer, and the step preventing covering layer have a convex shape on the side surface of the light emitting element.

7. The display device according to claim 4, characterized in that: The upper surface of the second portion is in contact with the anti-oxidation layer, and A lower surface of the second portion contacts the anti-step covering layer.

8. The display device according to claim 2, characterized in that: The amount of In in the second part was 90 wt %.

9. The display device according to claim 2, characterized in that: An upper surface of the second semiconductor layer and the first portion have a concavo-convex pattern.

10. The display device according to claim 2, characterized in that: The anti-oxidation layer and the anti-step covering layer include insulating materials, and the insulating material includes one of an organic material, an inorganic material, and an organic-inorganic hybrid material.

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