Display device

Abstract

A display device is disclosed. The display device includes a circuit layer and a light emitting element on and connected to the circuit layer. The circuit layer includes: a transistor including a semiconductor layer; an insulating layer on the semiconductor layer and having a side surface defining a contact hole of the insulating layer at which a portion of the semiconductor layer is exposed outside the insulating layer and an upper surface, the side surface extending from the upper surface; a bridge electrode extending along a side surface of the insulating layer and contacting a portion of the semiconductor layer exposed outside the insulating layer; and a connection electrode connecting the light emitting element to the semiconductor layer. The connection electrode includes a first connection electrode directly on the bridge electrode and spaced apart from a portion of the semiconductor layer exposed outside the insulating layer.

Description

Technical Field

[0001] The present disclosure herein relates to a display device and a method of providing the display device. More specifically, the present disclosure relates to a display device having high resolution and high-speed driving characteristics. Background Art

[0002] A display device includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) for controlling the plurality of pixels. Each of the plurality of pixels includes a display element and a driving circuit for controlling the display element. The driving circuit of the pixel may include a plurality of transistors connected to each other in an organized manner. Summary of the Utility Model

[0003] As the size and resolution of a display device having pixels gradually increase, the number of signal lines and connection electrodes connecting the display elements and transistors included in the pixels increases. As a result, the integration degree of the driving circuit included in the pixel increases.

[0004] The present disclosure provides a display device having improved reliability and a method of manufacturing (or providing) the display device.

[0005] Embodiments of the present utility model provide a display device, the display device including: a circuit layer; and a light-emitting element on and connected to the circuit layer, wherein the circuit layer includes: a transistor including a semiconductor layer; an insulating layer on the semiconductor layer, the insulating layer having: a side surface defining a contact hole of the insulating layer, a part of the semiconductor layer being exposed to the outside of the insulating layer at the contact hole; and an upper surface, the side surface extending from the upper surface; a bridging electrode extending along the side surface of the insulating layer and contacting a part of the semiconductor layer exposed to the outside of the insulating layer; and a connection electrode connected to the semiconductor layer, the connection electrode including a first connection electrode directly on the bridging electrode and spaced apart from a part of the semiconductor layer exposed to the outside of the insulating layer.

[0006] In an embodiment, the semiconductor layer includes an upper surface, the semiconductor layer being exposed to the outside of the insulating layer at the upper surface, and the connection electrode may further include a second connection electrode on the upper surface of the semiconductor layer.

[0007] In an embodiment, the second connection electrode may be spaced apart from the first connection electrode on the bridging electrode, and the second connection electrode may be electrically connected to the first connection electrode via the bridging electrode.

[0008] In an embodiment, the width of the contact hole may be about 0.5 micrometers to about 2 micrometers.

[0009] In an embodiment, the depth of the contact hole may be about 1 micrometer to about 1.5 micrometers.

[0010] In an embodiment, the bridging electrode may have a length along a side surface of the insulating layer, and the length of the bridging electrode may be less than the depth of the contact hole.

[0011] In an embodiment, the bridging electrode has an upper surface closest to the upper surface of the insulating layer, and a portion of the side surface of the insulating layer between the upper surface of the insulating layer and the upper surface of the bridging electrode is exposed to the outside of the bridging electrode. The first connection electrode may directly contact the upper surface of the bridging electrode and the portion of the side surface of the insulating layer exposed to the outside of the bridging electrode.

[0012] In an embodiment, the insulating layer may include: a first insulating layer on the semiconductor layer; and a second insulating layer on the first insulating layer, wherein the contact hole may pass through the first insulating layer and the second insulating layer.

[0013] In an embodiment, the contact hole may include: a first hole portion defined by a side surface of the first insulating layer; and a second hole portion defined by a side surface of the second insulating layer, wherein the size of the first hole portion may be smaller than the size of the second hole portion.

[0014] In an embodiment, the first connection electrode may include portions extending from the upper surface of the insulating layer and along the side surface of the insulating layer, and these portions are spaced apart from each other to define an upper hole in the first connection electrode, wherein the size of the upper hole may increase in a direction from the upper surface of the insulating layer to a portion of the transistor exposed to the outside of the insulating layer.

[0015] In an embodiment, the bridging electrode may include an N-type dopant.

[0016] In an embodiment, the circuit layer may further include an organic layer on the insulating layer and including side surfaces of upper contact holes where a portion of the first connection electrode defining the organic layer is exposed to the outside of the organic layer. Description of the Drawings

[0017] The drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention. In the drawings:

[0018] Figure 1 is a perspective view showing a display device according to an embodiment of the present invention;

[0019] Figure 2 is an exploded perspective view showing a display device according to an embodiment of the present invention;

[0020] Figure 3 is a cross-sectional view of a display panel according to an embodiment of the present invention;

[0021] Figure 4 is a top view of a display panel according to an embodiment of the present utility model;

[0022] Figure 5 is a view illustrating an equivalent circuit of a pixel according to an embodiment of the present utility model;

[0023] Figure 6 is a cross-sectional view of a display panel according to an embodiment of the present utility model;

[0024] Figure 7 is Figure 6 an enlarged view of region AA' of

[0025] Figure 8A is an enlarged view of a part of a display device according to an embodiment of the present utility model;

[0026] Figure 8B is an enlarged view of a part of a display device according to an embodiment of the present utility model;

[0027] Figure 8C is an enlarged view of a part of a display device according to an embodiment of the present utility model;

[0028] Figure 8D is Figure 6 an enlarged view of region BB' of

[0029] Figure 9A is a cross-sectional view of a display panel according to an embodiment of the present utility model;

[0030] Figure 9B is Figure 9A an enlarged view of region CC' of and

[0031] Figures 10A to 10E is a cross-sectional view showing sequential processes in a method for manufacturing (or providing) a display device according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0032] The present utility model may be modified in many alternative forms, and thus specific embodiments will be illustrated in the drawings and described in detail. However, it should be understood that it is not intended to limit the present utility model to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present utility model.

[0033] In this specification, when an element (or region, layer, part, etc.) is referred to as being related to another element (such as "disposed on" another element, "connected to" or "coupled to" another element), it means that the element can be directly disposed on the other element, directly connected to or directly coupled to the other element, or a third element can be disposed therebetween. In this specification, when an element (or region, layer, part, etc.) is referred to as being related to another element (such as "directly disposed" on another element), it means that no third element is disposed between the element and the other element. That is, when an element is "directly disposed" on another element, it means that the element and the other element are in "contact" with each other. Due to the contact, an interface can be formed therebetween.

[0034] Like reference numerals refer to like elements. In addition, in the drawings, the thickness, ratio, and dimensions of elements are exaggerated for the purpose of effectively describing the technical content.

[0035] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and a second element may also be referred to as a first element in a similar manner, without departing from the scope of the rights of the present utility model.

[0036] Unless the context clearly indicates otherwise, singular forms of terms may include plural forms. As used herein, "a", "the", and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, a reference to "a" element in a claim (followed by a reference to "the" element) includes one element and a plurality of elements. For example, unless the context clearly indicates otherwise, "element" and "at least one element" have the same meaning. "At least one" should not be construed as being limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. In the drawings and text of the present disclosure, reference numerals indicating the singular form of an element may also be used to refer to a plurality of singular elements.

[0037] In addition, terms such as "below", "under", "above", and "on" are used to describe the relationship of components shown in the drawings. These terms are used as relative concepts and are described with respect to the directions indicated in the drawings.

[0038] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation of that particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this utility model belongs. It should also be understood that terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the context of the prior art, and they are not to be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0040] It should be understood that the terms "comprising" or "having" are intended to specify the presence of the stated features, integers, steps, operations, elements, components, or combinations thereof in the present disclosure, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0041] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments. As such, variations in the shape of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein, but are to include deviations in shape, for example, resulting from manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features. Also, the sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of the regions and are not intended to limit the scope of the claims presented.

[0042] Hereinafter, embodiments of the present utility model will be described with reference to the accompanying drawings.

[0043] Figure 1 is a perspective view showing a display device DD according to an embodiment of the present utility model. Figure 2 is an exploded perspective view showing a display device DD according to an embodiment of the present utility model.

[0044] The display device DD can display an image IM via an active area AA-E. The active area AA-E can include a plane parallel to a plane defined by a first direction DR1 and a second direction DR2 that cross each other, or be disposed in a plane parallel to a plane defined by a first direction DR1 and a second direction DR2 that cross each other. A peripheral area NAA-E is adjacent to the active area AA-E. In a plan view, the peripheral area NAA-E can surround the active area AA-E. However, the peripheral area NAA-E can be disposed adjacent to only one side of the active area AA-E, or can be omitted.

[0045] The display device DD according to the present embodiment can include a housing HAU and a display module DM. The display module DM according to the present embodiment can include a display panel DP and a window member WM.

[0046] The window member WM can cover the entire outer side of the display module DM. The window member WM can include a transmissive area TA and a border area BZA. A front surface FS of the window member WM including the transmissive area TA and the border area BZA can correspond to or define a front surface of the display device DD. The transmissive area TA can correspond to Figure 1 the active area AA-E of the display device DD illustrated in Figure 1 and the border area BZA can correspond to

[0047] the peripheral area NAA-E of the display device DD illustrated in

[0048] The transmissive area TA can be an optically transparent area. The border area BZA can be an area having a relatively low light transmittance compared to the transmissive area TA. The border area BZA can have a predetermined color. The border area BZA is adjacent to the transmissive area TA and can surround the transmissive area TA in a plan view. However, the border area BZA can be disposed adjacent to only one side of the transmissive area TA, or a part of the border area BZA can be omitted. Figure 1 ). The display area DA of the display panel DP can be an area that is activated in response to an electrical signal. In the present embodiment, the display area DA can be an area in which an image IM (see Figure 1 ) is displayed. The display area DA of the display panel DP can correspond to Figure 1 the active area AA-E of the display device DD illustrated in

[0049] Although not shown in Figure 1 and Figure 2As shown in the figure, the input sensing unit serving as the input sensing layer can be provided on the display panel DP so as to face the display panel DP. The input sensing unit can sense an external input applied from the outside of the display module DM (or outside the display device DD). The external input can include various forms of external inputs such as light, heat, or pressure. The external input can be provided by an input tool such as a pen, a body part of a user, etc. The input sensing unit can be directly provided on the display panel DP or can be coupled to the display panel DP via a separate bonding member.

[0050] The housing HAU can accommodate the display panel DP and the like. The housing HAU can be coupled to the window member WM.

[0051] Figure 3 is a cross-sectional view of the display panel DP according to an embodiment of the present utility model. Illustratively, Figure 3 illustrates a cross-section of the display panel DP viewed from (or along) the first direction DR1. In the embodiment, Figure 3 the cross-section can also be defined as being viewed along the second direction DR2.

[0052] Referring to Figure 3 , the display panel DP can include a base layer BL, a circuit layer DP-CL provided on the base layer BL, a display element layer DP-OLED provided on the circuit layer DP-CL, and a encapsulation layer TFE provided on the display element layer DP-OLED. The display panel DP can include a display area DA and a non-display area NDA around the display area DA, but is not limited thereto.

[0053] The base layer BL can include a flexible plastic material such as polyimide (PI). The display element layer DP-OLED can be provided in the display area DA.

[0054] A plurality of pixels PX (see Figure 4 ) can be provided in the circuit layer DP-CL and the display element layer DP-OLED. Each of the pixels PX can include a transistor provided in the circuit layer DP-CL and a light-emitting element OLED (see Figure 5 ) provided in the display element layer DP-OLED and connected to one or more of the transistors. The structure of the pixel PX will be described in detail below.

[0055] The encapsulation layer TFE can be provided on the circuit layer DP-CL to cover the display element layer DP-OLED. The encapsulation layer TFE can protect the pixels PX from moisture, oxygen, and external foreign matters.

[0056] Figure 4 is a plan view of the display panel DP according to an embodiment of the present utility model.

[0057] Referring toFigure 4 , the display panel DP may include a scan driver SDV, a data driver DDV, a light-emitting driver EDV, and a plurality of pads PD in a pad region. The display panel DP may have a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2, but the planar shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA, but is not limited thereto.

[0058] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of light-emitting lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a first power line PL1 and a second power line PL2, and a connection line CNL. As used herein, "m" and "n" are natural numbers greater than 0.

[0059] The pixels PX may be disposed in the display area DA. The scan driver SDV and the light-emitting driver EDV may be disposed in the non-display area NDA adjacent to each of the long sides of the display panel DP. The data driver DDV may be disposed in the non-display area NDA adjacent to any one of the short sides of the display panel DP. When viewed in a plane, the data driver DDV may be adjacent to the lower end of the display panel DP closest to the pad region.

[0060] The scan lines SL1 to SLm may extend in the first direction DR1 to connect to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the second direction DR2 to connect to the pixels PX and the data driver DDV. The light-emitting lines EL1 to ELm may extend in the first direction DR1 to connect to the pixels PX and the light-emitting driver EDV.

[0061] The first power line PL1 may extend in the second direction DR2 and be disposed in the non-display area NDA. The first power line PL1 may be disposed between the display area DA and the light-emitting driver EDV.

[0062] The connection line CNL may extend in the first direction DR1 and be arranged in the second direction DR2 to connect to the first power line PL1 and the pixels PX. A first voltage may be applied to the pixels PX via the first power line PL1 and the connection line CNL connected to each other. The connection line CNL may be substantially defined as a part of the first power line PL1 for receiving the first voltage.

[0063] The second power line PL2 is provided in the non-display area NDA and can extend along the long side of the display panel DP and the other short side of the display panel DP where the data driver DDV is not provided. Compared with the scan driver SDV and the emission driver EDV, the second power line PL2 can be provided at a more peripheral position.

[0064] Although not illustrated, the second power line PL2 can extend toward the display area DA to be connected to the pixel PX. A second voltage having a level lower than the level of the first voltage can be applied to the pixel PX via the second power line PL2.

[0065] The first control line CSL1 is connected to the scan driver SDV and can extend toward the lower end of the display panel DP. The second control line CSL2 is connected to the emission driver EDV and can extend toward the lower end of the display panel DP. The data driver DDV can be provided between the first control line CSL1 and the second control line CSL2.

[0066] The pad PD is provided in the non-display area NDA adjacent to the lower end of the display panel DP and can be closer to the lower edge of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1 and the second power line PL2, the first control line CSL1 and the second control line CSL2 can be connected to the pad PD. The data lines DL1 to DLn are connected to the data driver DDV, and the data driver DDV can be connected to the pad PD corresponding to the data lines DL1 to DLn.

[0067] Although not illustrated, the display device DD (see Figure 1 ) can further include a timing controller for controlling the operations of the scan driver SDV, the data driver DDV, and the emission driver EDV, and a voltage generation unit for generating the first voltage and the second voltage. The timing controller and the voltage generation unit can be connected to the display panel DP at their corresponding pads PD via an external component such as a printed circuit board.

[0068] The scan driver SDV generates a plurality of scan signals as electrical signals, and the scan signals can be applied to the pixel PX via the scan lines SL1 to SLm. The data driver DDV generates a plurality of data voltages as electrical signals, and the data voltages can be applied to the pixel PX via the data lines DL1 to DLn. The emission driver EDV generates a plurality of emission signals as electrical signals, and the emission signals can be applied to the pixel PX via the emission lines EL1 to ELm.

[0069] The pixel PX can be provided with a data voltage in response to the scan signal. The pixel PX can display an image IM (see Figure 1 ) by emitting light having a brightness corresponding to the data voltage in response to the emission signal.

[0070] Figure 5 is a view showing an equivalent circuit of a pixel PXij according to an embodiment of the present invention. In Figure 5 , a pixel PXij connected to the i-th scan line SLi, the i-th emission line ELi, and the j-th data line DLj is exemplarily shown. Here, "i" and "j" represent natural numbers greater than 0.

[0071] Referring to Figure 5 , the pixel PXij may include a light-emitting element OLED and a pixel driving circuit PDC electrically connected to the light-emitting element OLED. The pixel driving circuit PDC may include transistors T1 to T7 and a capacitor CAP. The transistors T1 to T7 and the capacitor CAP may control the amount of current flowing in the light-emitting element OLED, and the light-emitting element OLED may generate light having a predetermined brightness according to the amount of current supplied thereto.

[0072] The i-th scan line SLi may include a first scan line to a third scan line GWi, GCi, and GIi of the i-th (hereinafter, also referred to as the first scan line to the third scan line). The first scan line GWi receiving the i-th write scan signal GWSi (hereinafter, also referred to as the write scan signal) may be defined as the i-th write scan line GWi. The second scan line GCi receiving the i-th compensation scan signal GCSi (hereinafter, also referred to as the compensation scan signal) may be defined as the compensation scan line GCi. The third scan line GIi receiving the i-th initialization scan signal GISi (hereinafter, also referred to as the initialization scan signal) may be defined as the initialization scan line GIi.

[0073] The transistors T1 to T7 may include a first transistor T1 to a seventh transistor T7. Each of the first transistor T1 to the seventh transistor T7 may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, the source electrode may be referred to as the source, the drain electrode may be referred to as the drain, and the gate electrode may be referred to as the gate.

[0074] In the present disclosure, "electrically connected (or connected) between a transistor and a signal line or between transistors" means that "an electrode of a transistor may have a unitary shape with a signal line to define a part of the signal line, or may be connected to the signal line via a third element such as a connection electrode".

[0075] The first transistor T1 to the seventh transistor T7 may each be a transistor having an oxide semiconductor layer as a semiconductor layer or a transistor having a low-temperature polysilicon (LTPS) semiconductor layer as a semiconductor layer. The first transistor T1 to the seventh transistor T7 may each be an N-type transistor or a P-type transistor. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may each be a PMOS transistor having an LTPS semiconductor layer, and the third transistor T3 and the fourth transistor T4 may each be an NMOS transistor having an oxide semiconductor layer. However, embodiments of the transistors T1 to T7 are not limited thereto. In addition, although an exemplary pixel driving circuit PDC including seven transistors T1 to T7 is illustrated, the number of transistors included in the pixel driving circuit PDC is not limited thereto.

[0076] The light-emitting element OLED may be defined as an organic light-emitting element. The light-emitting element OLED may include a first electrode AE and a second electrode CE. For example, the first electrode AE may be an anode, and the second electrode CE may be a cathode. The first electrode AE of the light-emitting element OLED may be electrically connected to a first voltage line VL1 that receives a first driving voltage ELVDD. The second electrode CE of the light-emitting element OLED may be electrically connected to a second voltage line VL2 that receives a second driving voltage ELVSS. The first voltage line VL1 may correspond to Figure 4 the first power line PL1 illustrated in Figure 4 and the second voltage line VL2 may correspond to

[0077] the second power line PL2 illustrated in.

[0078] The second transistor T2 may be electrically connected between the j-th data line DLj and the first transistor T1. The second transistor T2 may include a source connected to the j-th data line DLj, a drain connected to the second node ND2, and a gate connected to the first scan line GWi. The second transistor T2 and the first transistor T1 may be connected via the second node ND2. The second transistor T2 may be turned on by a write scan signal GWSi applied via the first scan line GWi. The second transistor T2 turned on by the write scan signal GWSi may transfer a data voltage Vd applied to the j-th data line DLj to the source of the first transistor T1. In the present embodiment, the second transistor T2 may be defined as a switching transistor.

[0079] The third transistor T3 may be connected between the fourth transistor T4 and the first transistor T1. The third transistor T3 may include a source connected to the first node ND1, a drain connected to the third node ND3, and a gate connected to the second scan line GCi. The third transistor T3 and the first transistor T1 may be connected via the third node ND3. The third transistor T3 may be turned on by a compensation scan signal GCSi applied via the second scan line GCi. The third transistor T3 turned on by the compensation scan signal GCSi may electrically connect the gate and the drain of the first transistor T1 to diode-connect the first transistor T1. In the present embodiment, the third transistor T3 may be defined as a compensation transistor.

[0080] The fourth transistor T4 may be electrically connected between the first initialization line VIL1 receiving the first initialization voltage Vint1 and the third transistor T3. The fourth transistor T4 may include a source connected to the first initialization line VIL1, a drain connected to the first node ND1, and a gate connected to the third scan line GIi. The fourth transistor T4 may be turned on by an initialization scan signal GISi applied via the third scan line GIi. The fourth transistor T4 turned on by the initialization scan signal GISi may transfer the first initialization voltage Vint1 to the first node ND1 to initialize the potential of the gate of the first transistor T1. In the present embodiment, the fourth transistor T4 may be defined as an initialization transistor.

[0081] The fifth transistor T5 may be electrically connected between the first voltage line VL1 receiving the first driving voltage ELVDD and the first transistor T1. The fifth transistor T5 may include a source connected to the first voltage line VL1, a drain connected to the second node ND2, and a gate connected to the i-th emission line ELi.

[0082] The sixth transistor T6 can be electrically connected between the first transistor T1 and the light-emitting element OLED. The sixth transistor T6 can include a source connected to the third node ND3, a drain connected to the first electrode AE of the light-emitting element OLED via the fourth node ND4, and a gate connected to the i-th light-emitting line ELi.

[0083] The fifth transistor T5 and the sixth transistor T6 can be turned on by a light-emitting signal ESi applied via the i-th light-emitting line ELi. The light-emitting duration of the light-emitting element OLED can be controlled by the light-emitting signal ESi. When the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current Id can be generated according to the voltage difference between the gate voltage of the first transistor T1 and the first driving voltage ELVDD, and the driving current Id can be supplied to the light-emitting element OLED via the sixth transistor T6, so that the light-emitting element OLED can emit light. In this embodiment, the fifth transistor T5 and the sixth transistor T6 can be defined as light-emitting control transistors.

[0084] The seventh transistor T7 can be electrically connected between the sixth transistor T6 and the second initialization line VIL2 that receives the second initialization voltage Vint2. The seventh transistor T7 can include a source connected to the fourth node ND4, a drain connected to the second initialization line VIL2, and a gate connected to the (i - 1)-th write scan line GWi-1. The gate of the seventh transistor T7 can be connected to the (i - 1)-th write scan line GWi-1 which is the previous stage of the i-th write scan line GWi. However, the embodiment of the present utility model is not limited thereto, and the gate of the seventh transistor T7 can be electrically connected to a separate fourth scan line.

[0085] The seventh transistor T7 can be turned on by the (i - 1)-th write scan signal GWSi-1 applied via the (i - 1)-th write scan line GWi-1. Through the turned-on seventh transistor T7, the second initialization voltage Vint2 can be transmitted to the fourth node ND4. The second initialization voltage Vint2 can have the same level as the first initialization voltage Vint1, but is not limited thereto, and can have a different level from the first initialization voltage Vint1. In this embodiment, the seventh transistor T7 can be defined as an initialization transistor.

[0086] The seventh transistor T7 can improve the ability of the pixel PXij to represent black. A part of the driving current Id can flow through the seventh transistor T7 as a bypass current. When a black image is displayed, the current with the amount of the current of the bypass current flowing through the seventh transistor T7 reduced from the driving current Id can be supplied to the light-emitting element OLED, so that the black image can be clearly displayed. That is, an accurate black luminance image can be achieved through the seventh transistor T7, so that the display device DD (see Figure 1)'s contrast ratio.

[0087] The capacitor CAP may include a first capacitor electrode receiving a first driving voltage ELVDD and a second capacitor electrode connected to a first node ND1. In the capacitor CAP, a charge corresponding to a voltage difference between the first capacitor electrode and the second capacitor electrode may be stored. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current (e.g., power current) flowing in the first transistor T1 may be determined based on the voltage stored in the capacitor CAP.

[0088] Figure 5 The configuration of the pixel driving circuit PDC illustrated in is merely exemplary, and the configuration of the pixel driving circuit PDC may be changed and implemented without being limited thereto.

[0089] Figure 6 is a cross-sectional view of a display panel DP according to an embodiment of the present utility model. Figure 6 Exemplarily illustrated are a light-emitting element OLED and some transistors T3 and T6 of the pixel driving circuit PDC (see Figure 5 ) connected to the light-emitting element OLED. The foregoing description may be applied to Figure 6 the components of the display panel DP illustrated in.

[0090] Referring to Figure 6 , the display panel DP may include a base layer BL and, in order from the base layer BL, a circuit layer DP-CL, a display element layer DP-OLED, and a packaging layer TFE.

[0091] The base layer BL may provide a base surface on which the circuit layer DP-CL is provided. The circuit layer DP-CL may include an insulating layer BFL and 10 to 80, transistors T3 and T6, and connection electrodes CNE11 to CNE13 and CNE-T. The insulating layer BFL and 10 to 80 may include a buffer layer BFL and a first insulating layer 10 to an eighth insulating layer 80 provided on the buffer layer BFL. However, the insulating layer included in the circuit layer DP-CL is not limited thereto and may vary depending on the configuration of the pixel driving circuit PDC included in the circuit layer DP-CL and the process for providing the circuit layer DP-CL. In an embodiment, one or more of the insulating layers BFL and 10 to 80 may be collectively referred to as an "insulating layer".

[0092] The buffer layer BFL can be disposed on the base layer BL. The buffer layer BFL can include at least one inorganic layer. For example, the buffer layer BFL can include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The buffer layer BFL can improve the bonding force between the semiconductor pattern layer (e.g., the sixth semiconductor pattern SP6) or the conductive pattern layer of the circuit layer DP-CL disposed on the base layer BL and the base layer BL.

[0093] Each of the first insulating layer 10 to the eighth insulating layer 80 can include an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The inorganic layer can include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the inorganic layer is not limited to the above examples. The organic layer can include at least one of acrylate resins (e.g., methacrylate resins), polyisoprene resins, ethylene resins, epoxy resins, urethane resins, cellulose resins, silicone resins, polyamide resins, and perylene resins. However, the material of the organic layer is not limited to the above examples.

[0094] The light-blocking pattern BML can be disposed on the buffer layer BFL. When the buffer layer BFL is omitted, the light-blocking pattern BML can be directly disposed on the base layer BL. The light-blocking pattern BML can include molybdenum. The light-blocking pattern BML can perform a shielding function. The light-blocking pattern BML can prevent the potential from affecting the transistors T1 to T7 due to the polarization phenomenon between the insulating layers 10 to 80 disposed on the light-blocking pattern BML (see Figure 5 ).

[0095] The sixth semiconductor pattern SP6 of the semiconductor layer can be disposed on the first insulating layer 10. The sixth semiconductor pattern SP6 can include a silicon semiconductor. For example, the sixth semiconductor pattern SP6 can include polysilicon or amorphous silicon. However, as long as the sixth semiconductor pattern SP6 has semiconductor characteristics, the material included in the sixth semiconductor pattern SP6 is not limited to the above examples.

[0096] Depending on whether it is doped, the sixth semiconductor pattern SP6 can include a plurality of regions having different electrical characteristics from each other. The first semiconductor pattern layer can include a first region having a high conductivity and a second region having a low conductivity. The first region can be doped with an N-type dopant or a P-type dopant. The P-type transistor can include a doped region that has been doped with a P-type dopant, and the N-type transistor can include a doped region that has been doped with an N-type dopant. The second region can be an undoped region, or a region doped to a lower concentration than the first region.

[0097] The conductivity (e.g., electrical conductivity) of the first region is greater than that of the second region, and the first region can substantially act as the source and drain of a transistor. The second region can substantially correspond to the channel (or active region) of the transistor. That is, in the first semiconductor pattern layer, the first region with high conductivity can be the source or drain of the transistor or a connecting signal line, and the second region with low conductivity can be the channel of the transistor.

[0098] The sixth semiconductor pattern SP6 can include a sixth source S6, a sixth channel A6, and a sixth drain D6. The sixth source S6 and the sixth drain D6 can extend from the sixth channel A6 in opposite directions from each other. That is, the sixth source S6 and the sixth drain D6 can be spaced apart on a plane, and the sixth channel A6 is interposed therebetween.

[0099] The first insulating layer 10 can be disposed on the buffer layer BFL. The first insulating layer 10 can cover the light-blocking pattern BML. The second insulating layer 20 can be disposed on the first insulating layer 10. The second insulating layer 20 can cover the sixth semiconductor pattern SP6.

[0100] The sixth gate electrode G6 can be disposed on the second insulating layer 20. The sixth gate electrode G6 can overlap with the sixth channel A6. In an embodiment, the sixth gate electrode G6 can act as a mask in the process of doping the sixth semiconductor pattern SP6.

[0101] Figure 6 The exemplary illustration shows that the sixth transistor T6 has a top-gate structure in which the sixth gate electrode G6 is disposed above the sixth semiconductor pattern SP6, but the embodiments of the present invention are not limited thereto, and the sixth transistor T6 can have a bottom-gate structure in which the sixth gate electrode G6 is disposed below the sixth semiconductor pattern SP6.

[0102] The aforementioned first transistor T1, second transistor T2, fifth transistor T5, and seventh transistor T7 (see Figure 5 ) can be transistors having the same structure as the sixth transistor T6. For example, the semiconductor patterns of the first transistor T1, second transistor T2, fifth transistor T5, and seventh transistor T7 (see Figure 5 ) can be formed from the first semiconductor pattern material layer in the same manner as the sixth semiconductor pattern SP6, and the gate electrodes of the first transistor T1, second transistor T2, fifth transistor T5, and seventh transistor T7 (see Figure 5 ) can be formed from the same conductive pattern material layer as the sixth gate electrode G6. However, the embodiments of the present invention are not necessarily limited thereto.

[0103] In an embodiment, when the semiconductor pattern and the sixth semiconductor pattern SP6 are formed of the first semiconductor pattern material layer in the same manner, such a semiconductor pattern may be in the same layer as the sixth semiconductor pattern SP6. Similarly, a gate electrode formed of the same conductive pattern material layer as the sixth gate electrode G6 may be in the same layer as the sixth gate electrode G6. Since they are in the same layer, the elements may be formed in the same process and / or include the same materials as each other, the elements may be corresponding parts of the same material layer, and the elements may be in the same layer by forming an interface with the same lower layer or the same upper layer, etc., but are not limited thereto.

[0104] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may cover the sixth gate electrode G6.

[0105] The scan line SL may be disposed on the third insulating layer 30. The scan line SL may correspond to some of the aforementioned first to third scan lines GWi, GCi, and GIi (see Figure 5 ).

[0106] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may cover the scan line SL.

[0107] The third semiconductor pattern SP3 may be disposed on the fourth insulating layer 40. The third semiconductor pattern SP3 may include an oxide semiconductor containing a metal oxide. The oxide semiconductor may include oxides of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium oxide (In2O3), titanium dioxide (TiO2), indium zinc tin oxide (IZTO), or zinc tin oxide (ZTO), etc. However, the embodiments of the present invention are not necessarily limited thereto.

[0108] Depending on whether the metal oxide is reduced, the third semiconductor pattern SP3 may include a plurality of regions having different electrical characteristics from each other. In the third semiconductor pattern SP3, a region where the metal oxide has been reduced (hereinafter, the reduced region) may have a higher conductivity than a region where the metal oxide has not been reduced (hereinafter, the non-reduced region). The reduced region may substantially serve as the source or drain of the transistor. The non-reduced region may substantially correspond to the channel (or active region) of the transistor.

[0109] The third semiconductor pattern SP3 may include a third source S3, a third channel A3, and a third drain D3. The third source S3 and the third drain D3 may extend from the third channel A3 in opposite directions from each other. That is, the third source S3 and the third drain D3 may be spaced apart on a plane, and the third channel A3 may be interposed therebetween.

[0110] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may cover the third semiconductor pattern SP3.

[0111] The third gate electrode G3 may be disposed on the fifth insulating layer 50. The third gate electrode G3 may overlap with the third channel A3. In an embodiment, the third gate electrode G3 may function as a mask in the process of doping the third semiconductor pattern SP3.

[0112] The third semiconductor pattern SP3 may overlap with a part of the scan line SL disposed below the third semiconductor pattern SP3. The part of the scan line SL that overlaps with the third semiconductor pattern SP3 may act as a gate of the third transistor T3 together with the third gate electrode G3. In this case, the third gate of the third transistor T3 may be doubly formed to have a sufficient amount of gate charge (e.g., electrical charge), and may be switched at high speed. In addition, since the scan line SL is disposed to overlap with the third semiconductor pattern SP3, it is possible to prevent the third semiconductor pattern SP3 from being damaged by light introduced from the lower part of the display panel DP. However, the above structure of the third transistor T3 is merely exemplary, and embodiments of the present invention are not limited thereto.

[0113] The aforementioned fourth transistor T4 (see Figure 5 ) may be a transistor having the same structure as the third transistor T3. For example, the semiconductor pattern of the fourth transistor T4 (see Figure 5 ) may be formed of the second semiconductor pattern material layer in the same manner as the third semiconductor pattern SP3, and the gate electrode of the fourth transistor T4 (see Figure 5 ) may be formed of the same conductive pattern material layer as the third gate electrode G3. However, embodiments of the present invention are not necessarily limited thereto.

[0114] The third semiconductor pattern SP3 of the third transistor T3 and the sixth semiconductor pattern SP6 of the sixth transistor T6 may be disposed on different layers (or in different layers), that is, corresponding patterns of different material layers. However, this is merely exemplary, and the semiconductor patterns of all the transistors included in the pixel driving circuit PDC (see Figure 5 ) may be disposed on the same layer (or in the same layer).

[0115] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may cover the third gate electrode G3.

[0116] The connection electrodes CNE11 to CNE13 may be disposed on the sixth insulating layer 60. The connection electrodes CNE11 to CNE13 may each have a structure in which metal materials such as titanium (Ti) / aluminum (Al) / titanium (Ti) are sequentially stacked along the thickness direction of the display panel DP. The display device DD (see Figure 1 ), and the thicknesses of the display panel DP and its various components or layers may be defined along the third direction DR3 (e.g., the thickness direction).

[0117] The connection electrodes CNE11 to CNE13 may include the 1-1 connection electrode CNE11 to the 1-3 connection electrode CNE13. The 1-1 connection electrode CNE11 to the 1-3 connection electrode CNE13 may be disposed at intervals from each other along the sixth insulating layer 60. In Figure 6 for convenience, the connection electrodes CNE11 to CNE13 are illustrated as having a flat upper surface by overlapping the entire contact holes CNT-11, CNT-12a, CNT-12b, and CNT-13 on a plane. In an embodiment, the connection electrodes CNE11 to CNE13 may be disposed along the inner surfaces of the contact holes CNT-11, CNT-12a, CNT-12b, and CNT-13.

[0118] The bridging electrodes BNE11, BNE12, and BNE13 may be disposed inside the contact holes CNT-11, CNT-12a, CNT-12b, and CNT-13. The connection electrodes CNE11 to CNE13 may be electrically connected to the semiconductor pattern layer via the bridging electrodes BNE11, BNE12, and BNE13. The bridging electrodes BNE11, BNE12, and BNE13 may include a first bridging electrode BNE11, a second bridging electrode BNE12, and a third bridging electrode BNE13. Details thereof will be described later.

[0119] The 1-1 connection electrode CNE11 may be connected to the sixth drain D6 of the sixth transistor T6 via the first bridging electrode BNE11. The 1-1 connection electrode CNE11 may be connected to the sixth drain D6 via the contact hole CNT-11 passing through the second insulating layer 20 to the sixth insulating layer 60 (or within the contact hole CNT-11 passing through the second insulating layer 20 to the sixth insulating layer 60).

[0120] The 1-2 connection electrode CNE12 may be connected to the sixth source S6 of the sixth transistor T6 via the second bridging electrode BNE12. The 1-2 connection electrode CNE12 may be connected to the sixth source S6 via the contact hole CNT-12a passing through the second insulating layer 20 to the sixth insulating layer 60.

[0121] The 1-2 connection electrode CNE12 can extend along a plane from the contact hole CNT-12a to overlap with the third drain D3 of the third transistor T3. The 1-2 connection electrode CNE12 can be further connected to the third drain D3 via a contact hole CNT-12b passing through the fifth insulating layer 50 and the sixth insulating layer 60. Accordingly, the third semiconductor pattern SP3 of the third transistor T3 and the sixth semiconductor pattern SP6 of the sixth transistor T6 provided in different layers from each other can be electrically connected to each other through the same connection electrode (e.g., the 1-2 connection electrode CNE12).

[0122] The 1-3 connection electrode CNE13 can be connected to the third source S3 of the third transistor T3 via the third bridging electrode BNE13. The 1-3 connection electrode CNE13 can be connected to the third source S3 via a contact hole CNT-13 passing through the fifth insulating layer 50 and the sixth insulating layer 60.

[0123] The seventh insulating layer 70 can be provided on the sixth insulating layer 60. The seventh insulating layer 70 can cover the 1-1 connection electrode CNE11 to the 1-3 connection electrode CNE13. The seventh insulating layer 70 can be an organic layer.

[0124] The upper connection electrode CNE-T can be provided on the seventh insulating layer 70. In addition, although not shown separately, some of the signal lines included in the display panel DP can be formed of the same conductive pattern material layer in the circuit layer DP-CL.

[0125] The upper connection electrode CNE-T can be connected to the 1-1 connection electrode CNE11 via an upper contact hole CNT-2 passing through the seventh insulating layer 70. The seventh insulating layer 70 can include a third connection electrode CNE3 that defines the seventh insulating layer 70 (see Figure 8D ) and a part of which is exposed to the outside of the seventh insulating layer 70 at the side surface of the upper contact hole CNT-2. Although Figure 6 it is illustrated that the width of the upper contact hole CNT-2 passing through the seventh insulating layer 70 is narrower than the widths of the contact holes CNT-12a and CNT-12b passing through the fifth insulating layer 50 and the sixth insulating layer 60, in an embodiment of the present invention, the width of the upper contact hole CNT-2 passing through the seventh insulating layer 70 can be greater than the widths of the contact holes CNT-12a and CNT-12b passing through the fifth insulating layer 50 and the sixth insulating layer 60. Here, the width of an element such as a contact hole can be defined along a plane. The width can be defined at different positions along the thickness or height of the element. The representative width of the element can be the maximum width, the minimum width, or a width therebetween.

[0126] Although not illustrated, when a plurality of upper contact holes CNT-2 passing through the seventh insulating layer 70 are provided, the separation distance between the upper contact holes CNT-2 passing through the seventh insulating layer 70 may be greater than the separation distance between the contact holes CNT-12a and CNT-12b passing through the fifth insulating layer 50 and the sixth insulating layer 60. Accordingly, the width of the upper contact holes CNT-2 passing through the seventh insulating layer 70 may be greater than the width of the contact holes CNT-12a and CNT-12b passing through the fifth insulating layer 50 and the sixth insulating layer 60.

[0127] The upper connection electrode CNE-T may be connected to the sixth drain D6 of the sixth transistor T6 via the 1-1 connection electrode CNE11. However, embodiments of the present invention are not limited thereto, and the upper connection electrode CNE-T may be omitted, or additional connection electrodes provided between the upper connection electrode CNE-T and the 1-1 connection electrode CNE11 may be further provided in the circuit layer DP-CL.

[0128] The eighth insulating layer 80 may be provided on the seventh insulating layer 70. The eighth insulating layer 80 may cover the upper connection electrode CNE-T. In the present specification, the eighth insulating layer 80 may be an organic layer.

[0129] At least one of the seventh insulating layer 70 and the eighth insulating layer 80 may include an organic layer. The organic layer may provide a flat surface by covering the steps between the particles present on the surface of the layer provided below the organic layer or between the components provided below the organic layer, so as to planarize the surface. In addition, the organic layer may relieve the stress between the components provided above and below the organic layer.

[0130] The display element layer DP-OLED may be provided on the circuit layer DP-CL. The display element layer DP-OLED may include a pixel defining film PDL and a light emitting element OLED. Each of the light emitting elements OLED may include a first electrode AE, a light emitting layer EM, and a second electrode CE.

[0131] The light emitting element OLED may include an organic light emitting element, a quantum dot light emitting element, a micro LED light emitting element, or a nano LED light emitting element. However, embodiments of the present invention are not limited thereto, and as long as light is generated or the amount of light is controlled in response to an electrical signal, the light emitting element OLED may include various embodiments.

[0132] Each of the light emitting elements OLED may be electrically connected to a transistor of a corresponding pixel driving circuit PDC (see Figure 5 ). Figure 6 Exemplarily illustrated is that each of the light emitting elements OLED is electrically connected to a corresponding sixth transistor T6.

[0133] The first electrode AE of the light-emitting element OLED may be disposed on the uppermost layer of the circuit layer DP-CL. For example, the first electrode AE may be disposed on the eighth insulating layer 80. The first electrode AE may be disposed at intervals along the eighth insulating layer 80. Each of the first electrodes AE may be connected to a corresponding upper connection electrode CNE-T via a contact hole CNT-U passing through the eighth insulating layer 80. Each of the first electrodes AE may be electrically connected to the sixth drain D6 via the corresponding upper connection electrode CNE-T together with the 1-1 connection electrode CNE11.

[0134] The pixel defining film PDL may be disposed on the uppermost layer of the circuit layer DP-CL. For example, the pixel defining film PDL may be disposed on the eighth insulating layer 80. In the pixel defining film PDL, a light-emitting opening PX-OP that overlaps each of the first electrodes AE and exposes a part of the corresponding first electrode AE to the outside of the pixel defining film PDL may be defined. The solid part of the pixel defining film PDL may define the light-emitting opening PX-OP.

[0135] In this embodiment, the area of the first electrode AE exposed by the light-emitting opening PX-OP may correspond to the light-emitting area PXA. That is, the display area DA of the display panel DP (see Figure 4 ) may include the light-emitting area PXA. The area (or planar region) where the solid part or material part of the pixel defining film PDL is provided may correspond to the non-light-emitting area NPXA. On a plane, the non-light-emitting area NPXA is adjacent to the light-emitting area PXA so as to surround the light-emitting area PXA, and the boundary of the light-emitting area PXA may be set with respect to the non-light-emitting area NPXA.

[0136] The pixel defining film PDL as the pixel defining layer may include a polymer resin. For example, the pixel defining film PDL may include a polyacrylate resin or a polyimide resin. Without being limited thereto, the pixel defining film PDL may further include an inorganic material.

[0137] The pixel defining film PDL may further include a light absorption material. For example, the pixel defining film PDL may include a black colorant such as a black dye or a black pigment. For example, the black colorant may include carbon black, a metal such as chromium, or an oxide thereof. However, the embodiments of the present invention are not necessarily limited thereto.

[0138] The light-emitting layer EM can be disposed on the first electrode AE. The light-emitting layer EM of the light-emitting element OLED can be correspondingly disposed with the light-emitting opening PX-OP respectively, and can be formed into a light-emitting pattern spaced apart on a plane. The light-emitting pattern can be a discrete shape along the plane. However, not limited thereto, the light-emitting layer EM of the light-emitting element OLED can be formed into a common layer by being formed as a single film across the pixel PX. The light-emitting layer EM can include an organic light-emitting material and / or an inorganic light-emitting material. For example, the light-emitting layer EM can include a fluorescent material, a phosphorescent material, an organometallic composite light-emitting material, or a quantum dot. The light-emitting layer EM can emit color light of any one of red, green, and blue.

[0139] The second electrode CE can be disposed on the light-emitting layer EM. The second electrode CE of the light-emitting element OLED can be provided as a common layer of monomers, and can overlap both the light-emitting region PXA and the non-light-emitting region NPXA. The second electrode CE is commonly disposed in the pixel PX (see Figure 4 ), and can be provided with a common voltage.

[0140] The light-emitting element OLED can further include a light-emitting control layer disposed between the first electrode AE and the second electrode CE. For example, the light-emitting control layer can include a hole control layer disposed between the first electrode AE and the light-emitting layer EM or an electron control layer disposed between the light-emitting layer EM and the second electrode CE. The hole control layer can include a hole injection layer, a hole transport layer, or an electron blocking layer, and the electron control layer can include an electron injection layer, an electron transport layer, or a hole blocking layer.

[0141] The encapsulation layer TFE can be disposed on the display element layer DP-OLED. The encapsulation layer TFE can seal the light-emitting element OLED. The encapsulation layer TFE can include at least one thin film of an inorganic film and an organic film. In an embodiment, the encapsulation layer TFE can include an inorganic film and an organic film disposed between the inorganic films.

[0142] The inorganic film of the encapsulation layer TFE can protect the light-emitting element OLED from the influence of moisture and / or oxygen. The inorganic film can include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the inorganic film is not limited to the above examples.

[0143] The organic film of the encapsulation layer TFE can protect the light-emitting element OLED from foreign substances such as dust particles. The organic film can include an acrylic resin. However, the material of the organic film is not limited to the above examples.

[0144] The first driving voltage ELVDD (see Figure 5 ) can be applied to the first electrode AE, and the second driving voltage ELVSS (see Figure 5) can be applied to the second electrode CE. Holes and electrons injected into the light-emitting layer EM recombine to form excitons, and when the excitons transition to the ground state, the light-emitting element OLED can emit light. Since the light-emitting element OLED emits light in response to an electrical signal applied thereto, the display panel DP can display an image IM (see Figure 4 ) through the display area DA (see Figure 1 ).

[0145] Figure 7 is Figure 6 an enlarged view of the region AA' of. Specifically, Figure 7 is a view showing the contact holes CNT-12b, the 1-2 connection electrode CNE12, and the second bridging electrode BNE12. Hereinafter, for ease of description, the 1-2 connection electrode CNE12 will be referred to as the connection electrode CNE, and the second bridging electrode BNE12 will be referred to as the bridging electrode BNE.

[0146] Referring to Figure 7 , the connection electrode CNE and the bridging electrode BNE can be connected to the third semiconductor pattern SP3 within the contact hole CNT-12b passing through the fifth insulating layer 50 and the sixth insulating layer 60 which are collective insulating layers. When passing through the layer, the hole or opening can extend through the entire thickness of the layer such that the hole or opening is open at both the upper surface and the lower surface of the layer. The connection electrode CNE can be electrically connected to the third semiconductor pattern SP3 via the bridging electrode BNE provided on the side surfaces of the fifth insulating layer 50 and the sixth insulating layer 60. In the present specification, the fifth insulating layer 50 may be referred to as the "first insulating layer", and the sixth insulating layer 60 may be referred to as the "second insulating layer".

[0147] The material included in the fifth insulating layer 50 which is the first thickness portion of the collective insulating layer is different from the material included in the sixth insulating layer 60 which is the second thickness portion of the collective insulating layer. The fifth insulating layer 50 includes silicon oxide, and the sixth insulating layer 60 includes silicon nitride. The fifth insulating layer 50 may be composed of silicon oxide, and the sixth insulating layer 60 may be composed of silicon nitride.

[0148] The contact hole CNT-12b may include a first hole H1 (e.g., a first hole portion) defined by the fifth insulating layer 50 together with a second hole H2 (e.g., a second hole portion) defined by the sixth insulating layer 60. The first hole H1 and the second hole H2 may be aligned with each other. The first hole H1 may be defined by a first side surface SS1 of the fifth insulating layer 50, and the second hole H2 may be defined by a second side surface SS2 of the sixth insulating layer 60. The first side surface SS1 and the second side surface SS2 may be coplanar with each other. The first hole H1 may expose at least a part of the upper surface of the third semiconductor pattern SP3 to the outside of the fifth insulating layer 50. The virtual center line of the first hole H1 and the virtual center line of the second hole H2 may be substantially the same. The first hole H1 and the second hole H2 may be aligned in a column along the thickness direction.

[0149] In an embodiment, the size of the first hole H1 and the size of the second hole H2 are equal to each other. The size may refer to a planar size such as a scale along a plane. The size of the first hole H1 and the size of the second hole H2 may be constant along the direction in which the contact hole CNT-12b extends (i.e., the third direction DR3). The shape of the first hole H1 and the shape of the second hole H2 are not limited thereto, and may have different sizes or scales along the plane at different positions along the third direction DR3.

[0150] The width W1 of the contact hole CNT-12b may be about 0.5 micrometers (μm) to about 2 micrometers (μm). For example, the width W1 of the contact hole CNT-12b may be about 1μm to about 1.8μm. The width W1 of the contact hole CNT-12b may be constant along the direction in which the contact hole CNT-12b is recessed (i.e., along the entire third direction DR3).

[0151] The recessed depth L1 (also referred to as the depth) of the contact hole CNT-12b may be about 1μm or greater. For example, the recessed depth L1 of the contact hole CNT-12b may be about 1μm to about 1.5μm. The recessed depth L1 may be the total depth of the contact hole CNT-12b including the sum of the thicknesses of the fifth insulating layer 50 and the sixth insulating layer 60.

[0152] The bridging electrode BNE may be disposed on the side surfaces SS1 and SS2 of the insulating layers 50 and 60. The bridging electrode BNE may directly contact the third semiconductor pattern SP3. The bridging electrode BNE is disposed along the side surfaces SS1 and SS2 of the insulating layers 50 and 60, and thus may extend perpendicular or orthogonal to the third semiconductor pattern SP3. The uppermost surface of the bridging electrode BNE may be coplanar with the upper surface defined by the upper surface of the sixth insulating layer 60 of the insulating layer.

[0153] The thickness of the bridging electrode BNE in the first direction DR1 is shown to be constant at different positions along the third direction DR3, but embodiments of the present invention are not limited thereto, and the thickness of the bridging electrode BNE may vary at a plurality of positions along the third direction DR3. For example, the thickness of the bridging electrode BNE measured in a direction orthogonal to the corresponding inner surface of the layer may gradually increase in a direction opposite to the recessed direction of the contact hole CNT-12b (that is, the third direction DR3). That is, the thickness may decrease as the distance to the semiconductor layer decreases. The thickness may be maximum at the upper surface of the collective insulating layer. The length of the bridging electrode BNE defined along the thickness direction may be equal to the recessed depth L1 of the contact hole CNT-12b.

[0154] The connection electrode CNE may include a first connection electrode CNE1 (for example, a first electrode portion) provided on the upper surface of the sixth insulating layer 60 and on the bridging electrode BNE and extending into the corresponding contact hole, and a second connection electrode CNE2 (for example, a second electrode portion) provided on the third semiconductor pattern SP3 and disconnected from the first electrode portion. The first connection electrode CNE1 and the second connection electrode CNE2 may include the same material as each other. For example, the first connection electrode CNE1 and the second connection electrode CNE2 may each have a structure in which a titanium (Ti) / aluminum (Al) / titanium (Ti) metal material is sequentially stacked.

[0155] According to an embodiment of the present invention, the bridging electrode BNE may include a material different from the materials of the first connection electrode CNE1 and the second connection electrode CNE2. For example, when the bridging electrode BNE contacts the third semiconductor pattern SP3, the bridging electrode BNE may include an N-type dopant. However, it is not limited thereto, and the material constituting the bridging electrode BNE may vary depending on the object electrically connected to the connection electrode CNE (for example, a semiconductor pattern or a metal layer). For example, the bridging electrode BNE may include a P-type dopant, or may include amorphous silicon (a-Si) or polycrystalline silicon.

[0156] The first connection electrode CNE1 and the second connection electrode CNE2 may be disposed spaced apart from each other. Different electrode portions may be disconnected from each other at positions along the inner sidewall of the insulating layer. The first connection electrode CNE1 and the second connection electrode CNE2 may be electrically connected to each other via a bridging electrode BNE. The first connection electrode CNE1 may be disposed spaced apart from the third semiconductor pattern SP3. The first connection electrode CNE1 and the third semiconductor pattern SP3 may be electrically connected to each other via a bridging electrode BNE. That is, the first connection electrode CNE1 may be directly and electrically connected to the third semiconductor pattern SP3 via the bridging electrode BNE, or may be connected to the second connection electrode CNE2 via the bridging electrode BNE and electrically connected to the third semiconductor pattern SP3, and the third semiconductor pattern SP3 is electrically connected to the second connection electrode CNE2.

[0157] When the display device DD (see Figure 1 ) has a high resolution, the planar width of the connection electrode CNE and the planar width of the contact hole CNT-12b are reduced to construct a pixel layout within a limited pixel pitch. When the width of the contact hole CNT-12b is reduced, due to the problem of step coverage in the process, the connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 that are disposed spaced apart (e.g., separated from each other). However, when the bridging electrode BNE extends along the inner surface of the insulating layers 50 and 60 that define the contact hole CNT-12b, the first connection electrode CNE1 and the second connection electrode CNE2 may be electrically connected to each other via the bridging electrode BNE. As a result, even when the number of signal lines increases and the integration degree of the circuit increases, the separated first connection electrode CNE1 and second connection electrode CNE2 are electrically connected to each other and function as a single connection electrode, so that the display device DD of the present utility model can have characteristics of high resolution, high-speed driving, and high robustness.

[0158] Figures 8A to 8C is an enlarged view of a part of a display device DD (see Figure 1 ) according to an embodiment of the present utility model. Figures 8A to 8C is Figure 6 an enlarged view of the region AA' of Figure 7 and shows an embodiment different from the embodiment shown in

[0159] Features that are the same as those described above will be briefly described or omitted. Figure 8A, the bridging electrode BNEa may be disposed on a part of the side surfaces SS1 and SS2 of the insulating layers 50 and 60. Specifically, the bridging electrode BNEa may be disposed on the entire first side surface SS1 of the fifth insulating layer 50 and on a part of the second side surface SS2 of the sixth insulating layer 60. The length L2 of the bridging electrode BNEa in the third direction DR3 may be less than the recess depth L1 of the contact hole CNT-12b. That is, the uppermost surface of the bridging electrode BNEa may be spaced apart from the upper surface of the insulating layer defined by the upper surface of the sixth insulating layer 60. The bridging electrode BNEa may have an upper surface closest to the upper surface of the insulating layer. The part of the side surface of the insulating layer between the upper surface of the insulating layer and the upper surface of the bridging electrode BNEa may be exposed to the outside of the bridging electrode BNEa.

[0160] The connecting electrode CNEa may include a first connecting electrode CNE1a disposed on the upper surface of the sixth insulating layer 60, a part of the second side surface SS2, and the bridging electrode BNEa, and a second connecting electrode CNE2 disposed on the third semiconductor pattern SP3. The first connecting electrode CNE1a may directly contact the upper surface of the bridging electrode BNEa and the part of the side surface of the insulating layer exposed to the outside of the bridging electrode BNEa. The first connecting electrode CNE1a and the second connecting electrode CNE2 may include the same material. For example, the first connecting electrode CNE1a and the second connecting electrode CNE2 may have a structure in which a titanium (Ti) / aluminum (Al) / titanium (Ti) metal material is sequentially stacked. The bridging electrode BNEa may include a material different from the materials of the first connecting electrode CNE1a and the second connecting electrode CNE2. For example, the bridging electrode BNEa may include an N-type dopant.

[0161] The first connecting electrode CNE1a and the second connecting electrode CNE2 may be spaced apart from each other. The first connecting electrode CNE1a and the second connecting electrode CNE2 may be electrically connected to each other via the bridging electrode BNEa.

[0162] Referring to Figure 8B , the connecting electrode may not be disposed in direct contact with the third semiconductor pattern SP3. Figure 7 The connecting electrode CNE illustrated in Figure 8B includes a first connecting electrode CNE1 disposed on the upper surface of the sixth insulating layer 60 and on the bridging electrode BNE, and a second connecting electrode CNE2 disposed on the third semiconductor pattern SP3. In contrast, in

[0163] The first connection electrode CNE1 may be disposed at a distance from the third semiconductor pattern SP3, and a part of the first side surface SS1 may be exposed outside the contact hole CNT-12b at a region between the first connection electrode CNE1 and the third semiconductor pattern SP3. Here, this region may be defined in the DR3-DR2 plane. The first connection electrode CNE1 and the third semiconductor pattern SP3 may be electrically connected to each other via a bridging electrode BNE that contacts each of the first connection electrode CNE1 and the third semiconductor pattern SP3. That is, the first connection electrode CNE1 may be electrically connected to the third semiconductor pattern SP3 via the bridging electrode BNE.

[0164] Referring to Figure 8C , the contact hole CNT-12ba may include a first hole H1a (e.g., a first hole portion) defined by the first side surface SS1a of the fifth insulating layer 50a and a second hole H2a (e.g., a second hole portion) defined by the second side surface SS2a of the sixth insulating layer 60a. The second width W2 of the first hole H1a and the third width W3 of the second hole H2a may be different from each other. For example, the third width W3 of the second hole H2a may be greater than the second width W2 of the first hole H1a. The difference between the third width W3 of the second hole H2a and the second width W2 of the first hole H1a may be about 0.2 μm or greater. For example, the difference in the first direction DR1 between the third width W3 of the second hole H2a and the second width W2 of the first hole H1a may be about 0.2 μm to about 0.3 μm. However, the difference between the third width W3 of the second hole H2a and the second width W2 of the first hole H1a is not limited to the above numerical range, and the difference between the third width W3 of the second hole H2a and the second width W2 of the first hole H1a may occur depending on the materials of the fifth insulating layer 50a and the sixth insulating layer 60a or the etching method used in the process of forming the corresponding contact hole, and may accordingly have different values.

[0165] The bridging electrode BNEb may be directly and commonly disposed on the first side surface SS1a and the second side surface SS2a. The bridging electrode BNEb may directly contact the third semiconductor pattern SP3. The bridging electrode BNEb is disposed along the first side surface SS1a and the second side surface SS2a, and thus may include a step according to the difference between the third width W3 of the second hole H2a and the second width W2 of the first hole H1a. The thickness of the bridging electrode BNEb measured in a direction orthogonal to the corresponding inner side surface of the insulating layer may have a constant value at corresponding positions along the contact hole CNT-12ba (e.g., along the third direction DR3).

[0166] The connection electrode CNEb may include a first connection electrode CNE1b and a second connection electrode CNE2. The first connection electrode CNE1b and the second connection electrode CNE2 may be spaced apart from each other. The first connection electrode CNE1b and the third semiconductor pattern SP3 may be electrically connected to each other via a bridging electrode BNEb. That is, the first connection electrode CNE1b may be directly and electrically connected to the third semiconductor pattern SP3 via the bridging electrode BNEb, or may be connected to the second connection electrode CNE2 via the bridging electrode BNEb and electrically connected to the third semiconductor pattern SP3, and the third semiconductor pattern SP3 is electrically connected to the second connection electrode CNE2.

[0167] Figure 8D is Figure 6 an enlarged view of the region BB' of. Specifically, Figure 8D is a view showing Figure 6 the contact hole CNT-11, the 1-1 connection electrode CNE11, and the first bridging electrode BNE11 of.

[0168] Referring to Figure 8D , the 1-1 connection electrode CNE11 and the first bridging electrode BNE11 may be connected to the sixth semiconductor pattern SP6 via the contact hole CNT-11 passing through the second to sixth insulating layers 20, 30, 40, 50, and 60. Specifically, the 1-1 connection electrode CNE11 may include a third connection electrode CNE3 as a third electrode portion provided on the upper surface of the sixth insulating layer 60 and on the first bridging electrode BNE11, and a fourth connection electrode CNE4 as a fourth electrode portion provided on the sixth semiconductor pattern SP6. The third connection electrode CNE3 and the fourth connection electrode CNE4 may each have a structure in which a titanium (Ti) / aluminum (Al) / titanium (Ti) metal material is sequentially stacked.

[0169] According to an embodiment of the present invention, the first bridging electrode BNE11 may include a material different from the materials of the third connection electrode CNE3 and the fourth connection electrode CNE4. For example, when the first bridging electrode BNE11 contacts the sixth semiconductor pattern SP6, the first bridging electrode BNE11 may include a P-type dopant. However, not limited thereto, the material constituting the first bridging electrode BNE11 may vary depending on the object (e.g., a semiconductor pattern or a metal layer) electrically connected to the 1-1 connection electrode CNE11. For example, the first bridging electrode BNE11 may include an N-type dopant, or may include amorphous silicon (a-Si) or polycrystalline silicon.

[0170] The third connection electrode CNE3 and the fourth connection electrode CNE4 may be spaced apart from each other. The third connection electrode CNE3 and the fourth connection electrode CNE4 may be electrically connected to each other via the first bridging electrode BNE11. The third connection electrode CNE3 may be spaced apart from the sixth semiconductor pattern SP6. The third connection electrode CNE3 and the sixth semiconductor pattern SP6 may be electrically connected to each other via the first bridging electrode BNE11.

[0171] Figure 9A is a cross-sectional view of a display panel DPa according to an embodiment of the present invention. Figure 9B is Figure 9A an enlarged view of the region CC' of. Redundant descriptions of the components of the display panel DPa illustrated in Figure 9A will be omitted.

[0172] Referring to Figure 9A , the upper bridging electrode BNE2 may be disposed in the upper contact hole CNT-2. The upper connection electrode CNE-T may be connected to the 1-1 connection electrode CNE11 via the upper contact hole CNT-2 passing through the seventh insulating layer 70. Specifically, the upper connection electrode CNE-T may be connected to the 1-1 connection electrode CNE11 via the upper bridging electrode BNE2.

[0173] Figure 9B is Figure 9A an enlarged view of the upper contact hole CNT-2, the upper connection electrode CNE-T, and the upper bridging electrode BNE2 of. Referring to Figure 9A and Figure 9B , the upper bridging electrode BNE2 may be disposed on a side surface of the seventh insulating layer 70 defining the upper contact hole CNT-2. The upper bridging electrode BNE2 may directly contact the 1-1 connection electrode CNE11. The upper bridging electrode BNE2 may be disposed along the side surface of the seventh insulating layer 70. The upper bridging electrode BNE2 may contact a portion of the third connection electrode CNE3 exposed outside the seventh insulating layer 70.

[0174] The upper connection electrode CNE-T may be disposed on the upper surface of the seventh insulating layer 70, extend into the upper contact hole CNT-2, and extend along the upper bridging electrode BNE2. According to an embodiment of the present invention, the upper bridging electrode BNE2 may include a material different from that of the upper connection electrode CNE-T. For example, the upper bridging electrode BNE2 may include amorphous silicon (a-Si) or polysilicon.

[0175] The upper connection electrode CNE-T and the 1-1 connection electrode CNE11 can be disposed at intervals from each other along the sidewall of the seventh insulating layer 70. The upper connection electrode CNE-T and the 1-1 connection electrode CNE11 can be electrically connected to each other via the upper bridging electrode BNE2. The upper connection electrode CNE-T can electrically connect the light-emitting element OLED to the 1-1 connection electrode CNE11, and the upper connection electrode CNE-T can be directly on the upper bridging electrode BNE2 and spaced apart from the portion of the third connection electrode CNE3 exposed outside the seventh insulating layer 70. Although Figure 9A and Figure 9B the upper bridging electrode BNE2 in Figure 8A or Figure 8C is shown as coplanar with the upper surface of the seventh insulating layer 70, the upper bridging electrode BNE2 can have a form similar to that of

[0176] Figures 10A to 10E is a cross-sectional view showing the structure of the sequential processes in the method for manufacturing (or providing) the display device DD (see Figure 1 ) according to an embodiment of the present invention.

[0177] Referring to Figure 10A and Figure 10B , the method for manufacturing (or providing) the display device DD according to an embodiment of the present invention may include providing a semiconductor pattern SP of a transistor, a first insulating layer 50 provided on the semiconductor pattern SP, a second insulating layer 60 provided on the first insulating layer 50, and forming (or providing) contact holes CNT in the insulating layer including both the first insulating layer 50 and the second insulating layer 60. In the present specification, the semiconductor pattern SP may mean the third semiconductor pattern SP3 of the semiconductor layer described above with reference to Figure 7 or the sixth semiconductor pattern SP6 of the semiconductor layer described above with reference to Figure 8D , or may mean another electrode having conductivity, etc. In addition, the contact hole CNT may mean the contact hole CNT-12b in Figure 7 or the contact hole CNT-11 in Figure 8D . That is, the semiconductor pattern SP represents a first conductive pattern that is exposed at the bottom of the contact hole and to which the second conductive pattern is electrically connected via the bridging conductive pattern.

[0178] The formation of the contact hole CNT may include forming a photoresist pattern PR on the second insulating layer 60. Thereafter, the formation of the contact hole CNT may include performing an etching process on the first insulating layer 50 and the second insulating layer 60. The etching process of the first insulating layer 50 and the second insulating layer 60 may include a plasma etching process performed by using the photoresist pattern PR as a mask. Since the contact hole CNT is formed, at least a part of the upper surface of the semiconductor pattern SP may be exposed outside the insulating layer. The sidewalls of the insulating layer define the contact hole CNT. The upper surface of the insulating layer may be the surface farthest from the exposed conductive pattern. The photoresist pattern PR may be removed from the upper surface of the insulating layer to expose the upper surface to Figure 10B the outside of the stacked structure shown in

[0179] Referring to Figure 10C and Figure 10D , a method for manufacturing a display device DD according to an embodiment of the present invention may include forming a bridging electrode BNE inside the contact hole CNT. In the present specification, the bridging electrode BNE may mean the bridging electrode BNE in Figure 7 or the first bridging electrode BNE11 in Figure 8D .

[0180] The formation of the bridging electrode BNE may include: forming a preliminary bridging electrode BNE-P of a bridging electrode material layer on the upper surface of the second insulating layer 60, extending into the contact hole CNT, along the side surface of the second insulating layer 60 and the side surface of the first insulating layer 50, and the semiconductor pattern SP; and etching the preliminary bridging electrode BNE-P.

[0181] The formation of the preliminary bridging electrode BNE-P may include a chemical vapor deposition (CVD) method of a silicon (Si)-based gas containing a low-concentration N-type dopant to have a constant resistance. For example, the preliminary bridging electrode BNE-P may be formed by depositing silicon (Si) containing an N-type dopant on the upper surface of the second insulating layer 60, the side surface of the second insulating layer 60, the side surface of the first insulating layer 50, and the semiconductor pattern SP by a method such as plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure CVD (APCVD), or low-pressure CVD (LPCVD).

[0182] The preliminary bridging electrode BNE-P may have a constant thickness in the third direction DR3. The thickness may be defined in a direction orthogonal to the profile of the underlying stacked structure (that is, orthogonal to the upper surface of the insulating layer, orthogonal to the side surfaces defining the contact hole CNT, and orthogonal to the upper surface of the exposed semiconductor pattern SP at the bottom of the contact hole CNT). However, embodiments of the present invention are not limited thereto, and the thickness of the preliminary bridging electrode BNE-P in the third direction DR3 may gradually decrease along the recessed direction of the contact hole CNT. That is, the thickness of the bridging electrode material layer decreases as the distance from the upper surface of the insulating layer increases along the thickness direction of the display device DD.

[0183] The etching of the preliminary bridging electrode BNE-P may include a plasma etching process. By performing plasma etching on the preliminary bridging electrode BNE-P, the portion of the preliminary bridging electrode BNE-P extending along the upper surface of the second insulating layer 60 and the portion of the preliminary bridging electrode BNE-P extending along the upper surface of the semiconductor pattern SP can be removed. Accordingly, the bridging electrode BNE formed only on the side surfaces of the insulating layers 50 and 60 can be provided. Depending on the time and intensity of the plasma etching process, the length of the bridging electrode BNE along the thickness direction can be formed to be less than the recessed depth of the contact hole CNT.

[0184] Referring to Figure 10E , a method for manufacturing a display device DD according to an embodiment of the present invention may include forming a connection electrode CNE inside the contact hole CNT. In this specification, the connection electrode CNE may mean Figure 7 the above-mentioned connection electrode CNE. The formation of the connection electrode CNE may include disposing the connection electrode CNE in the contact hole CNT and on the second insulating layer 60.

[0185] The connection electrode CNE can be formed by deposition in the contact hole CNT and on the second insulating layer 60. For example, the connection electrode CNE can be formed by a sputtering process. The connection electrode CNE can include a conductive material. The connection electrode CNE is formed by a sputtering process, and thus, due to the narrow width of the contact hole CNT, can be separately formed as a first connection electrode CNE1 disposed on the upper surface of the second insulating layer 60 and on the bridging electrode BNE, and a second connection electrode CNE2 disposed on the semiconductor pattern SP and disconnected from the first connection electrode CNE1. That is, due to the step coverage problem caused by the sputtering process, a disconnection of the material layer for providing the connection electrode CNE occurs, such that the first connection electrode CNE1 and the second connection electrode CNE2 spaced apart from each other can be formed of the same material layer. In an embodiment, the provision of the first connection electrode CNE1 and the provision of the second connection electrode CNE2 are performed simultaneously with each other, such that the first connection electrode CNE1 and the second connection electrode CNE2 are corresponding portions of the same material layer.

[0186] As Figure 10E shown, the first connection electrode CNE1 includes portions extending from the upper surface of the insulating layer and along its side surface. These portions are spaced apart from each other at the upper surface of the insulating layer and along the contact hole CNT to define an upper hole in the first connection electrode CNE1. The size of the upper hole can be defined between the facing inner surfaces of these portions and has a size in the planar direction. The size of the upper hole defined by these portions of the first connection electrode CNE1 increases in the direction from the upper surface of the insulating layer to the portion of the transistor exposed to the outside of the insulating layer (e.g., in the direction opposite to the Figure 10E third direction DR3 shown).

[0187] However, since the bridging electrode BNE is disposed on the side surfaces of the insulating layers 50 and 60, the first connection electrode CNE1 and the second connection electrode CNE2 spaced apart from each other along the bridging electrode BNE can be electrically connected to each other. As a result, even when the number of signal lines increases and the integration degree of the circuit increases, the first connection electrode CNE1 and the second connection electrode CNE2 physically disconnected from each other are electrically connected to each other, such that the display device DD of the present utility model can have high resolution, high-speed driving, and high robustness characteristics.

[0188] The display device of the present utility model may include a first connection electrode and a second connection electrode physically spaced apart from each other in a contact hole. However, when the bridging electrode is disposed along a side surface of the contact hole defined by the insulating layer, the first connection electrode and the second connection electrode may be electrically connected to each other through contact of the two electrodes with the bridging electrode. As a result, even when the number of signal lines increases and the integration degree of the circuit increases, the first connection electrode and the second connection electrode physically disconnected from each other are electrically connected to each other, so that the display device of the present utility model can have characteristics of high resolution, high-speed driving, and high robustness.

[0189] Although the present utility model has been described with reference to preferred embodiments thereof, those skilled in the art will understand that various modifications and changes in form and detail may be made without departing from the spirit and scope of the present utility model as set forth in the claims.

[0190] Accordingly, the technical scope of the present utility model is not intended to be limited to what is set forth in the detailed description of the specification, but is intended to be defined by the claims.

Claims

1. A display device, comprising: Circuit layer; as well as a light emitting element on and connected to the circuit layer, Wherein, the circuit layer includes: A transistor including a semiconductor layer; an insulating layer on the semiconductor layer, the insulating layer having: a side surface defining a contact hole of the insulating layer, a portion of the semiconductor layer being exposed outside the insulating layer at the contact hole; and an upper surface, the side surface extending from the upper surface; a bridging electrode extending along the side surface of the insulating layer and contacting the portion of the semiconductor layer exposed outside the insulating layer; and A connection electrode is connected to the semiconductor layer, the connection electrode comprising a first connection electrode directly on the bridge electrode and spaced apart from the portion of the semiconductor layer exposed outside the insulating layer.

2. The display device according to claim 1, wherein: The semiconductor layer includes an upper surface at which the semiconductor layer is exposed to the outside of the insulating layer, and The connection electrode further includes a second connection electrode on the upper surface of the semiconductor layer.

3. The display device according to claim 2, wherein: The second connecting electrode is spaced apart from the first connecting electrode along the bridge electrode, and The second connection electrode is electrically connected to the first connection electrode via the bridge electrode.

4. The display device according to claim 3, wherein: The contact hole has a width of 0.5 micrometers to 2 micrometers.

5. The display device according to claim 3, wherein: The contact hole has a depth of 1 micrometer to 1.5 micrometers.

6. The display device according to claim 1, wherein: The bridge electrode has a length along the side surface of the insulating layer, and The length of the bridge electrode is smaller than the depth of the contact hole.

7. The display device according to claim 1, wherein: The bridging electrode has an upper surface closest to the upper surface of the insulating layer, A portion of the side surface of the insulating layer between the upper surface of the insulating layer and the upper surface of the bridge electrode is exposed to the outside of the bridge electrode, and The first connection electrode directly contacts the upper surface of the bridge electrode and the portion of the side surface of the insulating layer exposed outside the bridge electrode.

8. The display device according to claim 1, wherein: The insulating layer includes: a first insulating layer on the semiconductor layer; and a second insulating layer on the first insulating layer, and The contact hole passes through the first insulating layer and the second insulating layer.

9. The display device according to claim 8, wherein: The contact hole comprises: a first hole portion defined by a side surface of the first insulating layer; a second hole portion defined by a side surface of the second insulating layer, and The first hole portion has a size smaller than that of the second hole portion.

10. The display device according to claim 1, wherein: The first connection electrode includes portions extending from the upper surface of the insulating layer and along the side surface of the insulating layer, the portions being spaced apart from each other to define an upper hole in the first connection electrode, and The size of the upper hole increases in a direction from the upper surface of the insulating layer to the portion of the transistor exposed outside the insulating layer.

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