Multi-channel serial port time sequence analysis system based on programmable chip

Abstract

The utility model relates to a multichannel serial port time sequence analysis system based on a programmable chip, which comprises a main chip and a temperature compensation crystal oscillator module, the main chip is in two-way communication connection with an upper computer, and the main chip is provided with a timestamp information framing module, a serial port analysis module and a self-timekeeping module. And the self-timekeeping module is in communication connection with the temperature compensation crystal oscillator module, receives a temperature signal of the temperature compensation crystal oscillator module and stabilizes a timestamp output by the self-timekeeping module. The timestamp information framing module is in communication connection with the serial port analysis module and receives multiple groups of data frames. And the timestamp information framing module is in communication connection with the self-timekeeping module, receives timestamps corresponding to the multiple groups of data frames, generates the data frames with the timestamps, and transmits the data frames to an upper computer. Implementers in the field can obtain more accurate arrival time of different serial port data frames through the system. When a plurality of serial ports carry out uncorrelated instruction actions, the system can well execute or analyze the state of the instruction actions, and the problem that the serial ports are noisy and disordered is avoided.

Description

Technical Field

[0001] This application relates to the technical field of serial communication timing analysis, and particularly to a multi-channel serial port timing analysis system based on a programmable chip. Background Art

[0002] Serial communication is a common data transmission method. It transmits data serially, that is, sending and receiving data bit by bit. Serial communication is usually used to connect a computer to external devices, and there are many types of interface types, including I2C, SPI, UART, RS232, RS422, RS485, and CAN, etc.

[0003] In the actual usage environment, often a master device will conduct serial communication activities on multiple interfaces. While performing communication transmission, in some usage scenarios, it is necessary to perform timing analysis on the reception or transmission of serial data. For example, in a high-precision integrated navigation system, it is necessary to obtain the arrival times of multiple navigation information to determine the cooperation status and delay of various types of information, etc. At present, the accuracy of obtaining the reception time of serial data is relatively low, and it is difficult to obtain the precise time when different serial data frames arrive. When there are associated instruction actions among multiple serial ports, the instruction actions cannot be executed or analyzed well, and it is easy to have a problem of chaos and disorder among multiple serial ports. Utility Model Content

[0004] In view of this, this application proposes a multi-channel serial port timing analysis system based on a programmable chip to solve the above problems.

[0005] According to one aspect of this application, there is provided a multi-channel serial port timing analysis system based on a programmable chip, including: a main chip and a temperature-compensated crystal oscillator module; the main chip is bidirectionally communicatively connected to a host computer;

[0006] The main chip has a timestamp information framing module, a serial port parsing module, and an autonomous timing module;

[0007] The autonomous timing module is communicatively connected to the temperature-compensated crystal oscillator module, receives the temperature signal of the temperature-compensated crystal oscillator module, adjusts the output frequency, and stabilizes the timestamp output by the autonomous timing module;

[0008] The timestamp information framing module is communicatively connected to the serial port parsing module and receives multiple groups of data frames;

[0009] The timestamp information framing module is communicatively connected to the autonomous timing module, receives the timestamps corresponding to multiple groups of the data frames, generates data frames with timestamps, and transmits them to the host computer.

[0010] In a possible implementation, the self-timing module includes: a local communication unit, a positioning signal parsing unit, and a local clock generation unit; the communication unit is bidirectionally communicatively connected to the host computer;

[0011] The communication unit is communicatively connected to the local clock generation unit and sends the first clock information of the host computer to the local clock generation unit;

[0012] The positioning signal parsing unit is communicatively connected to the local clock generation unit and sends the second clock information of the external positioning signal device to the local clock generation unit;

[0013] The local clock generation unit is communicatively connected to the temperature-compensated crystal oscillator module and selects the first clock information or the second clock information as the reference clock.

[0014] In a possible implementation, the temperature-compensated crystal oscillator module includes: a crystal oscillator chip and a temperature sensor; the input end of the crystal oscillator chip is communicatively connected to the temperature sensor, and the output end of the crystal oscillator chip is communicatively connected to the local clock generation unit.

[0015] In a possible implementation, the number of the serial port parsing modules is two or more, and the output ends of the multiple serial port parsing modules are all communicatively connected to the receiving end of the timestamp information framing module.

[0016] In a possible implementation, the temperature-compensated crystal oscillator module further includes: a resistor, a first capacitor, and a second capacitor; the +VS pin of the crystal oscillator chip is electrically connected to one end of the first capacitor, one end of the first capacitor is electrically connected to the 3.3V power supply, the other end of the first capacitor is electrically connected to the GND pin of the crystal oscillator chip, the OUTPUT pin of the crystal oscillator chip is electrically connected to one end of the resistor, the other end of the resistor is electrically connected to one end of the second capacitor, and the other end of the resistor is electrically connected to the local clock generation unit; the other ends of the first capacitor and the second capacitor are both grounded.

[0017] In a possible implementation, the model of the crystal oscillator chip is LFTCXO075792Cutte.

[0018] In a possible implementation, the capacitance value of the first capacitor is 0.1 μF, and the capacitance value of the second capacitor is 10 pF.

[0019] In a possible implementation, the resistance value of the resistor is 33R.

[0020] In a possible implementation, the main chip is communicatively connected to the host computer through a local bus for setting.

[0021] In a possible implementation, the main chip is an FPGA chip.

[0022] Advantages of the present application:

[0023] The multi-channel serial port timing analysis system based on a programmable chip proposed in the present application has a simple connection method, and those skilled in the art can obtain more accurate arrival times of different serial port data frames through this system. Specifically,

[0024] Therefore, when multiple serial ports have uncorrelated instruction actions, the system can also better execute or analyze the status of their instruction actions, avoiding the problem of noisy disorder among multiple serial ports.

[0025] According to the following detailed description of exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present application will become clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings included in and constituting a part of this specification, together with the specification, illustrate exemplary embodiments, features, and aspects of the present application and are used to explain the principles of the present application.

[0027] Figure 1 Schematic diagram showing the principle of the multi-channel serial port timing analysis system based on a programmable chip according to an embodiment of the present application;

[0028] Figure 2 Circuit diagram showing the temperature-compensated crystal oscillator module according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0030] It should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application or simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0032] As used herein, the term "exemplary" means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" herein need not be construed as superior or better than other embodiments.

[0033] In addition, for a better illustration of the present application, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present application can be implemented without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present application.

[0034] As Figure 1 and Figure 2 shown, the multi-channel serial port timing analysis system based on a programmable chip includes: a main chip and a temperature-compensated crystal oscillator module 200. The main chip is bidirectionally communicatively connected to the host computer. The main chip has a timestamp information framing module 110, a serial port parsing module 120, and an autonomous timing module. The autonomous timing module is communicatively connected to the temperature-compensated crystal oscillator module 200, receives the temperature signal of the temperature-compensated crystal oscillator module 200, adjusts the output frequency, and stabilizes the timestamp output by the autonomous timing module. The timestamp information framing module 110 is communicatively connected to the serial port parsing module 120 and receives multiple groups of data frames. The timestamp information framing module 110 is communicatively connected to the autonomous timing module, receives the timestamps corresponding to the multiple groups of data frames, generates data frames with timestamps, and transmits them to the host computer.

[0035] The multi-channel serial port timing analysis system based on a programmable chip proposed in this embodiment has a simple connection method and is convenient for implementers in this field to operate, and can obtain more accurate arrival times of different serial port data frames. When multiple serial ports have unassociated instruction actions, the system can also better execute or analyze the status of their instruction actions, avoiding the problem of noisy disorder among multiple serial ports. Specifically, the serial port parsing module 120 correspondingly parses the data frames of different serial ports and transmits the data frames to the timestamp information framing module 110. The timestamp information framing module 110 correspondingly receives the clock information from the self-timing module, processes the data frames of different serial ports, and generates data frames with timestamps, so that multiple serial ports are more orderly and can better execute or analyze the status of instruction actions. Among them, due to the setting of the temperature compensated crystal oscillator module 200, the temperature compensated crystal oscillator module 200 can adjust the clock information in the self-timing, that is, the temperature information obtained by the temperature sensor is transmitted to the crystal oscillator chip, and the crystal oscillator chip is communicatively connected to the local clock generation unit 133 in the self-timing module. The output frequency can be adjusted through the compensation circuit inside the main chip to offset the influence of temperature changes on the frequency, thereby achieving the temperature compensation effect and obtaining more accurate serial port timing information.

[0036] In one specific embodiment, the self-timing module includes: a local communication unit 131, a positioning signal parsing unit 132, and a local clock generation unit 133. The communication unit is in bidirectional communication connection with the host computer. The communication unit is in communication connection with the local clock generation unit 133 and sends the first clock information of the host computer to the local clock generation unit 133. The positioning signal parsing unit 132 is in communication connection with the local clock generation unit 133 and sends the second clock information of the external positioning signal device to the local clock generation unit 133. The local clock generation unit 133 is in communication connection with the temperature-compensated crystal oscillator module 200 and selects the first clock information or the second clock information as the reference clock. In this embodiment, it should be noted that the local communication unit 131 mainly realizes data communication with the host computer, and the content mainly includes clock information and serial port data frames. The transmission channel is the local bus, and the local communication unit 131 transmits the first clock information to the local clock generation module. The positioning signal parsing unit 132 needs to receive the positioning data, parse the clock information carried therein, and transmit the second clock information to the local clock generation unit 133. The local clock generation unit 133 simultaneously obtains the clock information provided by the host computer and the external positioning device, and selects one of the clock information as the initial clock according to the instruction of the host computer. After selecting the initial clock information, self-maintenance is required, that is, the nanosecond-level clock information is timed inside the local clock generation unit 133, and this process is called self-timing. It should also be noted that during the self-timing process, the local clock generation unit 133 needs to periodically calibrate the time with the externally input clock source to ensure the update of the local reference time, or perform clock calibration when there is a large error. When the local clock generation unit 133 performs self-timing, the clock signal generated by the temperature-compensated crystal oscillator module 200 is used as the basic unit for counting and timing.

[0037] In one specific embodiment, the temperature-compensated crystal oscillator module 200 includes: a crystal oscillator chip Y2 and a temperature sensor. The input end of the crystal oscillator chip Y2 is in communication connection with the temperature sensor, and the output end of the crystal oscillator chip Y2 is in communication connection with the local clock generation unit 133. In this embodiment, it should be noted that the temperature-compensated crystal oscillator module 200 is used to provide a stable clock signal, and can automatically adjust the output frequency according to the change of the ambient temperature to maintain the accuracy of the clock signal. The temperature-compensated crystal oscillator module 200 usually consists of a crystal oscillator and a temperature sensor. To solve the influence of temperature on the frequency of the crystal oscillator, a temperature sensor is introduced in the temperature-compensated crystal oscillator. The temperature sensor can sense the ambient temperature and feedback the temperature information to the crystal oscillator. The crystal oscillator adjusts the output frequency through an internal compensation circuit according to the received temperature information to offset the influence of temperature change on the frequency, so as to achieve the temperature compensation effect.

[0038] In one specific embodiment, the number of serial port parsing modules 120 is more than two, and the output ends of multiple serial port parsing modules 120 are all communicatively connected to the receiving end of the timestamp information framing module 110. In this embodiment, it should be noted that the serial port parsing module 120 needs to complete the function of receiving data from different serial port modules. There are various types of serial port communications. While each serial port module parses data, it adds a specified special character to the serial port data as the data frame header, and sends the parsed data together with the data frame header to the timestamp information framing module 110 as a complete data frame. When the timestamp information framing module 110 receives the serial port data frame, it identifies the frame header information and recombines the timestamp information into the serial port data frame at that moment. The module should have the ability to process multiple serial port data frames simultaneously to ensure recombination is completed in the first instance. The recombined data will be written into the buffer and sent to the local communication module one by one, and finally reach the host computer.

[0039] In one specific embodiment, the temperature-compensated crystal oscillator module 200 further includes: a resistor R145, a first capacitor C100, and a second capacitor C101. The +VS (positive power supply) pin of the crystal oscillator chip Y2 is electrically connected to one end of the first capacitor C100. One end of the first capacitor C100 is electrically connected to the 3.3V power supply. The OUTPUT (output) pin of the crystal oscillator chip Y2 is electrically connected to one end of the resistor R145. The other end of the resistor R145 is electrically connected to one end of the second capacitor C101. The other end of the resistor R145 is electrically connected to the local clock generation unit 133. The other end of the first capacitor C100 is electrically connected to the GND (ground) pin of the crystal oscillator chip Y2. The other ends of the first capacitor C100 and the second capacitor C101 are both grounded.

[0040] In one specific embodiment, the model of the crystal oscillator chip Y2 is LFTCXO075792Cutte. In this embodiment, it should be noted that the LFTCXO075792Cutte chip is a TCXO oscillator from IQD Frequency Products, with a smaller package size and higher frequency stability.

[0041] In one specific embodiment, the capacitance value of the first capacitor C100 is 0.1 μF, and the capacitance value of the second capacitor C101 is 10 pF. It should also be noted that in one specific embodiment, the resistance value of the resistor R145 is 33R.

[0042] In one specific embodiment, the main chip is communicatively connected to the host computer through a local bus. In this embodiment, it should be noted that the local bus is a communication interface used to connect various hardware devices in a computer system. It is a set of electronic signal lines for transmitting data and control signals within the computer. The local bus usually consists of multiple parallel lines for transmitting addresses, data, and control signals.

[0043] In one specific embodiment, the main chip is an FPGA chip. As a field-programmable chip, the FPGA chip has faster computing and processing capabilities and more precise timing control, providing nanosecond-level timing accuracy for recording the transceiver time of serial port data. The communication data transmission between the FPGA chip and the host computer is completed through the local bus, including serial port data, control instructions, clock information, etc. Furthermore, it should be noted that the initial clock information running inside the FPGA chip needs to be provided externally. A reference external clock source is generally provided by the host computer communicating with the FPGA chip, or can also be provided by an external positioning signal device. The FPGA chip needs to support two ways of obtaining clock information. After the FPGA chip obtains the external clock information, it generates and maintains local clock information, that is, self-timing, which needs to be realized by the high-stability clock provided by the temperature-compensated crystal oscillator to ensure the stable operation of the clock system of the FPGA chip in a long-term or temperature-changing environment. The FPGA chip needs to have the ability to correct the clock. Especially when receiving the positioning signal, when there is a deviation between the locally running clock information and the clock information provided by the external positioning signal device, the local clock information needs to be adjusted and updated according to the allowable error size.

[0044] In summary, it should be added that the host computer refers to a computer system that communicates with and controls the lower computer (such as an embedded system, sensor, actuator, etc.). It usually runs on a PC or an industrial control computer and is used to monitor, control, and manage lower computer devices. The host computer can interact with the lower computer through serial ports, Ethernet, wireless communication, etc. Here, the FPGA chip belongs to the lower computer.

[0045] It should be noted that a data frame is the basic unit of data transmission in a computer network. In a local area network, data is transmitted from one node to another in the form of electromagnetic waves through a specific medium (such as optical fiber, twisted pair, etc.). The data link layer is responsible for transmitting data frames error-free between two adjacent nodes. Each frame includes a certain amount of data and some necessary control information (such as synchronization information, address information, error control, etc.). A data frame consists of three parts: a frame header, frame data, and a frame tail. The frame header and frame tail contain some necessary control information, such as synchronization information, address information, error control, etc.; the frame data area contains the data packet passed down from the network layer. When sending data, the data frame will be encapsulated in a specific way to ensure the integrity and accuracy of the data during transmission. When receiving data, the receiving party will parse the data frame in the same way to restore the original data packet.

[0046] It should be noted that a timestamp is a number or string used to represent a specific point in time, and its main purpose is to record and manage time information. Recording event time: Timestamps can accurately record the exact time when an event occurs, such as transactions, logins, and messages. And timestamps can be used to compare the times when different events occur, so as to determine the order or time difference. Or data can be sorted by timestamp to display or retrieve data in chronological order. And since timestamps record the creation or modification time of data, they can be used as an anti-tampering mechanism to detect any unauthorized changes.

[0047] It should be noted that although the multi-channel serial port timing analysis system based on a programmable chip is introduced by taking this application as an example above, those skilled in the art can understand that this application should not be limited thereto. In fact, users can flexibly set parameters according to their personal preferences and / or actual application scenarios as long as it is reasonable.

[0048] The various embodiments of this application have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the disclosed embodiments.

Claims

1. A multi-channel serial port timing analysis system based on a programmable chip, characterized in that Including: A main chip and a temperature-compensated crystal oscillator module; the main chip is bidirectionally communicatively connected to a host computer; The main chip has a timestamp information framing module, a serial port parsing module, and an autonomous timing module; The autonomous timing module is communicatively connected to the temperature-compensated crystal oscillator module, receives the temperature signal of the temperature-compensated crystal oscillator module, adjusts the output frequency, and stabilizes the timestamp output by the autonomous timing module; The timestamp information framing module is communicatively connected to the serial port parsing module and receives multiple groups of data frames; The timestamp information framing module is communicatively connected to the autonomous timing module, receives the timestamps corresponding to multiple groups of the data frames, generates a data frame with a timestamp, and transmits it to the host computer.

2. The multi-channel serial port timing analysis system based on a programmable chip according to claim 1, wherein The autonomous timing module includes: a local communication unit, a positioning signal parsing unit, and a local clock generation unit; the communication unit is bidirectionally communicatively connected to the host computer; The communication unit is communicatively connected to the local clock generation unit and sends the first clock information of the host computer to the local clock generation unit; The positioning signal parsing unit is communicatively connected to the local clock generation unit and sends the second clock information of an external positioning signal device to the local clock generation unit; The local clock generation unit is communicatively connected to the temperature-compensated crystal oscillator module and selects the first clock information or the second clock information as the reference clock.

3. The multi-channel serial port timing analysis system based on a programmable chip according to claim 2, wherein The temperature-compensated crystal oscillator module includes: a crystal oscillator chip and a temperature sensor; the input end of the crystal oscillator chip is communicatively connected to the temperature sensor, and the output end of the crystal oscillator chip is communicatively connected to the local clock generation unit.

4. The multi-channel serial port timing analysis system based on a programmable chip according to claim 1, characterized in that, The number of the serial port parsing modules is two or more, and the output ends of the multiple serial port parsing modules are all communicatively connected to the receiving end of the timestamp information framing module.

5. The multi-channel serial port timing analysis system based on a programmable chip according to claim 3, wherein The temperature-compensated crystal oscillator module further includes: a resistor, a first capacitor, and a second capacitor; the +VS pin of the crystal oscillator chip is electrically connected to one end of the first capacitor, one end of the first capacitor is electrically connected to a 3.3V power supply, the other end of the first capacitor is electrically connected to the GND pin of the crystal oscillator chip, the OUTPUT pin of the crystal oscillator chip is electrically connected to one end of the resistor, the other end of the resistor is electrically connected to one end of the second capacitor, and the other end of the resistor is electrically connected to the local clock generation unit; the other ends of the first capacitor and the second capacitor are both grounded.

6. The multi-channel serial port timing analysis system based on a programmable chip according to claim 3, wherein The model of the crystal oscillator chip is LFTCXO075792Cutte.

7. The multi-channel serial port timing analysis system based on a programmable chip according to claim 5, wherein The capacitance value of the first capacitor is 0.1 μF, and the capacitance value of the second capacitor is 10 pF.

8. The multi-channel serial port timing analysis system based on a programmable chip according to claim 5, wherein, The resistance value of the resistor is 33R.

9. The multi-channel serial port timing analysis system based on a programmable chip according to any one of claims 1-4, characterized in that The main chip is communicatively connected to the host computer through a local bus for setting.

10. The multi-channel serial port timing analysis system based on a programmable chip according to any one of claims 1-4, characterized in that, The main chip is an FPGA chip.

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