Display device

Abstract

A display device according to an embodiment of the present disclosure includes pixels, each of the pixels including a first transistor including a first sub-driving transistor and a second sub-driving transistor, and a bypass transistor including a second sub-driving transistor and a third sub-driving transistor, the first sub-driving transistor has a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, and the second sub-driving transistor has a gate electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to a fourth node, and the bypass transistor is connected in parallel with one of the first sub-driving transistor and the second sub-driving transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0090693, filed on July 12, 2023, which is hereby incorporated by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device. Background art

[0004] With the development of information technology, display devices that connect users to information have become increasingly important. For example, in various applications, the use of liquid crystal display devices and organic light - emitting display devices is increasing.

[0005] Display devices can be used indoors and outdoors. When a display device is used outdoors, since there is usually more ambient light, it is necessary to emit light with a higher brightness than indoors. To achieve higher brightness, a higher voltage may be required.

[0006] However, a higher voltage requirement may be undesirable because it usually translates into higher power consumption. In addition, a higher voltage may exceed the voltage range supported by the display device. Summary of the utility model

[0007] The technical problem to be solved by the present disclosure is to provide a display device that can display an image with high brightness even when a higher voltage is not provided.

[0008] A display device according to an embodiment of the present disclosure may include pixels, each of the pixels may include a first transistor and a bypass transistor, the first transistor may include a first sub - driving transistor and a second sub - driving transistor, the first sub - driving transistor may have a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, the second sub - driving transistor may have a gate electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to a fourth node, and the bypass transistor is connected in parallel with one of the first sub - driving transistor and the second sub - driving transistor.

[0009] The bypass transistor may be turned off in a first mode and turned on in a second mode.

[0010] For the same input image, the pixel may output an image with a first brightness in the first mode and an image with a second brightness in the second mode, and the second brightness may be greater than the first brightness.

[0011] The gate electrode of the bypass transistor may be connected to a bypass line, and the bypass lines may be commonly connected to the pixels.

[0012] The gate electrode of the bypass transistor can be connected to any one of the bypass lines, the pixel can include a pixel group connected to the same scan line, and different pixel groups can be connected to different bypass lines.

[0013] The gate electrode of the bypass transistor can be connected to any one of the bypass lines, the pixel can include a pixel group connected to the same data line, and different pixel groups can be connected to different bypass lines.

[0014] The bypass transistor can include a first sub-bypass transistor and a second sub-bypass transistor connected in series. The gate electrode of the first sub-bypass transistor can be connected to any one of the first bypass lines, and the gate electrode of the second sub-bypass transistor can be connected to any one of the second bypass lines.

[0015] The first bypass line can extend in a direction not parallel to the direction in which the second bypass line extends.

[0016] The pixel can include a first pixel group connected to the same scan line. Different first pixel groups can be connected to different first bypass lines. The pixel can include a second pixel group connected to the same data line, and different second pixel groups can be connected to different second bypass lines.

[0017] The width of the first channel of the first sub-driving transistor can be equal to the width of the second channel of the second sub-driving transistor, and the length of the first channel can be equal to the length of the second channel.

[0018] The width of the first channel of the first sub-driving transistor can be equal to the width of the second channel of the second sub-driving transistor, and the length of the first channel can be longer than the length of the second channel.

[0019] The width of the first channel of the first sub-driving transistor can be less than the width of the second channel of the second sub-driving transistor, and the length of the first channel can be equal to the length of the second channel.

[0020] The width of the first channel of the first sub-driving transistor can be less than the width of the second channel of the second sub-driving transistor, and the length of the first channel can be longer than the length of the second channel.

[0021] The bypass transistor and the first sub-driving transistor can be connected in parallel.

[0022] Each of the pixels may further include: a second transistor having a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the second node; a third transistor having a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to the fourth node; a fourth transistor having a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode receiving a first initialization voltage; a fifth transistor having a gate electrode connected to the third scan line, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor having a gate electrode connected to the third scan line, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; and a seventh transistor having a gate electrode connected to the first scan line, a first electrode receiving a second initialization voltage, and a second electrode connected to the fifth node.

[0023] The bypass transistor may include a first sub-bypass transistor and a second sub-bypass transistor connected in series. The first sub-bypass transistor may have a gate electrode connected to the first bypass line, a first electrode, and a second electrode connected to the third node, and the second sub-bypass transistor may have a gate electrode connected to the second bypass line, a first electrode connected to the second node, and a second electrode connected to the first electrode of the first sub-bypass transistor.

[0024] Each of the pixels may further include: a second transistor having a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the second node; a third transistor having a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode connected to the fourth node; a fourth transistor having a gate electrode connected to the third scan line, a first electrode connected to the first node, and a second electrode receiving a first initialization voltage; a fifth transistor having a gate electrode connected to the fourth scan line, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor having a gate electrode connected to the fourth scan line, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; a seventh transistor having a gate electrode connected to the fifth scan line, a first electrode receiving a second initialization voltage, and a second electrode connected to the fifth node; and a bias transistor having a gate electrode connected to the fifth scan line, a first electrode receiving a bias voltage, and a second electrode connected to the second node.

[0025] The channels of the third transistor and the fourth transistor may include an oxide semiconductor.

[0026] The bypass transistor and the second sub-driving transistor may be connected in parallel.

[0027] Each of the pixels may further include: a second transistor having a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the second node; a third transistor having a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to the fourth node; a fourth transistor having a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode receiving a first initialization voltage; a fifth transistor having a gate electrode connected to the third scan line, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a sixth transistor having a gate electrode connected to the third scan line, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; and a seventh transistor having a gate electrode connected to the first scan line, a first electrode receiving a second initialization voltage, and a second electrode connected to the fifth node. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the concepts of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the concepts of the present disclosure and, together with the description, serve to explain the principles of the concepts of the present disclosure.

[0029] Figure 1 is a diagram for explaining a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is a diagram for explaining a pixel according to an embodiment of the present disclosure.

[0031] Figure 3 and Figure 4 is a diagram for explaining an example of a method for driving Figure 2 the pixels.

[0032] Figures 5 to 10 is for explaining Figure 2 an example of the layout of a pixel circuit.

[0033] Figure 11 is a diagram for explaining a pixel according to another embodiment of the present disclosure.

[0034] Figures 12 to 14 is a diagram for explaining a display device according to other embodiments of the present disclosure.

[0035] Figure 15 is for explaining Figure 14 the pixels of a display device.

[0036] Figure 16 is a diagram for explaining a pixel according to yet another embodiment of the present disclosure.

[0037] Figure 17is an example diagram for explaining a method for driving Figure 16 the pixels.

[0038] Figures 18 to 27 is an example diagram for explaining Figure 16 the layout of a pixel circuit.

[0039] Figures 28 to 31 is a diagram for explaining the widths and lengths of channels of a first sub-driving transistor and a second sub-driving transistor according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily implement the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0041] To clearly describe the present disclosure, parts irrelevant to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification. Therefore, the above reference numerals can also be used in other drawings.

[0042] In addition, for ease of description, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown, and thus the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated to clearly represent layers and regions.

[0043] In addition, in the description, the expression "the same" may mean "substantially the same". That is, it may be similar enough to convince those of ordinary skill in the art that they are the same. In other expressions, "substantially" may be omitted.

[0044] Figure 1 is a diagram for explaining a display device according to an embodiment of the present disclosure.

[0045] Referring to Figure 1 , a display device 10a according to an embodiment of the present disclosure may include a timing controller 11, a data driver 12, a scan driver 13, and a pixel unit 14.

[0046] The timing controller 11 may receive gray levels for an input image (or an input frame). The gray levels may include a first color gray level, a second color gray level, and a third color gray level. The first color gray level may be a gray level for representing a first color, the second color gray level may be a gray level for representing a second color, and the third color gray level may be a gray level for representing a third color.

[0047] In addition, the timing controller 11 can receive control signals for an image. The control signals can include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a data enable signal. The vertical synchronization signal can include a plurality of pulses and can indicate the end of a previous frame period and the start of a current frame period based on the time points at which each pulse occurs. The interval between adjacent pulses of the vertical synchronization signal can correspond to one frame period. The horizontal synchronization signal can include a plurality of pulses and can indicate the end of a previous horizontal period and the start of a new horizontal period based on the time points at which each pulse occurs. The interval between adjacent pulses of the horizontal synchronization signal can correspond to one horizontal period. The data enable signal can have an enable level for a specific horizontal period and a disable level for the remaining periods. When the data enable signal is at the enable level, it can indicate that color gray levels are provided during the corresponding horizontal period.

[0048] The timing controller 11 can provide gray levels that are rendered or corrected to meet the specifications of the display device 10a to the data driver 12. In addition, the timing controller 11 can provide a clock signal, a scan start signal, etc. to the scan driver 13. In addition, the timing controller 11 can provide a bypass signal CB to the pixel unit 14. In Figure 1 an embodiment, the bypass signal CB can be a global signal that is commonly provided to all pixels of the pixel unit 14.

[0049] The data driver 12 can generate a data voltage VD to be provided to the data lines using the gray levels and control signals received from the timing controller 11. For example, the data driver 12 can sample the gray levels using a clock signal and apply the data voltage VD corresponding to the gray levels to the data lines in units of pixel rows. A pixel row can refer to pixels connected to the same scan line. The data lines can extend from the data driver 12 toward the pixel unit 14 in a first direction DR1. The data lines can be arranged parallel to each other in a second direction DR2 perpendicular to the first direction DR1.

[0050] The scan driver 13 can receive a clock signal, a scan start signal, etc. from the timing controller 11 and generate a scan signal SC to be provided to the scan lines. The scan driver 13 can sequentially provide the scan signal SC having pulses at a conductive level to the scan lines. For example, the scan driver 13 can be configured in the form of a shift register and can generate the scan signal SC by sequentially transmitting the scan start signal in the form of pulses at a conductive level to the next-stage circuit under the control of the clock signal.

[0051] The scan driver 13 can include a plurality of sub-scan drivers according to the type of the scan signal SC. In this case, each of the plurality of sub-scan drivers can be configured in the form of a shift register.

[0052] The scanning lines can extend from the scanning driver 13 towards the pixel unit 14 in the second direction DR2. The scanning lines can be arranged parallel to each other in the first direction DR1. According to an embodiment, the scanning driver 13 or the sub-scanning driver can be positioned from the pixel unit 14 in the second direction DR2. In this case, the scanning lines can extend in a direction opposite to the second direction DR2.

[0053] The pixel unit 14 can include pixels. Each pixel can be connected to a corresponding data line and a corresponding scanning line. The pixel unit 14 can include a first pixel that emits light of a first color, a second pixel that emits light of a second color, and a third pixel that emits light of a third color. The first color, the second color, and the third color can be different colors. For example, the first color can be one of red, green, and blue, the second color can be one of red, green, and blue different from the first color, and the third color can be one of red, green, and blue different from the first color and the second color. In some embodiments, magenta, cyan, and yellow can be used instead of red, green, and blue as the first color to the third color.

[0054] The pixel unit 14 can be arranged in various shapes such as a diamond RGB-stripe, S-stripe, Real RGB, or standard and the like.

[0055] The pixels of the pixel unit 14 can be positioned on a plane defined by the first direction DR1 and the second direction DR2. The direction of the emitted light can be a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2.

[0056] In Figure 1 the embodiment, the gate electrode of the bypass transistor of each pixel can be connected to a bypass line. In this case, the bypass lines can be commonly connected to the pixels. For example, the bypass lines can have a mesh shape covering the pixel unit 14. All the pixels of the pixel unit 14 can commonly receive the above-mentioned bypass signal CB.

[0057] Figure 2 is a diagram for explaining a pixel according to an embodiment of the present disclosure.

[0058] Reference Figure 2, the pixel SPija may include a pixel circuit SPCa and a light-emitting element LD, where i and j may be integers greater than 0. The pixel circuit SPCa may include transistors T1, T2, T3, T4, T5, T6, T7, and T8a and a storage capacitor Cst. The pixel SPija may refer to a pixel connected to the i-th scan line and the j-th data line. Here, the pixel SPija may be a first pixel for representing a first color. Since a second pixel for representing a second color and a third pixel for representing a third color may have the same configuration as the first pixel, repeated descriptions will be omitted.

[0059] Reference Figure 2 , a circuit composed of P-type transistors will be described as an example. However, it will be understood that by changing the polarity of the voltage applied to the gate terminal, the circuit can be redesigned as a circuit composed of N-type transistors. Similarly, the circuit can be redesigned as a circuit composed of a combination of P-type transistors and N-type transistors. A P-type transistor generally may refer to a transistor in which the amount of current increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. An N-type transistor generally may refer to a transistor in which the amount of current increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. The transistors may be configured in various forms such as thin-film transistors (TFTs), field-effect transistors (FETs), or bipolar junction transistors (BJTs). Since this description can be equivalently applied to the following drawings, redundant descriptions will be omitted.

[0060] The first transistor T1 may have a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the fourth node N4. The first transistor T1 may be a driving transistor.

[0061] The first transistor T1 may include a first sub-driving transistor T1-1 and a second sub-driving transistor T1-2. The first sub-driving transistor T1-1 may have a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The second sub-driving transistor T1-2 may have a gate electrode connected to the first node N1, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0062] The second transistor T2 may have a gate electrode connected to the first scan line GWi, a first electrode connected to the data line VDj, and a second electrode connected to the second node N2. The second transistor T2 may be a scanning transistor.

[0063] The third transistor T3 may have a gate electrode connected to the first scan line GWi, a first electrode connected to the first node N1, and a second electrode connected to the fourth node N4. The third transistor T3 may be a diode-connected transistor. The third transistor T3 may include a first sub-transistor T3-1 and a second sub-transistor T3-2 connected in series.

[0064] The fourth transistor T4 may have a gate electrode connected to the second scan line GIi, a first electrode connected to the first node N1, and a second electrode receiving a first initialization voltage VINT. The fourth transistor T4 may be a gate initialization transistor. The fourth transistor T4 may include a first sub-transistor T4-1 and a second sub-transistor T4-2 connected in series.

[0065] The fifth transistor T5 may have a gate electrode connected to the third scan line EMi, a first electrode receiving a first power supply voltage ELVDD, and a second electrode connected to the second node N2.

[0066] The fifth transistor T5 may be a first emission control transistor.

[0067] The sixth transistor T6 may have a gate electrode connected to the third scan line EMi, a first electrode connected to the fourth node N4, and a second electrode connected to the fifth node N5. The sixth transistor T6 may be a second emission control transistor.

[0068] The seventh transistor T7 may have a gate electrode connected to the first scan line GWi, a first electrode receiving a second initialization voltage VAINT, and a second electrode connected to the fifth node N5. The seventh transistor T7 may be an anode initialization transistor.

[0069] The bypass transistor T8a may have a gate electrode receiving a bypass signal CB, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The bypass transistor T8a may be connected in parallel to the first sub-driving transistor T1-1.

[0070] A first electrode of the storage capacitor Cst may receive the first power supply voltage ELVDD, and a second electrode of the storage capacitor Cst may be connected to the first node N1.

[0071] The light-emitting element LD may have an anode connected to the fifth node N5 and a cathode receiving the second power supply voltage ELVSS. The light-emitting element LD may emit light of one of a first color, a second color, and a third color. The light-emitting element LD may be a light-emitting diode. The light-emitting element LD may be configured as an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot / well light-emitting diode, etc. In the present embodiment, each pixel SPija includes only one light-emitting element LD, but in another embodiment, each pixel may include a plurality of light-emitting elements. In this case, the plurality of light-emitting elements may be connected in series, in parallel, or in series and parallel.

[0072] In an embodiment, the i-th second scan line GIi may be the same as the (i-1)-th first scan line GWi. In this case, the second scan line GIi and the first scan line GWi may be connected to the same scan driver (or sub-scan driver).

[0073] In another embodiment, the i-th second scan line GIi may be different from the (i-1)-th first scan line GWi. In this case, the second scan line GIi and the first scan line GWi may be connected to different sub-scan drivers.

[0074] Figure 3 and Figure 4 are diagrams for illustrating an example of a method for driving Figure 2 the pixels.

[0075] First, a scan signal at a cut-off level (logic high level) may be applied to the third scan line EMi to cut off the fifth transistor T5 and the sixth transistor T6, and the pixel SPija may be in a non-emitting state.

[0076] Next, a scan signal at a conductive level (logic low level) may be applied to the second scan line GIi to turn on the fourth transistor T4. Accordingly, the first initialization voltage VINT may be applied to the first node N1. The first initialization voltage VINT may be a voltage low enough and may bias the first transistor T1 to be turned on.

[0077] Next, a scan signal at a conductive level (logic low level) may be applied to the first scan line GWi to turn on the second transistor T2, the third transistor T3, and the seventh transistor T7.

[0078] Therefore, the data voltage of the data line VDj can be applied to the first node N1 through the turned-on second transistor T2, first transistor T1, and third transistor T3. In this case, the voltage of the first node N1 can be a compensated voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst can hold a voltage corresponding to the difference between the first power supply voltage ELVDD and the compensated voltage.

[0079] In addition, since the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and the light-emitting element LD can be initialized with an electric charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, a low gray level can be easily represented by the light-emitting element LD.

[0080] Next, a scan signal with a conductive level (logic low level) can be applied to the third scan line EMi to turn on the fifth transistor T5 and the sixth transistor T6. Therefore, a path can be formed for the drive current to flow from the first power supply voltage ELVDD through the fifth transistor T5, first transistor T1, sixth transistor T6, and light-emitting element LD toward the second power supply voltage ELVSS.

[0081] The drive current amount can be adjusted according to the voltage held in the storage capacitor Cst. The light-emitting element LD can emit light with a brightness corresponding to the drive current amount. The light-emitting element LD can emit light until a scan signal with a cut-off level is applied to the third scan line EMi.

[0082] Reference Figure 4 , the bypass transistor T8a can be turned off in the first mode MODE1 and turned on in the second mode MODE2. For example, a bypass signal CB with a cut-off level (logic high level) can be provided in the first mode MODE1, and a bypass signal CB with a conductive level (logic low level) can be provided in the second mode MODE2.

[0083] For the same input image, the pixel SPija can output an image with a first brightness in the first mode MODE1 and an image with a second brightness in the second mode MODE2. In this case, the second brightness can be greater than the first brightness.

[0084] Since the bypass transistor T8a is turned off in the first mode MODE1, both the first sub-driving transistor T1-1 and the second sub-driving transistor T1-2 can be present in the path of the driving current. On the other hand, since the bypass transistor T8a is turned on in the second mode MODE2, the driving current can pass through the bypass transistor T8a instead of the first sub-driving transistor T1-1. Therefore, in the second mode MODE2, only the second sub-driving transistor T1-2 can be present in the path of the driving current. Accordingly, the channel length of the first transistor T1 in the second mode MODE2 can be shorter than the channel length of the first transistor T1 in the first mode MODE1.

[0085] Thus, even when the data voltage, the first power supply voltage ELVDD, the second power supply voltage ELVSS, the first initialization voltage VINT, and the second initialization voltage VAINT are the same, the second luminance in the second mode MODE2 can be higher than the first luminance in the first mode MODE1. Accordingly, according to the present embodiment, a display device capable of achieving high luminance without a higher voltage can be provided.

[0086] Figures 5 to 10 is a diagram for explaining Figure 2 an example of the layout of the pixel circuit.

[0087] Referring to Figure 5 , the pixel circuit SPCa may have a structure in which a stacked substrate SUB, an active layer ACL, a first insulating layer INL1, a first electrode layer CEL1, a second insulating layer INL2, a second electrode layer CEL2, a third insulating layer INL3, a third electrode layer CEL3, a fourth insulating layer INL4, and a fourth electrode layer CEL4 are stacked.

[0088] The substrate SUB may be made of various materials such as glass, polymers, and metals. The substrate SUB may be selected from a rigid substrate and a flexible substrate according to the product to be applied. When the substrate SUB includes a polymeric organic material, the substrate SUB may be made of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetyl cellulose, cellulose acetate propionate, etc. On the other hand, the substrate SUB may be made of a fiber-reinforced plastic (FRP).

[0089] Although not shown, a barrier layer or a buffer layer may be selectively formed on the substrate SUB to prevent impurities from diffusing from the substrate SUB or moisture from penetrating from the substrate SUB into the active layer ACL made of a semiconductor. The barrier layer or the buffer layer may be made of silicon nitride (SiN x ), silicon oxide (SiO x) made of silicon oxynitride (SiO x N y ), etc.

[0090] The active layer ACL can be a semiconductor layer. For example, the active layer ACL can be made of polysilicon, amorphous silicon, oxide semiconductor, organic semiconductor, etc. The active layer ACL can include the channels, first electrodes, and second electrodes of each of transistors T1 to T8a. The first electrodes and second electrodes of each of transistors T1 to T8a can be doped with impurities.

[0091] The first electrode layer CEL1, second electrode layer CEL2, third electrode layer CEL3, and fourth electrode layer CEL4 can be conductive layers. Each electrode layer can be composed of a single layer or multiple layers, and can be made of known conductors such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or platinum (Pt).

[0092] The first insulating layer INL1, second insulating layer INL2, third insulating layer INL3, and fourth insulating layer INL4 can be interposed to electrically isolate the active layer ACL and the first electrode layer CEL1, second electrode layer CEL2, third electrode layer CEL3, and fourth electrode layer CEL4. The electrode patterns can be connected to each other through contact holes formed in each of the insulating layers INL1, INL2, INL3, and INL4. The insulating layers INL1, INL2, INL3, and INL4 can be formed of an organic insulating film, an inorganic insulating film, or an organic / inorganic insulating film, etc., and can be composed of a single layer or multiple layers. For example, the insulating layers INL1, INL2, INL3, and INL4 can be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), etc. Hereinafter, in Figures 6 to 10 , the insulating layers INL1, INL2, INL3, and INL4 are not shown separately.

[0093] Refer to Figure 6 , and a pattern of the active layer ACL is shown as an example.

[0094] Refer to Figure 7, by way of example, the pattern of the first electrode layer CEL1 may overlap with the active layer ACL. The portion of the first electrode layer CEL1 that overlaps with the active layer ACL may form the gate electrodes T1-1g, T1-2g, T2g, T3-1g, T3-2g, T4-1g, T4-2g, T5g, T6g, T7g, and T8ag of the transistors T1-1, T1-2, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, and T8a. The portion of the active layer ACL that overlaps with the gate electrodes T1-1g, T1-2g, T2g, T3-1g, T3-2g, T4-1g, T4-2g, T5g, T6g, T7g, and T8ag may form the channels of the transistors T1-1, T1-2, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, and T8a. The portions of the active layer ACL that are spaced apart from each other with channels interposed therebetween may form the first and second electrodes of the transistors T1-1, T1-2, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, and T8a.

[0095] In addition, some patterns of the first electrode layer CEL1 may form the first scan line GWi, the second scan line GIi, the third scan line EMi, and the second electrode Cst2e of the storage capacitor Cst.

[0096] Reference Figure 8 , by way of example, the pattern of the second electrode layer CEL2 overlaps with the active layer ACL and the first electrode layer CEL1. Some patterns of the second electrode layer CEL2 may form the first electrode Cst1e of the storage capacitor Cst and the bypass line CBL. The bypass line CBL may be a line to which a bypass signal CB is applied.

[0097] Reference Figure 9 In the embodiment of reference

[0098] Reference Figure 10 In the embodiment of reference

[0099] Figure 11 is a diagram for illustrating a pixel according to another embodiment of the present disclosure.

[0100] Referring Figure 11 , the pixel SPijb may include a pixel circuit SPCb and a light-emitting element LD. When describing Figure 11 the pixel SPijb, descriptions overlapping with those of the pixel SPija of Figure 2 will be omitted.

[0101] The bypass transistor T8b may be connected in parallel to the second sub-driving transistor T1-2. The bypass transistor T8b may have a gate electrode receiving a bypass signal CB, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0102] In Figure 11 the case of the embodiment of Figure 2 , in the second mode MODE2, the driving current may not pass through the second sub-driving transistor T1-2. In the second mode MODE2, the driving current may flow from the first power supply voltage ELVDD through the fifth transistor T5, the first sub-driving transistor T1-1, the bypass transistor T8b, the sixth transistor T6, and the light-emitting element LD toward the second power supply voltage ELVSS. Therefore, the channel length of the first transistor T1 in the second mode MODE2 may be shorter than the channel length of the first transistor T1 in the first mode MODE1, and the same effect as that in the pixel SPija of

[0103] Figures 12 to 14 is a diagram for illustrating a display device according to other embodiments of the present disclosure.

[0104] When describing Figures 12 to 14 the display devices 10b, 10c, and 10d of Figure 1 , descriptions overlapping with those of the display device 10a of

[0105] Referring Figure 12 , the display device 10b may include a first mode selector 15.

[0106] The first mode selector 15 may be connected to the pixel unit 14 through first bypass lines CBL11, CBL12, ……, and CBL1n, where n may be an integer greater than 0. The first bypass lines CBL11, CBL12, ……, and CBL1n may extend in the second direction DR2 or in a direction opposite to the second direction DR2. The first bypass lines CBL11, CBL12, ……, and CBL1n may be arranged parallel to each other in the first direction DR1. The first bypass lines CBL11, CBL12, ……, and CBL1n may be arranged parallel to the scan lines.

[0107] The gate electrode of the bypass transistor of each pixel of the pixel unit 14 may be connected to any one of the first bypass lines CBL11, CBL12, ……, and CBL1n. The pixels of the pixel unit 14 may include a first pixel group (e.g., a pixel row) connected to the same scan line. Different first pixel groups (e.g., pixel rows) may be connected to different first bypass lines CBL11, CBL12, ……, and CBL1n.

[0108] According to the present embodiment, the first mode selector 15 may drive certain pixel rows in the second mode MODE2 and drive the remaining pixel rows in the first mode MODE1.

[0109] Reference Figure 13 , the display device 10c may include a second mode selector 16.

[0110] The second mode selector 16 may be connected to the pixel unit 14 through the second bypass lines CBL21, CBL22, ……, and CBL2m, where m may be an integer greater than 0. The second bypass lines CBL21, CBL22, ……, and CBL2m may extend in the first direction DR1 or in the direction opposite to the first direction DR1. The second bypass lines CBL21, CBL22, ……, and CBL2m may be arranged parallel to each other in the second direction DR2. The second bypass lines CBL21, CBL22, ……, and CBL2m may be arranged parallel to the data lines.

[0111] The gate electrode of the bypass transistor of each pixel of the pixel unit 14 may be connected to any one of the second bypass lines CBL21, CBL22, ……, and CBL2m. The pixels of the pixel unit 14 may include a second pixel group (e.g., a pixel column) connected to the same data line. Different second pixel groups (e.g., pixel columns) may be connected to different second bypass lines CBL21, CBL22, ……, and CBL2m.

[0112] According to the present embodiment, the second mode selector 16 may drive certain pixel columns in the second mode MODE2 and drive the remaining pixel columns in the first mode MODE1.

[0113] Reference Figure 14 , the display device 10d may include a first mode selector 15 and a second mode selector 16.

[0114] The first mode selector 15 can be connected to the pixel unit 14 via the first bypass lines CBL11, CBL12, ……, and CBL1n, where n can be an integer greater than 0. The first bypass lines CBL11, CBL12, ……, and CBL1n can extend in the second direction DR2 or in the direction opposite to the second direction DR2. The first bypass lines CBL11, CBL12, ……, and CBL1n can be arranged parallel to each other in the first direction DR1. The first bypass lines CBL11, CBL12, ……, and CBL1n can be arranged parallel to the scan lines.

[0115] The second mode selector 16 can be connected to the pixel unit 14 via the second bypass lines CBL21, CBL22, ……, and CBL2m, where m can be an integer greater than 0. The second bypass lines CBL21, CBL22, ……, and CBL2m can extend in the first direction DR1 or in the direction opposite to the first direction DR1. The second bypass lines CBL21, CBL22, ……, and CBL2m can be arranged parallel to each other in the second direction DR2. The second bypass lines CBL21, CBL22, ……, and CBL2m can be arranged parallel to the data lines.

[0116] The first bypass lines CBL11, CBL12, ……, and CBL1n can be arranged to cross the second bypass lines CBL21, CBL22, ……, and CBL2m.

[0117] Each pixel can be connected to one of the first bypass lines CBL11, CBL12, ……, and CBL1n and one of the second bypass lines CBL21, CBL22, ……, and CBL2m.

[0118] Pixels can include a first pixel group (e.g., a pixel row) connected to the same scan line, and different first pixel groups can be connected to different first bypass lines CBL11, CBL12, ……, and CBL1n. In addition, pixels can include a second pixel group (e.g., a pixel column) connected to the same data line, and different second pixel groups can be connected to different second bypass lines CBL21, CBL22, ……, and CBL2m.

[0119] Figure 15 is a diagram for illustrating Figure 14 the pixels of the display device.

[0120] In Figure 15 the components of the pixel SPijc, the description of the components overlapping with the components of the pixel SPija in Figure 2 will be omitted.

[0121] Refer to Figure 15, the bypass transistor T8c of the pixel SPijc may include a first sub-bypass transistor T8c1 and a second sub-bypass transistor T8c2 connected in series.

[0122] The gate electrode of the first sub-bypass transistor T8c1 may be connected to a first bypass line CBL1i among the first bypass lines CBL11, CBL12, ……, and CBL1n. The gate electrode of the second sub-bypass transistor T8c2 may be connected to a second bypass line CBL2j among the second bypass lines CBL21, CBL22, ……, and CBL2m.

[0123] When a bypass signal of a conduction level is applied to the first bypass line CBL1i and the second bypass line CBL2j and both the first sub-bypass transistor T8c1 and the second sub-bypass transistor T8c2 are turned on, the pixel SPijc may be driven in the second mode MODE2. In other cases, the pixel SPijc may be driven in the first mode MODE1.

[0124] As described above, according to Figure 14 and Figure 15 's embodiment, a specific area of the pixel unit 14 may be driven in the second mode MODE2, and the remaining area may be driven in the first mode MODE1.

[0125] Figure 16 is a diagram for illustrating a pixel according to another embodiment of the present disclosure.

[0126] Referring to Figure 16 , the pixel SPijd may include a pixel circuit SPCd and a light-emitting element LD, where i and j may be integers greater than 0. The pixel circuit SPCd may include transistors T1, T2, T3d, T4d, T5, T6, T7, T8d, and T9d and a storage capacitor Cst. The pixel SPijd may refer to a pixel connected to the i-th scan line and the j-th data line. Here, the pixel SPijd may be a first pixel for representing a first color. Since the second pixel for representing a second color and the third pixel for representing a third color may have the same configuration as the first pixel, repeated descriptions will be omitted.

[0127] In this embodiment, the P-type transistor may be a polysilicon transistor. In the polysilicon transistor, the channel of the active layer may include polysilicon. For example, the polysilicon transistor may be a low-temperature polysilicon (LTPS) thin-film transistor. The polysilicon transistor may have a high electron mobility and thus may have fast driving characteristics.

[0128] In this embodiment, the N-type transistor can be an oxide transistor. In the oxide transistor, the channel of the active layer can include an oxide semiconductor. For example, the oxide transistor can be a low-temperature polycrystalline oxide (LTPO) thin-film transistor. The oxide transistor can have a lower charge mobility than a polysilicon transistor. Therefore, in the off state, the oxide transistor can have a smaller leakage current than a polysilicon transistor.

[0129] The first transistor T1 can have a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the fourth node N4. The first transistor T1 can also include a sub-gate electrode. The sub-gate electrode can receive the first power supply voltage ELVDD. The first transistor T1 can be a driving transistor. The first transistor T1 can be a P-type transistor.

[0130] The first transistor T1 can include a first sub-driving transistor T1-1 and a second sub-driving transistor T1-2. The first sub-driving transistor T1-1 can have a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The second sub-driving transistor T1-2 can have a gate electrode connected to the first node N1, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0131] The second transistor T2 can have a gate electrode connected to the first scan line GWi, a first electrode connected to the data line VDj, and a second electrode connected to the second node N2. The second transistor T2 can be a scan transistor. The second transistor T2 can be a P-type transistor.

[0132] The third transistor T3d can have a gate electrode connected to the second scan line GCi, a first electrode connected to the first node N1, and a second electrode connected to the fourth node N4. The third transistor T3d can also include a sub-gate electrode. The sub-gate electrode can be connected to the second scan line GCi. The third transistor T3d can be a diode-connected transistor. The third transistor T3d can be an N-type transistor.

[0133] The fourth transistor T4d can have a gate electrode connected to the third scan line GIi, a first electrode connected to the first node N1, and a second electrode receiving the first initialization voltage VINT. The fourth transistor T4d can also include a sub-gate electrode. The sub-gate electrode can be connected to the third scan line GIi. The fourth transistor T4d can be a gate initialization transistor. The fourth transistor T4d can be an N-type transistor.

[0134] The fifth transistor T5 may have a gate electrode connected to the fourth scan line EMi, a first electrode receiving a first power supply voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 may be a first emission control transistor. The fifth transistor T5 may be a P-type transistor.

[0135] The sixth transistor T6 may have a gate electrode connected to the fourth scan line EMi, a first electrode connected to the fourth node N4, and a second electrode connected to the fifth node N5. The sixth transistor T6 may be a second emission control transistor. The sixth transistor T6 may be a P-type transistor.

[0136] The seventh transistor T7 may have a gate electrode connected to the fifth scan line GBi, a first electrode receiving a second initialization voltage VAINT, and a second electrode connected to the fifth node N5. The seventh transistor T7 may be an anode initialization transistor. The seventh transistor T7 may be a P-type transistor.

[0137] The bypass transistor T8d may have a gate electrode receiving a bypass signal CB, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The bypass transistor T8d may be connected in parallel to the first sub-driving transistor T1-1. The bypass transistor T8d may be a P-type transistor.

[0138] The bias transistor T9d may have a gate electrode connected to the fifth scan line GBi, a first electrode for receiving a bias voltage VOBS, and a second electrode connected to the second node N2. The bias transistor T9d may be a P-type transistor.

[0139] The first electrode of the storage capacitor Cst may receive the first power supply voltage ELVDD, and the second electrode of the storage capacitor Cst may be connected to the first node N1.

[0140] The light-emitting element LD may have an anode connected to the fifth node N5 and a cathode receiving a second power supply voltage ELVSS. The light-emitting element LD may emit light of one of a first color, a second color, and a third color. The light-emitting element LD may be a light-emitting diode. The light-emitting element LD may be configured as an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot / well light-emitting diode, etc. In the present embodiment, each pixel SPijd includes only one light-emitting element LD, but in another embodiment, each pixel may include a plurality of light-emitting elements. In this case, the plurality of light-emitting elements may be connected in series, in parallel, or in series and in parallel.

[0141] Figure 17 is an example for explaining a method for driving Figure 16 the pixels.

[0142] First, a scan signal with a cut-off level (logic high level) can be applied to the fourth scan line EMi to cut off the fifth transistor T5 and the sixth transistor T6, and the pixel SPijd can be in a non-emission state.

[0143] Next, a scan signal with a conductive level (logic high level) can be applied to the third scan line GIi to turn on the fourth transistor T4d. Thus, the first initialization voltage VINT can be applied to the first node N1. The first initialization voltage VINT can be a voltage low enough and can bias the first transistor T1 to be turned on.

[0144] Next, a scan signal with a conductive level (logic high level) can be applied to the second scan line GCi to turn on the third transistor T3d. In addition, a scan signal with a conductive level (logic low level) can be applied to the first scan line GWi to turn on the second transistor T2.

[0145] Thus, the data voltage of the data line VDj can be applied to the first node N1 through the turned-on second transistor T2, the first transistor T1, and the third transistor T3d. In this case, the voltage of the first node N1 can be a compensated voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst can hold a voltage corresponding to the difference between the first power supply voltage ELVDD and the compensated voltage.

[0146] Next, a scan signal with a conductive level (logic low level) can be applied to the fifth scan line GBi to turn on the seventh transistor T7 and the bias transistor T9d. Thus, the second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and the light-emitting element LD can be initialized with an electric charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Thus, a low gray level can be easily represented in the light-emitting element LD.

[0147] Next, a scan signal with a conductive level (logic low level) can be applied to the fourth scan line EMi to turn on the fifth transistor T5 and the sixth transistor T6. Thus, a path can be formed for the drive current to flow from the first power supply voltage ELVDD through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting element LD toward the second power supply voltage ELVSS.

[0148] The drive current amount can be adjusted according to the voltage held in the storage capacitor Cst. The light-emitting element LD can emit light with a brightness corresponding to the drive current amount. The light-emitting element LD can emit light until a scan signal with a cut-off level is applied to the fourth scan line EMi. The operations in the first mode MODE1 and the second mode MODE2 can refer to Figure 4 the description.

[0149] Figures 18 to 27 is a diagram for illustrating Figure 16 an example of the layout of a pixel circuit.

[0150] Referring to Figure 18 , the pixel circuit SPCd may have a structure in which a substrate SUB, a first electrode layer CEL1, a first insulating layer INL1, a first active layer ACL1, a second insulating layer INL2, a second electrode layer CEL2, a third insulating layer INL3, a third electrode layer CEL3, a fourth insulating layer INL4, a second active layer ACL2, a fifth insulating layer INL5, a fourth electrode layer CEL4, a sixth insulating layer INL6, a fifth electrode layer CEL5, a seventh insulating layer INL7, and a sixth electrode layer CEL6 are sequentially stacked.

[0151] The substrate SUB may be made of various materials such as glass, polymers, and metals. The substrate SUB may be selected from a rigid substrate and a flexible substrate according to the product to be applied. When the substrate SUB includes a polymeric organic material, the substrate SUB may be made of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. On the other hand, the substrate SUB may be made of fiberglass-reinforced plastic (FRP).

[0152] The first active layer ACL1 and the second active layer ACL2 may be semiconductor layers. For example, the first active layer ACL1 may be made of polysilicon, and the second active layer ACL2 may be made of an oxide semiconductor. The first active layer ACL1 may include the channels, first electrodes, and second electrodes of each of transistors T1, T2, T5, T6, T7, T8d, and T9d. The second active layer ACL2 may include the channels, first electrodes, and second electrodes of each of transistors T3d and T4d. The first electrodes and second electrodes of each of transistors T1 to T9d may be doped with impurities.

[0153] The first electrode layer CEL1, the second electrode layer CEL2, the third electrode layer CEL3, the fourth electrode layer CEL4, the fifth electrode layer CEL5, and the sixth electrode layer CEL6 may be conductive layers. Each electrode layer may be composed of a single layer or multiple layers and may be made of known conductors such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or platinum (Pt).

[0154] The first insulating layer INL1, the second insulating layer INL2, the third insulating layer INL3, the fourth insulating layer INL4, the fifth insulating layer INL5, the sixth insulating layer INL6, and the seventh insulating layer INL7 can be interposed to electrically isolate the active layers ACL1 and ACL2 and the first electrode layer CEL1, the second electrode layer CEL2, the third electrode layer CEL3, the fourth electrode layer CEL4, the fifth electrode layer CEL5, and the sixth electrode layer CEL6. The electrode patterns can be connected to each other through contact holes formed in each of the insulating layers INL1, INL2, INL3, INL4, INL5, INL6, and INL7. The insulating layers INL1, INL2, INL3, INL4, INL5, INL6, and INL7 can be formed of an organic insulating film, an inorganic insulating film, an organic / inorganic insulating film, etc., and can be composed of a single layer or multiple layers. For example, the insulating layers INL1, INL2, INL3, INL4, INL5, INL6, and INL7 can be formed of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), etc.

[0155] Hereinafter, in Figures 19 to 27 , the insulating layers INL1, INL2, INL3, INL4, INL5, INL6, and INL7 are not shown separately.

[0156] Figure 19 The pattern of the first electrode layer CEL1 in an exemplary embodiment is shown. Some patterns of the first electrode layer CEL1 can constitute the sub-gate electrode T1sg of the first transistor T1.

[0157] Figure 20 The pattern of the first active layer ACL1 in an exemplary embodiment is shown. The first active layer ACL1 can include the channels T1-1c, T1-2c, T2c, T5c, T6c, T7c, T8c, and T9c of the transistors T1-1, T1-2, T2, T5, T6, T7, T8d, and T9d. The portions of the first active layer ACL1 that are spaced apart from each other and have channels interposed therebetween can constitute the first and second electrodes of the transistors T1-1, T1-2, T2, T5, T6, T7, T8d, and T9d.

[0158] Figure 21Shows the pattern of the second electrode layer CEL2 in an exemplary embodiment. The second electrode layer CEL2 may include gate electrodes T1-1g, T1-2g, T2g, T5g, T6g, T7g, T8g, and T9g of transistors T1-1, T1-2, T2, T5, T6, T7, T8d, and T9d. The gate electrodes T1-1g, T1-2g, T2g, T5g, T6g, T7g, T8g, and T9g may overlap with channels T1-1c, T1-2c, T2c, T5c, T6c, T7c, T8c, and T9c.

[0159] In addition, some patterns of the second electrode layer CEL2 may form the first scan line GWi, the fourth scan line EMi, the fifth scan line GBi, and the second electrode Cst2e of the storage capacitor Cst.

[0160] Figure 22 Shows the pattern of the third electrode layer CEL3 in an exemplary embodiment. Some patterns of the third electrode layer CEL3 may form the first electrode Cst1e of the storage capacitor Cst and the second initialization line VAINTL. The second initialization voltage VAINT may be applied to the second initialization line VAINTL.

[0161] Figure 23 Shows the pattern of the second active layer ACL2 in an exemplary embodiment. The second active layer ACL2 may include channels T3c and T4c of transistors T3d and T4d. Portions of the second active layer ACL2 that are spaced apart from each other with channels interposed therebetween may form the first and second electrodes of transistors T3d and T4d.

[0162] Figure 24 Shows the pattern of the fourth electrode layer CEL4 in an exemplary embodiment. The fourth electrode layer CEL4 may include gate electrodes T3g and T4g of transistors T3d and T4d. The gate electrodes T3g and T4g may overlap with channels T3c and T4c.

[0163] In addition, some patterns of the fourth electrode layer CEL4 may form the second scan line GCi, the third scan line GIi, the bypass line CBL, and the bias line VOBSL. The bypass signal CB may be applied to the bypass line CBL. The bias voltage VOBS may be applied to the bias line VOBSL.

[0164] Figure 25 Depicts the pattern of the fifth electrode layer CEL5 in an exemplary embodiment. Some patterns of the fifth electrode layer CEL5 may form the first initialization line VINTL. The first initialization voltage VINT may be applied to the first initialization line VINTL.

[0165] Figure 26Shows the pattern of the sixth electrode layer CEL6 in an exemplary embodiment. Some patterns of the sixth electrode layer CEL6 can form the first power supply line ELVDDL and the data line VDj. The first power supply voltage ELVDD can be applied to the first power supply line ELVDDL.

[0166] Figure 27 Depicts the first electrode layer CEL1, the first active layer ACL1, the second electrode layer CEL2, the third electrode layer CEL3, the second active layer ACL2, the fourth electrode layer CEL4, the fifth electrode layer CEL5, and the sixth electrode layer CEL6 that overlap each other.

[0167] Figures 28 to 31 Depicts the widths and lengths of the channels of the first sub-driving transistor and the second sub-driving transistor according to an embodiment of the present disclosure.

[0168] Figures 28 to 31 Is Figure 20 An enlarged view of the portion of the first active layer ACL1 where the first channel CH1-1 of the first sub-driving transistor T1-1 and the second channel CH1-2 of the second sub-driving transistor T1-2 are located. The following embodiments can be similarly applied to Figures 1 to 15 The sub-driving transistors T1-1 and T1-2, and their repeated descriptions will be omitted.

[0169] Refer to Figure 28 , the width W1 of the first channel CH1-1 of the first sub-driving transistor T1-1 can be equal to the width W2 of the second channel CH1-2 of the second sub-driving transistor T1-2. In addition, the length L1 of the first channel CH1-1 can be equal to the length L2 of the second channel CH1-2.

[0170] For example, the width W1 of the first channel CH1-1 can be 3.5 μm (micrometers), and the length L1 can be 13.5 μm. The width W2 of the second channel CH1-2 can be 3.5 μm, and the length L2 can be 13.5 μm.

[0171] In this case, in the first mode MODE1, the width of the channel of the first transistor T1 can be 3.5 μm, and the length can be 27.0 μm. In addition, in the second mode MODE2, the width of the channel of the first transistor T1 can be 3.5 μm, and the length can be 13.5 μm.

[0172] Refer to Figure 29, the width W1 of the first channel CH1-1 of the first sub-driving transistor T1-1 may be equal to the width W2 of the second channel CH1-2 of the second sub-driving transistor T1-2. However, the length L1 of the first channel CH1-1 may be different from the length L2 of the second channel CH1-2 (e.g., longer than the length L2 of the second channel CH1-2).

[0173] For example, the width W1 of the first channel CH1-1 may be 3.5 μm, and the length L1 may be 16.5 μm. The width W2 of the second channel CH1-2 may be 3.5 μm, and the length L2 may be 10.5 μm.

[0174] In this case, in the first mode MODE1, the width of the channel of the first transistor T1 may be 3.5 μm, and the length may be 27.0 μm. In addition, in the second mode MODE2, the width of the channel of the first transistor T1 may be 3.5 μm, and the length may be 10.5 μm.

[0175] Therefore, according to Figure 29 's embodiment, compared with Figure 28 's embodiment, because a larger driving current can be generated due to the shorter channel in the second mode MODE2, higher brightness can be achieved.

[0176] Referring to Figure 30 , the width W1 of the first channel CH1-1 of the first sub-driving transistor T1-1 may be different from the width W2 of the second channel CH1-2 of the second sub-driving transistor T1-2 (e.g., smaller than the width W2 of the second channel CH1-2 of the second sub-driving transistor T1-2). In this case, the length L1 of the first channel CH1-1 may be equal to the length L2 of the second channel CH1-2.

[0177] For example, the width W1 of the first channel CH1-1 may be 3.0 μm, and the length L1 may be 13.5 μm. In addition, the width W2 of the second channel CH1-2 may be 4.2 μm, and the length L2 may be 13.5 μm.

[0178] In this case, in the first mode MODE1, the width of the channel of the first transistor T1 may be 3.5 μm, and the length may be 27.0 μm (for comparison, the width is equal to Figure 28 's width). In the second mode MODE2, the width of the channel of the first transistor T1 may be 3.5 μm, and the length may be 11.25 μm (11.25 = 13.5 * 3.5 / 4.2) (for comparison, the width is equal to Figure 28 's width).

[0179] Therefore, according toFigure 30 The embodiment of Figure 28 Compared with the embodiment of

[0180] Referring to Figure 31 , the width W1 and length L1 of the first channel CH1-1 of the first sub-driving transistor T1-1 can be different from the width W2 and length L2 of the second channel CH1-2 of the second sub-driving transistor T1-2. In the depicted example, the width W1 of the first channel CH1-1 is less than the width W2 of the second channel CH1-2, and the length L1 of the first channel CH1-1 can be greater than the length L2 of the second channel CH1-2.

[0181] In one embodiment, the width W1 of the first channel CH1-1 can be 3.0 μm, and the length L1 can be 15.65 μm. The width W2 of the second channel CH1-2 can be 4.2 μm, and the length L2 can be 10.5 μm.

[0182] In this case, in the first mode MODE1, the width of the channel of the first transistor T1 can be 3.5 μm, and the length can be 27.0 μm (for comparison, the width is equal to Figure 28 the width in the embodiment of Figure 28 ). In the second mode MODE2, the width of the channel of the first transistor T1 can be 3.5 μm, and the length can be 8.75 μm (8.75 = 10.5 * 3.5 / 4.2) (for comparison, the width is the same as in

[0183] Therefore, according to Figure 31 the embodiment of Figure 28 , Figure 29 and Figure 30 Compared with the embodiments of

[0184] The display device according to an embodiment of the present disclosure can display an image with high brightness even when a higher voltage is not provided.

[0185] The accompanying drawings and the above detailed description of the present disclosure are merely illustrative of the present disclosure. It should be understood that the present disclosure is disclosed only for the purpose of illustration and is not intended to limit the meaning or scope of the present disclosure as set forth in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments are possible without departing from the scope of the present disclosure. Therefore, the actual technical protection scope of the present disclosure should be determined by the technical idea of the appended claims.

Claims

1. A display device, characterized in that, Comprising: Pixels Each of the pixels includes a first transistor and a bypass transistor, The first transistor includes a first sub-driving transistor and a second sub-driving transistor, The first sub-driving transistor has a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, The second sub-driving transistor has a gate electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to a fourth node, and The bypass transistor is connected in parallel with one of the first sub-driving transistor and the second sub-driving transistor.

2. The display device according to claim 1, wherein The bypass transistor is turned off in the first mode and turned on in the second mode.

3. The display device according to claim 2, characterized in that For the same input image, the pixel outputs an image with a first brightness in the first mode and an image with a second brightness in the second mode, and The second brightness is greater than the first brightness.

4. The display device according to claim 1, wherein The gate electrode of the bypass transistor is connected to a bypass line, and The bypass lines are commonly connected to the pixels.

5. The display device according to claim 1, wherein The gate electrode of the bypass transistor is connected to any one of the bypass lines, The pixel includes a group of pixels connected to the same scan line, and Different groups of pixels are connected to different bypass lines.

6. The display device according to claim 1, wherein The gate electrode of the bypass transistor is connected to any one of the bypass lines, The pixel includes a group of pixels connected to the same data line, and Different groups of pixels are connected to different bypass lines.

7. The display device according to claim 1, wherein The bypass transistor includes a first sub-bypass transistor and a second sub-bypass transistor connected in series, The gate electrode of the first sub-bypass transistor is connected to any one of the first bypass lines, and The gate electrode of the second sub-bypass transistor is connected to any one of the second bypass lines.

8. The display device according to claim 7, wherein The first bypass line extends in a direction not parallel to the direction in which the second bypass line extends.

9. The display device according to claim 7, characterized in that, The pixel includes a first group of pixels connected to the same scan line, Different first groups of pixels are connected to different first bypass lines, The pixel includes a second group of pixels connected to the same data line, and Different second groups of pixels are connected to different second bypass lines.

10. The display device according to claim 1, characterized in that, The width of the first channel of the first sub-driving transistor is equal to the width of the second channel of the second sub-driving transistor, and The length of the first channel is equal to the length of the second channel.

Images