Array substrate, display panel and display device
By designing two types of shielding parts with different patterns on the array substrate, we distinguish the defects that require immediate repair and delayed repair, and solve the scrapping problem of embedded touch products due to particles, and improve the production yield and production efficiency.
Patent Information
- Application Number
- CN202422211506.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2034-09-10
AI Technical Summary
In the prior art, when the particles of the embedded touch product fall between the second metal layer and the third metal layer, laser repair cannot be carried out, resulting in product scrapping and affecting production yield and production time.
Two types of shielding parts with different patterns are designed on the array substrate. Through the design of the first type of shielding parts with marking parts and the second type of shielding parts without marking parts, we distinguish defects that need to be repaired immediately and defects that can be repaired after the array substrate is completed, ensuring the effectiveness of laser maintenance.
Improve product yield, avoid scrapping caused by the inability to laser repair, and ensure the continuity of production efficiency and production time.
Smart Images
Figure CN223123343U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of display, in particular to an array substrate, a display panel and a display device. Background Art
[0002] With the development of technology, display devices are widely used in many electronic products, such as mobile phones, tablet computers, watches, cars, etc. A display panel generally includes an array substrate and an opposing substrate (color filter substrate). Taking the array substrate as an example, thin film transistors, signal lines, etc. are arranged in an array thereon. Generally, production is carried out in a dust-free clean room. If particles in the air fall on the substrate during the production process, it may cause defects such as open circuits or short circuits in the product. These defects will cause abnormal display in the display panel (such as vertical bright lines, etc.), and then this display panel can only be downgraded or even scrapped, resulting in a decrease in production yield. However, if the open circuits caused by these particles are repaired and the particles causing short circuits are eliminated through the method of laser repair, the display panel may be able to display normally and the production yield can be improved.
[0003] During the repair process, taking the example that particles fall on the second metal layer, the operator can operate a laser repair machine to disperse the particles on the second metal layer circuit by laser energy, and repair the circuit if there is an open circuit caused by the particles. In actual operation, if these defects are found directly after the second metal layer is fabricated and the product is sent for laser repair, it will affect the production schedule of the entire batch of products. Therefore, the general method is to first mark / record the positions of the product to be repaired, and the product continues the subsequent production process. After the manufacturing process of the array substrate is completed, the laser repair of the previously marked points is carried out together. With the progress of technology, in-cell touch (iTP) products are becoming more and more popular. Please refer to Figure 1 , Figure 1 which is a partial cross-sectional schematic diagram of an array substrate in the prior art. In in-cell touch products, there will be a third metal layer M3 circuit as a touch electrode lead, and the third metal layer M3 circuit covers part of the second metal layer M2 circuit. As Figure 1 shown, when the aforementioned particle P is located between the second metal layer M2 circuit and the third metal layer M3 circuit above it, due to the shielding of the third metal layer M3 circuit, laser repair can no longer be carried out, resulting in the scrapping of the product. Summary of the Utility Model
[0004] The purpose of the utility model is to provide an array substrate, a display panel and a display device to solve the above problems.
[0005] To achieve the above object, the present utility model provides an array substrate, which includes a plurality of gate lines, a plurality of data lines, a plurality of touch electrode lines, a plurality of first type shielding members, and a plurality of second type shielding members. The plurality of gate lines extend along a first direction, and the plurality of gate lines include a first gate line; the plurality of data lines extend along a second direction, and the plurality of data lines include a first data line and a second data line to form a first sub-pixel unit and a second sub-pixel unit with the first gate line. The first sub-pixel unit has a first thin film transistor connected to the first gate line and the first data line, and the second sub-pixel unit has a second thin film transistor connected to the first gate line and the second data line; the plurality of touch electrode lines extend along the second direction, and the plurality of touch electrode lines include a first touch electrode line, and the first touch electrode line at least partially covers the first data line; a first type shielding member is provided corresponding to the first thin film transistor, and a second type shielding member is provided corresponding to the second thin film transistor; wherein, each first type shielding member includes a first shielding portion and a first identification portion, the first identification portion is disposed beside the first shielding portion and is not connected to the first shielding portion, and each second type shielding member includes a second shielding portion and does not include an identification portion.
[0006] As an optional technical solution, the first thin film transistor has a first semiconductor layer, the second thin film transistor has a second semiconductor layer, the first shielding portion is provided corresponding to the first semiconductor layer, and the second shielding portion is provided corresponding to the second semiconductor layer.
[0007] As an optional technical solution, the first shielding portion is rectangular, and the first identification portion is trapezoidal, circular, triangular or rectangular.
[0008] As an optional technical solution, the size of the first identification portion is much smaller than that of the first shielding portion.
[0009] As an optional technical solution, the plurality of data lines include a third data line, the third data line, the first data line and the second data line are arranged along the first direction or the first data line, the second data line and the third data line are arranged along the first direction. The third data line and the first gate line form a third sub-pixel unit, the third sub-pixel unit has a third thin film transistor, and a second type shielding member is provided corresponding to the third thin film transistor.
[0010] As an optional technical solution, the plurality of gate lines include a second gate line, the first gate line and the second gate line are arranged along the second direction, the first data line and the second gate line form a fourth sub-pixel unit, the fourth sub-pixel unit has a fourth thin film transistor, and a first type shielding member is provided corresponding to the fourth thin film transistor.
[0011] As an alternative technical solution, the multiple gate lines and the first data lines form a plurality of first-type sub-pixel units, each first-type sub-pixel unit having a corresponding first-type thin-film transistor, and each first-type thin-film transistor being correspondingly provided with a first-type shielding member.
[0012] As an alternative technical solution, the multiple gate lines and the second data lines form a plurality of second-type sub-pixel units, each second-type sub-pixel unit having a corresponding second-type thin-film transistor, and each second-type thin-film transistor being correspondingly provided with a second-type shielding member.
[0013] In addition, the present utility model further provides a display panel, which includes the aforementioned array substrate, a counter substrate, and a sealing member, and the array substrate and the counter substrate are hermetically connected via the sealing member.
[0014] The present utility model further provides a display device, which includes the aforementioned display panel and a backlight module, and the display panel is located on the backlight module.
[0015] In the present utility model, two types of shielding members with different patterns are formed. When the production of each data line and the source and drain electrodes of each thin-film transistor is completed, it is easy to distinguish, via the two types of shielding members, the defects that need to be repaired immediately from the defects that can be repaired after the production of the array substrate is completed. This can not only improve the product yield rate through repair but also ensure the production efficiency and avoid affecting the product production schedule.
[0016] The present utility model will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but this is not a limitation to the present utility model. Description of the Drawings
[0017] Figure 1 is a partial cross-sectional schematic view of an array substrate in the prior art;
[0018] Figure 2A is a schematic view of the array substrate of the present utility model;
[0019] Figure 2B is a partial top view of the array substrate of the present utility model;
[0020] Figure 3 is Figure 2B a partial enlarged schematic view of
[0021] Figure 4 is a schematic view of the display panel of the present utility model;
[0022] Figure 5 is a schematic view of the display device of the present utility model. Detailed Description of the Embodiments
[0023] To further understand the purpose, structure, features and functions of the present utility model, the following detailed description is provided in conjunction with embodiments.
[0024] The following descriptions of the embodiments refer to the attached drawings to illustrate specific embodiments in which the present utility model can be implemented. Directional terms mentioned in the present utility model, such as "upper", "lower", "front", "rear", "left", "right", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for explaining and understanding the present utility model, rather than for limiting the present utility model.
[0025] Please refer to Figures 2A to 5 , Figure 2A which is a schematic diagram of the array substrate of the present utility model, Figure 2B which is a partial top view of the array substrate of the present utility model, Figure 3 is Figure 2B a partial enlarged schematic diagram of Figure 4 which is a schematic diagram of the display panel of the present utility model, Figure 5 which is a schematic diagram of the display device of the present utility model.
[0026] Combined with Figure 2A , Figure 2B and Figure 3 as shown, the array substrate 100 includes a first substrate (not labeled), a plurality of gate lines Gm to Gn, a plurality of data lines Dp to Dq, a plurality of touch electrode lines TLx to TLy (not shown), a plurality of first type shielding members SM1 and a plurality of second type shielding members SM2, where m, n, p, q, x, y are positive integers, and n > m, q > p, y > x. The plurality of gate lines Gm to Gn extend along the first direction F1, are arranged along the second direction F2 and include a first gate line G1. The plurality of data lines Dp to Dq extend along the second direction F2, are arranged along the first direction F1 and include a first data line D1 and a second data line D2. The plurality of touch electrode lines TLx to TLy extend along the second direction F2, are arranged along the first direction F1 and include a first touch electrode line TL1 (see Figure 3)。The first gate line G1, the first data line D1, and the second data line D2 form the first sub-pixel unit P1 and the second sub-pixel unit P2. The first sub-pixel unit P1 has a first thin-film transistor t1 connected to the first gate line G1 and the first data line D1, and the second sub-pixel unit P2 has a second thin-film transistor t2 connected to the first gate line G1 and the second data line D2. A first type of shielding member SM1 is provided corresponding to the first thin-film transistor t1, and a second type of shielding member SM2 is provided corresponding to the second thin-film transistor t2. Further, the first touch electrode line TL1 at least partially covers the first data line D1. Wherein, each first type of shielding member SM1 includes a first shielding portion s1 and a first identification portion r1, and the first identification portion r1 is disposed beside the first shielding portion s1 and is not connected to the first shielding portion s1. Each second type of shielding member SM2 includes a second shielding portion s2 and does not include an identification portion.
[0027] In an embodiment, the manufacturing steps of the array substrate 100 include:
[0028] Form a shielding metal layer M0, pattern the shielding metal layer M0 to form the first type of shielding member SM1 and the second shielding member SM2, and form a buffer layer over the entire surface;
[0029] Form a semiconductor film layer on the buffer layer, pattern the semiconductor film layer to form the semiconductor layers of the respective thin-film transistors, and form an insulating layer over the entire surface; As Figure 3 shown, the first thin-film transistor t1 has a first semiconductor layer, the second thin-film transistor t2 has a second semiconductor layer, the first shielding portion s1 is disposed corresponding to the first semiconductor layer, and the second shielding portion s2 is disposed corresponding to the second semiconductor layer.
[0030] Form a first metal layer M1, pattern the first metal layer M1 to form a plurality of gate lines Gm to Gn and the gates of the respective thin-film transistors, and cover an interlayer dielectric layer thereon; For the convenience of illustration and description, Figure 2B the gate lines Gm to Gn are not shown in the figure.
[0031] Form a second metal layer M2, pattern the second metal layer M2 to form a plurality of data lines Dp to Dq and the sources and drains of the respective thin-film transistors, and cover a planarization layer thereon;
[0032] Form a third metal layer M3, pattern the third metal layer M3 to form a plurality of touch electrode lines TLx to TLy. The plurality of touch electrode lines TLx to TLy cover a part of the plurality of data lines Dp to Dq. For the convenience of illustration and description, Figure 2B the plurality of touch electrode lines TLx to TLy are not shown in the figure, Figure 3 and the first touch electrode line TL1 is shown in the figure.
[0033] In one embodiment, the manufacturing process of the array substrate 100 further includes forming a first passivation layer, a common electrode layer, a second passivation layer, a pixel electrode layer, etc., which will not be elaborated herein.
[0034] In the prior art, the shape and structure of the shielding member corresponding to each thin film transistor are the same. Therefore, before forming multiple touch electrode lines TLx to TLy, the structural traces at each sub-pixel unit on the array substrate 100 are the same. After forming multiple data lines Dp to Dq and the source and drain electrodes of each thin film transistor using the second metal layer M2, if there are particles falling on it, since the structural traces everywhere are the same, the operator cannot distinguish whether the position where the particles fall will cover the touch electrode lines subsequently.
[0035] On the array substrate 100 of the present invention, two types of shielding members with different patterns are formed. The shielding member corresponding to the sub-pixel unit that will be covered with a third metal layer M3 such as touch electrode lines TLx to TLy later is the first type of shielding member SM1 (with a first identification portion r1), and the shielding member corresponding to the sub-pixel unit that will not be covered with a third metal layer M3 such as touch electrode lines TLx to TLy later is the second type of shielding member SM2 (without an identification portion). In this way, when detecting after the production of multiple data lines Dp to Dq and the source and drain electrodes of each thin film transistor is completed, the operator can distinguish, according to the two types of shielding members, which defect locations will cover the touch electrode lines later and need to be repaired immediately, otherwise it will be impossible to repair later and lead to downgrading or scrapping; and which defect locations will not have touch electrode lines later, and can be repaired after the array substrate 100 is manufactured, so as to avoid affecting the overall product production schedule. In this way, it is possible to distinguish the defects that need to be repaired immediately and the defects that can be repaired after the array substrate 100 is manufactured when the production of each data line Dp to Dq and the source and drain electrodes of each thin film transistor is completed, which can not only improve the product yield through repair, but also ensure the production efficiency.
[0036] As Figure 2B 、 Figure 3 shown, the first shielding portion s1 and the second shielding portion s2 are rectangular, and the first identification portion r1 is trapezoidal, circular, triangular or rectangular. In actual operation, it is not limited thereto. The first shielding portion s1 and the second shielding portion s2 respectively correspond to the first semiconductor layer of the first thin film transistor t1 and the second semiconductor layer of the second thin film transistor t2 to shield and protect them. In actual operation, the shielding metal layer M0 can also form shielding members in other areas, not limited to corresponding to the semiconductor layers of each thin film transistor.
[0037] In one embodiment, the size of the first identification portion r1 is much smaller than that of the first shielding portion s1. Thus, while facilitating the operator to distinguish the types of the shielding members, the influence of the setting of the first identification portion r1 on the light transmittance of the array substrate 100 is avoided. In actual operation, if the first identification portion r1 and the second shielding portion s1 are set to be connected, it will increase the difficulty for the operator to distinguish. For example, it is impossible to determine whether the extra part of the first shielding portion s1 is the first identification portion r1 or a deformation of the first shielding portion s1 during the manufacturing process. The utility model avoids the occurrence of the foregoing situation by setting the first identification portion r1 and the first shielding portion s1 to be non-connected to each other.
[0038] As Figure 2A and Figure 2B shown, the array substrate 100 further includes a third data line D3 extending along the second direction F2. The third data line D3, the first data line D1, and the second data line D2 are arranged along the first direction F1. The third data line D3 and the first gate line G1 form a third sub-pixel unit P3. The third sub-pixel unit P3 has a third thin film transistor t3 to be connected to the first gate line G1 and the third data line D3. A second type of shielding member SM2 is provided corresponding to the third thin film transistor t3. In another embodiment, the first data line D1, the second data line D2, and the third data line D3 are arranged along the first direction F1. The third data line D3 and the first gate line G1 form a third sub-pixel unit P3. The third sub-pixel unit P3 has a third thin film transistor t3 to be connected to the first gate line G1 and the third data line D3. A second type of shielding member SM2 is provided corresponding to the third thin film transistor t3.
[0039] As Figure 2B shown, in this embodiment, along the first direction F1, every 3 sub-pixel units form a pixel unit. Among them, a touch control electrode line is covered on the data line corresponding to 1 sub-pixel unit. That is, along the first direction F1, a touch control electrode line is covered on 1 out of every 3 data lines; in other embodiments, this is not limited thereto.
[0040] As Figure 2A and Figure 2BAs shown, in one embodiment, the array substrate 100 further includes a second gate line G2 extending along a first direction F1. The first gate line G1 and the second gate line G2 are arranged along a second direction F1. The first data line D1 and the second gate line G2 form a fourth sub-pixel unit P4. The fourth sub-pixel unit has a fourth thin film transistor t4, and a first type of shielding member SM2 is provided corresponding to the fourth thin film transistor t4. In this embodiment, the first thin film transistor t1 is connected to one side of the first data line D1, and the fourth thin film transistor t4 is connected to the corresponding other side of the first data line D1. However, this is not limiting. In other embodiments, the first thin film transistor t1 and the fourth thin film transistor t4 may be connected to the same side of the first data line D1.
[0041] In one embodiment, multiple gate lines Gm to Gn and the first data line D1 form multiple first type of sub-pixel units. Each first type of sub-pixel unit has a corresponding first type of thin film transistor, and each first type of thin film transistor is correspondingly provided with a first type of shielding member SM1. At the same time, multiple gate lines Gm to Gn and the second data line D2 form multiple second type of sub-pixel units. Each second type of sub-pixel unit has a corresponding second type of thin film transistor, and each second type of thin film transistor is correspondingly provided with a second type of shielding member SM2.
[0042] In one embodiment, multiple gate lines Gm to Gn and multiple data lines Dp to Dq form multiple first type of sub-pixel units and multiple second type of sub-pixel units. Each first type of sub-pixel unit has a corresponding first type of thin film transistor, and each first type of thin film transistor is correspondingly provided with a first type of shielding member SM1. Each second type of sub-pixel unit has a corresponding second type of thin film transistor, and each second type of thin film transistor is correspondingly provided with a second type of shielding member SM2.
[0043] In one embodiment, the array substrate 100 can be applied to a display panel. As Figure 4 shown, the display panel 1000 includes an array substrate 100, a counter substrate 200, and a sealant 300. The array substrate 100 and the counter substrate 200 are hermetically connected via the sealant 300. In one embodiment, the counter substrate 200 can be a color filter substrate, which includes a second substrate 210, a black matrix layer 220, and a color filter layer 230. The black matrix layer 220 has a plurality of apertures 221 distributed in an array, and the color filter layer 230 is at least located within the plurality of apertures 221.
[0044] In one embodiment, the projection of the first identification portion r1 on the second substrate 210 is located within the projection of the black matrix layer 220 on the second substrate 210. That is, the first identification portion r1 is provided at an opaque portion of the display panel 1000 to avoid affecting the light transmittance of the display panel 1000.
[0045] In one embodiment, the display panel 1000 can be applied to the display device 10. The display device 10 is, for example, an in-vehicle display device. The display panel 1000 is, for example, a liquid crystal display panel. The in-vehicle display device further includes a backlight module 2000, and the display panel 1000 is disposed on the backlight module 2000.
[0046] In the present utility model, two types of shielding members formed with different patterns can easily distinguish the defects that need to be repaired immediately and the defects that can be repaired after the array substrate 100 is manufactured when the data lines and the source and drain electrodes of the thin film transistors are manufactured. This can not only improve the product yield through repair, but also ensure the production efficiency and avoid affecting the production schedule of the product.
[0047] Of course, the present utility model can also have many other embodiments. Without departing from the spirit and essence of the present utility model, those skilled in the art can make various corresponding changes and deformations according to the present utility model. However, these corresponding changes and deformations should all fall within the protection scope of the appended claims of the present utility model.
Claims
1. An array substrate, characterized in that, The array substrate includes a plurality of gate lines extending in a first direction, the plurality of gate lines including a first gate line; a plurality of data lines extending in a second direction, the plurality of data lines including a first data line and a second data line to form a first sub-pixel unit and a second sub-pixel unit with the first gate line, the first sub-pixel unit having a first thin film transistor connected to the first gate line and the first data line, and the second sub-pixel unit having a second thin film transistor connected to the first gate line and the second data line; a plurality of touch electrode lines extending in the second direction, the plurality of touch electrode lines including a first touch electrode line, and the first touch electrode line at least partially covering the first data line; and a plurality of first type shielding members and a plurality of second type shielding members, with a first type shielding member provided corresponding to the first thin film transistor and a second type shielding member provided corresponding to the second thin film transistor; wherein each first type shielding member includes a first shielding portion and a first identification portion, the first identification portion being disposed beside the first shielding portion and not connected to the first shielding portion, and each second type shielding member includes a second shielding portion and does not include an identification portion.
2. The array substrate according to claim 1, wherein The first thin film transistor has a first semiconductor layer, the second thin film transistor has a second semiconductor layer, the first shielding portion is provided corresponding to the first semiconductor layer, and the second shielding portion is provided corresponding to the second semiconductor layer.
3. The array substrate according to claim 1, wherein, The first shielding portion is rectangular, and the first identification portion is trapezoidal, circular, triangular or rectangular.
4. The array substrate according to claim 1, wherein The size of the first identification portion is much smaller than that of the first shielding portion.
5. The array substrate according to claim 1, characterized in that The plurality of data lines includes a third data line, the third data line, the first data line and the second data line are arranged in the first direction or the first data line, the second data line and the third data line are arranged in the first direction, the third data line and the first gate line form a third sub-pixel unit, the third sub-pixel unit has a third thin film transistor, and a second type shielding member is provided corresponding to the third thin film transistor.
6. The array substrate according to claim 1, wherein The plurality of gate lines includes a second gate line, the first gate line and the second gate line are arranged in the second direction, the first data line and the second gate line form a fourth sub-pixel unit, the fourth sub-pixel unit has a fourth thin film transistor, and a first type shielding member is provided corresponding to the fourth thin film transistor.
7. The array substrate according to claim 1, characterized in that The plurality of gate lines and the first data line form a plurality of first type sub-pixel units, each first type sub-pixel unit having a corresponding first type thin film transistor, and each first type thin film transistor is correspondingly provided with a first type shielding member.
8. The array substrate according to claim 7, wherein The plurality of gate lines and the second data line form a plurality of second type sub-pixel units, each second type sub-pixel unit having a corresponding second type thin film transistor, and each second type thin film transistor is correspondingly provided with a second type shielding member.
9. A display panel, characterized in that, including the array substrate according to any one of claims 1 to 8; and a counter substrate; and a sealant, the array substrate and the counter substrate being hermetically connected via the sealant.
10. A display device, characterized in that, including the display panel according to claim 9; and a backlight module, the display panel being located on the backlight module.