Pixel sensor array

Abstract

A pixel sensor array may include a plurality of pixel sensors to generate color information associated with incident light and a time of flight (time of flight) sensor circuit to generate distance information associated with the incident light. The color information and the distance information may be used to generate a three-dimensional time-of-flight color image. In some embodiments, a ToF sensor circuit may be included under a deep trench isolation (DTI) structure, the DTI structure surrounding the pixel sensors in a top view of the pixel sensor array.

Description

Technical Field

[0001] The present disclosure relates to a pixel sensor array. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) image sensor may include a plurality of pixel sensors. The pixel sensor of the CMOS image sensor may include a transfer transistor, and the transfer transistor may include a photodiode for converting photons of incident light into photoelectric current and a transfer gate for controlling the flow of the photoelectric current between the photodiode and the drain region. The drain region is used to receive the photoelectric current so that the photoelectric current can be measured and / or transferred to other regions of the CMOS image sensor. Summary of the Utility Model

[0003] The present disclosure provides a pixel sensor array. The pixel sensor array includes a plurality of pixel sensors arranged in a grid, a deep trench isolation structure surrounding the pixel sensors in a top view of the pixel sensor array, and a time-of-flight sensor circuit located below the deep trench isolation structure.

[0004] The present disclosure provides a pixel sensor array. The pixel sensor array includes a plurality of pixel sensors arranged in a grid, a deep trench isolation structure surrounding the pixel sensors in a top view of the pixel sensor array, and a time-of-flight sensor circuit located below the deep trench isolation structure. The time-of-flight sensor circuit includes a control gate and a drain gate. The top view area of the drain gate is larger than the top view area of the control gate.

[0005] The present disclosure provides a pixel sensor array, including a plurality of pixel sensors, a deep trench isolation structure, and a time-of-flight sensor circuit. The pixel sensor includes a four-cell quadratic phase detection pixel sensor. The deep trench isolation structure surrounds a plurality of sub-regions of the four-cell quadratic phase detection pixel sensor in a top view of the pixel sensor array. The time-of-flight sensor circuit is located below the deep trench isolation structure, and the time-of-flight sensor circuit is surrounded by the periphery of the sub-regions included in the sub-regions of the four-cell quadratic phase detection pixel sensor. Description of the Drawings

[0006] Aspects of the present disclosure may be best understood when read in conjunction with the following detailed description with reference to the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1A to 1F is a diagram of an exemplary implementation of the ToF sensor circuit described herein;

[0008] Figure 2 A diagram of an example implementation of a ToF sensing operation performed by the ToF sensor circuit described in this document;

[0009] Figure 3A and Figure 3B A diagram of an example implementation of the ToF sensor circuit described in this document;

[0010] Figures 4A to 4F A diagram of an example implementation of the pixel sensor array described in this document;

[0011] Figures 5A to 5F A diagram of an example implementation of the pixel sensor array described in this document;

[0012] Figures 6A to 6F A diagram of an example implementation of the pixel sensor array described in this document;

[0013] Figures 7A to 7K A diagram of an example implementation of the image sensor device described in this document;

[0014] Figure 8A and Figure 8B A diagram of an example implementation of the pixel sensor array described in this document;

[0015] Figure 9 A flowchart related to an example process of forming the pixel sensor array described in this document.

[0016]

Symbol Explanation

[0017] 100: ToF sensor circuit

[0018] 102: Hole

[0019] 104: Control gate

[0020] 106: Control gate

[0021] 108: Drain gate

[0022] 110: p-type part

[0023] 112: n-type part

[0024] 114: Floating diffusion region

[0025] 116: Floating diffusion region

[0026] 118: Drain region

[0027] 414: Drain region

[0028] 120: Substrate

[0029] 410: Substrate

[0030] 122: Deep well

[0031] 124: First doped region

[0032] 126: Doped well

[0033] 128: Second doped region

[0034] 130: Doped guard ring

[0035] 132: Third doped region

[0036] 134: Contact

[0037] 136: Contact

[0038] 138: Dielectric layer

[0039] 434: Dielectric layer

[0040] 720: Dielectric layer

[0041] 200: Example implementation

[0042] 300: Example implementation

[0043] 700: Example implementation

[0044] 202: Emitted light

[0045] 204: Received light

[0046] 206: Sensing window

[0047] 208: Sensing window

[0048] 210: Drain window

[0049] 400: Pixel sensor array

[0050] 500: Pixel sensor array

[0051] 600: Pixel sensor array

[0052] 800: Pixel sensor array

[0053] 402: Pixel sensor

[0054] 404: Sub-region

[0055] 406: Microlens

[0056] 408: DTI structure

[0057] 412: Photodiode

[0058] 416: Transfer gate

[0059] 418: Oxide layer

[0060] 420: High-k dielectric liner

[0061] 422: Buffer layer

[0062] 424: Grid structure

[0063] 426: Color filter region

[0064] 428: Lower layer

[0065] 430: Incident light

[0066] 432: BEOL region

[0067] 714: BEOL region

[0068] 436: Metallization layer

[0069] 722: Metallization layer

[0070] 438: Interconnect

[0071] 502: Four-cell pixel sensor

[0072] 702: First wafer

[0073] 704: Second wafer

[0074] 706: Image sensor die

[0075] 708: Circuit system die

[0076] 710: Image sensor device

[0077] 712: Device region

[0078] 716: Bonding interface

[0079] 718: Semiconductor device

[0080] 724: Bonding pad

[0081] 726: Bonding pad

[0082] 728: Groove

[0083] 900: Process

[0084] 910: Square

[0085] 920: Square

[0086] 930: Square

[0087] 940: Square

[0088] A - A, B - B, C - C: Line

[0089] D - D, E - E: Line

[0090] D1~D9: Dimension

[0091] T P : Duration

[0092] t ToF : TOF Duration Detailed Implementation Manner

[0093] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0094] In addition, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0095] A time - of - flight (ToF) sensor (e.g., a sensor that uses germanium - on - silicon technology to implement depth sensing) can be used in a system designed to detect the distance to an object in a region. Generally, a given ToF sensor detects the phase difference between a signal transmitted by the system and the corresponding signal received by the given ToF sensor (after the signal is reflected by an object in the region). This phase difference can be used to determine the distance to the object that reflected the signal. In some cases, the output from a ToF sensor array can be used to generate distance information that indicates the distance to an object in the region.

[0096] The embodiments described herein provide an image sensor that includes a two-tap lock-in ToF sensor circuit and an associated pixel sensor array. The ToF sensor circuit described herein is configured to generate distance information using lateral electric field charge modulation (LEFM) and a two-stage charge transfer technique. The ToF sensor circuit can generate a sense current that is modulated by operating and repeating multiple time windows (e.g., two time windows for a two-tap lock-in ToF sensor circuit), and the modulation signals from the time windows are integrated in an integrator or a low-pass filter that can be implemented as a charge accumulation of the sense current. The integration of the sense current can correspond to the correlation difference between the sense current and the time window function, which enables the generation of a time-correlated component as the distance information for each of the ToF sensor circuits. Each ToF sensor circuit can be used to generate distance information for a relatively small sensing area (e.g., a sub-micron area), thereby enabling high-speed modulation for the image sensor and enabling fast generation of distance information (e.g., sub-nanosecond distance sensing).

[0097] In addition, as described herein, the two-tap lock-in ToF sensor circuit described herein can be fabricated using CMOS processing technology and integrated into the pixel sensor array to enable the generation of a three-dimensional color image (or a three-dimensional night vision image) using the distance information generated by the ToF sensor circuit. The ToF pixel sensor can include multiple control gates and one or more drain gates. The control gates and the drain gates can be located under a deep trench isolation (DTI) structure of the pixel sensors surrounding the pixel sensor array. The control gates can be used to apply a lateral electric field and transfer the sense current from the pixel sensor to respective floating diffusion regions. Before generating the sense current, one or more bleed gates can be used to drain unwanted charges from the ambient light from the pixel sensor.

[0098] The control gates can be activated during different time windows to accumulate charges associated with the sense current. The sense current in the time window can be modulated by operating and repeating the time window, and the modulation signals from the time window can be integrated in an integrator or a low-pass filter that can be implemented as a charge accumulation of the sense current to generate the distance information of the ToF pixel sensor.

[0099] In this way, the ToF sensor circuit described herein can be included in a CMOS image sensor (CIS) to implement a time-resolved CIS. The time-resolved CIS can include a ToF sensor circuit and a plurality of visible light pixel sensors (such as a plurality of red-green-blue (RGB) pixel sensors) and / or infrared (IR) pixel sensors (such as near infrared (NIR) pixel sensors), and other examples. The output of the ToF pixel sensor (such as distance information) and the output of the visible light pixel sensor (such as image information) can be used to generate an image (referred to herein as a three-dimensional (3D) ToF color image) indicating both the distance to an object in a region and the color of the object in the region. That is, the time-resolved CIS described herein enables the distance information determined by the ToF pixel sensor and the color information determined by the image pixel sensor to be combined, so as to enable the generation of a 3D ToF color image indicating both the distance to an object in a region and the color of the object in the region.

[0100] Figures 1A to 1F FIG. is a diagram of an exemplary implementation of the ToF sensor circuit 100 described herein. The ToF sensor circuit 100 can be used to generate distance information associated with incident light, such as a sense current indicating the round-trip time or time of flight of the incident light.

[0101] Figure 1A Shows a top-down view of an exemplary implementation of the ToF sensor circuit 100. As Figure 1A shown, the ToF sensor circuit 100 includes a hole 102 through which the ToF sensor circuit 100 senses incident light. The ToF sensor circuit 100 can include one or more control gates 104, one or more control gates 106, and one or more drain gates 108. In some embodiments, a plurality of drain gates 108 are located on opposite sides of the hole 102. The control gate 104 can be located on a first side of the drain gate 108, and the control gate 106 can be located on a second side of the drain gate 108. The first side and the second side can be opposite sides of the drain gate 108.

[0102] As Figure 1AAs further shown, the control gate 104, the control gate 106, and the drain gate 108 may each include a p-type portion 110 and an n-type portion 112. The p-type portion 110 may include a semiconductor material (such as silicon (Si), polysilicon) doped with one or more p-type dopants such as phosphorus (P) and / or arsenic (As) and other examples. The n-type portion 112 may include a semiconductor material doped with one or more n-type dopants such as boron (B) and / or indium (In) and other examples. The control gate 104, the control gate 106, and / or the drain gate 108 may be implemented by a field effect transistor (FET) such as a planar FET, a finFET, a nanostructure FET (such as a gate all around (GAA) FET), and / or another type of FET.

[0103] The control gate 104 may be used to control the flow of the sense current toward the floating diffusion region 114 adjacent to the control gate 104. The sense current may be generated by the ToF sensor circuit 100 based on the photon absorption of the incident light. The control gate 106 may be used to control the flow of the sense current toward the floating diffusion region 116 adjacent to the control gate 106. The drain gate 108 may be used to empty the ToF sensor circuit 100 before sensing the incident light.

[0104] The ToF sensor circuit 100 may be used to generate distance information using the LEFM and two-stage charge transfer techniques. The sense current generated by the ToF sensor circuit 100 may be modulated by controlling the lateral electric field between the floating diffusion region 114 and the floating diffusion region 116. Specifically, the control gate 104 and the control gate 106 may act as taps for controlling the lateral electric field, so the ToF sensor circuit 100 may be referred to as a dual-tap locked ToF sensor circuit. For example, during one time window, the sense current may be transferred to the floating diffusion region 114 by activating the control gate 104 while deactivating the control gate 106, causing the lateral electric field to tilt toward the floating diffusion region 114. During another time window, the sense current may be transferred to the floating diffusion region 116 by activating the control gate 106 while deactivating the control gate 104, which causes the lateral electric field to tilt toward the floating diffusion region 116. Before the time window, the drain gate 108 may be activated while the control gate 104 and the control gate 106 are deactivated to empty the underlying sensing region of the ToF sensor circuit 100 via the drain region 118 adjacent to the drain gate 108, thereby removing any residual charge from the ambient light.

[0105] The width of the p-type portion 110 of the control gate 104 (corresponding to Figure 1A the dimension D1 in Figure 1AThe dimensions D2) therein can be of substantially the same width to facilitate uniform sensing current modulation in the ToF sensor circuit 100. Additionally, the width of the p-type portion 110 of the control gate 104 and the width of the p-type portion 110 of the control gate 106 can be less than the width of the p-type portion 110 of the drain gate 108 (corresponding to Figure 1A the dimension D3) therein to facilitate high-speed and lossless charge modulation of the sensing current generated by the ToF sensor circuit 100. For example, the ratios of the widths of the p-type portions 110 of the control gate 104 and the control gate 106 to the width of the p-type portion 110 of the drain gate 108 (D1:D3 and D2:D3) can be included in the range greater than 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for high-speed and low-leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure.

[0106] The width of the n-type portion 112 of the control gate 104 (corresponding to Figure 1A the dimension D4) therein and the width of the n-type portion 112 of the control gate 106 (corresponding to Figure 1A the dimension D5) therein can be of substantially the same width to facilitate uniform sensing current modulation in the ToF sensor circuit 100. Additionally, the width of the p-type portion 110 of the control gate 104 and / or the width of the n-type portion 112 of the control gate 106 can be less than the width of the n-type portion 112 of the drain gate 108 (corresponding to Figure 1A the dimension D6) therein to facilitate high-speed and low-leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. For example, the ratios of the widths of the n-type portions 112 of the control gate 104 and the control gate 106 to the width of the n-type portion 112 of the drain gate 108 (D4:D6 and D5:D6) can be included in the range greater than 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for high-speed and lossless charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure.

[0107] The ratio (D1:D4) of the width of the p-type portion 110 of the control gate 104 to the width of the n-type portion 112 of the control gate 104 can be in the range of about 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for the high speed and low leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure. The ratio (D2:D5) of the width of the p-type portion 110 of the control gate 106 to the width of the n-type portion 112 of the control gate 106 can be in the range of about 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for the high speed and low leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure. The ratio (D3:D6) of the width of the p-type portion 110 of the drain gate 108 to the width of the n-type portion 112 of the drain gate 108 can be in the range of about 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for the high speed and low leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure.

[0108] The length of the control gate 104 (corresponding to Figure 1A the dimension D7 in Figure 1A and the length of the control gate 106 (corresponding to Figure 1A the dimension D8 in can be of substantially the same length to facilitate uniform sensing current modulation in the ToF sensor circuit 100. Additionally, the length of the control gate 104 and the length of the control gate 106 can be less than the length of the drain gate 108 (corresponding to Figure 1A the dimension D9 in to facilitate the high speed and low leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. For example, the ratios (D7:D9 and D8:D9) of the lengths of the control gate 104 and the control gate 106 to the length of the drain gate 108 can be included in the range greater than 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for the high speed and non-destructive charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure.

[0109] The ratio of the length of the p-type portion 110 of the control gate 104 to the length of the n-type portion 112 of the control gate 104 can be in the range of about 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for the high speed and low leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure. The ratio of the length of the p-type portion 110 of the control gate 106 to the length of the n-type portion 112 of the control gate 106 can be in the range of about 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for the high speed and low leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure. The ratio of the length of the p-type portion 110 of the drain gate 108 to the width of the n-type portion 112 of the drain gate 108 can be in the range of about 1:1 to about 1:1000 to achieve a low slope of the lateral electric field generated in the ToF sensor circuit 100, which is beneficial for the high speed and low leakage charge modulation of the sensing current generated by the ToF sensor circuit 100. However, other values within this range are also within the scope of the present disclosure.

[0110] Figure 1B An alternative embodiment is described where the control gate 104 and the control gate 106 are angled in the ToF sensor circuit 100. This reduces the distance between the floating diffusion region 114 and the floating diffusion region 116, which can further facilitate the high speed and low leakage charge modulation of the sensing current generated by the ToF sensor circuit 100.

[0111] Figure 1C A cross-sectional view of the ToF sensor circuit 100 along Figure 1A and Figure 1B along line A-A in is described. As shown in Figure 1C the ToF sensor circuit 100 may include a substrate 120, a deep well 122 located in the substrate 120, a first doped region 124 located in the deep well 122, a doped well 126 located in the deep well 122, a second doped region 128 located above the doped well 126, a doped guard ring 130 located in the deep well 122 and surrounding the first doped region 124, and a third doped region 132 located above the doped guard ring 130. The third doped region 132 may include an annular region having a shape similar to the shape of the doped guard ring 130.

[0112] The first doped region 124, the doped well 126, and the second doped region 128 may be a single-photon avalanche diode (SPAD) unit of the ToF sensor circuit 100. Specifically, in Figure 1CIn the example described, the SPAD cell can be P + N high-voltage input / output (I / O) SPAD cell, where the substrate 120 is a p-type substrate, the deep well 122 is a deep n-type well, the first doped region 124 is an n-type doped region, the doped well 126 is a p-type doped well, the second doped region 128 is a p-type doped region, the doped guard ring 130 is a deep n-type pinned photodiode (DNPPD) region, and the third doped region 132 is an n-type doped region. The via 102 can be included above the first doped region 124 and the second doped region 128, and the floating diffusion regions 114 and 116 can be included in the doped well 126.

[0113] As Figure 1C further shown, the third doped region 132 can be coupled to the contact 134, and the second doped region 128 can be coupled to the contact 136. The contacts 134 and 136 can extend through the dielectric layer 138 on the substrate 120. The contacts 134 and 136 can include tungsten (W), cobalt (Co), titanium (Ti), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), ruthenium (Ru), metal alloys, and / or another type of conductive material and other examples. The dielectric layer 138 can include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon carbide (SiC x ), or a mixture thereof, such as silicon carbonitride (SiCN) or silicon oxynitride (SiON) and other examples.

[0114] Figure 1D Illustrates a cross-sectional view of the ToF sensor circuit 100 along Figure 1A and Figure 1B along line B-B in. As Figure 1D shown, the drain region 118 can be included in the doped well 126, and the drain gate 108 can be included above the doped well 126 and above the dielectric layer 138.

[0115] Figure 1E and Figure 1F illustrate alternative embodiments of the ToF sensor circuit 100 for the embodiments described in combination with Figure 1C and Figure 1D described and described. In Figure 1E and Figure 1F In the embodiment of the ToF sensor circuit 100, the SPAD cell can be N +P High-Voltage I / O SPAD Cell, where the substrate 120 is a p-type substrate, the deep well 122 is omitted, the first doped region 124 is a p-type doped region, the doped well 126 is an n-type doped well, the second doped region 128 is an n-type doped region, the doped guard ring 130 is a deep p-well global guard ring, and the third doped region 132 is a p-type doped region.

[0116] As indicated above, Figures 1A to 1F is provided as an example. Other examples may differ from those Figures 1A to 1F described.

[0117] Figure 2 is a diagram of an example implementation 200 of a ToF sensing operation performed by the ToF sensor circuit 100 described herein. As Figure 2 shown, the emitted light 202 is emitted from the ToF sensor circuit 100 within a duration T P After the ToF duration t ToF the received light 204 (which is at least a part of the emitted light 202 reflected from the object) is received at the ToF sensor circuit 100. The distance L between the ToF sensor circuit 100 and the object can be determined as:

[0118]

[0119] where S FD1 is a sense current generated based on a part of the received light 204 during the sensing window 206, and S FD2 is a sense current generated based on another part of the received light 204 during another sensing window 208. During the sensing window 206, the control gate 106 can be activated, and both the control gate 104 and the drain gate 108 can be deactivated. This causes the lateral electric field to tilt towards the floating diffusion region 114, which enables the sense current to accumulate in the floating diffusion region 114 of the sensing window 206. During the sensing window 208, the control gate 104 can be activated, and both the control gate 106 and the drain gate 108 can be deactivated. This causes the lateral electric field to tilt towards the floating diffusion region 116, which enables the sense current to accumulate in the floating diffusion region 116 of the sensing window 208. Before the sensing window 206 and the sensing window 208, for the discharge window 210, the drain gate 108 can be activated (while the control gate 104 and the control gate 106 can be deactivated), and in this discharge window 210, the residual charge is discharged to the drain region 118.

[0120] As indicated above, Figure 2 is provided as an example. Other examples may differ from those Figure 2 described.

[0121] Figure 3A andFigure 3B is a diagram of an example implementation 300 of the ToF sensor circuit 100 described herein. Except for the omission of the n-type portions 112 from the self-control gate 104 and the control gate 106, Figure 3A illustrates an example implementation similar to the example implementation in Figure 1A , which reduces the complexity of manufacturing the ToF sensor circuit 100 while still achieving sufficient lateral electric field control of the ToF sensor circuit. Except for the omission of the n-type portions 112 from the self-control gate 104 and the control gate 106, Figure 3B illustrates an example implementation similar to the example implementation in Figure 1B , which reduces the complexity of manufacturing the ToF sensor circuit 100 while still achieving sufficient lateral electric field control of the ToF sensor circuit.

[0122] As indicated above, Figure 3A and Figure 3B are provided as examples. Other examples may differ from what is described with respect to Figure 3A and Figure 3B .

[0123] Figures 4A to 4F is a diagram of an example implementation of the pixel sensor array 400 described herein. The pixel sensor array 400 may be included on a sensor die of an image sensor device such as a CIS device or a time-resolved CIS device.

[0124] Figure 4A illustrates a top-down view of the pixel sensor array 400. As shown in Figure 4A , the pixel sensor array 400 includes a plurality of pixel sensors 402 for generating photocurrents for generating images and / or videos. The pixel sensors 402 may be arranged in a grid pattern. In some embodiments, at least one subset of the pixel sensors 402 is configured to absorb photons of light within a specific wavelength range of visible light (e.g., red, blue, or green light) and to generate color information (e.g., a photocurrent corresponding to the intensity of the wavelength associated with the incident light corresponding to a specific color). For example, one or more first pixel sensors 402 may be configured to absorb photons of light within a specific wavelength range of visible light corresponding to green light, one or more second pixel sensors 402 may be configured to absorb photons of light within a specific wavelength range of visible light corresponding to red light, one or more third pixel sensors 402 may be configured to absorb photons of light within a specific wavelength range of visible light corresponding to blue light, and so on. In some embodiments, one or more pixel sensors 402 may be configured to absorb photons of invisible light, such as photons of light within a wavelength range corresponding to IR or NIR.

[0125] In some embodiments, the pixel sensor array 400 may include a group or region of pixel sensors 402 configured for secondary light detection. As an example, Figure 4A the portion of the pixel sensor array 400 illustrated in may be referred to as a four-cell (4C) quadratic phase detector (QPD) region, and the pixel sensors 402 in the QPD region may be QPD pixel sensors. The pixel sensor array 400 may include Figure 4A one or more of the four-cell QPD regions illustrated in. The pixel sensors 402 in the four-cell QPD region may include a plurality of sub-regions 404 and a microlens (e.g., a single microlens 406) located above the plurality of sub-regions 404. Each sub-region 404 of the pixel sensor 402 may include a photodiode configured to generate a photocurrent based on photon absorption in the photodiode. The photocurrents generated by the photodiodes in the sub-regions 404 of the pixel sensor 402 may be selected such that a single unified photocurrent is provided from the pixel sensor 402 to circuitry on an associated circuit die of the image sensor device.

[0126] The pixel sensor 402 may be electrically and optically isolated by a deep trench isolation (DTI) structure 408 included in the pixel sensor array 400. The DTI structure 408 may include a plurality of interconnecting and intersecting trenches filled with one or more types of materials, such as dielectric materials (e.g., oxide-containing materials, high dielectric constant (high-k) dielectric materials), polysilicon materials, and / or another type of material. The DTI structure 408 may be included around the perimeter of the pixel sensor 402 such that the DTI structure 408 surrounds the pixel sensor 402 in a grid shape. Additionally, as Figure 4A shown in, the DTI structure 408 may surround the sub-regions 404 of the pixel sensor 402 (as well as the photodiodes and drain regions included therein). The DTI structure 408 may extend into the substrate of the pixel sensor array 400 and may extend downward into the substrate along at least a portion of the photodiodes of the pixel sensors 402 included in the pixel sensor array 400.

[0127] Figure 4B A top-down view illustrating an alternative embodiment in which the microlens 406 is offset (or off-centered) relative to other structures of the pixel sensor 402. The offset microlens 406 enables the pixel sensor array 400 to be used in embodiments in which incident light is directed at an angle (e.g., off-axis incident light) to the pixel sensor 402 in a manner that increases photon absorption, quantum efficiency (QE), and / or full well conversion (FWC) of the pixel sensor 402.

[0128] As Figure 4C and Figure 4D shown in the top-down view of and , the pixel sensor array 400 may include one or more ToF sensor circuits 100 for generating distance information associated with incident light (e.g., a sensing current indicating the round-trip time of propagation of the incident light). The combination of the color information generated by the pixel sensor 402 and the distance information generated by the ToF sensor circuit 100 can be used to generate a 3D ToF color image. In some embodiments, multiple ToF sensor circuits 100 may be included under the DTI structure 408 and around the perimeter of the pixel sensor 402. For example, the ToF sensor circuit 100 may be included around each sub-region 404 of the pixel sensor 402. This enables the ToF sensor circuit 100 to generate distance information for each sub-region 404 of the pixel sensor 402.

[0129] As Figure 4C and Figure 4D shown, the control gates 104 and 106 of the ToF sensor circuit 100 may be located on opposite sides of the sub-region 404 of the pixel sensor 402. The aperture 102 of the ToF sensor circuit 100 may correspond to an opening through the DTI structure 408. The drain gate 108 of the ToF sensor circuit 100 may be located on opposite sides of the sub-region 404 of the pixel sensor 402 such that the control gate 104 and the drain gate 108 are on adjacent sides of the sub-region 404 of the pixel sensor 402, and the control gate 106 and the drain gate 108 are on adjacent sides of the sub-region 404 of the pixel sensor 402. In Figure 4C the example embodiment of , the control gates 104 and 106 and the drain gate 108 of the ToF sensor circuit 100 include both a p-type portion 110 and an n-type portion 112. In Figure 4D the example embodiment of , the n-type portion 112 is omitted from the control gates 104 and 106, and the n-type portion 112 is only included in the drain gate 108.

[0130] As Figure 4C and Figure 4DAs further shown, the floating diffusion regions 114 and 116 of the ToF sensor circuit 100 surrounding the sub-region 404 of the pixel sensor 402 can be shared by two or more ToF sensor circuits 100. For example, the floating diffusion region 114 can be shared and included in the ToF sensor circuit 100 adjacent to the sub-region 404 of the pixel sensor 402. As another example, the floating diffusion region 116 can be shared and included in the ToF sensor circuit 100 adjacent to the sub-region 404 of the pixel sensor 402. In some embodiments, the sub-region 404 of the pixel sensor 402 can share the floating diffusion region 114 with a first adjacent sub-region and can share the floating diffusion region 116 with a second adjacent sub-region different from the first adjacent sub-region.

[0131] The floating diffusion region 114 of the ToF sensor circuit 100 can be located at the first corner between the control gate 104 and the drain gate 108 of the sub-region 404 of the pixel sensor 402, while the floating diffusion region 116 of the ToF sensor circuit 100 can be located at the second corner opposite the first corner and between the control gate 106 and another drain gate 108 of the sub-region 404. The floating diffusion region 114 of the ToF sensor circuit 100 surrounding the sub-region 404 of the pixel sensor 402 can be located on the opposite sides of the pixel sensor 402. The floating diffusion region 114 can be located between the control gates 104 of the ToF sensor circuits 100 adjacent to the sub-region 404 of the pixel sensor 402 and can be located beside the ends of the drain gates 108 of the adjacent ToF sensor circuits 100. The floating diffusion region 116 of the ToF sensor circuit 100 surrounding the sub-region 404 of the pixel sensor 402 can be located on the opposite sides of the pixel sensor 402. The floating diffusion region 116 can be located between the drain gates 108 of the ToF sensor circuits 100 adjacent to the sub-region 404 of the pixel sensor 402 and can be located beside the ends of the control gates 106 of the adjacent ToF sensor circuits 100. The floating diffusion regions 114 and 116 can be located on the adjacent sides of the pixel sensor 402.

[0132] As Figure 4C and Figure 4D As further shown, the ToF sensor circuits 100 surrounding the sub-region 404 of the pixel sensor 402 can all share the same drain region 118. Thus, a single drain region 118 can be associated with the pixel sensor 402. The drain region 118 can be located in the crossroads region of the pixel sensor 402 where the four corners of the sub-region 404 meet. The drain region 118 can be located beside the ends of the control gates 106 of the ToF sensor circuits 100 and beside the ends of a subset of the drain gates 108 of the ToF sensor circuits 100.

[0133] Figure 4E Illustrate Figure 4AAn example pixel sensor 402 in a four-cell QPD region of the pixel sensor array 400 described in Figure 4A , Figure 4C and Figure 4D A cross-sectional view of line C-C as described in Figure 4E . As shown in

[0134] Figure 4E , the pixel sensor 402 may include a plurality of sub-regions 404. The sub-regions 404 may be configured in a horizontally adjacent or side-by-side configuration in the substrate 410 of the pixel sensor array 400. The substrate 410 may include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate in which semiconductor pixels can be formed. In some embodiments, the substrate 410 is formed of silicon (Si) (e.g., a silicon substrate), a material containing silicon, a group III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or another type of semiconductor material capable of generating charge from photons of incident light. In some embodiments, the substrate 410 is formed of a doped material such as doped silicon (e.g., a p-type doped material or an n-type doped material).

[0135] Each of the sub-regions 404 may include a respective photodiode 412, and the respective photodiodes 412 are included in the substrate 410. The photodiode 412 may include a plurality of regions doped with various types of ions to form a p-n junction region or a PIN junction region (e.g., a junction region between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, the substrate 410 may be doped with an n-type dopant to form one or more n-type regions of the photodiode 412, and the substrate 410 may be doped with a p-type dopant to form the p-type region of the photodiode 412. The photodiode 412 can be used to absorb photons of incident light that enter the substrate 410 via the hole 102. The absorption of the photons causes the photodiode 412 to accumulate charge (referred to as a photocurrent) due to the photoelectric effect. The photons can bombard the photodiode 412, which causes the emission of electrons in the photodiode 412. The photocurrent generated by the photodiode 412 can be transferred and / or stored in an associated drain region 414 in the substrate 410. The drain region 414 may include a doped portion of the substrate 410 (e.g., an n-type doped portion, a p-type doped portion).

[0136] As Figure 4EAs further shown, each of the sub-regions 404 may include a transfer gate 416. The transfer gate 416 may be located at the front surface of the substrate 410. The transfer gate 416 in the sub-region 404 of the pixel sensor 402 is used to transfer the photocurrent generated by the photodiode 412 in the sub-region 404 to the drain region 414 of the sub-region 404. The transfer gate 416 may be implemented by an FET, such as a planar FET, a finFET, a nanostructure FET (e.g., a GAA FET), and / or another type of FET.

[0137] The pixel sensor array 400 may include a plurality of regions and / or structures for providing electrical isolation and / or optical isolation between the photodiodes 412 of the sub-regions 404 of the pixel sensors 402 in the pixel sensor array 400 and / or between the pixel sensors 402 and adjacent pixel sensors 402. For example, the pixel sensor array 400 may include a DTI structure 408, and the DTI structure 408 includes a grid-like structure that extends into the substrate 410 and surrounds the photodiodes 412 of the sub-regions 404 of the pixel sensors 402 included in the pixel sensor array 400.

[0138] The DTI structure 408 may include one or more trenches extending downward into the substrate 410. The trenches may extend from the back surface of the substrate 410 opposite to the front surface into the substrate 410. Therefore, the pixel sensor array 400 may be referred to as a backside illuminated (BSI) pixel sensor array because photons enter the photodiode 412 from the back surface of the substrate 410. Thus, the DTI structure 408 may be referred to as a backside DTI (BDTI) structure. Alternatively, the DTI structure 408 may include a frontside DTI (FDTI) structure extending from the front surface of the substrate 410 into the substrate. The DTI structure 408 may extend completely through the substrate 410 from the back surface to the front surface to provide complete isolation between adjacent pixel sensors 402. However, a portion of the substrate 410 is included under the DTI structure 408 between the sub-regions 404 of the pixel sensors 402 so that the photocurrents generated by the photodiodes 412 in the sub-regions 404 can be mixed and / or combined into a unified photocurrent, and this unified photocurrent can be used for QPD-based autofocus operation of the image sensor device including the pixel sensor array 400.

[0139] The DTI structure 408 may include one or more layers. The one or more layers may include an oxide layer 418 and a high-k (high dielectric constant) dielectric liner 420, among other examples. A portion of the oxide layer 418 may extend along the top of the backside surface of the substrate 410 as a buffer layer 422. The oxide layer 418 may be used to reflect incident light toward the photodiode 412 to increase the quantum efficiency of the pixel sensor 402 and reduce optical crosstalk between the pixel sensor 402 and one or more neighboring pixel sensors 402. In some embodiments, the oxide layer 418 comprises an oxide material such as silicon oxide (SiO x ). In some embodiments, silicon nitride (Si x N y ), silicon carbide (SiC x ), or a mixture thereof (such as silicon carbonitride (SiCN), silicon oxynitride (SiON), or another type of dielectric material) is used in place of the oxide layer 418. The high-k dielectric liner 420 may include silicon nitride (Si x N y ), silicon carbide (SiC x ), aluminum oxide (Al x O y , such as Al2O3), tantalum oxide (Ta x O y , such as Ta2O5), hafnium oxide (HfO x , such as HfO2), and / or another high-k dielectric material.

[0140] As Figure 4E further shown, the drain gate 108 of the ToF sensor circuit 100 associated with the pixel sensor 402 may be located below the DTI structure 408. In other cross-sectional views of the pixel sensor 402 (e.g., a cross-sectional view along the perimeter of the pixel sensor 402), the control gate 104, the control gate 106, the floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may be located below the DTI structure 408. The control gate 104, the control gate 106, and the drain gate 108 may be located in a dielectric layer below the front side surface of the substrate 410. The floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may be located in the substrate 410 below the DTI structure 408. The floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may include a doped portion of the substrate 410 below the DTI structure 408.

[0141] The mesh structure 424 can be disposed above and / or on a buffer layer 422 above the backside surface of the substrate 410. The mesh structure 424 can include a plurality of interconnect structures formed of one or more layers, which are etched to form the interconnect structures. In a top view of the mesh structure 424, the mesh structure 424 has a mesh-like configuration similar to the DTI structure 408. Specifically, the mesh structure 424 can be located above the DTI structure 408 and conform to the shape and / or configuration of the DTI structure 408, except that the mesh structure 424 can be omitted between sub-regions 404 of the pixel sensor 402 and can instead be included only around the periphery of the pixel sensor 402. The mesh structure 424 can be used in combination with the DTI structure 408 to provide enhanced optical crosstalk reduction for the pixel sensors 402 in the pixel sensor array 400.

[0142] The mesh structure 424 can include an oxide mesh, a dielectric mesh, a color filter in a box (CIAB) mesh, and / or a composite metal grid (CMG), among other examples. In some embodiments, the mesh structure 424 includes a metal layer and a dielectric layer above and / or on the metal layer. The metal layer can include tungsten (W), cobalt (Co), and / or another type of metal or metal-containing material. The dielectric layer can include an organic material, an oxide, a nitride, and / or another type of dielectric material, such as silicon oxide (SiO x )(e.g., silicon dioxide (SiO2)), hafnium oxide (HfO x ), hafnium silicon oxide (HfSiO x ), aluminum oxide (Al x O y ), silicon nitride (Si x N y ), zirconium oxide (ZrO x ), magnesium oxide (MgO x ), yttrium oxide (Y x O y ), tantalum oxide (Ta x O y ), titanium oxide (TiO x ), lanthanum oxide (La x O y ), barium oxide (BaO x ), silicon carbide (SiC), lanthanum aluminum oxide (LaAlO x ), strontium oxide (SrO), zirconium silicon oxide (ZrSiO x ), and / or calcium oxide (CaO), among other examples.

[0143] The color filter region 426 can be included in the region between the columns of the grid structure 424. For example, the color filter region 426 can be formed between the columns of the grid structure 424 above the photodiodes 412 of the pixel sensor 402. In this way, instead of having individual color filter regions 426 above each of the sub-regions 404, a single color filter region 426 is included above the photodiodes 412 of the sub-regions 404 of the pixel sensor 402. Each pixel sensor 402 in the pixel sensor array 400 can include a single color filter region 426. The refractive index of the color filter region 426 can be greater than the refractive index of the grid structure 424 to increase the likelihood of total internal reflection in the color filter region 426 at the interface between the sidewalls of the color filter region 426 and the sidewalls of the grid structure 424, which can increase the quantum efficiency of the pixel sensor 402.

[0144] The color filter region 426 can be used to filter incident light to allow incident light of a specific wavelength to pass through to the photodiodes 412 of the pixel sensor 402. For example, the color filter region 426 can filter red light for the pixel sensor 402. As another example, the color filter region 426 can filter green light for the pixel sensor 402. As another example, the color filter region 426 can filter blue light for the pixel sensor 402.

[0145] The blue filter region can allow a component of the incident light near a wavelength of 450 nanometers to pass through the color filter region 426 and block other wavelengths. The green filter region can allow a component of the incident light near a wavelength of 550 nanometers to pass through the color filter region 426 and block other wavelengths. The red filter region can allow a component of the incident light near a wavelength of 650 nanometers to pass through the color filter region 426 and block other wavelengths. The yellow filter region can allow a component of the incident light near a wavelength of 580 nanometers to pass through the color filter region 426 and block other wavelengths.

[0146] In some embodiments, the color filter region 426 can be non-discriminating or non-filtering, which can define a white pixel sensor. The non-discriminating or non-filtering color filter region 426 can include a material that allows light of all wavelengths to enter the associated photodiode 412. In some embodiments, the color filter region 426 can be a NIR bandpass filter region, which can define a NIR pixel sensor. The NIR bandpass filter region 426 can include a material that allows a portion of the incident light in the NIR wavelength range to pass through to the associated photodiode 412 while blocking visible light.

[0147] The lower layer 428 may be included above and / or on the color filter region 426. The lower layer 428 may include a substantially flat layer that provides a substantially flat dielectric substrate on which the microlenses 406 may be formed. The microlenses 406 may be included above the color filter region 426 of the pixel sensor 402. In this way, a single microlens 406 is included above a single color filter region 426 of the pixel sensor 402 and above the photodiodes 412 (e.g., as opposed to individual microlenses for each of the photodiodes 412 of the pixel sensor 402). The microlenses 406 may be formed to focus the incident light 430 toward the photodiodes 412 of the sub-region 404 of the pixel sensor 402.

[0148] As Figure 4E further shown, the back end of line (BEOL) region 432 may be included on the front side of the substrate 410. The BEOL region 432 may include one or more dielectric layers 434 and one or more metallization layers 436, and the one or more metallization layers 436 are included in the one or more dielectric layers 434 to electrically connect portions of the pixel sensor array 400. The one or more dielectric layers 434 may include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon carbide (SiC x ), or mixtures thereof, such as silicon carbonitride (SiCN) or silicon oxynitride (SiON), and other examples. The one or more metallization layers 436 may include trenches, vias, interconnects, posts, pillars, single damascene structures, and / or dual damascene structures, and other examples. The one or more metallization layers 436 may include tungsten (W), cobalt (Co), titanium (Ti), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), ruthenium (Ru), metal alloys, and / or another type of conductive material, and other examples. The control gates 104, control gates 106, drain gates 108, floating diffusion regions 114, floating diffusion regions 116, and / or drain regions 118 may be electrically connected to the one or more metallization layers 436 via the interconnects 438. The interconnects 438 may include tungsten (W), cobalt (Co), titanium (Ti), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), ruthenium (Ru), metal alloys, and / or another type of conductive material, and other examples.

[0149] Figure 4F Illustrated Figure 4B is an example pixel sensor 402 in the four-cell QPD region of the pixel sensor array 400 illustrated in Figure 4B , Figure 4C and Figure 4D along another cross-sectional view of line C-C illustrated in Figure 4F Illustrated corresponding toFigure 4B An alternative implementation of a top-down view of the pixel sensor array 400 in Figure 4B , where the microlenses 406 are offset (or off-center) relative to other structures of the pixel sensors 402. Additionally, the grid structure 424, the color filter region 426, and / or the underlying layer 428 may also be offset (or off-center) relative to other structures of the pixel sensors 402.

[0150] As indicated above, Figures 4A to 4F is provided as an example. Other examples may be different from what is Figures 4A to 4F described with respect to

[0151] Figures 5A to 5F is a diagram of an example implementation of the pixel sensor array 500 described herein. The pixel sensor array 500 may be included on a sensor die of an image sensor device such as a CIS device or a time-resolved CIS device.

[0152] As Figures 5A to 5F shown in Figures 5A to 5F , an example implementation of the pixel sensor array 500 may include a combination and / or configuration of layers and / or structures similar to the example implementation of the pixel sensor array 400 described and illustrated in connection with Figures 4A to 4F For example, an example implementation of the pixel sensor array 500 may include components 402-438. However, as Figure 5A and Figure 5B shown in Figure 5A and Figure 5B , an example implementation of the pixel sensor array 500 may include four-cell (4C) pixel sensors 502, each of the four-cell pixel sensors 502 including four pixel sensors 402 arranged in a grid, where each pixel sensor 402 of the four-cell pixel sensors 502 includes an individual microlens 406. Each of the pixel sensors 402 in the four-cell pixel sensors 502 may be used to absorb photons of light within the same specific wavelength range of the incident light 430.

[0153] As Figure 5C and Figure 5DAs shown in the top-down view in [reference], the pixel sensor array 500 may include one or more ToF sensor circuits 100 for generating distance information associated with incident light (e.g., a sensing current indicating the round-trip distance traveled by the incident light). The combination of color information generated by the four-cell pixel sensor 502 and the distance information generated by the ToF sensor circuit 100 can be used to generate a 3D ToF color image. In some embodiments, multiple ToF sensor circuits 100 may be included under the DTI structure 408 and around the periphery of the four-cell pixel sensor 502. For example, the ToF sensor circuit 100 may be included around each pixel sensor 402 of the four-cell pixel sensor 502. This enables the ToF sensor circuit 100 to generate distance information for each of the pixel sensors 402 of the four-cell pixel sensor 502.

[0154] As Figure 5C and Figure 5D shown in [reference], the control gates 104 and 106 of the ToF sensor circuit 100 may be located on opposite sides of the pixel sensor 402 of the four-cell pixel sensor 502. The aperture 102 of the ToF sensor circuit 100 may correspond to an opening through the DTI structure 408. The drain gate 108 of the ToF sensor circuit 100 may be located on the opposite side of the pixel sensor 402 of the four-cell pixel sensor 502 such that the control gate 104 and the drain gate 108 are on adjacent sides of the pixel sensor 402 of the four-cell pixel sensor 502, and the control gate 106 and the drain gate 108 are on adjacent sides of the pixel sensor 402 of the four-cell pixel sensor 502. In Figure 5C an example embodiment in [reference], the control gates 104 and 106 and the drain gate 108 of the ToF sensor circuit 100 include both p-type portions 110 and n-type portions 112. In Figure 5D an example embodiment in [reference], the n-type portion 112 is omitted from the control gates 104 and 106, and the n-type portion 112 is only included in the drain gate 108.

[0155] As Figure 5C and Figure 5DAs further shown, the floating diffusion regions 114 and 116 of the ToF sensor circuit 100 of the pixel sensor 402 surrounding the four-unit pixel sensor 502 can be shared by two or more ToF sensor circuits 100. For example, the floating diffusion region 114 can be shared and included in the ToF sensor circuit 100 of the neighboring pixel sensor 402 surrounding the four-unit pixel sensor 502. As another example, the floating diffusion region 116 can be shared and included in the ToF sensor circuit 100 of the neighboring pixel sensor 402 surrounding the four-unit pixel sensor 502. In some embodiments, the pixel sensor 402 of the four-unit pixel sensor 502 can share the floating diffusion region 114 with a first neighboring pixel sensor and can share the floating diffusion region 116 with a second neighboring pixel sensor different from the first neighboring pixel sensor.

[0156] The floating diffusion region 114 of the ToF sensor circuit 100 can be located at the first corner between the control gate 104 and the drain gate 108 of the pixel sensor 402 of the four-unit pixel sensor 502, while the floating diffusion region 116 of the ToF sensor circuit 100 can be located at the second corner opposite the first corner and between the control gate 106 and another drain gate 108 of the pixel sensor 402. The floating diffusion region 114 of the ToF sensor circuit 100 surrounding the four-unit pixel sensor 502 can be located on opposite sides of the four-unit pixel sensor 502. The floating diffusion region 114 can be located between the control gates 104 of the ToF sensor circuits 100 neighboring the pixel sensor 402 surrounding the four-unit pixel sensor 502 and can be located beside the ends of the drain gates 108 of the neighboring ToF sensor circuits 100. The floating diffusion region 116 of the ToF sensor circuit 100 of the pixel sensor 402 surrounding the four-unit pixel sensor 502 can be located on opposite sides of the four-unit pixel sensor 502. The floating diffusion region 116 can be located between the drain gates 108 of the ToF sensor circuits 100 neighboring the pixel sensor 402 surrounding the four-unit pixel sensor 502 and can be located beside the ends of the control gates 106 of the neighboring ToF sensor circuits 100. The floating diffusion regions 114 and 116 can be located on the neighboring sides of the four-unit pixel sensor 502.

[0157] As Figure 5C and Figure 5DAs further shown, the ToF sensor circuit 100 of the pixel sensor 402 surrounding the four - unit pixel sensor 502 can all share the same drain region 118. Thus, a single drain region 118 can be associated with the four - unit pixel sensor 502. The drain region 118 can be located in the cross - road region of the four - unit pixel sensor 502, where the four corners of the pixel sensor 402 meet. The drain region 118 can be located next to the end of the control gate 106 of the ToF sensor circuit 100 and next to the ends of a subset of the drain gates 108 of the ToF sensor circuit 100.

[0158] Figure 5E Description Figure 5A An example four - unit pixel sensor 502 in the four - unit QPD region of the pixel sensor array 500 described in Figure 5C and Figure 5D A cross - sectional view along line D - D as described in Figure 5F Description Figure 5B An example four - unit pixel sensor 502 in the four - unit QPD region of the pixel sensor array 500 described in Figure 5C and Figure 5D Another cross - sectional view along line D - D as described in Figure 5E and Figure 5F As shown in

[0159] As Figure 5E and Figure 5FAs further shown, the drain gate 108 of the ToF sensor circuit 100 associated with the four-cell pixel sensor 502 may be located below the DTI structure 408. In other cross-sectional views of the four-cell pixel sensor 502 (e.g., cross-sectional views along the perimeter of the four-cell pixel sensor 502), the control gate 104, the control gate 106, the floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may be located below the DTI structure 408. The control gate 104 and the control gate 106, as well as the drain gate 108, may be located in a dielectric layer below the front surface of the substrate 410. The floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may be located in the substrate 410 below the DTI structure 408. The floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may include doped portions of the substrate 410 below the DTI structure 408.

[0160] As indicated above, Figures 5A to 5F is provided as an example. Other examples may be different from those Figures 5A to 5F described with respect to

[0161] Figures 6A to 6F is a diagram of an example implementation of the pixel sensor array 600 described herein. The pixel sensor array 600 may be included on a sensor die of an image sensor device such as a CIS device or a time-resolved CIS device.

[0162] As Figures 6A to 6F shown, an example implementation of the pixel sensor array 600 may include a combination and / or configuration of layers and / or structures similar to the example implementation of the pixel sensor array 400 described in connection with Figures 4A to 4F illustrations and descriptions. For example, an example implementation of the pixel sensor array 600 may include components 402 to 438. However, as Figure 6A and Figure 6B shown, an example implementation of the pixel sensor array 600 may include one-cell (1C) pixel sensors 402 distributed throughout the pixel sensor array 600.

[0163] As Figure 6C and Figure 6DAs shown in the top-down view in [FIGURE REFERENCE], the pixel sensor array 600 may include one or more ToF sensor circuits 100 for generating distance information associated with incident light (e.g., a sense current indicating the round-trip distance traveled by the incident light). The combination of color information generated by the pixel sensor 402 and the distance information generated by the ToF sensor circuit 100 may be used to generate a 3D ToF color image. In some embodiments, the ToF sensor circuit 100 may be included under the DTI structure 408 and around the periphery of one or more of the pixel sensors 402. This enables the ToF sensor circuit 100 to generate distance information for each of the one or more pixel sensors 402.

[0164] As Figure 6C and Figure 6D shown in [FIGURE REFERENCE], the control gates 104 and 106 of the ToF sensor circuit 100 may be located on opposite sides of the pixel sensor 402. The aperture 102 of the ToF sensor circuit 100 may correspond to an opening through the DTI structure 408. The drain gate 108 of the ToF sensor circuit 100 may be located on the opposite side of the pixel sensor 402 such that the control gate 104 and the drain gate 108 are on adjacent sides of the pixel sensor 402, and the control gate 106 and the drain gate 108 are on adjacent sides of the pixel sensor 402. In Figure 6C an example embodiment in [FIGURE REFERENCE], the control gates 104 and 106 and the drain gate 108 of the ToF sensor circuit 100 include both a p-type portion 110 and an n-type portion 112. In Figure 6D an example embodiment in [FIGURE REFERENCE], the n-type portion 112 is omitted from the control gates 104 and 106, and the n-type portion 112 is only included in the drain gate 108.

[0165] As Figure 6C and Figure 6D further shown in [FIGURE REFERENCE], the floating diffusion regions 114 and 116 of the ToF sensor circuit 100 surrounding the pixel sensor 402 may be shared by two or more ToF sensor circuits 100. For example, the floating diffusion region 114 may be shared and included in the ToF sensor circuit 100 surrounding an adjacent pixel sensor 402. As another example, the floating diffusion region 116 may be shared and included in the ToF sensor circuit 100 surrounding an adjacent pixel sensor 402. In some embodiments, the pixel sensor 402 may share the floating diffusion region 114 with a first adjacent pixel sensor and may share the floating diffusion region 116 with a second adjacent pixel sensor different from the first adjacent pixel sensor.

[0166] The floating diffusion region 114 of the ToF sensor circuit 100 may be located at the first corner of the pixel sensor 402 between the control gate 104 and the drain gate 108, while the floating diffusion region 116 of the ToF sensor circuit 100 may be located at the second corner of the pixel sensor 402 opposite the first corner and between the control gate 106 and another drain gate 108. The ToF sensor circuit 100 surrounding multiple pixel sensors 402 may all share the same drain region 118. Thus, a single drain region 118 may be associated with multiple ToF sensor circuits 100 and multiple pixel sensors 402. The drain region 118 may be located in the intersection region of multiple pixel sensors 402, where the four corners of the pixel sensor 402 meet. The drain region 118 may be located beside the end of the control gate 106 of the ToF sensor circuit 100 and beside the ends of a subset of the drain gates 108 of the ToF sensor circuit 100.

[0167] Figure 6E Description Figure 6A The example pixel sensor 402 in the four-cell QPD region of the pixel sensor array 600 described in Figure 6C and Figure 6D Cross-sectional view along the line E-E described in Figure 6F Description Figure 6B The example pixel sensor 402 in the four-cell QPD region of the pixel sensor array 600 described in Figure 6C and Figure 6D Another cross-sectional view along the line E-E described in Figure 6E and Figure 6F As shown in

[0168] As Figure 6E and Figure 6FAs further shown, the drain gate 108 of the ToF sensor circuit 100 associated with the pixel sensor 402 may be located below the DTI structure 408. In other cross-sectional views of the pixel sensor 402 (e.g., cross-sectional views along the perimeter of the pixel sensor 402), the control gate 104, the control gate 106, the floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may be located below the DTI structure 408. The control gate 104, the control gate 106, and the drain gate 108 may be located in a dielectric layer below the front surface of the substrate 410. The floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may be located in the substrate 410 below the DTI structure 408. The floating diffusion regions 114, the floating diffusion regions 116, and / or the drain regions 118 may include doped portions of the substrate 410 below the DTI structure 408.

[0169] As indicated above, Figures 6A to 6F is provided as an example. Other examples may differ from what is Figures 6A to 6F described.

[0170] Figures 7A to 7K is a diagram of an example implementation 700 of an image sensor device described herein. Although the example implementation 700 includes forming a pixel sensor array 600 in an image sensor device, semiconductor processing techniques may be used to form one or more implementations of the pixel sensor array 400, one or more implementations of the pixel sensor array 500, and / or one or more implementations of the pixel sensor array 800 (in combination with Figure 8A and / or Figure 8B described). In some implementations, one or more of the semiconductor processing operations described in combination with Figures 7A to 7K may be performed using one or more semiconductor processing tools such as deposition tools, exposure tools, developer tools, etching tools, planarization tools, electroplating tools, ion implantation tools, and / or bonding tools, as well as other examples.

[0171] Turning Figure 7A to, one or more of the semiconductor processing operations in the example implementation 700 may be performed in conjunction with the substrate 410. The substrate 410 may be provided as a semiconductor wafer or another type of semiconductor workpiece.

[0172] As Figure 7B shown, multiple regions of the substrate 410 may be doped to form the photodiodes 412 for one or more pixel sensors 402. An ion implantation tool may be used to dope the substrate 410 to form one or more n-type regions and / or one or more p-type regions of the photodiodes 412. The ion implantation tool may be used to implant p + ions in the substrate 410 to form p-type regions and / or may implant n +Ions are used to form an n-type region.

[0173] As Figure 7B further shown in, one or more regions of the substrate 410 may be doped to form drain regions 414 of one or more pixel sensors 402. In some embodiments, an ion implantation tool may be used to dope by implanting n + ions to form the drain regions 414.

[0174] As Figure 7C shown in, one or more ToF sensor circuits 100 may be formed. The substrate 120 of the ToF sensor circuit 100 may be part of the substrate 410 or may be included in the substrate 410. One or more portions of the substrate 120 may be doped (e.g., using an ion implantation tool) to form deep wells 122 (which may be omitted in some embodiments). One or more portions of the substrate 120 may be doped to form a first doped region 124 in the deep well 122. One or more portions of the substrate 120 may be doped to form a doped well 126 above the first doped region 124 and in the deep well 122. The doped well 126 may include floating diffusion regions 114 and 116 and a drain region 118. One or more portions of the substrate 120 may be doped to form a doped guard ring 130 in the deep well 122 and around the first doped region 124 and the doped well 126. One or more portions of the substrate 120 may be doped to form a second doped region 128 above the first doped region 124 and the doped well 126. One or more portions of the substrate 120 may be doped to form a third doped region 132 above the doped guard ring 130.

[0175] As Figure 7D shown in, a transfer gate 416 may be formed above the front surface of the substrate 410. In addition, a drain gate 108, control gates 106 (not shown) and 104 (not shown) are formed above the front surface of the substrate 410. In some embodiments, a gate dielectric layer may be formed on the front surface of the substrate 410, and the control gates 104 and 106, the drain gate 108 and the transfer gate 416 may be formed above and / or on the gate dielectric layer. In some embodiments, a deposition tool is used to deposit the control gates 104 and 106, the drain gate 108 and the transfer gate 416. In some embodiments, the control gates 104 and 106, the drain gate 108 and / or the transfer gate 416 may include polysilicon doped with one or more types of dopants to form a p-type portion 110 and an n-type portion 112 or only form the p-type portion 110 without forming the n-type portion (e.g., in some embodiments, for the control gates 104 and 106). In some embodiments, the control gates 104 and 106, the drain gate 108 and / or the transfer gate 416 may include a high-k dielectric and a metal material (e.g., a metal gate or MG).

[0176] As Figure 7D Figure 7D Further shown as in, one or more dielectric layers 434 may be formed on the front side of the substrate 410. A deposition tool may be used to deposit the one or more dielectric layers 434 in a physical vapor deposition (PVD) operation, an atomic layer deposition (ALD) operation, a chemical vapor deposition (CVD) operation, an oxidation operation, or another type of deposition operation. In some embodiments, a planarization tool may be used to planarize the one or more dielectric layers 434 after depositing the one or more dielectric layers 434. The one or more dielectric layers 434 may be formed over the control gates 104 and 106, the drain gate 108, and / or the transfer gate 416.

[0177] As Figure 7D Figure 7D Further shown as in, interconnects 438 may be formed in the one or more dielectric layers 434. The interconnects 438 may be formed to be electrically coupled and / or physically coupled to the control gates 104 and 106, the drain gate 108, the floating diffusion regions 114 and 116 (not shown), the drain regions 118 (not shown), the drain region 414, and / or the transfer gate 416. A deposition tool, an exposure tool, and / or a developer tool may be used to pattern a masking layer, and an etching tool may be used to form grooves or openings in the one or more dielectric layers 434 based on the pattern. One or more deposition tools may be used to deposit the interconnects 438 in the grooves or openings to electrically couple and / or physically couple the control gates 104 and 106, the drain gate 108, the floating diffusion regions 114 and 116 (not shown), the drain regions 118 (not shown), the drain region 414, and / or the transfer gate 416 to the interconnects 438.

[0178] As Figure 7E Figure 7E As shown in, a BEOL region 432 may be formed over the front side surface of the substrate 410. The metallization layer 436 may be electrically coupled and / or physically coupled to the interconnects 438. A deposition tool may be used to deposit the one or more dielectric layers 434 in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, or another type of deposition operation. In some embodiments, a planarization tool may be used to planarize the one or more dielectric layers 434 after depositing the one or more dielectric layers 434. In some embodiments, the BEOL region 432 may be formed in multiple layers. For example, a first dielectric layer may be deposited, and a first metallization layer (M1 metallization layer) may be formed in the first dielectric layer; a second dielectric layer may be deposited, and a second metallization layer (M2 metallization layer) may be formed in the second dielectric layer; and so on.

[0179] As Figure 7FAs shown, a pixel sensor array 600 can be formed on a first wafer 702, and this first wafer 702 is bonded to a second wafer 704 using a bonding tool. A plurality of image sensor dies 706 (such as system on chip (SoC) dies) can be formed on the first wafer 702, and the pixel sensor array 600 can be included on the image sensor die 706, and this image sensor die 706 is bonded to a circuit die 708 (such as an application specific integrated circuit (ASIC) die) from the second wafer 704 to form an image sensor device 710. The circuit die 708 can include a device region 712 and a BEOL region 714, and the device region 712 includes associated control circuitry for the pixel sensor array 600. The image sensor die 706 (including the pixel sensor array 600) and the circuit die 708 can be bonded at a bonding interface 716 between the BEOL region 432 and the BEOL region 714.

[0180] As Figure 7G As shown, the circuit die 708 can include one or more semiconductor devices 718 (such as transistors, capacitors, resistors, memory cells) in the device region 712. The BEOL region 714 can be formed above the device region 712. A deposition tool can be used to deposit one or more dielectric layers 720 of the BEOL region 714 in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, or another type of deposition operation. Deposition can be used to deposit one or more metallization layers 722 of the BEOL region 714 in a PVD operation, an ALD operation, a CVD operation, an electroplating operation (such as an electroplating process operation), and / or another type of deposition operation. In some embodiments, a planarization tool can be used to planarize one or more dielectric layers after depositing the one or more dielectric layers. In some embodiments, the BEOL region 714 can be formed in multiple layers. For example, a first dielectric layer can be deposited, and a first metallization layer (M1 metallization layer) can be formed in the first dielectric layer; a second dielectric layer can be deposited, and a second metallization layer (M2 metallization layer) can be formed in the second dielectric layer; and so on.

[0181] As Figure 7GAs further shown, the bonding interface 716 may include a dielectric-to-dielectric bonding interface (wherein one or more dielectric layers 434 are bonded to one or more dielectric layers 720) and / or a metal-to-metal bonding interface, wherein the bonding pads 724 of the image sensor die 706 are bonded to the bonding pads 726 of the circuit system die 708. The bonding pads 724 and the bonding pads 726 may each include tungsten (W), cobalt (Co), titanium (Ti), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), ruthenium (Ru), metal alloys, and / or another type of conductive material, among other examples.

[0182] As Figure 7H shown, the recess 728 may be formed in the substrate 410 from the backside surface of the substrate 410. In some embodiments, a pattern in a photoresist layer is used to pattern the recess 728. The recess 728 may be formed above the control gates 104 and 106 (not shown) and the drain gate 108. Additionally, the recess 728 may be formed above the floating diffusion regions 114 and 116 (not shown) and the drain region 118 (not shown).

[0183] A deposition tool may be used to form a photoresist layer on the backside surface of the substrate 410. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool may be used to develop portions of the photoresist layer and remove those portions to expose the pattern. An etch tool may be used to etch the substrate 410 based on the pattern to form the recess 728. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). Alternatively, the pattern in the photoresist layer may be used to transfer the pattern to a hard mask layer for forming the recess 728.

[0184] As Figure 7I shown, a high-k dielectric liner 420 may be formed on the sidewalls and bottom surface of the recess 728. A deposition tool may be used to conformally deposit the high-k dielectric liner 420 in a PVD operation, an ALD operation, a CVD operation, and / or another type of deposition operation. The high-k dielectric liner 420 may be further deposited on the backside surface of the substrate 410. In some embodiments, the high-k dielectric liner 420 is subsequently removed from the backside surface of the substrate 410. In some embodiments, the high-k dielectric liner 420 remains on the backside surface of the substrate 410 (e.g., as an anti-reflection coating).

[0185] As Figure 7IAs further shown in, the groove 728 may be filled with an oxide layer 418 over the high-k dielectric liner 420 to form a DTI structure 408 in the groove 728. The DTI structure 408 may extend into the substrate 410 around the pixel sensors 402 of the pixel sensor array 600. As Figure 7I As further shown in, the material of the oxide layer 418 may be deposited over the backside surface of the substrate 410 to form a buffer layer 422. A deposition tool may be used to deposit the oxide layer 418 in the groove in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, or another type of deposition operation to form the DTI structure 408. A deposition tool may be used to deposit the buffer layer 422 in a PVD operation, an ALD operation, a CVD operation, an oxidation operation, and / or another type of deposition operation. In some embodiments, a planarization tool may be used to planarize the buffer layer 422 after depositing the buffer layer 422.

[0186] As Figure 7J shown in, a grid structure 424 may be formed over the DTI structure 408. In a PVD operation, an ALD operation, a CVD operation, an oxidation operation, an electroplating operation, and / or another suitable deposition operation, a deposition tool may deposit a layer of the grid structure 424 over and / or on the buffer layer 422. A portion of the layer may be removed with an etching tool to form the grid structure 424.

[0187] As Figure 7K shown in, a color filter region 426 may be formed between the grid structures 424, a lower layer 428 may be formed over the color filter region 426 and the grid structures 424, and a microlens 406 may be formed over and / or on the lower layer 428.

[0188] As indicated above, Figures 7A to 7K is provided as an example. Other examples may be different from what is described with respect to Figures 7A to 7K what is described.

[0189] Figure 8A and Figure 8B are diagrams of example embodiments of the pixel sensor array 800 described herein. The pixel sensor array 800 may be included on a sensor die of an image sensor device such as a CIS device or a time-resolved CIS device. The pixel sensor array 800 may include a configuration of pixel sensors 402, such as the 4C QPD configuration of the pixel sensor 402 described herein, the four-unit pixel sensor configuration of the pixel sensor 402 described herein, the 1C configuration of the pixel sensor 402 described herein, and / or another configuration of the pixel sensor 402.

[0190] As Figure 8A and Figure 8BAs shown, the floating diffusion region 116 can be located between the control gates 106 adjacent to the ToF sensor circuit 100 and beside the ends of the drain gates 108 adjacent to the ToF sensor circuit 100. The drain region 118 shared by the ToF sensor circuits 100 can be located beside the ends of all the drain gates 108 of the ToF sensor circuit 100.

[0191] In Figure 8A the example implementation of, the control gates 104 and 106 of the ToF sensor circuit 100 and the drain gates 108 include both p-type portions 110 and n-type portions 112. In Figure 8B the example implementation of, the n-type portions 112 are omitted from the control gates 104 and 106, and the n-type portions 112 are only included in the drain gates 108.

[0192] As indicated above, Figure 8A and Figure 8B are provided as examples. Other examples may be different from what is described with respect to Figure 8A and Figure 8B described.

[0193] Figure 9 is a flowchart associated with process 900 for forming the pixel sensor array described herein. In some embodiments, Figure 9 one or more process blocks of are performed using one or more semiconductor processing tools such as deposition tools, exposure tools, developer tools, etching tools, planarization tools, electroplating tools, ion implantation and / or bonding tools, and other examples.

[0194] As Figure 9 shown, process 900 may include forming a plurality of pixel sensors (block 910) in the pixel sensor array on the image sensor die. For example, as described herein, one or more semiconductor processing tools can be used to form a plurality of pixel sensors 402 in the pixel sensor array (such as pixel sensor array 400, pixel sensor array 500, pixel sensor array 600) on the image sensor die 706.

[0195] As Figure 9 further shown, process 900 may include forming a plurality of ToF sensor circuits (block 920) around the plurality of pixel sensors on the image sensor die. For example, as described herein, one or more semiconductor processing tools can be used to form a plurality of ToF sensor circuits 100 around the plurality of pixel sensors 402 on the image sensor die 706.

[0196] As Figure 9As further shown, process 900 may include bonding the image sensor die to the circuitry die (block 930) after forming a plurality of pixel sensors and a plurality of ToF sensor circuits. For example, as described herein, one or more semiconductor processing tools may be used to bond the image sensor die 706 to the circuitry die 708 after forming a plurality of pixel sensors 402 and a plurality of ToF sensor circuits 100.

[0197] As Figure 9 As further shown, process 900 may include forming a DTI structure (block 940) around the plurality of pixel sensors and over the plurality of ToF sensor circuits after bonding the image sensor die to the circuitry die. For example, as described herein, one or more semiconductor processing tools may be used to form a DTI structure 408 around the plurality of pixel sensors 402 and over the plurality of ToF sensor circuits 100 after bonding the image sensor die to the circuitry die.

[0198] Process 900 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0199] In a first embodiment, forming the ToF sensor circuit 100 of the plurality of ToF sensor circuits 100 includes: forming a first doped region 124 in a substrate (e.g., substrate 120, substrate 410) of the image sensor die 706; forming a doped well 126 over the first doped region 124; forming a doped guard ring 130 around the first doped region 124 and the doped well 126; forming a second doped region 128 over the doped well 126; and forming a third doped region 132 over the doped guard ring 130.

[0200] In a second embodiment, either alone or in combination with the first embodiment, the first doped region includes a first p-type doped region, the doped well includes an n-type doped well, the doped guard ring includes a p-type doped guard ring, the second doped region includes an n-type doped region, and the third doped region includes a second p-type doped region.

[0201] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, the first doped region 124 includes a first n-type doped region, the doped well 126 includes a p-type doped well, the doped guard ring includes an n-type doped guard ring, the second doped region 128 includes a p-type doped region, and the third doped region 132 includes a second n-type doped region.

[0202] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming the ToF sensor circuit 100 further includes forming a deep n-type well (such as the deep well 122) in a substrate, and a first n-type doped region, a p-type doped well, and an n-type doped guard ring are formed in the deep n-type well.

[0203] Although Figure 9 example blocks of the process 900 are shown, in some embodiments, the process 900 includes more blocks, fewer blocks, different blocks from those Figure 9 depicted, or blocks configured in a different manner from those depicted. Additionally or alternatively, two or more of the blocks of the process 900 may be performed in parallel.

[0204] In this way, the pixel sensor array can include a plurality of pixel sensors for generating color information associated with incident light and a ToF sensor circuit for generating distance information associated with incident light. The color information and the distance information can be used to generate a 3D ToF color image. The ToF sensor circuit can be included under the DTI structure, which surrounds the plurality of pixel sensors in a top view of the pixel sensor array.

[0205] As described in more detail above, some embodiments described herein provide a pixel sensor array. This pixel sensor array includes a plurality of pixel sensors arranged in a grid. This pixel sensor array includes a DTI structure that surrounds the plurality of pixel sensors in a top view of the pixel sensor array. This pixel sensor array includes a time-of-flight sensor circuit located under the DTI structure.

[0206] In some embodiments, the time-of-flight sensor circuit includes a first control gate, a second control gate, a first drain gate, and a second drain gate. The first control gate is located on a first side of a pixel sensor among the plurality of pixel sensors. The second control gate is located on a second side of the pixel sensor. The first drain gate is located on a third side of the pixel sensor. The second drain gate is located on a fourth side of the pixel sensor.

[0207] In some embodiments, the first side and the second side are a plurality of first opposite sides of the pixel sensor, and the third side and the fourth side are a plurality of second opposite sides of the pixel sensor.

[0208] In some embodiments, the first side and the second side are a plurality of first adjacent sides of the pixel sensor, and the third side and the fourth side are a plurality of second adjacent sides of the pixel sensor.

[0209] In some embodiments, the time-of-flight sensor circuit further includes a first floating diffusion region, a second floating diffusion region, and a drain region. The first floating diffusion region is located at a first corner of the pixel sensor. The second floating diffusion region is located at a second corner of the pixel sensor. The drain region is located at a third corner of the pixel sensor.

[0210] In some embodiments, the deep trench isolation structure surrounds multiple sub-regions of each of the multiple pixel sensors, and the time-of-flight sensor circuit includes a first control gate, a second control gate, a first drain gate, and a second drain gate. The first control gate is located on a first side of a sub-region of the pixel sensor among the multiple pixel sensors. The second control gate is located on a second side of the sub-region of the pixel sensor. The first drain gate is located on a third side of the sub-region of the pixel sensor. The second drain gate is located on a fourth side of the sub-region of the pixel sensor.

[0211] In some embodiments, the time-of-flight sensor circuit further includes a first floating diffusion region, a second floating diffusion region, and a drain region. The first floating diffusion region is located at a first corner of the sub-region of the pixel sensor. The second floating diffusion region is located at a second corner of the sub-region of the pixel sensor. The drain region is located at a third corner of the sub-region of the pixel sensor.

[0212] As described in more detail above, some embodiments described herein provide a pixel sensor array. This pixel sensor array includes a plurality of pixel sensors arranged in a grid. This pixel sensor array includes a DTI structure surrounding the plurality of pixel sensors in a top view of the pixel sensor array. This pixel sensor array includes a ToF sensor circuit located below the DTI structure. This ToF sensor circuit includes a control gate and a drain gate, wherein the top view area of the drain gate is larger than the top view area of the control gate.

[0213] In some embodiments, the control gate is located at a first side of the pixel sensor among the multiple pixel sensors. The drain gate is located at a second side of the multiple pixel sensors. The first side and the second side are adjacent sides of the pixel sensor.

[0214] In some embodiments, the control gate is located at a first side of the pixel sensor among the multiple pixel sensors. The drain gate is located at a second side of the multiple pixel sensors. The first side and the second side are opposite sides of the pixel sensor.

[0215] In some embodiments, the time-of-flight sensor circuit is included around the periphery of a four-cell pixel sensor among the multiple pixel sensors.

[0216] In some embodiments, the plurality of pixel sensors includes a four-cell quadri-phase detector pixel sensor. A deep trench isolation structure surrounds a plurality of sub-regions of the four-cell quadri-phase detector pixel sensor. A time-of-flight sensor circuit is included around the periphery of a sub-region of the plurality of sub-regions of the four-cell quadri-phase detector pixel sensor.

[0217] In some embodiments, the time-of-flight sensor circuit further includes a drain region located at a corner between four of the plurality of sub-regions of the four-cell quadri-phase detector pixel sensor.

[0218] In some embodiments, the time-of-flight sensor circuit further includes a first diffusion region located at a corner between two of the plurality of sub-regions of the four-cell quadri-phase detector pixel sensor.

[0219] In some embodiments, the drain gate includes a first p-type portion and an n-type portion. The control gate includes only a second p-type portion.

[0220] As described in more detail above, some embodiments described herein provide a method of forming a pixel sensor array. The method includes forming a plurality of pixel sensors in a pixel sensor array on an image sensor die. The method includes forming a plurality of ToF sensor circuits around the plurality of pixel sensors on the image sensor die. The method includes bonding the image sensor die to a circuit system die after forming the plurality of pixel sensors and the plurality of ToF sensor circuits. The method includes forming a DTI structure around the plurality of pixel sensors and above the plurality of ToF sensor circuits after bonding the image sensor die to the circuit system die.

[0221] In some embodiments, forming the time-of-flight sensor circuit among the plurality of time-of-flight sensor circuits includes the following steps. Forming a first doped region in a substrate of the image sensor die. Forming a doped well above the first doped region. Forming a doped guard ring around the first doped region and the doped well. Forming a second doped region above the doped well. Forming a third doped region above the doped guard ring.

[0222] In some embodiments, the first doped region includes a first p-type doped region. The doped well includes an n-type doped well. The doped guard ring includes a p-type doped guard ring. The second doped region includes an n-type doped region. The third doped region includes a second p-type doped region.

[0223] In some embodiments, the first doped region includes a first n-type doped region. The doped well includes a p-type doped well. The doped guard ring includes an n-type doped guard ring. The second doped region includes a p-type doped region. The third doped region includes a second n-type doped region.

[0224] In some embodiments, forming a time-of-flight sensor circuit further includes the following steps. Form a deep n-type well in a substrate. A first n-type doped region, a p-type doped well, and an n-type doped guard ring are formed in the deep n-type well.

[0225] As used herein and depending on the context, "meeting a threshold value" may refer to a value greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, equal to a threshold value, not equal to a threshold value, or the like.

[0226] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or attaining the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A pixel sensor array, characterized in that, Comprising: A plurality of pixel sensors, arranged in a grid; A deep trench isolation structure that surrounds the plurality of pixel sensors in a top view of the pixel sensor array; And A time-of-flight sensor circuit, located below the deep trench isolation structure.

2. The pixel sensor array according to claim 1, wherein Wherein the time-of-flight sensor circuit includes: A first control gate, located on a first side of a pixel sensor among the plurality of pixel sensors; A second control gate, located on a second side of the pixel sensor; A first drain gate, located on a third side of the pixel sensor; and A second drain gate, located on a fourth side of the pixel sensor.

3. The pixel sensor array according to claim 2, wherein Wherein the first side and the second side are a plurality of first opposite sides of the pixel sensor; and Wherein the third side and the fourth side are a plurality of second opposite sides of the pixel sensor.

4. The pixel sensor array according to claim 2, wherein Wherein the first side and the second side are a plurality of first adjacent sides of the pixel sensor; and Wherein the third side and the fourth side are a plurality of second adjacent sides of the pixel sensor.

5. The pixel sensor array according to claim 1, wherein Wherein the deep trench isolation structure surrounds a plurality of sub-regions of each of the plurality of pixel sensors; And Wherein the time-of-flight sensor circuit includes: A first control gate, located on a first side of a sub-region of a pixel sensor among the plurality of pixel sensors; A second control gate, located on a second side of the sub-region of the pixel sensor; A first drain gate, located on a third side of the sub-region of the pixel sensor; and A second drain gate, located on a fourth side of the sub-region of the pixel sensor.

6. A pixel sensor array, characterized in that, Comprising: A plurality of pixel sensors, arranged in a grid; A deep trench isolation structure that surrounds the plurality of pixel sensors in a top view of the pixel sensor array; And A time-of-flight sensor circuit, located below the deep trench isolation structure, Wherein the time-of-flight sensor circuit includes: A control gate; and A drain gate, Wherein a top view area of the drain gate is larger than a top view area of the control gate.

7. The pixel sensor array according to claim 6, wherein Wherein the control gate is located at a first side of a pixel sensor among the plurality of pixel sensors; Wherein the drain gate is located at a second side of the plurality of pixel sensors; and Wherein the first side and the second side are a plurality of adjacent sides of the pixel sensor.

8. The pixel sensor array according to claim 6, wherein Wherein the control gate is located at a first side of a pixel sensor among the plurality of pixel sensors; Wherein the drain gate is located at a second side of the plurality of pixel sensors; and Wherein the first side and the second side are a plurality of opposite sides of the pixel sensor.

9. A pixel sensor array, characterized in that, Comprising: A plurality of pixel sensors, including a four-cell quadratic phase detector pixel sensor; A deep trench isolation structure that surrounds a plurality of sub-regions of the four-cell quadratic phase detector pixel sensor in a top view of the pixel sensor array; And A time-of-flight sensor circuit, located below the deep trench isolation structure, wherein the time-of-flight sensor circuit is included around a perimeter of a sub-region among the plurality of sub-regions of the four-cell quadratic phase detector pixel sensor.

10. The pixel sensor array according to claim 9, wherein, Wherein the time-of-flight sensor circuit further includes a drain region, located at a corner between four of the plurality of sub-regions of the four-cell quadratic phase detector pixel sensor.

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