Array substrate based on multi-via-hole lap joint and display device

Abstract

The utility model discloses an array substrate based on multi-via-hole lap joint and a display device. The array substrate comprises a first grid metal wire, a second grid metal wire and an SD metal wire. A first via hole, a second via hole and a third via hole; the first gate metal wire and the second gate metal wire are arranged adjacently; the first gate metal wire is in lap joint with the SD metal wire through a first via hole; the second gate metal wire and the SD metal wire are in lap joint through the second via hole and the third via hole. Through adding via hole connection of SD metal wires, resistances of adjacent gate metal wires are close to or equal, and through carrying out resistance matching on the adjacent gate metal wires, the problem of brightness difference of a display panel caused by resistance difference of adjacent wires due to different connection of the adjacent wires is solved, and the brightness of the display panel is improved. And the display quality of the display device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of wiring of liquid crystal display screens, and particularly relates to an array substrate and a display device based on multi-via lapping. Background Art

[0002] A liquid crystal display screen includes an array substrate, a counter substrate, and a liquid crystal layer located between the two substrates. On the side of the array substrate facing the liquid crystal layer, there are thin film transistors, pixel electrodes, etc. The array substrate generally includes a plurality of pixel units, and a thin film transistor (English: Thin Film Transistor; abbreviation: TFT) is arranged in each pixel unit. The thin film transistor is a basic circuit element for controlling the display brightness of the corresponding pixel unit. Among them, the thin film transistor generally includes a gate electrode, an active layer, a source electrode, and a drain electrode. The source-drain electrode includes a source electrode and a drain electrode, and the active layer provides a conductive channel for the source electrode and the drain electrode.

[0003] The working principle of the display panel is as follows: The electric field between the counter substrate and the array substrate causes the liquid crystal to rotate. By changing the voltage to adjust the electric field strength, the torsion and angle of the liquid crystal material can be controlled, so as to control the light transmittance of this area, and finally obtain the desired image. Among them, the array substrate includes gate lines, data lines, pixel electrodes, and thin film transistors.

[0004] However, in the existing display panel, the adjacent wirings are connected differently, resulting in different resistances of adjacent wirings. For example, one of the adjacent two lines has a via connection, while the other line does not have a via connection. There is a resistance difference between the line with a via and the line without a via connection, causing a brightness difference in the display screen, thereby reducing the display quality. Summary of the Utility Model

[0005] In the existing display panel, the adjacent wirings are connected differently, resulting in different resistances of adjacent wirings, which causes a brightness difference in the display panel.

[0006] In view of the above problems, an array substrate and a display device based on multi-via lapping are proposed. By increasing the via connection to the SD metal trace, the resistances of adjacent gate metal traces are made close or equal. Through resistance matching of adjacent gate metal traces, the problem that the adjacent wirings are connected differently, resulting in different resistances of adjacent wirings, and causing a brightness difference in the display panel is solved, and the display quality of the display device is improved.

[0007] In a first aspect, an array substrate based on multi-via lapping includes:

[0008] A first gate metal trace;

[0009] A second gate metal trace;

[0010] An SD metal trace;

[0011] The first via hole, the second via hole, and the third via hole;

[0012] The first gate metal trace and the second gate metal trace are adjacently routed;

[0013] The first gate metal trace and the SD metal trace are overlapped through the first via hole;

[0014] The second gate metal trace and the SD metal trace are overlapped through the second via hole and the third via hole.

[0015] In a first possible implementation manner of the array substrate based on multi-via-hole overlap described in the first aspect of the present utility model, the second gate metal trace is overlapped with the SD metal trace through the second via hole, and the SD metal trace is overlapped with the second gate metal trace again through the third via hole.

[0016] In a second aspect, an array substrate based on multi-via-hole overlap includes:

[0017] A first gate metal trace;

[0018] A second gate metal trace;

[0019] A first SD metal trace;

[0020] A second SD metal trace and a third SD metal trace;

[0021] A first via hole, a second via hole, a third via hole, a fourth via hole, and a fifth via hole;

[0022] The first gate metal trace and the second gate metal trace are adjacently routed;

[0023] The first gate metal trace and the first SD metal trace are overlapped through the first via hole;

[0024] The second gate metal trace and the second SD metal trace are overlapped through the second via hole and the third via hole, and the second gate metal trace and the third SD metal trace are overlapped through the fourth via hole and the fifth via hole.

[0025] In a first possible implementation manner of the array substrate based on multi-via-hole overlap described in the second aspect of the present utility model, the second gate metal trace is overlapped with the second SD metal trace through the second via hole, and the second SD metal trace is overlapped with the second gate metal trace again through the third via hole.

[0026] Combined with the first possible implementation manner of the second aspect of the present utility model, in the second possible implementation manner, the second gate metal trace is overlapped with the third SD metal trace through the fourth via, and the third SD metal trace is overlapped with the second gate metal trace again through the fifth via.

[0027] Combined with the first or second possible implementation manner of the second aspect of the present utility model, in the third possible implementation manner, the second SD metal trace and the third SD metal trace are adjacently wired on the second gate metal trace.

[0028] In a third aspect, a display device includes the array substrate described in the first aspect or the second aspect.

[0029] Implementing the array substrate and the display device based on multi-via overlap of the present utility model, by increasing the via connection to the SD metal trace, the resistance of adjacent gate metal traces is made close to or equal, and through resistance matching of adjacent gate metal traces, the problem that different adjacent wiring connections result in different resistances of adjacent wirings and cause differences in brightness on the display panel is solved, improving the display quality of the display device. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 It is a schematic diagram of the via connection of the first gate metal trace in Embodiment 1 of the present utility model;

[0032] Figure 2 It is a schematic diagram of the via connection of the second gate metal trace in Embodiment 1 of the present utility model;

[0033] Figure 3 It is a schematic diagram of the via connection of the second gate metal trace in Embodiment 2 of the present utility model;

[0034] The names of the parts referred to by the numbers in the drawings are: 100 - the first gate metal trace, 200 - the SD metal trace, 300 - the second gate metal trace, 400 - the second SD metal trace, 500 - the third SD metal trace, 101 - the first via, 102 - the second via, 103 - the third via, 104 - the fourth via, 105 - the fifth via. Detailed Embodiments

[0035] The following will clearly and completely describe the technical solutions in the present utility model in conjunction with the accompanying drawings in the utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all embodiments. Based on the embodiments in the present utility model, other embodiments obtained by those of ordinary skill in the art without creative efforts all fall within the protection scope of the present utility model.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the specification of the present utility model herein are only for the purpose of describing specific embodiments, and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0038] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application.

[0039] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0040] In the existing display panel, the adjacent wirings are connected differently, resulting in different resistances of the adjacent wirings and causing differences in brightness of the display panel.

[0041] In view of the above problems, an array substrate and a display device based on multi-via lap joint are proposed.

[0042] In the first aspect, as Figure 1 , Figure 1It is a schematic diagram of via connection of the first gate metal trace 100 in Embodiment 1 of the present utility model; An array substrate based on multi-via lap joint includes a first gate metal trace 100, a second gate metal trace 300, and an SD metal trace; a first via 101, a second via 102, and a third via 103; The first gate metal trace 100 and the second gate metal trace 300 are adjacent to each other for wiring; The first gate metal trace 100 and the SD metal trace are lap-jointed through the first via 101; The second gate metal trace 300 and the SD metal trace are lap-jointed through the second via 102 and the third via 103.

[0043] Further, as Figure 2 , Figure 2 It is a schematic diagram of via connection of the second gate metal trace 300 in Embodiment 1 of the present utility model; The second gate metal trace 300 is lap-jointed with the SD metal trace through the second via 102, and the SD metal trace is lap-jointed with the second gate metal trace 300 again through the third via 103.

[0044] Figure 1 The first gate metal trace 100 (Gate) is connected to the SD metal trace through a first via 101, which can be understood as converting from the gate metal trace (Gate) to the SD metal trace for wiring. If the gate metal trace adjacent to the above-mentioned first gate metal trace 100 is not wired through a via, compared with the wiring situation where the first gate metal trace 100 (Gate) is connected to the SD metal trace 200 through a first via 101, there is a resistance difference between the two adjacent metal traces.

[0045] In this embodiment, the second gate metal trace 300 is connected to the SD metal trace through the second via 102, and the SD metal trace 200 is then connected to the second gate metal trace 300 through the third via 103, that is, the second gate metal trace 300 undergoes two via connections and finally remains the second gate metal trace 300. The resistances of the two adjacent gate metal traces for wiring are close. By increasing the via connection to the SD metal trace, the resistances of the adjacent gate metal traces are made close or equal. By performing resistance matching on the adjacent gate metal traces, the problem that the adjacent wiring connections are different, resulting in a resistance difference in the adjacent wiring and causing a brightness difference in the display panel, is solved, and the display quality of the display device is improved.

[0046] Second aspect, an array substrate based on multi-via lap joint, comprising a first gate metal trace 100, a second gate metal trace 300, a first SD metal trace 400; a second SD metal trace 500 and a third SD metal trace; a first via 101, a second via 102, a third via 103, a fourth via 104 and a fifth via 105; the first gate metal trace 100 and the second gate metal trace 300 are adjacent in wiring; the first gate metal trace 100 and the first SD metal trace are lap-jointed through the first via 101; the second gate metal trace 300 and the second SD metal trace 400 are lap-jointed through the second via 102 and the third via 103, and the second gate metal trace 300 and the third SD metal trace 500 are lap-jointed through the fourth via 104 and the fifth via 105.

[0047] Further, as Figure 3 , Figure 3 is a via connection schematic diagram of the second gate metal trace 300 in Embodiment 2 of the present utility model; in a first possible implementation manner, the second gate metal trace 300 is lap-jointed with the second SD metal trace 400 through the second via 102, and the second SD metal trace 400 is lap-jointed with the second gate metal trace 300 again through the third via 103.

[0048] Further, as Figure 3 , the second gate metal trace 300 is lap-jointed with the third SD metal trace 500 through the fourth via 104, and the third SD metal trace 500 is lap-jointed with the second gate metal trace 300 again through the fifth via 105.

[0049] Further, as Figure 3 , the second SD metal trace 400 and the third SD metal trace 500 are adjacent in wiring on the second gate metal trace 300.

[0050] In this embodiment, as Figure 3 , the first gate metal trace 100 and the first SD metal trace are lap-jointed through the first via 101; the second gate metal trace 300 and the second SD metal trace 400 are lap-jointed through the second via 102 and the third via 103, and the second gate metal trace 300 and the third SD metal trace 500 are lap-jointed through the fourth via 104 and the fifth via 105. That is, the second gate metal trace 300 undergoes four via connections and finally remains the second gate metal trace 300, and the resistances of the two adjacent gate metal traces are close. By increasing the via connections to the SD metal traces, the resistances of the adjacent gate metal traces are made close or equal. By performing resistance matching on the adjacent gate metal traces, the problem that the wiring connections of the adjacent gate metal traces are different, resulting in different adjacent wiring resistances and causing brightness differences in the display panel, is solved, and the display quality of the display device is improved.

[0051] In a third aspect, a display device includes the array substrate of the first aspect or the second aspect.

[0052] Implementing the array substrate and the display device based on multi-via overlap of the present utility model, by increasing the via connection to the SD metal trace, the resistance of adjacent gate metal traces is made close to or equal. By performing resistance matching on adjacent gate metal traces, the problem that different adjacent wiring connections result in different adjacent wiring resistances, leading to brightness differences in the display panel, is solved, and the display quality of the display device is improved.

[0053] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. An array substrate based on multi-via overlapping, characterized in that Comprising: The first gate metal trace; The second gate metal trace; The SD metal trace; The first via, the second via and the third via; The first gate metal trace and the second gate metal trace are adjacent to each other for routing; The first gate metal trace and the SD metal trace are overlapped through the first via; The second gate metal trace and the SD metal trace are overlapped through the second via and the third via.

2. The array substrate based on multi-via lapping according to claim 1, wherein The second gate metal trace is overlapped with the SD metal trace through the second via, and the SD metal trace is overlapped with the second gate metal trace again through the third via.

3. An array substrate based on multi-via overlapping, characterized in that, Comprising: The first gate metal trace; The second gate metal trace; The first SD metal trace; The second SD metal trace and the third SD metal trace; The first via, the second via, the third via, the fourth via and the fifth via; The first gate metal trace and the second gate metal trace are adjacent to each other for routing; The first gate metal trace and the first SD metal trace are overlapped through the first via; The second gate metal trace and the second SD metal trace are overlapped through the second via and the third via, and the second gate metal trace and the third SD metal trace are overlapped through the fourth via and the fifth via.

4. The array substrate based on multi-via lap joint according to claim 3, wherein, The second gate metal trace is overlapped with the second SD metal trace through the second via, and the second SD metal trace is overlapped with the second gate metal trace again through the third via.

5. The array substrate based on multi-via overlapping according to claim 4, wherein The second gate metal trace is overlapped with the third SD metal trace through the fourth via, and the third SD metal trace is overlapped with the second gate metal trace again through the fifth via.

6. The array substrate based on multi-via overlapping according to claim 5, characterized in that, The second SD metal trace and the third SD metal trace are adjacent to each other for routing on the second gate metal trace.

7. A display device, characterized in that, Comprising the array substrate based on multi-via overlap according to any one of claims 1-6.

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