Array substrate and display device

Abstract

The utility model provides an array substrate and a display device, and belongs to the technical field of display. The array substrate comprises a substrate body, pixel units arranged on the substrate body, a first test line, a first test terminal, a gating circuit, a plurality of first bonding pads arranged side by side in the first direction, a plurality of second bonding pads arranged side by side in the first direction, a plurality of third bonding pads arranged side by side in the first direction and an electrostatic discharge structure. The first bonding pad, the gating circuit and the second bonding pad are all located in the first sub-binding area, the first bonding pad is closer to the display area than the second bonding pad, and the gating circuit is arranged between the first bonding pad and the second bonding pad; the third bonding pad is located in the second sub-binding area; the first bonding pad and the second bonding pad are configured to be in binding connection with the driving chip; the first test terminal is located in the wiring area; the two ends of the first test line penetrate through the first sub-binding area, extend to the wiring area and are electrically connected with the first test terminal; at least one end of the first test line is electrically connected with the electrostatic discharge structure.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display, and particularly relates to an array substrate and a display device. Background Art

[0002] During the preparation and use of display products, internal static electricity will inevitably be generated. The generated static electricity will continuously accumulate at the tips of metal traces inside the product, such as. Once the accumulation reaches a certain level, a large instantaneous discharge will occur, which is Electro-Static Discharge (ESD), that is, tip discharge, resulting in irreversible damage such as short circuits of metal traces and device burnout, seriously affecting the product yield. Utility Model Content

[0003] The present disclosure aims to solve at least one of the technical problems in the prior art, and provides an array substrate and a display device.

[0004] In a first aspect, the technical solution adopted to solve the technical problems of the present disclosure is an array substrate, which has a display area and a bonding area located on one side of the display area; the bonding area includes a first sub-bonding area, a second sub-bonding area located on the side of the first sub-bonding area away from the display area, and a wiring area surrounding the first sub-bonding area and the second sub-bonding area;

[0005] The array substrate includes a substrate, pixel units disposed on the substrate, a first test line, a first test terminal, a selection circuit, a plurality of first pads arranged side by side in a first direction, a plurality of second pads arranged side by side in the first direction, a plurality of third pads arranged side by side in the first direction, and an electrostatic discharge structure; the pixel units are located in the display area;

[0006] The first pads, the selection circuit, and the second pads are all located in the first sub-bonding area, and the first pads are closer to the display area than the second pads, and the selection circuit is disposed between the first pads and the second pads; the third pads are located in the second sub-bonding area;

[0007] The first pads and the second pads are both configured to be bonded and connected to a driving chip; the third pads are configured to be bonded and connected to a flexible circuit board;

[0008] The first test terminal is located in the wiring area; both ends of the first test line pass through the first sub-bonding area and extend to the wiring area, and are electrically connected to the first test terminal;

[0009] At least one end of the first test line is electrically connected to the electrostatic discharge structure.

[0010] In some embodiments, the array substrate further includes a peripheral region disposed around the display region, and a fan-out region disposed between the peripheral region and the bonding region;

[0011] The array substrate further includes a second test terminal, a second test line, a plurality of touch electrode lines extending along a second direction, and touch leads electrically connected to the touch electrode lines; the second test terminal is located in the routing region; both ends of the second test line pass through the first sub-bonding region and extend to the routing region; both ends of the touch electrode lines pass through the display region and extend to the peripheral region, and the touch leads pass through the fan-out region, with one end extending to the peripheral region and electrically connected to the touch electrode lines, and the other end extending to the first sub-bonding region and electrically connected to the first pad; the second direction is disposed intersecting the first direction;

[0012] The strobe circuit includes switching transistors corresponding one-to-one to the touch leads; a first pole of the switching transistor is electrically connected to the first pad connected to the corresponding touch lead, a second pole is electrically connected to the first test line, and a control pole is electrically connected to the second test line.

[0013] In some embodiments, the array substrate includes a common electrode bus located in the peripheral region and surrounding the display region, and a first common lead extending from the peripheral region to the routing region; the common electrode bus includes two first sub-segments extending along the first direction and disposed opposite to each other, and two second sub-segments extending along the second direction and disposed opposite to each other; the first sub-segments and the second sub-segments are connected end to end in sequence;

[0014] Two ends of one of the first sub-segments close to the first sub-bonding region are respectively electrically connected to first ends of two of the first common leads; a second end of the first common lead is electrically connected to one end of the first test line;

[0015] The first common lead, the first sub-segment, and the second sub-segment are multiplexed as at least a part of the electrostatic discharge structure.

[0016] In some embodiments, the first common lead and the first test line are disposed on the same layer and connected as an integral structure.

[0017] In some embodiments, for at least one of the first common leads, the second end of the first common lead and one end of the first test line are both electrically connected to the same first test terminal.

[0018] In some embodiments, the array substrate further includes a first jumper wire located in the routing region;

[0019] The first common lead and the first test line are disposed on the same layer and at intervals;

[0020] The first test line and the first adapter line are on different layers; the first test line is electrically connected to the first common lead through the first adapter line;

[0021] The first adapter line is reused as another part of the electrostatic discharge structure.

[0022] In some embodiments, the array substrate further includes a third test terminal located in the wiring area;

[0023] For at least one of the first common leads, the second end of the first common lead and the first end of the first adapter line are both electrically connected to the same third test terminal, and the second end of the first adapter line and one end of the first test line are both electrically connected to the same first test terminal.

[0024] In some embodiments, the array substrate further includes a driving chip and a common pad located in the first sub-bonding area;

[0025] The common pad, the plurality of first pads, and the plurality of second pads are respectively bonded to the driving chip; the common pad and the first pads are arranged side by side along the first direction;

[0026] The first test line is spaced from the second pad; in the normal display stage, the switching transistor is turned off, and the driving chip provides a second operating voltage to the touch electrode line through the first pad and provides a first reference voltage to the common electrode bus through the common pad to load the first reference voltage on the first test line.

[0027] In some embodiments, the second operating voltage and the first reference voltage are the same.

[0028] In some embodiments, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged in a direction away from the substrate;

[0029] The first test line, the second test line, the common electrode bus, the first common lead, and the control electrode of the switching transistor are all located in the first conductive layer;

[0030] The touch electrode line, the touch lead, the first and second poles of the switching transistor are all located in the second conductive layer;

[0031] The first adapter line is located in the third conductive layer; at least part of the film layers of the first test terminal, the second test terminal, the third test terminal, the first pad, the second pad, the third pad, and the common pad are located in the third conductive layer.

[0032] In some embodiments, the electrostatic discharge structure includes at least one redundant pad located in the second sub-bonding area, and a second jumper wire located in the routing area and corresponding to the redundant pad one by one;

[0033] The first test line includes a first test sub-segment located in the first sub-bonding area and a second test sub-segment located in the routing area;

[0034] For any one of the redundant pads, the first end of the redundant pad is electrically connected to the second test sub-segment through the corresponding second jumper wire, and the second end of the redundant pad is floating.

[0035] In some embodiments, the electrostatic discharge structure includes at least one redundant pad located in the first sub-bonding area, and a second jumper wire located in the first sub-bonding area and corresponding to the redundant pad one by one;

[0036] The first test line includes a first test sub-segment located in the first sub-bonding area and a second test sub-segment located in the routing area;

[0037] For any one of the redundant pads, the first end of the redundant pad is electrically connected to the second test sub-segment through the corresponding second jumper wire, and the second end of the redundant pad is floating.

[0038] In some embodiments, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged in a direction away from the substrate;

[0039] The first test line, the second test line, and the control electrode of the switching transistor are located in the first conductive layer;

[0040] The touch electrode line, the touch lead, the first and second poles of the switching transistor are all located in the second conductive layer;

[0041] The second jumper wire is located in the third conductive layer; at least part of the film layers of the first test terminal, the second test terminal, the first pad, the second pad, the third pad, and the redundant pad are located in the third conductive layer.

[0042] In some embodiments, the electrostatic discharge structure includes a plurality of protrusions located in the first sub-bonding area. The protrusions are connected to the first test line as an integral structure and protrude along the side away from the switching transistor.

[0043] In some embodiments, in addition to the two ends, the first test line further includes a first connection node located in the middle area and electrically connected to the second pole of the switching transistor;

[0044] The protrusions are arranged between adjacent first connection nodes in the extending direction of the first test line.

[0045] In some embodiments, the electrostatic discharge structure is located in the wiring area. One end of the electrostatic discharge structure is electrically connected to the first test line, and the other end extends to the edge of the wiring area.

[0046] In some embodiments, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged in a direction away from the substrate;

[0047] The first test line, the second test line, and the control electrode of the switching transistor are all located in the first conductive layer;

[0048] The touch electrode line, the touch lead, the first and second poles of the switching transistor are all located in the second conductive layer;

[0049] The electrostatic discharge structure is located in the third conductive layer; at least part of the film layers of the first test terminal, the second test terminal, the first pad, the second pad, and the third pad are located in the third conductive layer.

[0050] In some embodiments, the line width of the electrostatic discharge structure is greater than the line width of the first test line.

[0051] In some embodiments, the array substrate further includes a flexible circuit board and a fourth pad located in the second sub-bonding area, and a third jumper wire located in the wiring area;

[0052] The fourth pad is bonded and connected to the flexible circuit board, and the fourth pad is electrically connected to the portion of the first test line located in the first sub-bonding area through the third jumper wire;

[0053] In the normal display stage, the switching transistor is turned off, and the flexible circuit board provides a first reference voltage to the first test line through the fourth pad to load the first reference voltage on the first test line.

[0054] In some embodiments, the array substrate further includes a driving chip located in the first sub-bonding area;

[0055] A plurality of first pads and a plurality of second pads are respectively bonded and connected to the driving chip;

[0056] In the normal display stage, the switching transistor is turned off, and the driving chip provides a second working voltage to the touch electrode line through the first pad.

[0057] In some embodiments, the array substrate further includes a flexible circuit board and a fourth pad located in the second sub-bonding area, a fifth pad located in the first sub-bonding area, a third jumper wire located in the routing area, and a fourth jumper wire located in the first sub-bonding area; the fifth pad and the second pad are arranged side by side along the second direction;

[0058] The fourth pad is bonded and connected to the flexible circuit board, the fourth pad is electrically connected to the fifth pad through the third jumper wire, and the fifth pad is electrically connected to the part of the first test line located in the first sub-bonding area through the fourth jumper wire;

[0059] In the normal display stage, the switching transistor is turned off, and the flexible circuit board provides a first reference voltage to the first test line through the fourth pad and the fifth pad.

[0060] In some embodiments, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged along a direction away from the substrate;

[0061] The first test line, the second test line, the third jumper wire, and the control electrode of the switching transistor are all located in the first conductive layer;

[0062] The touch electrode line, the touch lead, the first pole and the second pole of the switching transistor are all located in the second conductive layer;

[0063] The fourth jumper wire is located in the third conductive layer; at least part of the film layers of the first pad, the second pad, the third pad, the fourth pad, and the fifth pad are located in the third conductive layer.

[0064] In some embodiments, the second working voltage is the same as the first reference voltage.

[0065] In a second aspect, an embodiment of the present disclosure further provides a display device, including the array substrate according to any one of the first aspects. Description of the Drawings

[0066] Figure 1 It is a wiring schematic diagram of a touch test line in an existing display product;

[0067] Figure 2 It is a schematic diagram of the array substrate under Example 1 provided by the embodiment of the present disclosure;

[0068] Figure 3 It is a schematic diagram of a connection relationship between a first common lead and a first test line provided by the embodiment of the present disclosure;

[0069] Figure 4Schematic diagram of the array substrate under Example 2 provided by the present disclosure;

[0070] Figure 5 Schematic diagram of another connection relationship between the first common lead and the first test line provided by the present disclosure;

[0071] Figure 6 Schematic diagram of the film stack of the array substrate under Example 1 provided by the present disclosure;

[0072] Figure 7 Schematic diagram of the film stack of the array substrate under Example 2 provided by the present disclosure;

[0073] Figure 8 Schematic diagram of the array substrate under Example 3 provided by the present disclosure;

[0074] Figure 9 For Figure 8 Partial enlarged view of the pad structure in

[0075] Figure 10 Schematic diagram of the film stack of the array substrate under Example 3 provided by the present disclosure;

[0076] Figure 11 Schematic diagram of the connection relationship between the redundant pad and the second jumper wire provided by the present disclosure;

[0077] Figure 12 Schematic diagram of the connection relationship between the third jumper wire and the fourth jumper wire provided by the present disclosure;

[0078] Figure 13a Schematic diagram of the array substrate under Example 4 provided by the present disclosure;

[0079] Figure 13b Schematic diagram of the array substrate under Example 5 provided by the present disclosure;

[0080] Figure 14 Schematic diagram of the array substrate under Example 6 provided by the present disclosure;

[0081] Figure 15 Schematic diagram of the array substrate under Example 7 provided by the present disclosure;

[0082] Figure 16 Schematic diagram of the film stack of the array substrate under Example 7 provided by the present disclosure;

[0083] Figure 17 Schematic diagram of the connection relationship between the peripheral AT trace and the fifth jumper wire provided by the present disclosure;

[0084] Figure 18Schematic diagram of the wiring of the second test line provided by the embodiments of the present disclosure;

[0085] Figure 19 Schematic diagram of the connection relationship between the sixth pad and the sixth jumper wire provided by the embodiments of the present disclosure;

[0086] Figure 20 Schematic diagram of the electrical connection relationship of a fourth pad provided by the embodiments of the present disclosure;

[0087] Figure 21 Schematic diagram of another electrical connection relationship of the fourth pad provided by the embodiments of the present disclosure. Detailed implementation manners

[0088] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Usually, the components of the embodiments of the present disclosure described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed present disclosure, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0089] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure belongs. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, terms such as "a", "an", or "the" do not denote a quantity limitation, but mean that there is at least one. Words such as "including" or "comprising" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connection" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0090] In the present disclosure, "a plurality of or several" means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0091] In the embodiments of the present disclosure, the first direction X, the second direction Y, and the third direction Z intersect pairwise. In the present disclosure, taking the first direction X and the second direction Y being perpendicular to each other in the plane of the substrate, the first direction X being the horizontal direction (or the extension direction of the gate line Gate), the second direction Y being the vertical direction (or the extension direction of the data line Data), and the third direction Z being the vertical direction perpendicular to the plane of the substrate as an example for illustration, but it does not limit the present disclosure.

[0092] In the embodiments of the present disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern and then using the same mask plate through a single patterning process. Depending on the different specific patterns, the patterning process may include multiple exposure, development, or etching processes in sequence, and the specific patterns formed in the same layer may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0093] Before introducing the specific structure of the array substrate of the present disclosure, the application scenarios and circuit structures of the array substrate provided by the present disclosure are described in detail first. The array substrate of the present disclosure can be applied to liquid crystal display, that is, a liquid crystal array substrate.

[0094] The transistor adopted in the embodiments of the present disclosure can be a thin-film transistor, a field-effect transistor, or other devices with the same characteristics. Since the source and drain of the adopted transistor are symmetric, there is no difference between its source and drain. In the embodiments of the present disclosure and subsequent descriptions, to distinguish the source and drain of the transistor, one of the poles is called the first pole, the other pole is called the second pole, and the gate is called the control pole. In addition, the transistor can be divided into N-type and P-type according to its characteristics. Among them, an N-type thin-film transistor refers to N-type ion doping in the active layer of the thin-film transistor; a P-type thin-film transistor refers to P-type ion doping in the active layer of the thin-film transistor. The working level signal of the N-type thin-film transistor is a high-level signal; the working level signal of the P-type thin-film transistor is a low-level signal.

[0095] In the related art, performance testing is often performed during the manufacturing process of display products to improve the product yield. For example, before IC bonding, an external device provides a test signal to the circuits inside the array substrate through the test lines inside the array substrate, and the performance test result is determined by judging whether the product can be normally lit. However, during the design process of the array substrate, its internal circuits are complex. When the routing paths of the introduced test lines are long, ESD is likely to occur at the ends, easily causing irreversible damages such as short circuits of metal traces and device burnout, seriously affecting the product yield.

[0096] Figure 1 It is a wiring schematic diagram of a touch test line in an existing display product. In the related art, as Figure 1 shown, the display product has a display area AA, a terminal side (Data Pad, DP) longitudinally located below the display area AA, and a non-terminal side (Data Pad Opposite, DPO) longitudinally located above the display area AA. The display product includes a substrate 1, touch electrode lines Tx, a touch test line Tx_Test, and a test terminal CT pad. During the test stage in the manufacturing process of the display product, the switch circuit SW is turned on, and an external device accesses through the test terminal CT pad and provides a common signal (Vcom) to the touch test line Tx_Test. The touch test line Tx_Test is used to transmit the common signal (Vcom) and supply it to the touch electrode lines Tx through the switch circuit SW in the on state.

[0097] During the normal display stage of the display product, the switch circuit SW is turned off. At this time, a flexible printed circuit board (FPC) is used to provide a reference ground signal (GND) to the touch test line Tx_Test through the input terminal In of the driving chip (IC). At the same time, the driving chip (IC) is started, and a common signal (Vcom) is provided to the touch electrode lines Tx through the output terminal Out of the driving chip (IC).

[0098] As Figure 1 shown, it can be seen that the touch test line Tx_Test spans across the entire array substrate and is electrically connected to the input terminal In of the driving chip (IC). The input terminal In is electrically connected to the pin end FPC PIN of the flexible printed circuit board (FPC). The pin end FPCPIN is equivalent to the tip of a long wire and is prone to charge accumulation. During many manufacturing stages such as cutting, bonding, and transportation, ESD is likely to occur, resulting in irreversible damages such as short circuits of metal traces and device burnout, seriously affecting the product yield.

[0099] In view of this, the embodiments of the present disclosure provide an array substrate that substantially eliminates one or more of the problems caused by the limitations and defects of the related art.

[0100] Figure 2 Schematic diagram of the array substrate under Example 1 provided by this disclosure, as Figure 2 shown, the array substrate has a display area AA and a bonding area BB located on one side of the display area AA; the bonding area BB includes a first sub-bonding area BB1, a second sub-bonding area BB2 located on the side of the first sub-bonding area BB1 away from the display area AA, and a wiring area BB3 surrounding the first sub-bonding area BB1 and the second sub-bonding area BB2. The array substrate includes a substrate 1, pixel units (not shown in the figure) disposed on the substrate 1, a first test line 2, a first test terminal 31, a gating circuit 4, a plurality of first pads 51 arranged side by side along a first direction X, a plurality of second pads 52 arranged side by side along the first direction X, a plurality of third pads 53 arranged side by side along the first direction X, and an electrostatic discharge structure 6. Among them, the material of the substrate 1 may include but is not limited to one of polyimide (PI), polyethylene naphthalene-2,6-dicarboxylate (PEN), polyethylene terephthalate (PET), flexible plastic colorless polyimide (CPI), thermoplastic urethane (TUP), or ultra-thin glass (UTG). The substrate 11 may also be made of a rigid transparent material such as glass, which can effectively support other film layers thereon. In practical applications, appropriate materials can be selected according to actual needs. Exemplarily, the substrate 1 may be a single-layer structure or a multi-layer structure. The multi-layer substrate 1 may have an inorganic thin film added between layers as a buffer layer, and the material of the buffer layer may be one or a combination of multiple layers of amorphous silicon (a-Si), silicon nitride (SiNx), and silicon oxide (SiOx).

[0101] The pixel units are located in the display area AA; the first pads 51, the gating circuit 4, and the second pads 52 are all located in the first sub-bonding area BB1, and the first pads 51 are closer to the display area AA than the second pads 52, and the gating circuit 4 is disposed between the first pads 51 and the second pads 52; the third pads 53 are located in the second sub-bonding area BB2. Both the first pads 51 and the second pads 52 are configured to be bonded and connected to a driving chip (not shown in the figure); the third pads 53 are configured to be bonded and connected to a flexible circuit board (not shown in the figure). Among them, the second pads 52 are electrically connected to the input pins of the driving chip, the first pads 51 are electrically connected to the output pins of the driving chip, and the third pads 53 are electrically connected to the output pins of the flexible circuit board.

[0102] The first test terminal 31 is located in the routing area BB3; both ends of the first test line 2 pass through the first sub-bonding area BB1 and extend to the routing area BB3, and are electrically connected to the first test terminal 31; when the gating circuit 4 is in the on state, the first test terminal 31 provides a first operating voltage to the first test line 2 to test the display and / or touch function of the display area AA, etc. Here, the first test terminal 31 is a contact pad. Here, an external test device is needed to connect to the first test terminal 31 and provide the first operating voltage to the first test line 2 through the first test terminal 31. At this time, the gating circuit 4 is in the on state, so the first operating voltage can be transmitted to the structure to be tested located in the display area AA, such as a touch electrode or a data line (Data), etc., to test whether the pixel unit is normally lit, etc.

[0103] At least one end of the first test line 2 is electrically connected to an electrostatic discharge structure 6 for dispersing the static electricity on the first test line 2.

[0104] For ease of understanding, the present disclosure takes the first test line 2 as an example of the test line of the touch electrode line Tx for illustration. In some embodiments, the array substrate further includes a peripheral area CC disposed around the display area AA, and a fan-out area DD disposed between the peripheral area CC and the bonding area BB. As Figure 2 shown, the array substrate further includes a second test terminal 32, a second test line 7, a plurality of touch electrode lines Tx extending along the second direction Y, and a touch lead 8 electrically connected to the touch electrode line Tx. The touch electrode lines Tx and the touch leads 8 are arranged in one-to-one correspondence. The touch electrode line Tx is electrically connected to a touch electrode (not shown in the figure), and the touch electrode line Tx and the touch electrode can be arranged in a one-to-one or one-to-many manner. Among them, the second test terminal 32 is located in the routing area BB3; both ends of the second test line 7 pass through the first sub-bonding area BB1 and extend to the routing area BB3, and at least one end is electrically connected to the second test terminal 32; for example, the second test terminal 32 includes two, and both ends of the second test line 7 are electrically connected to the second test terminal 32 to receive a control signal by using the second test terminal 32.

[0105] Both ends of the touch electrode line Tx pass through the display area AA and extend to the peripheral area CC. The touch lead 8 is a fan-out trace. The touch lead 8 passes through the fan-out area DD, one end of which extends to the peripheral area CC and is electrically connected to the touch electrode line Tx, and the other end extends to the first sub-bonding area BB1 and is electrically connected to the first pad 51; the touch leads 8 and the first pads 51 are arranged in one-to-one correspondence. The second direction Y intersects with the first direction X, for example, the second direction Y is perpendicular to the first direction X.

[0106] During the test stage in the preparation process of the array substrate, the driving chip is not bonded; during the normal display stage of the array substrate, the driving chip is bonded.

[0107] The strobe circuit 4 includes switching transistors 41 corresponding one-to-one to the touch leads 8; a plurality of switching transistors 41 are arranged side by side along the first direction X. The first pole S of the switching transistor 41 is electrically connected to the first pad 51 connected to the corresponding touch lead 8, the second pole D is electrically connected to the first test line 2, and the control pole G is electrically connected to the second test line 7.

[0108] In the embodiment of the present disclosure, the switching transistor 41 is taken as an example of an N-type thin film transistor for description, but the present disclosure is not limited to the N-type thin film transistor. Here, it is necessary to use an external test device to connect the second test terminal 32 and provide a control signal to the second test line 7 through the second test terminal 32. The second test line 7 is electrically connected to the control pole of the switching transistor 41. In response to receiving the control signal, when the control signal is a high-level signal, the switching transistor 41 is turned on; the first test line 2 is electrically connected to the second pole of the switching transistor 41, and the first working voltage is transmitted to the touch lead 8 through the turned-on switching transistor 41, and thus transmitted to the touch electrode line Tx electrically connected to the touch lead 8. In this environment, it is tested whether the pixel unit is normally lit.

[0109] The main extension directions of the first test line 2 and the second test line 7 are both the first direction X. The orthographic projections of the first test line 2 and the second test line 7 on the substrate 1 can straddle the orthographic projections of the extension lines of all the touch electrode lines Tx on the substrate 1.

[0110] As Figure 2 shown, the first test line 2 is a long trace. By being electrically connected to the first test line 2 through the electrostatic discharge structure 6, the electrostatic discharge structure 6 can be used to release the static electricity on the first test line 2, avoiding ESD of the first test line 2 and affecting the product yield.

[0111] The specific structure of the electrostatic discharge structure 6 will be elaborated in detail below with different embodiments.

[0112] In some embodiments, as Figure 2As shown in the figure, the array substrate includes a common electrode bus 9 located in the peripheral area CC and surrounding the display area AA, and a first common lead 101 extending from the peripheral area CC to the routing area BB3; the common electrode bus 9 includes two first sub-segments 91 extending along the first direction X and arranged opposite to each other, and two second sub-segments 92 extending along the second direction Y and arranged opposite to each other; the first sub-segment 91 and the second sub-segment 92 are connected end to end in sequence. The two ends of one first sub-segment 91 close to the first sub-bonding area BB1 are respectively electrically connected to the first ends of two first common leads 101; the second end of the first common lead 101 is electrically connected to one end of the first test line 2; the first common lead 101, the first sub-segment 91 and the second sub-segment 92 are multiplexed as at least a part of the electrostatic discharge structure 6, and the static electricity on the first test line 2 is introduced into the first sub-segment 91 and the second sub-segment 92 by using the first common lead 101, and the static electricity is dispersed by using the first sub-segment 91 and the second sub-segment 92 to achieve electrostatic discharge.

[0113] During the test stage of the array substrate, a first operating voltage is provided to the first test line 2; at this time, since the first test line 2 is electrically connected to the first common lead 101, the first common lead 101 is also connected to the first operating voltage, so that the common electrode bus 9 is connected to the first operating voltage. Optionally, the first operating voltage is a common voltage (Vcom), for example, -3V; the common electrode bus 9 can provide the common voltage (Vcom) to the redundant touch electrode line (Tx_dummy).

[0114] The array substrate further includes a second common lead 102 and a common pad 50 corresponding to the second common lead 102. Among them, the second common lead 102 passes through the fan-out area DD, one end of which extends to the peripheral area CC and is electrically connected to the common electrode bus 9, and the other end extends to the first sub-bonding area BB1 and is electrically connected to the common pad 50.

[0115] During the normal display stage of the array substrate, the driving chip is bonded, and a first reference voltage is provided to the common electrode bus 9 through the common pad 50; at this time, since the common electrode bus 9 is electrically connected to the first test line 2 through the first common lead 101, the first test line 2 is also connected to the first reference voltage. Optionally, the first reference voltage is a common voltage (Vcom), for example, -3V; the common electrode bus 9 can provide the common voltage (Vcom) to the redundant touch electrode line (Tx_dummy).

[0116] Optionally, the line width of the common electrode bus 9 is greater than the line width of the first test line 2, which is beneficial to dispersing static charges.

[0117] Optionally, the line width of the second sub-segment 92 in direct contact with the first common lead 101 is greater than the line width of the first test line 2.

[0118] Optionally, the line width of the first common lead 101 is greater than the line width of the first test line 2.

[0119] Figure 3 FIG. is a schematic diagram of a connection relationship between the first common lead 101 and the first test line 2 provided in an embodiment of the present disclosure. In a possible implementation manner, as Figure 3 shown, the first common lead 101 and the first test line 2 can be disposed on the same layer and connected as an integral structure, and the static electricity on the first test line 2 can be quickly introduced into the common electrode bus 9 through the first common lead 101 connected integrally therewith to disperse charges.

[0120] As Figure 2 shown, for at least one first common lead 101, the second end of the first common lead 101 and one end of the first test line 2 are both electrically connected to the same first test terminal 31.

[0121] Exemplarily, the array substrate has two first test terminals 31, which are respectively electrically connected to both ends of the first test line 2.

[0122] Exemplarily, the array substrate has one first test terminal 31, which is electrically connected to one end of the first test line 2.

[0123] Figure 4 FIG. is a schematic diagram of the array substrate under Example 2 provided in an embodiment of the present disclosure; Figure 5 FIG. is a schematic diagram of another connection relationship between the first common lead 101 and the first test line 2 provided in an embodiment of the present disclosure. In another possible implementation manner, as Figure 4 and Figure 5 shown, the array substrate further includes a first jumper wire 111 located in the routing area BB3; the first common lead 101 and the first test line 2 are on the same layer and are spaced apart; the first test line 2 and the first jumper wire 111 are not on the same layer; the first test line 2 is electrically connected to the first common lead 101 through the first jumper wire 111; the first common lead 101, the first sub-segment 91 and the second sub-segment 92 are multiplexed as part of the electrostatic discharge structure 6, and the first jumper wire 111 is multiplexed as another part of the electrostatic discharge structure 6.

[0124] Exemplarily, there are two first jumper wires 111. One end of one of them is electrically connected to the second end of one first common lead 101, and the second end of the first jumper wire 111 is electrically connected to one end (first end A) of the first test line 2; one end of the other is electrically connected to the second end of the other first common lead 101, and the second end of the first jumper wire 111 is electrically connected to the other end (second end B) of the first test line 2.

[0125] As Figure 4As shown, the array substrate further includes a third test terminal 33 located in the wiring area BB3. For example, the first test terminal 31, the second test terminal 32, and the third test terminal 33 are arranged side by side in the first direction X, and the third test terminal 33 is located on the side of the first test terminal 31 away from the second test terminal 32. For at least one first common lead 101, the second end of the first common lead 101 and the first end of the first jumper wire 111 are both electrically connected to the same third test terminal 33, and the second end of the first jumper wire 111 and one end of the first test line 2 are both electrically connected to the same first test terminal 31.

[0126] Exemplarily, the array substrate has two first test terminals 31, which are respectively electrically connected to both ends of the first test line 2.

[0127] Exemplarily, the array substrate has one first test terminal 31, which is electrically connected to one end of the first test line 2.

[0128] In this embodiment, the first common lead 101 and the first test line 2 are arranged on the same layer and are bridged by the first jumper wire 111 on different layers. The two first common leads 101, the first jumper wire 111, the first sub-segment 91, and the second sub-segment 92 are multiplexed as an electrostatic discharge structure 6. Using the electrically connected first jumper wire 111 and the first common lead 101, the static electricity on the first test line 2 is introduced into the first sub-segment 91 and the second sub-segment 92, and the first sub-segment 91 and the second sub-segment 92 are used to disperse the static electricity to achieve electrostatic discharge.

[0129] Compared with the array substrate in Example 2, the array substrate in Example 1 saves the third test terminal 33. During the test stage of the array substrate, only by using the first test terminal 31, it is possible to simultaneously supply power to the common electrode bus 9 and the first test line 2, saving the wiring space.

[0130] In some embodiments, such as Figure 2 or Figure 4 as shown, the first test line 2 is arranged at an interval from the second pad 52.

[0131] In Example 1 and Example 2, by simply adjusting the connection structure of the first test line 2, for example, interrupting the connection relationship between the first test line 2 and the second pad 52, and by connecting the first test line 2 and the first common lead 101 to form an electrostatic ring, the adverse effects caused by ESD can be avoided.

[0132] In some embodiments, for the above Example 1 and Example 2, such as Figure 2 or Figure 4As shown, the array substrate further includes a driving chip (not shown in the figure) located in the first sub-bonding region BB1 and a common pad 50; the common pad 50, a plurality of first pads 51, and a plurality of second pads 52 are respectively bonded and connected to the driving chip; the common pad 50 and the first pads 51 are arranged side by side along the first direction X, and are located on one side of the first pads 51 close to the edge of the first sub-bonding region BB1.

[0133] As Figure 2 or Figure 4 shown, the first test line 2 is arranged at an interval from the second pad 52; in the normal display stage, the switching transistor 41 is turned off, and the driving chip provides a second working voltage to the touch electrode line Tx through the first pad 51, and provides a first reference voltage to the common electrode bus 9 through the common pad 50 to load the first reference voltage on the first test line 2.

[0134] In this embodiment, it is set that the first test line 2 is disconnected from the second pad 52. Compared with the existing structure as Figure 1 shown, in the normal display stage, instead of providing a reference ground signal through the flexible circuit board, the first reference voltage is provided to the first test line 2 through the common pad 50 by means of the second common lead 102 and the first common lead 101.

[0135] Optionally, the range of the first reference voltage is between -3V and 0V. For example, the first reference voltage is the ground voltage 0V or the common voltage -3V.

[0136] In some embodiments, the first working voltage and the second working voltage are the same. For example, both the first working voltage and the second working voltage are common voltages.

[0137] In some embodiments, the second working voltage and the first reference voltage are the same and are both common voltages, such as -3V. In the normal display stage of the product, compared with providing a reference ground signal to the first test line 2 in the related art, in the present disclosure, the second working voltage and the first reference voltage are the same and are both common voltages. In this way, there is no voltage difference between the source and the drain of the switching transistor 41 in the off stage, reducing touch noise, thereby improving the stability of the common signal of the touch electrode line Tx and facilitating the recognition of the user's true touch position.

[0138] In some embodiments, the first working voltage, the second working voltage, and the first reference voltage are the same, for example, they are all common voltages.

[0139] Figure 6 This is a schematic diagram of the film stack of the array substrate under Example 1 provided by the embodiments of the present disclosure. In some embodiments, for Example 1, as Figure 6As shown, the array substrate includes a first conductive layer 01, a second conductive layer 02, and a third conductive layer 03 that are sequentially arranged in a direction away from the substrate 1; among them, the first test line 2, the second test line 7, the common electrode bus 9, the first common lead 101, and the control electrode G of the switching transistor 41 are all located on the first conductive layer 01; the touch electrode line Tx, the touch lead 8, the first pole S and the second pole D of the switching transistor 41 are all located on the second conductive layer 02; at least part of the film layers of the first test terminal 31, the second test terminal 32, the first pad 51, the second pad 52, the third pad 53, and the common pad 50 are located on the third conductive layer 03. The connection ends of the first test terminal 31, the second test terminal 32, the first pad 51, the second pad 52, the third pad 53, and the common pad 50 are located on the third conductive layer 03.

[0140] Exemplarily, the first test terminal 31, the second test terminal 32, the first pad 51, the second pad 52, the third pad 53, and the common pad 50 all include a multi-layer connection structure. Among them, the connection ends of the first test terminal 31 and the second test terminal 32 are the ends connected to the external test equipment. The connection ends of the first pad 51, the second pad 52, and the common pad 50 are the bonding ends bonded to the driving chip. The connection end of the third pad 53 is the bonding end bonded to the flexible circuit board. The connection end is located at the top layer of the multi-layer connection structure, that is, on the third conductive layer 03. The connection end of the first test terminal 31 located on the third conductive layer 03 can be transferred through a first overlapping portion (not shown in the figure) located on the second conductive layer 02 and then electrically connected to the first test line 2. Similarly, the connection end of the second test terminal 32 located on the third conductive layer 03 can be transferred through a second overlapping portion (not shown in the figure) located on the second conductive layer 02 and then electrically connected to the second test line 7. The connection end of the common pad 50 located on the third conductive layer 03 can be transferred through a third overlapping portion (not shown in the figure) located on the second conductive layer 02 and then electrically connected to the second common lead 102 located on the first conductive layer 01. The connection end of the second pad 52 located on the third conductive layer 03 can be transferred through a fourth overlapping portion (not shown in the figure) located on the second conductive layer 02 and then electrically connected to the first connection portion 521 located on the first conductive layer 01; the connection end of the third pad 53 located on the third conductive layer 03 can be transferred through a fifth overlapping portion (not shown in the figure) located on the second conductive layer 02 and then electrically connected to the second connection portion 531 located on the first conductive layer 01.

[0141] Figure 7 It is a schematic diagram of the film layer stack of the array substrate under Example 2 provided by the present disclosure. In some embodiments, for Example 1, as Figure 7As shown, the array substrate includes a first conductive layer 01, a second conductive layer 02, and a third conductive layer 03 that are sequentially arranged in a direction away from the substrate 1; among them, the first test line 2, the second test line 7, the common electrode bus 9, the first common lead 101, and the control electrode G of the switching transistor 41 are all located in the first conductive layer 01; the touch electrode line Tx, the touch lead 8, the first pole S and the second pole D of the switching transistor 41 are all located in the second conductive layer 02; the first jumper line 111 is located in the third conductive layer 03; at least part of the film layers (connection ends) of the first test terminal 31, the second test terminal 32, the third test terminal 33, the first pad 51, the second pad 52, the third pad 53, and the common pad 50 are located in the third conductive layer 03.

[0142] It should be noted that Figure 6 and Figure 7 the film stack structure shown only represents the stacking relationship of each film layer and does not represent the actual position and size.

[0143] Exemplarily, the third test terminal 33 includes a multi-layer connection structure. Among them, the connection end is located at the top layer, that is, the third conductive layer 03. The connection end of the third test terminal 33 located in the third conductive layer 03 can be transferred through a sixth overlapping portion (not shown in the figure) located in the second conductive layer 02 and then electrically connected to the first common lead 101 located in the first conductive layer 01.

[0144] For Example 1, as Figure 6 shown, both the first test line 2 and the first common lead 101 are located in the first conductive layer 01 and are connected as an integral structure and electrically connected to the common electrode bus 9 to conduct the static charges on the first test line 2.

[0145] For Example 2, as Figure 7 shown, both the first test line 2 and the first common lead 101 are located in the first conductive layer 01 and are spaced apart; the first test line 2 and the first common lead 101 are bridged through the first jumper line 111 located on the second conductive layer 02. The first test terminal 31, the third test terminal 33, and the first jumper line 111 are all located in the third conductive layer 03; the first test terminal 31, the first jumper line 111, and the third test terminal 33 are connected as an integral structure.

[0146] Optionally, the second common lead 102 is located in the first conductive layer 01 and is connected to the common electrode bus 9 as an integral structure.

[0147] As Figure 6As shown, a gate insulating layer GI is further included between the first conductive layer 01 and the second conductive layer 02. Between the second conductive layer 02 and the third conductive layer 03, a first passivation layer PVX1, a planarization layer PLN, and a second passivation layer PVX2 are sequentially arranged in a direction away from the substrate 1. The first test line 2 is electrically connected to the second pole D of the switching transistor 41 through a first via V1 penetrating the gate insulating layer GI; the first pole S of the switching transistor 41 is arranged on the same layer as the touch lead 8, and the two are connected as an integrated structure. Exemplarily, the first pad 51 can be electrically connected to the first pad 51 through a second via (not shown in the figure) sequentially penetrating the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2, or the first pad 51 is electrically connected to the touch lead 8 through a third via V3 sequentially penetrating the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2; the touch lead 8 is arranged on the same layer as the touch electrode line Tx, and the two are connected as an integrated structure. The common pad 50 is electrically connected to the second common lead 102 through a fourth via V4 sequentially penetrating the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2. The first test terminal 31 is electrically connected to the first test line 2 through a fifth via V5 sequentially penetrating the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2. The second test terminal 32 is electrically connected to the second test line 7 through a sixth via V6 sequentially penetrating the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2.

[0148] As Figure 7 shown, the first test terminal 31 is electrically connected to the first test line 2 through a fifth via V5 sequentially penetrating the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2. The third test terminal 32 is electrically connected to the first common lead 101 through a seventh via V7 sequentially penetrating the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2.

[0149] The materials of the first passivation layer PVX1 and the second passivation layer PVX2 can be the same, including organic materials and / or inorganic materials. Among them, the organic passivation materials include polyimide-based; the inorganic passivation materials are, for example, silicon oxide-based (such as silicon dioxide SiO2) and silicon nitride (such as trisilicon tetranitride Si3N4), etc. The material of the planarization layer PLN can include, but is not limited to, one or a combination of resin-based materials such as acrylic, polyimide, epoxy resin, polyester, photoresist, polyacrylate, polyamide, silicone, etc.; or, elastic materials such as urethane, thermoplastic polyurethane (TPU), etc.

[0150] For the above Example 1, in related products (such as Figure 1Based on the above, only the mask plate of the first conductive layer 01 needs to be changed, so that the first test line 2 and the first common lead 101 are connected as a whole, and the connection between the first test line 2 and the second pad 52 is interrupted. Therefore, the provision of the electrostatic discharge structure 6 of the present disclosure does not affect the entire manufacturing process. Only the mask plate of the first conductive layer 01 needs to be changed, and the impact on the product manufacturing stage is relatively low.

[0151] For example 2 above, in related products (such as Figure 1 Based on the above, it is necessary to change a mask plate of the first conductive layer 01 and a mask plate of the third conductive layer 03. Changing the mask plate of the first conductive layer 01 interrupts the connection between the first test line 2 and the second pad 52; changing the mask plate of the second conductive layer 02 allows the first test line 2 to be connected to the first common lead 101 via the first cross-layer adapter line 111. Therefore, the configuration of the electrostatic discharge structure 6 disclosed in the present invention does not affect the entire manufacturing process. Only some mask plates need to be changed, which has a relatively low impact on the product preparation stage.

[0152] Figure 8 This is a schematic diagram of an array substrate according to Example 3 of an embodiment of the present disclosure. Figure 9 for Figure 8 In some embodiments, as shown in FIG. Figure 8 and Figure 9 As shown, the array substrate further includes at least one redundant pad 56 located in the second sub-binding area BB2, and a second transfer line 112 located in the routing area BB3 and corresponding one-to-one with each redundant pad 56. The first test line 2 includes a first test sub-segment 21 located in the first sub-binding area BB1 and a second test sub-segment 22 located in the routing area BB3. For any redundant pad 56, the first end of the redundant pad 56 is electrically connected to the second test sub-segment 22 via the corresponding second transfer line 112, and the second end of the redundant pad 56 is floating.

[0153] Alternatively, as Figure 9As shown, the first sub-binding region BB1 includes a plurality of them, and the plurality of first sub-binding regions BB1 are arranged side by side in the first direction X. The second sub-binding region BB2 includes a plurality of them, and the plurality of second sub-binding regions BB2 are arranged side by side with the first direction X, and the second sub-binding regions BB2 correspond to the first sub-binding regions BB1 one by one. The first test sub-segment 21 includes a plurality of them, and are respectively located in different first sub-binding regions BB1; the second test sub-segment 22 includes a plurality of them, and are respectively connected to both ends of the first test sub-segment 21. For any second test sub-segment 22, it is electrically connected to at least one second jumper wire 112, and releases static electricity through the redundant pad 56, so as to disperse the tip charges on a single fourth pad 54. During the test stage, the second end of the fourth pad 54 is floating, and the first end is electrically connected to the first test sub-segment 21; during the normal display stage, the fourth pad 54 is bonded to the flexible circuit board for providing a first reference voltage to the first test line 2.

[0154] Taking two first sub-binding regions BB1 as an example, the first test sub-segment 21 includes two; the second test sub-segment 22 includes three. Among them, the second test sub-segment 22 located at the end of the first test line 2 is electrically connected to a redundant pad 56 through a second jumper wire 112. The connection node of the second jumper wire 112 and the second test sub-segment 22 is the second connection node N2. Here, the redundant pad 56 connected to the second jumper wire 112 is the one closest to the second connection node N2. The closer to the second connection node N2, the shorter the second jumper wire 112 and the lower the ESD risk; at the same time, the redundant pad 56 is used to disperse the tip charges on a single fourth pad 54, further reducing the ESD risk. The second test sub-segment 22 located between two adjacent first test sub-segments 21 is electrically connected to two redundant pads 56 through two second jumper wires 112 respectively. One of the second jumper wires 112 is adjacent to a first sub-binding region BB1 at the second connection node N2 of the second test sub-segment 22 and is electrically connected to the closest redundant pad 56; the other second jumper wire 112 is adjacent to another first sub-binding region BB1 at the second connection node N2 of the second test sub-segment 22 and is electrically connected to the closest redundant pad 56.

[0155] Optionally, the binding region BB includes a first sub-binding region BB1 and a second sub-binding region BB2. The first test line 2 includes a first test sub-segment 21 located in the first sub-binding and a second test sub-segment 22 located in the second sub-binding region BB2. The second test sub-segment 22 includes two, and are respectively connected to both ends of the first test sub-segment 21. For any second test sub-segment 22, it is electrically connected to at least one second jumper wire 112, and releases static electricity through the closest redundant pad 56, so as to disperse the tip charges on a single fourth pad 54.

[0156] Figure 10Schematic diagram of film layer stacking of an array substrate according to Example 3 provided in an embodiment of the present disclosure. Figure 10 As shown, the array substrate includes a first conductive layer 01, a second conductive layer 02 and a third conductive layer 03 arranged in sequence along a direction away from the base substrate 1; wherein, the first test line 2, the second test line 7 and the control electrode G of the switching transistor 41 are located in the first conductive layer 01; the touch electrode line Tx, the touch lead 8, the first electrode S and the second electrode D of the switching transistor 41 are all located in the second conductive layer 02; the second adapter line 112 is located in the third conductive layer 03; the first test terminal 31 (not shown in the figure), the second test terminal 32, the fourth test terminal 34, the first solder pad 51, the second solder pad 52 (not shown in the figure), the third solder pad 53 (not shown in the figure) and at least part of the film layer of the redundant solder pad 56 is located in the third conductive layer 03.

[0157] It should be noted that Figure 10 The film layer stacking structure shown only represents the stacking relationship of each film layer, and does not represent the actual position and size.

[0158] Exemplarily, the redundant pad 56 includes a multi-layer connection structure, in which the discharge end is located on the top layer, that is, the third conductive layer 03. The discharge end of the redundant pad 56 located on the third conductive layer 03 can be transferred through the seventh overlapping portion (not shown in the figure) located on the second conductive layer 02, and then electrically connected to the second transfer line 112 located on the first conductive layer 01. The fourth test terminal 34 includes a multi-layer connection structure, in which the connection end is located on the top layer, that is, the third conductive layer 03. The connection end of the fourth test terminal 34 located on the third conductive layer 03 can be transferred through the eighth overlapping portion (not shown in the figure) located on the second conductive layer 02, and then electrically connected to the first common lead 101 located on the first conductive layer 01.

[0159] Figure 11 A schematic diagram of the connection relationship between the redundant pad and the second adapter provided in an embodiment of the present disclosure, such as Figure 11 As shown, the first test line 2 is a long trace; the second transfer line 112 includes a first transfer sub-segment 1121 and a second transfer sub-segment 1122 connected to the first transfer sub-segment 1121. The first transfer sub-segment 1121 is located on the third conductive layer 03, and the second transfer sub-segment 1122 is located on the first conductive layer 01. The first test line 2 (the second test sub-segment 22) and the second transfer sub-segment 1122 are on the same layer, but are spaced apart. The second test sub-segment 22 and the second transfer sub-segment 1122 are transferred across layers through the first transfer sub-segment 1121. Figure 10 and Figure 11As shown, the second test sub-segment 22 is electrically connected to the first transfer sub-segment 1121 through the eighth via V8 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the flat layer PLN and the second passivation layer PVX2; the first transfer sub-segment 1121 is electrically connected to the second transfer sub-segment 1122 through the ninth via V9 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the flat layer PLN and the second passivation layer PVX2; the second transfer sub-segment 1122 is electrically connected to the redundant pad 56 through the tenth via V10 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the flat layer PLN and the second passivation layer PVX2.

[0160] In this embodiment, the second transfer sub-segment 1122 and the first test line 2 on the same layer are disconnected and are bridged by the first transfer sub-segment 1121 on a different layer to avoid ESD of long traces on the same layer. Especially in the product preparation stage, the second transfer sub-segment 1122 and the first test line 2 in the first conductive layer 01 are disconnected, which can reduce the ESD risk before the third conductive layer 03 is formed.

[0161] like Figure 8 As shown, the array substrate includes a common electrode bus 9 located in the peripheral area CC and surrounding the display area AA, a first common lead 101 extending from the peripheral area CC to the routing area BB3, and a fourth test terminal 34 located in the routing area BB3. The common electrode bus 9 includes two first sub-segments 91 extending in a first direction X and arranged opposite each other, and two second sub-segments 92 extending in a second direction Y and arranged opposite each other. The first sub-segments 91 and the second sub-segments 92 are connected end to end. The two ends of a first sub-segment 91 near the first sub-binding area BB1 are electrically connected to the first ends of the two first common leads 101, respectively. The second end of the first common lead 101 is electrically connected to the fourth test terminal 34. The fourth test terminal 34 is configured to provide a common voltage, such as -3V, to the common electrode bus 9 via an external power supply during the test phase. The array substrate also includes a second common lead 102 and a common pad 50 corresponding to the second common lead 102. The second common lead 102 passes through the fan-out area DD, with one end extending to the peripheral area CC and electrically connected to the common electrode bus 9, and the other end extending to the first sub-bonding area BB1 and electrically connected to the common pad 50. The common pad 50 is configured to bond the driver chip during the normal display phase and provide a common voltage, such as -3V, to the common electrode bus 9 through the common pad 50.

[0162] like Figure 10 As shown, the common electrode bus 9, the first common lead 101 and the second common lead 102 are all located on the first conductive layer 01; the fourth test terminal 34 and the common pad 50 are located on the third conductive layer 03. The common electrode bus 9, the first common lead 101 and the second common lead 102 are connected as an integrated structure.

[0163] Figure 12 Schematic diagram of the connection relationship between the third jumper wire 113 and the fourth jumper wire 114 provided in the embodiments of the present disclosure. As Figure 8 and Figure 12 shown, the array substrate further includes a fourth pad 54 located in the second sub-bonding region BB2, a fifth pad 55 located in the first sub-bonding region BB1, a third jumper wire 113 located in the routing region BB3, and a fourth jumper wire 114 located in the first sub-bonding region BB1. The fifth pad 55 and the second pad 52 are arranged side by side along the second direction Y. The fourth pad 54 is configured to be bonded and connected to the flexible circuit board. The fourth pad 54 is electrically connected to the fifth pad 55 through the third jumper wire 113, and the fifth pad 55 is electrically connected to the first test sub-segment 21 through the fourth jumper wire 114.

[0164] As Figure 10 and Figure 12 shown, the fourth jumper wire 114 is located in the third conductive layer 03. The third jumper wire 113 is located in the first conductive layer 01 or the second conductive layer 02; at least part of the film layers of the fourth pad 54 and the fifth pad 55 are located in the third conductive layer 03. Among them, the bonding ends of the fourth pad 54 and the fifth pad 55 are both located in the third conductive layer 03.

[0165] Optionally, as Figure 10 and Figure 12 shown, the third jumper wire 113 includes a double-layer metal trace arranged in a stacked manner, which are respectively located in the first conductive layer 01 and the second conductive layer 02.

[0166] Figure 13a Schematic diagram of the array substrate under Example 4 provided in the embodiments of the present disclosure, Figure 13b Schematic diagram of the array substrate under Example 5 provided in the embodiments of the present disclosure. In some embodiments, as Figure 13a shown, the electrostatic discharge structure 6 includes at least one redundant pad 56 located in the first sub-bonding region BB1, and a second jumper wire 112 located in the first sub-bonding region BB1 and corresponding to the redundant pad 56 one by one. The first test line 2 includes a first test sub-segment 21 located in the first sub-bonding region BB1 and a second test sub-segment 22 located in the routing region BB3; for any redundant pad 56, the first end of the redundant pad 56 is electrically connected to the second test sub-segment 22 through the corresponding second jumper wire 112, and the second end of the redundant pad 56 is floating.

[0167] The difference between Example 4 and Example 5 compared with Example 3 is that: by providing redundant pads 56 in the first sub-bonding region BB1, the tip charges of a single fourth pad 54 are dispersed, thereby reducing the ESD risk.

[0168] Optionally, as Figure 13aAs shown, the redundant pad 56 and the first pad 51 are arranged side by side along the first direction X. The redundant pad 56 is closer to the edge of the first sub-bonding area BB1 than the first pad 51 arranged side by side. For example, it is closer to the first edge of the first sub-bonding area BB1 opposite to each other along the first direction X.

[0169] Optionally, as Figure 13b shown, the redundant pad 56 and the second pad 52 are arranged side by side along the first direction X. The redundant pad 56 is closer to the edge of the first sub-bonding area BB1 than the second pad 52 arranged side by side. For example, it is closer to the first edge of the first sub-bonding area BB1 opposite to each other along the first direction X.

[0170] Optionally, the redundant pad 56 is closer to the first edge than the common pad 50.

[0171] It should be noted that for the other film layer structures in Example 4 and Example 5, reference can be made to the description in Example 3, and the repeated parts will not be elaborated.

[0172] Figure 14 Schematic diagram of the array substrate under Example 6 provided by the present disclosure. In some embodiments, as Figure 14 shown, the electrostatic discharge structure 6 includes a plurality of protrusions 13 located in the first sub-bonding area BB1. The plurality of protrusions 13 are connected to the side of the first test line 2 far away from the switching transistor 41. Optionally, the protrusion 13 and the first test line 2 are connected as an integral structure and protrude along the side far away from the switching transistor 41. The protrusion 13 is located in the first conductive layer 01.

[0173] Optionally, as Figure 14 shown, in addition to the two ends, the first test line 2 further includes a first connection node located in the middle area and electrically connected to the second pole D of the switching transistor 41; along the extending direction of the first test line 2, protrusions 13 are arranged between adjacent first connection nodes. The protrusions 13 are distributed on the first test line 2 to disperse the charges on the first test line 2, thereby reducing the ESD risk.

[0174] Optionally, the electrostatic discharge structure 6 further includes a plurality of protrusions 13 located in the routing area BB3. The plurality of protrusions 13 are connected to the side of the first test line 2 far away from the switching transistor 41.

[0175] It should be noted that for the other film layer structures in Example 6, reference can be made to the description in Example 3, and the repeated parts will not be elaborated.

[0176] Figure 15 Schematic diagram of the array substrate under Example 7 provided by the present disclosure. In some embodiments, as Figure 15As shown, the electrostatic discharge structure 6 is located in the wiring area BB3. One end of the electrostatic discharge structure 6 is electrically connected to the first test line 2, and the other end extends to the edge of the wiring area BB3 for discharging static electricity to the periphery of the array substrate.

[0177] In some embodiments, as Figure 15 shown, the array substrate further includes a cutting area EE located in the peripheral area CC away from the display area AA, and an outer peripheral area FF located away from the peripheral area CC in the cutting area EE; the electrostatic discharge structure 6 is located in the outer peripheral area FF and extends along the second direction Y; the array substrate further includes a conductive line 60 located in the outer peripheral area FF and extending along the second direction Y and a fifth transfer line 115 located in the cutting area EE; the electrostatic discharge structure 6 is located in the wiring area BB3, one end is electrically connected to the first test line 2, and the other end extends to the edge of the wiring area BB3 and is connected to one end of the fifth transfer line 115, and the other end of the fifth transfer line 115 is electrically connected to the middle area of the conductive line 60.

[0178] The conductive line 60 is a wide wiring line that extends from the DPO side of the array substrate to the DP side. In this embodiment, through the electrostatic discharge structure 6 and the fifth transfer line 115, the static electricity on the first test line 2 located in the bonding area BB is introduced onto the conductive line 60 located in the outer peripheral area FF to disperse the charge, thereby reducing the risk of ESD occurring in many process stages such as cutting, bonding, and transportation of the product.

[0179] Optionally, the line width of the conductive line 60 is greater than the line width of the first test line 2; and / or, the line width of the electrostatic discharge structure 6 is greater than the line width of the first test line 2, which is convenient for discharging static electricity.

[0180] Optionally, both ends of the conductive line 60 are floating.

[0181] Optionally, the electrostatic discharge structure 6 and the fifth transfer line 115 are connected as an integral structure.

[0182] It should be noted that since the array factory needs to perform product functional inspection and screening on the full-process array substrate, it is necessary to set wiring (hereinafter referred to as the peripheral AT wiring) for transmitting array detection signals on the array substrate to confirm whether the array substrate can work properly. It should be emphasized that in the prior art, the peripheral AT wiring itself serves as a test line and is electrically connected to the structure to be tested, rather than being connected to the first test line 2 in the present disclosure. And the present disclosure multiplexes the peripheral AT wiring as the electrostatic discharge structure 6 electrically connected to the first test line 2. While discharging the static electricity on the long wiring (the first test line 2), it does not affect the entire manufacturing process. Only the mask plate of the third conductive layer 03 needs to be changed, and the impact on the product manufacturing stage is relatively low.

[0183] Optionally, one end of the peripheral AT trace is electrically connected to the fifth test terminal 35, and the other end is floating.

[0184] It should be noted that before leaving the factory, the structure of the peripheral region FF of the array substrate of the present disclosure can be bent to the backlight side or used as the border of the display device. Alternatively, the array substrate can also be cut, and the structure located in the peripheral region FF can be cut off along the cutting region EE.

[0185] Figure 16 It is a schematic diagram of the film stack of the array substrate under Example 7 provided by the present disclosure. In some embodiments, as Figure 16 shown, the array substrate includes a first conductive layer 01, a second conductive layer 02, and a third conductive layer 03 sequentially arranged in a direction away from the substrate 1; the first test line 2, the second test line 7, the common electrode bus 9, the first common lead 101, the second common lead 102, the conductive line 60, and the control electrode G of the switching transistor 41 are all located in the first conductive layer 01; the touch electrode line Tx, the touch lead 8, the third jumper line 113, the first pole S and the second pole D of the switching transistor 41 are all located in the second conductive layer 02; the fourth jumper line 114, the fifth jumper line 115, and the electrostatic discharge structure 6 are all located in the third conductive layer 03; at least part of the film layers of the first test terminal 31, the second test terminal 32, the fourth test terminal 34, the common pad 50, the first pad 51, the second pad 52 (not shown in the figure), the third pad 53 (not shown in the figure), the fourth pad 54, and the fifth pad 55 are located in the third conductive layer 03.

[0186] Figure 17 It is a schematic diagram of the connection relationship between the peripheral AT trace and the fifth jumper line 115 provided by the embodiment of the present disclosure. As Figure 16 and Figure 17 shown, one end of the first test line 2 is electrically connected to the first test terminal 31 through a fifth via V5 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2; the first test terminal 31 and the fifth jumper line 115 are connected as an integral structure; the fifth jumper line 115 passes through the cutting region EE from the trace region BB3 and extends to the peripheral region FF, and is electrically connected to the peripheral AT trace (electrostatic discharge structure 6) through an eleventh via V11 that sequentially penetrates the gate insulating line GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2.

[0187] In this embodiment, the fifth jumper line 115 is used to bridge the first test line 2 and the peripheral AT trace, preventing the first test line 2 and / or the peripheral AT trace from extending into the cutting region EE and being corroded.

[0188] In some embodiments, for Examples 3 to 7 above, the array substrate further includes a driving chip and a common pad 50 located in the first sub-bonding region BB1; the common pad 50, the plurality of first pads 51, and the plurality of second pads 52 are respectively bonded and connected to the driving chip; the common pad 50 and the first pad 51 are arranged side by side in the first direction X, and are located on one side of the first pad 51 close to the edge of the first sub-bonding region BB1.

[0189] As Figure 8 , Figure 13a , Figure 13b , Figure 14 or Figure 15 shown, in the normal display stage, the switching transistor 41 is turned off, and the driving chip provides a second operating voltage to the touch electrode line Tx through the first pad 51, and provides a first reference voltage to the common electrode bus 9 through the common pad 50, so as to load the first reference voltage on the first test line 2.

[0190] Optionally, the second operating voltage and the first reference voltage are the same and are both common voltages, such as -3V.

[0191] In some embodiments, the array substrate further includes a flexible circuit board located in the second sub-bonding region BB2. The fourth pad 54 is bonded and connected to the flexible circuit board, the fourth pad 54 is electrically connected to the fifth pad 55 through a third jumper wire 113, and the fifth pad 55 is electrically connected to the first test sub-segment 21 through a fourth jumper wire 114.

[0192] As Figure 8 , Figure 13a , Figure 13b , Figure 14 or Figure 15 shown, in the normal display stage, the switching transistor 41 is turned off, and the flexible circuit board provides a first reference voltage to the first test line 2 through the fourth pad 54 and the fifth pad 55.

[0193] Optionally, the second operating voltage and the first reference voltage are the same and are both common voltages, such as -3V. In this way, there is no voltage difference between the source and the drain during the off stage of the switching transistor 41, reducing the touch noise, thereby improving the stability of the common signal of the touch electrode line Tx and facilitating the identification of the user's true touch position.

[0194] Figure 18 This is a wiring schematic diagram of the second test line provided by the embodiments of the present disclosure. Optionally, as Figure 18 shown, the array substrate further includes a sixth jumper wire 116 located in the routing area BB3 and a sixth pad 57 located in the second sub-bonding region BB2; the second test line 7 is electrically connected to the sixth pad 57 through the sixth jumper wire 116. The sixth pad 57 is configured to be bonded and connected to the flexible circuit board.

[0195] During the normal display stage, the flexible circuit board provides a low-level signal to the second test line 7 through the sixth pad 57 to control the switching transistor 41 to be cut off; at the same time, the flexible circuit board provides a first reference voltage to the first test line 2 through the fourth pad 54 and the fifth pad 55.

[0196] Figure 19 Schematic diagram of the connection relationship between the sixth pad and the sixth jumper wire provided by the embodiment of the present disclosure. Optionally, the sixth jumper wire 116 includes a third jumper sub-segment 1161 and a fourth jumper sub-segment 1162 electrically connected to the third jumper sub-segment 1161; the third jumper sub-segment 1161 is located in the third conductive layer 03, and the fourth jumper sub-segment 1162 is located in the first conductive layer 01. The second test line 7 and the fourth jumper sub-segment 1162 are on the same layer but are spaced apart. The second test line 7 and the fourth jumper sub-segment 1162 are transferred through the third jumper sub-segment 1161 to avoid the ESD of the long trace (the second test line 7) on the same layer. Especially during the product preparation stage, the fourth jumper sub-segment 1162 and the second test line 7 in the first conductive layer 01 are disconnected, which can reduce the ESD risk before the formation of the third conductive layer 03.

[0197] In some embodiments, for the above Examples 3 to 7, the array substrate further includes a flexible circuit board located in the second sub-bonding area BB2. The flexible circuit board is bonded to the fourth pad 54, and the fourth pad 54 is electrically connected to the first test sub-segment 21 through the third jumper wire 113. During the normal display stage, the switching transistor 41 is cut off, and the flexible circuit board provides a first reference voltage to the first test line 2 through the fourth pad 54 to load the first reference voltage for the first test line 2.

[0198] Taking Example 3 as an example, optionally, the fourth pad 54 can be a redundant pad 56 located in the second sub-bonding area BB2. Optionally, the fourth pad 54 is different from the redundant pad 56. The fourth pad 54 is located in the middle area of the second sub-bonding area BB2 and is adjacent to the third pad 53.

[0199] Figure 20 Schematic diagram of the electrical connection relationship of a fourth pad 54 provided by the embodiment of the present disclosure, as Figure 20 shown, a redundant pad 56 located in the second sub-bonding area BB2 is reused as the fourth pad 54, which is used to disperse charges during the test stage and is bonded and connected to the flexible circuit board during the normal display stage to provide a first reference voltage to the first test line 2.

[0200] Figure 21 Schematic diagram of another electrical connection relationship of a fourth pad 54 provided by the embodiment of the present disclosure, as Figure 21As shown, the fourth pad 54 is different from the redundant pad 56; in the normal display stage, the fourth pad 54 is bound and connected to the flexible circuit board for providing a first reference voltage to the first test line 2. In the test stage, the first end of the fourth pad 54 is electrically connected to the first test line 2, and the second end is floating.

[0201] Similarly, the structural relationship between the flexible circuit board and the fourth pad 54 in this embodiment is also applicable to Examples 4 to 7, and the repeated parts will not be described again.

[0202] The embodiment of the present disclosure also provides a display device, which includes the array substrate in any one of the above embodiments. The display device can be, for example, any product with a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, etc. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be described here, nor should it be regarded as a limitation to the present disclosure.

[0203] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. An array substrate, characterized in that, It has a display area and a bonding area located on one side of the display area; the bonding area includes a first sub-bonding area, a second sub-bonding area located on the side of the first sub-bonding area away from the display area, and a wiring area surrounding the first sub-bonding area and the second sub-bonding area; The array substrate includes a substrate, pixel units disposed on the substrate, a first test line, a first test terminal, a strobe circuit, a plurality of first pads arranged side by side in a first direction, a plurality of second pads arranged side by side in the first direction, a plurality of third pads arranged side by side in the first direction, and an electrostatic discharge structure; the pixel units are located in the display area; The first pads, the strobe circuit, and the second pads are all located in the first sub-bonding area, and the first pads are closer to the display area than the second pads, and the strobe circuit is disposed between the first pads and the second pads; the third pads are located in the second sub-bonding area; The first pads and the second pads are both configured to be bonded and connected to a driving chip; the third pads are configured to be bonded and connected to a flexible circuit board; The first test terminal is located in the wiring area; both ends of the first test line pass through the first sub-bonding area and extend to the wiring area, and are electrically connected to the first test terminal; At least one end of the first test line is electrically connected to the electrostatic discharge structure.

2. The array substrate according to claim 1, wherein The array substrate further includes a peripheral area surrounding the display area, and a fan-out area disposed between the peripheral area and the bonding area; The array substrate further includes a second test terminal, a second test line, a plurality of touch electrode lines extending in a second direction, and a touch lead electrically connected to the touch electrode lines; the second test terminal is located in the wiring area; both ends of the second test line pass through the first sub-bonding area and extend to the wiring area; both ends of the touch electrode lines pass through the display area and extend to the peripheral area, the touch lead passes through the fan-out area, one end of which extends to the peripheral area and is electrically connected to the touch electrode lines, and the other end extends to the first sub-bonding area and is electrically connected to the first pads; the second direction intersects with the first direction; The strobe circuit includes switching transistors corresponding one by one to the touch leads; a first pole of the switching transistor is electrically connected to the first pad connected to the corresponding touch lead, a second pole is electrically connected to the first test line, and a control pole is electrically connected to the second test line.

3. The array substrate according to claim 2, wherein The array substrate includes a common electrode bus located in the peripheral area and surrounding the display area, and a first common lead extending from the peripheral area to the wiring area; the common electrode bus includes two first sub-segments extending in the first direction and oppositely arranged, and two second sub-segments extending in the second direction and oppositely arranged; the first sub-segments and the second sub-segments are connected end to end in sequence; Both ends of one of the first sub-segments close to the first sub-bonding area are respectively electrically connected to the first ends of two of the first common leads; the second ends of the first common leads are electrically connected to one end of the first test line; The first common lead, the first sub-segment, and the second sub-segment are multiplexed as at least a part of the electrostatic discharge structure.

4. The array substrate according to claim 3, wherein, The first common lead and the first test line are disposed on the same layer and connected as an integral structure.

5. The array substrate according to claim 3 or 4, characterized in that, For at least one of the first common leads, the second end of the first common lead and one end of the first test line are both electrically connected to the same first test terminal.

6. The array substrate according to claim 3, wherein The array substrate further includes a first jumper wire located in the routing area; The first common lead and the first test line are on the same layer and spaced apart; The first test line and the first jumper wire are on different layers; the first test line is electrically connected to the first common lead through the first jumper wire; The first jumper wire is multiplexed as another part of the electrostatic discharge structure.

7. The array substrate according to claim 6, wherein The array substrate further includes a third test terminal located in the routing area; For at least one of the first common leads, the second end of the first common lead and the first end of the first jumper wire are both electrically connected to the same third test terminal, and the second end of the first jumper wire and one end of the first test line are both electrically connected to the same first test terminal.

8. The array substrate according to claim 4 or 6, wherein The array substrate further includes a driving chip and a common pad located in the first sub-bonding area; The common pad, a plurality of first pads, and a plurality of second pads are respectively bonded and connected to the driving chip; the common pad and the first pads are arranged side by side along the first direction; The first test line and the second pads are spaced apart; in the normal display stage, the switching transistor is turned off, and the driving chip provides a second operating voltage to the touch electrode line through the first pads and provides a first reference voltage to the common electrode bus through the common pad to load the first reference voltage to the first test line.

9. The array substrate according to claim 8, wherein The second operating voltage and the first reference voltage are the same.

10. The array substrate according to claim 4 or 6, characterized in that The array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged in a direction away from the substrate; The first test line, the second test line, the common electrode bus, the first common lead, and the control electrode of the switching transistor are all located in the first conductive layer; The touch electrode line, the touch lead, the first and second electrodes of the switching transistor are all located in the second conductive layer; The first jumper wire is located in the third conductive layer; at least part of the film layers of the first test terminal, the second test terminal, the third test terminal, the first pad, the second pad, the third pad, and the common pad are located in the third conductive layer.

11. The array substrate according to claim 2, wherein, The electrostatic discharge structure includes at least one redundant pad located in the second sub-bonding area and a second jumper wire located in the routing area and corresponding to the redundant pad one by one; The first test line includes a first test sub-segment located in the first sub-bonding area and a second test sub-segment located in the routing area; For any one of the redundant pads, the first end of the redundant pad is electrically connected to the second test sub-segment through the corresponding second jumper wire, and the second end of the redundant pad is floating.

12. The array substrate according to claim 2, wherein The electrostatic discharge structure includes at least one redundant pad located in the first sub-bonding area, and a second jumper wire located in the first sub-bonding area and corresponding to the redundant pad one by one; The first test line includes a first test sub-segment located in the first sub-bonding area and a second test sub-segment located in the wiring area; For any one of the redundant pads, the first end of the redundant pad is electrically connected to the second test sub-segment through the corresponding second jumper wire, and the second end of the redundant pad is floating.

13. The array substrate according to claim 11 or 12, characterized in that, The array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged in a direction away from the substrate; The first test line, the second test line, and the control electrode of the switching transistor are located in the first conductive layer; The touch electrode line, the touch lead, the first and second poles of the switching transistor are all located in the second conductive layer; The second jumper wire is located in the third conductive layer; at least part of the film layers of the first test terminal, the second test terminal, the first pad, the second pad, the third pad, and the redundant pad are located in the third conductive layer.

14. The array substrate according to claim 2, wherein The electrostatic discharge structure includes a plurality of protrusions located in the first sub-bonding area. The protrusions are connected to the first test line as an integral structure and protrude along a side away from the switching transistor.

15. The array substrate according to claim 14, wherein In addition to the two ends, the first test line further includes a first connection node located in the middle area and electrically connected to the second pole of the switching transistor; The protrusions are arranged between adjacent first connection nodes in the extending direction of the first test line.

16. The array substrate according to claim 2, wherein The electrostatic discharge structure is located in the wiring area. One end of the electrostatic discharge structure is electrically connected to the first test line, and the other end extends to the edge of the wiring area.

17. The array substrate according to claim 16, wherein The array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged in a direction away from the substrate; The first test line, the second test line, and the control electrode of the switching transistor are all located in the first conductive layer; The touch electrode line, the touch lead, the first and second poles of the switching transistor are all located in the second conductive layer; The electrostatic discharge structure is located in the third conductive layer; at least part of the film layers of the first test terminal, the second test terminal, the first pad, the second pad, and the third pad are all located in the third conductive layer.

18. The array substrate according to claim 16 or 17, characterized in that, The line width of the electrostatic discharge structure is greater than the line width of the first test line.

19. The array substrate according to claim 11, 12, 14 or 16, characterized in that, The array substrate further includes a flexible circuit board and a fourth pad located in the second sub-bonding area, and a third jumper wire located in the wiring area; The fourth pad is bound to the flexible circuit board, and the fourth pad is electrically connected to the part of the first test line located in the first sub-bonding area through the third jumper wire; In the normal display stage, the switching transistor is turned off, and the flexible circuit board provides a first reference voltage to the first test line through the fourth pad to load the first reference voltage for the first test line.

20. The array substrate according to claim 11, 12, 14 or 16, characterized in that, The array substrate further includes a driving chip located in the first sub-bonding area; A plurality of first pads and a plurality of second pads are respectively bonded and connected to the driving chip; In the normal display stage, the switching transistor is turned off, and the driving chip provides a second operating voltage to the touch electrode line through the first pad.

21. The array substrate according to claim 20, wherein The array substrate further includes a flexible circuit board and a fourth pad located in the second sub-bonding area, a fifth pad located in the first sub-bonding area, a third jumper wire located in the routing area, and a fourth jumper wire located in the first sub-bonding area; the fifth pad and the second pad are arranged side by side along the second direction; The fourth pad is bonded and connected to the flexible circuit board, the fourth pad is electrically connected to the fifth pad through the third jumper wire, and the fifth pad is electrically connected to the portion of the first test line located in the first sub-bonding area through the fourth jumper wire; In the normal display stage, the switching transistor is turned off, and the flexible circuit board provides a first reference voltage to the first test line through the fourth pad and the fifth pad.

22. The array substrate according to claim 21, wherein The array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged in a direction away from the substrate; The first test line, the second test line, the third jumper wire, and the control electrode of the switching transistor are all located in the first conductive layer; The touch electrode line, the touch lead, the first and second electrodes of the switching transistor are all located in the second conductive layer; The fourth jumper wire is located in the third conductive layer; at least part of the film layers of the first pad, the second pad, the third pad, the fourth pad, and the fifth pad are located in the third conductive layer.

23. The array substrate according to claim 22, wherein The second operating voltage is the same as the first reference voltage.

24. A display device, characterized in that, Comprising the array substrate according to any one of claims 1 to 23.

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