Matrix lock control circuit supporting lock double-end control

Abstract

The utility model discloses a matrix lock control circuit supporting lock double-end control in the technical field of electromagnetic locks, which comprises lock interface circuits, a CPU (central processing unit) main control circuit and an MOS (metal oxide semiconductor) control circuit electrically connected between the lock interface circuits and the CPU main control circuit, the MOS control circuit comprises PMOS (P-channel metal oxide semiconductor) tubes and NMOS (N-channel metal oxide semiconductor) tubes, one PMOS tube is connected to lock control positive electrodes of a plurality of lock interface circuits, and the other PMOS tube is connected to lock control positive electrodes of the CPU main control circuit. One NMOS tube is multiplexed on lock control negative electrodes of a plurality of lock interface circuits, a PMOS is used for controlling an electromagnetic lock positive electrode, an NMOS is used for controlling an electromagnetic lock negative electrode, multiplexing control of a plurality of electromagnetic locks is achieved, and the functions that double-end control of the electromagnetic locks is considered at the same time and only a small number of IO ports are consumed are achieved. Compared with single-end control, double-end control has the advantages of being good in stability, smaller in turn-off current and higher in fault resistance rate.

Description

Technical Field

[0001] The utility model relates to the technical field of electromagnetic locks, in particular to a matrix lock control circuit supporting double-end control of the lock. Background Art

[0002] Electromagnetic locks are intelligent locks that can be unlocked by controlling a switching circuit. Electromagnetic locks are generally inductive loads, and their opening is controlled by briefly energizing the control coil.

[0003] For the on / off control of electromagnetic locks, the existing technology mainly adopts independent control of IO ports, where one IO port controls one lock. If multiple electromagnetic locks are controlled, too many IO ports need to be occupied, resulting in low fault resistance rate and uneven distribution of the off current due to the quality of the MOS tube. Utility Model Content

[0004] The purpose of this section is to summarize some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and in the abstract and title of the present invention to avoid obscuring the purpose of this section, the abstract and the title of the utility model, and such simplifications or omissions shall not be used to limit the scope of the present invention.

[0005] Therefore, the purpose of this utility model is to provide a matrix lock control circuit that supports dual-end lock control. This circuit uses PMOS transistors to control the positive pole of the electromagnetic lock and NMOS transistors to control the negative pole of the electromagnetic lock, enabling multiplexed control of multiple electromagnetic locks. This allows for dual-end control of the electromagnetic locks while consuming only a small number of I / O ports. Compared to single-end control, dual-end control offers advantages in stability, lower shutdown current, and higher fault immunity.

[0006] To solve the above technical problems, the present invention provides a matrix lock control circuit supporting double-end lock control, which adopts the following technical solution: it includes a lock interface circuit, a CPU main control circuit, and a MOS control circuit electrically connected between the lock interface circuit and the CPU main control circuit. The MOS control circuit includes a PMOS transistor and an NMOS transistor. One of the PMOS transistors is connected to the lock control positive electrodes of multiple lock interface circuits, and one of the NMOS transistors is reused on the lock control negative electrodes of multiple lock interface circuits.

[0007] Optionally, one of the PMOS tubes is connected to the lock control positive electrodes of four lock interface circuits, and one of the NMOS tubes is multiplexed on the lock control negative electrodes of four lock interface circuits.

[0008] Optionally, the lock interface circuit includes an interface CN1, pin 1 of the interface CN1 is grounded, pin 4 of the interface CN1 is connected to the positive electrode of LED1 and to the PMOS tube through the PMOS terminal, the negative electrode of LED1 is connected to the first end of the resistor R237, and the second end of the resistor R237 is connected to the NMOS tube through the NMOS terminal.

[0009] Optionally, pin 3 of the interface CN1 is connected to the anode of diode D49 and the anode of diode D18, pin 4 of the interface CN1 is connected to the cathode of diode D49, and the cathode of diode D18 is connected to an NMOS tube through an NMOS terminal.

[0010] Optionally, pin 5 of the NMOS tube is grounded, and pin 6 of the NMOS tube is multiplexed on the NMOS terminal of the lock interface circuit.

[0011] Optionally, pin 1 of the NMOS tube is connected to a first end of a resistor R186 , a second end of the resistor R186 is connected to a first end of a resistor R103 and a CPU main control circuit, and a second end of the resistor R103 is grounded.

[0012] Optionally, pin 2 of the PMOS tube is connected to a power supply, pin 3 of the PMOS tube is connected to the collector of the transistor Q8 and the first end of the resistor R51, the second end of the resistor R51 is connected to the power supply, and the emitter of the transistor Q8 is grounded; pin 4 of the PMOS tube is connected to the PMOS terminal of the lock interface circuit.

[0013] Optionally, the base of the transistor Q8 is connected to the first end of the resistor R195, the second end of the resistor R195 is connected to the first end of the resistor R199 and the CPU main control circuit, and the second end of the resistor R199 is grounded.

[0014] In summary, the present invention has at least one of the following beneficial effects:

[0015] This new design uses a PMOS transistor to control the positive pole of the electromagnetic lock and an NMOS transistor to control the negative pole, enabling multiplexed control of multiple electromagnetic locks. This allows for dual-ended control of the electromagnetic locks while consuming only a small number of IO ports. Compared to single-ended control, dual-ended (double-sided) control offers advantages in stability, lower shutdown current, and higher fault immunity. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 This is a schematic diagram of the circuit structure of the utility model;

[0018] Figure 2 This is a schematic diagram of the MOS control circuit of the utility model;

[0019] Figure 3 This is a schematic diagram of the lock interface circuit of the utility model. DETAILED DESCRIPTION

[0020] The following will combine the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all the embodiments. All other embodiments obtained by ordinary technicians in this field without making creative work based on the embodiments in the present invention fall within the scope of protection of the present invention.

[0021] In the description of this utility model, it should be noted that the terms "upper," "lower," "inner," "outer," "top / bottom," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this utility model and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "provided with," "mounted / connected," and "connected" should be understood in a broad sense. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be internal communication between two components. For those skilled in the art, the specific meanings of the above terms in this utility model can be understood according to the specific circumstances.

[0023] Example 1

[0024] Reference Figure 1The utility model discloses a matrix lock control circuit supporting double-end lock control, comprising a lock interface circuit, a CPU main control circuit, and a MOS control circuit electrically connected between the lock interface circuit and the CPU main control circuit.

[0025] Reference Figure 3 The lock interface circuit includes an interface CN1, which is used as an interface for the electromagnetic lock. Pin 1 of the interface CN1 is grounded, pin 4 of the interface CN1 is connected to the positive electrode of LED1 and to the PMOS tube through the PMOS terminal, the negative electrode of LED1 is connected to the first end of the resistor R237, and the second end of the resistor R237 is connected to the NMOS tube through the NMOS terminal. LED1 and R237 form an LED light circuit. When the PMOS tube and the NMOS tube are turned on, the electromagnetic lock will open and the LED light will light up.

[0026] Pin 3 of the interface CN1 is connected to the anode of the diode D49 and the anode of the diode D18, and pin 4 of the interface CN1 is connected to the cathode of the diode D49. The cathode of the diode D18 is connected to the NMOS tube through the NMOS terminal. D49 is used for freewheeling, and D18 is used to reduce the impact caused by the reuse of the NMOS tube.

[0027] Reference Figure 2 The MOS control circuit is actually a P and N MOS combination circuit, including a PMOS tube and an NMOS tube. The NMOS tube has pins 1, 5, and 6. Pin 5 of the NMOS tube is grounded, and pin 6 of the NMOS tube is multiplexed on the NMOS terminal of the lock interface circuit. Pin 1 of the NMOS tube is connected to the first end of resistor R186, and the second end of the resistor R186 is connected to the first end of resistor R103 and the CPU main control circuit. The second end of the resistor R103 is grounded. Resistor R186 has a current limiting function, and resistor R103 has a pull-down function to prevent the CPU main control circuit from being unlocked due to a slow power-on reaction time.

[0028] The PMOS transistor has pins 2, 3, and 4. Pin 2 of the PMOS transistor is connected to the power supply, and pin 3 of the PMOS transistor is connected to the collector of transistor Q8 and the first end of resistor R51. The second end of resistor R51 is connected to the power supply, and the emitter of transistor Q8 is grounded. Pin 4 of the PMOS transistor is connected to the PMOS terminal of the lock interface circuit. Due to the characteristics of the PMOS transistor, the CPU main control circuit cannot be completely shut down, so transistor Q8 is required to assist in shutting down. R51 is a pull-up resistor that prevents the MOS control circuit from conducting when powered on.

[0029] The base of the transistor Q8 is connected to the first end of the resistor R195, the second end of the resistor R195 is connected to the first end of the resistor R199 and the CPU main control circuit, the second end of the resistor R199 is grounded, the resistor R195 is used to limit the current of the transistor Q8, and the resistor R199 has a pull-down effect to prevent the CPU main control circuit from unlocking due to a slow power-on reaction time.

[0030] One PMOS transistor can be connected to the positive control terminals of four lock interface circuits, and one NMOS transistor can be reused at the negative control terminals of four lock interface circuits, thus achieving multiplexing. This can reduce the occupation of a large number of IO ports, reduce the lock shutdown current, and thus improve the quiescent current stability.

[0031] The above are all preferred embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. Therefore, any equivalent changes made based on the structure, shape, and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A matrix lock control circuit supporting double-end lock control, characterized by: It includes a lock interface circuit, a CPU main control circuit and a MOS control circuit electrically connected between the lock interface circuit and the CPU main control circuit. The MOS control circuit includes a PMOS tube and an NMOS tube, one PMOS tube is connected to the lock control positive poles of multiple lock interface circuits, and one NMOS tube is multiplexed on the lock control negative poles of multiple lock interface circuits.

2. The matrix lock control circuit supporting double-end lock control according to claim 1, characterized in that: One of the PMOS tubes is connected to the lock control positive electrodes of the four lock interface circuits, and one of the NMOS tubes is multiplexed on the lock control negative electrodes of the four lock interface circuits.

3. The matrix lock control circuit supporting double-end lock control according to claim 2, characterized in that: The lock interface circuit includes an interface CN1, pin 1 of the interface CN1 is grounded, pin 4 of the interface CN1 is connected to the positive electrode of LED1 and to the PMOS tube through the PMOS terminal, the negative electrode of LED1 is connected to the first end of the resistor R237, and the second end of the resistor R237 is connected to the NMOS tube through the NMOS terminal.

4. The matrix lock control circuit supporting double-end lock control according to claim 3, characterized in that: Pin 3 of the interface CN1 is connected to the anode of the diode D49 and the anode of the diode D18, and pin 4 of the interface CN1 is connected to the cathode of the diode D49. The cathode of the diode D18 is connected to the NMOS tube through the NMOS terminal.

5. The matrix lock control circuit supporting double-end lock control according to claim 3, characterized in that: Pin 5 of the NMOS tube is grounded, and pin 6 of the NMOS tube is multiplexed on the NMOS connection terminal of the lock interface circuit.

6. A matrix lock control circuit supporting double-end lock control according to any one of claims 1 to 5, characterized in that: Pin 1 of the NMOS tube is connected to a first end of a resistor R186 , a second end of the resistor R186 is connected to a first end of a resistor R103 and a CPU main control circuit, and a second end of the resistor R103 is grounded.

7. The matrix lock control circuit supporting double-end lock control according to claim 3, characterized in that: Pin 2 of the PMOS tube is connected to a power supply, pin 3 of the PMOS tube is connected to the collector of the transistor Q8 and the first end of the resistor R51, the second end of the resistor R51 is connected to the power supply, and the emitter of the transistor Q8 is grounded; pin 4 of the PMOS tube is connected to the PMOS terminal of the lock interface circuit.

8. The matrix lock control circuit supporting double-end lock control according to claim 7, characterized in that: The base of the transistor Q8 is connected to the first end of the resistor R195 , the second end of the resistor R195 is connected to the first end of the resistor R199 and the CPU main control circuit, and the second end of the resistor R199 is grounded.

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