FPGA plug-in multi-chip DDR4 architecture based on double-sided symmetric layout

Abstract

The utility model belongs to the field of radar processing module PCB design, and particularly relates to an FPGA plug-in multi-piece DDR4 architecture based on double-face symmetric layout, which comprises an FPGA chip, a substrate and a plurality of pieces of DDR4 chips, the FPGA chip is arranged in the center of the front face of the substrate, half of DDR4 chips are distributed on the periphery of the FPGA chip in a half-surrounding mode, the DDR4 chips on the front face of the substrate are divided into two equal groups, and the two groups of DDR4 chips are symmetrically arranged. The other half number of DDR4 chips are arranged on the back face of the substrate, and the DDR4 chips on the back face of the substrate and the DDR4 chips on the front face of the substrate are arranged in a mirror symmetry mode. The method and the device can be suitable for PCB design of multiple DDR4 chips, especially for a miniaturized large-capacity storage module with a high integration level, the design is optimized, the structural size limitation is met, the working efficiency of PCB design is improved, and the design and production cost of a printed board is reduced; and the module performance is further improved through rule optimization control.

Description

Technical Field

[0001] The present application relates to the field of radar processing module PCB design, and in particular to an FPGA external multi-chip DDR4 architecture based on a double-sided symmetrical layout. Background Art

[0002] As embedded systems become increasingly powerful and implement more functions, their operating frequencies are increasing. DDR operating frequencies have also gradually increased from 133MHz to 200MHz, enabling greater system bandwidth and better performance. However, higher operating frequencies also place greater demands on system stability, requiring hardware designers to exercise greater restraint and consideration in circuit layout and routing. The DDR circuit design is the most crucial component influencing the proper and stable operation of the entire system.

[0003] To meet the system's high-bandwidth and high-integration design requirements, the design uses a high-performance FPGA (V9) as its core and externally incorporates four 16GB DDR4 pre-processing modules. This provides the radar processor with a multifunctional, high-throughput, and highly reliable front-end pre-processing application platform. The module's dimensions are required to be 51cm*51cm. Traditional DDR layout and routing has the following drawbacks:

[0004] 1) DDR4 has two topologies: Fly-By, where all chips are placed on the same layer to ensure good signal integrity, but this takes up valuable board space and fails to meet module miniaturization requirements; Clamshell, where all chips can be placed on both the top and bottom layers, saving significant board space but hindering data communication.

[0005] 2) Each DDR group contains 64 data lines and 18 address lines. The number of wiring lines is huge and the rules are strict. Routing them sequentially will consume a lot of time and labor costs.

[0006] 3) The module design includes four groups of DDR to meet the needs of ultra-large capacity storage, but wiring differences will cause the signal consistency between each group of DDR to deteriorate, ultimately leading to reduced module performance.

[0007] DDR layout and routing methods need to be improved and perfected to meet new module design requirements. Summary of the Invention

[0008] In order to solve the above problems, the present application provides an FPGA external multi-chip DDR4 architecture based on a double-sided symmetrical layout, including: an FPGA chip, a substrate, and multiple DDR4 chips;

[0009] The FPGA chip is placed in the center of the front of the substrate, and half of the DDR4 chips are distributed around the FPGA chip. The DDR4 chips on the front of the substrate are divided into two equal groups, and the two groups of DDR4 chips are arranged symmetrically.

[0010] The other half of the DDR4 chips are arranged on the back of the substrate, and the DDR4 chips on the back of the substrate are arranged in a mirror-symmetrical manner with the DDR4 chips on the front.

[0011] Preferably, the number of the DDR4 chips is 32, with 16 chips on the front side and 16 chips on the back side of the substrate.

[0012] Preferably, each group of DDR4 chips adopts a FLY-BY topology.

[0013] Preferably, all DDR4 chips on the front side of the substrate are located in the same plane, and all DDR4 chips on the back side of the substrate are located in the same plane.

[0014] Preferably, all DDR4 chips on the front side of the substrate use three routing layers, and all DDR4 chips on the back side of the substrate use three routing layers.

[0015] Preferably, the routing of each group of DDR4 chips is the same.

[0016] Preferably, the fan-out vias of the DDR4 chip adopt a buried blind via process.

[0017] Preferably, the FPGA chip does not have other functional circuits arranged on one side of the DDR4 chip.

[0018] Preferably, the FPGA chip is arranged at a mirror image position on the reverse side of the substrate along with other components.

[0019] Advantages of this application include:

[0020] 1) Under the premise of ensuring the DDR4 topology, the use of positive and negative mounting not only ensures good signal integrity and improves module performance and reliability, but also saves a lot of space costs and meets the demand for module miniaturization;

[0021] 2) DDR4's layout is strictly symmetrical, so layout and routing do not have to be performed one by one. Just complete one group, and the remaining three groups can be completed in a horizontally symmetrical and mirror-symmetrical manner. This saves a lot of time and labor costs, improves work efficiency, and greatly reduces the need for later proofreading and review, reducing the probability of errors.

[0022] 3) The buried blind via process further optimizes the stack-up design, using the least number of layers to complete DDR4 routing. This not only saves production costs, but also better solves the problems of reference plane and signal interference, ensuring the reliability of signal transmission.

[0023] 4) The layout and routing of the four DDR4 groups can be completely consistent, greatly enhancing the signal consistency between the groups and further improving module performance.

[0024] This application can be applied to the PCB design of multiple DDR4 chips, especially small and large-capacity storage modules with high integration, to optimize the design, meet the structural size restrictions, improve the efficiency of PCB design, reduce the design and production costs of printed circuit boards, and further improve the module performance through rule optimization control. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the module's TOP layer DDR4 layout. The BOTTOM layer and TOP layer layouts maintain mirror symmetry, and wiring is also performed using a replicated mirror method.

[0026] Figure 2 This is a schematic diagram of the routing layer design. Taking the 20th layer as an example, the TOP layer and the BOTTOM layer are completed using 3 layers of routing respectively. DETAILED DESCRIPTION

[0027] To make the technical solution and its advantages of the present application clearer, the technical solution of the present application will be described in further detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of the present application and are only used to explain the present application, not to limit the present application. It should be noted that, for ease of description, only the parts related to the present application are shown in the accompanying drawings, and other related parts can refer to the general design. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other to obtain new embodiments.

[0028] This application provides an FPGA external multi-chip DDR4 architecture based on a double-sided symmetrical layout, including: an FPGA chip, a substrate, and multiple DDR4 chips;

[0029] The FPGA chip is placed in the center of the front of the substrate, and half of the DDR4 chips are distributed around the FPGA chip. The DDR4 chips on the front of the substrate are divided into two equal groups, and the two groups of DDR4 chips are arranged symmetrically.

[0030] The other half of the DDR4 chips are arranged on the back of the substrate, and the DDR4 chips on the back of the substrate are arranged in a mirror-symmetrical manner with the DDR4 chips on the front.

[0031] In some optional embodiments, the number of the DDR4 chips includes 32, with 16 chips on the front side and 16 chips on the back side of the substrate.

[0032] In some optional implementations, each group of DDR4 chips adopts a FLY-BY topology.

[0033] In some optional embodiments, all DDR4 chips on the front side of the substrate are located in the same plane, and all DDR4 chips on the back side of the substrate are located in the same plane.

[0034] In some optional embodiments, all DDR4 chips on the front side of the substrate use 3 routing layers, and all DDR4 chips on the back side of the substrate use 3 routing layers.

[0035] In some optional implementations, the routing of each group of DDR4 chips is the same.

[0036] In some optional implementations, the fan-out vias of the DDR4 chip adopt a buried blind via process.

[0037] In some optional implementations, the FPGA chip does not have other functional circuits arranged on one side of the DDR4 chip.

[0038] In some optional implementations, the FPGA chip and other components are arranged at mirror-image positions on the reverse side of the substrate.

[0039] The specific steps for setting up the game are as follows:

[0040] 1) Determine the number of stacked layers to ensure that each group of DDR4 has independent routing layers and complete reference planes. The reference for setting routing layers and reference planes is Figure 2 ;

[0041] 2) According to the results of the imported structure diagram, manually place the first set of DDR4 chips and termination resistors. Select FLY_BY for the topology structure and choose to place them on the TOP layer. The layout method is referenced Figure 1 Pay attention to the connection relationship with the FPGA and choose the most convenient way to adjust the wiring within the group;

[0042] 3) Determine the layout of the second group of DDR4 and termination resistors using a horizontally symmetrical method based on the layout results of the first group. After completion, perform fine-tuning within the group based on the actual routing relationship;

[0043] 4) The remaining two DDR4 groups are placed on the BOTTOM layer of the printed circuit board, maintaining a complete mirror image relationship with the TOP layer;

[0044] 5) Complete the layout of other devices and set constraint rules;

[0045] 6) Start TOP layer DDR4 wiring, fan-out vias use buried blind hole process, according to the specific wiring rules, complete the first group of wiring, routing layer reference Figure 2 ;

[0046] 7) Copy the first set of routing results to the second set of DDR4. Since the layout may be fine-tuned within the group, the routing also needs to be adjusted accordingly, but most of the routing can be completed by copying;

[0047] 8) After completing the TOP layer DDR4 wiring, perform a rule check first to confirm that all traces and vias are correctly copied, and use the mirror operation to complete the BOTTOM layer DDR4 wiring.

[0048] This completes the layout and routing of all 32 DDR4 chips. Subsequent verification and proofreading only requires checking the corresponding contents on the TOP layer. If corrections are required, only the two DDR4 groups on the TOP layer need to be modified, while the other two groups can still be modified using a mirrored method.

[0049] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout, It is characterized by: include: An FPGA chip, substrate, and multiple DDR4 chips; The FPGA chip is placed in the center of the front of the substrate, and half of the DDR4 chips are distributed around the FPGA chip. The DDR4 chips on the front of the substrate are divided into two equal groups, and the two groups of DDR4 chips are arranged symmetrically. The other half of the DDR4 chips are arranged on the back of the substrate, and the DDR4 chips on the back of the substrate are arranged in a mirror-symmetrical manner with the DDR4 chips on the front.

2. The FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout according to claim 1 is characterized in that: The number of DDR4 chips includes 32, with 16 chips on the front and 16 chips on the back of the substrate.

3. The FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout according to claim 1 is characterized in that: Each group of DDR4 chips adopts FLY-BY topology.

4. The FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout according to claim 1, characterized in that: All DDR4 chips on the front side of the substrate are located on the same plane, and all DDR4 chips on the back side of the substrate are located on the same plane.

5. The FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout according to claim 1 is characterized in that: All DDR4 chips on the front side of the substrate use 3 routing layers, and all DDR4 chips on the back side of the substrate use 3 routing layers.

6. The FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout according to claim 1, characterized in that: The routing of each set of DDR4 chips is the same.

7. The FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout according to claim 1, characterized in that: The fan-out vias of DDR4 chips use a buried blind via process.

8. The FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout according to claim 1, characterized in that: The FPGA chip does not have other functional circuits arranged on one side of the DDR4 chip.

9. The FPGA external multi-chip DDR4 architecture based on double-sided symmetrical layout according to claim 1, characterized in that: The FPGA chip and other components are arranged in a mirror image position on the reverse side of the substrate.

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