Analog signal sampling circuit and encoder chip
Through the signal segmented amplification and detection module, the angle accuracy of the encoder is improved, the problem of uneven angle calculation accuracy in the prior art is solved, and the design of the miniaturized encoder is realized.
Patent Information
- Application Number
- CN202422207645.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2034-09-09
AI Technical Summary
The existing sampling technology cannot guarantee the angular accuracy of the encoder, and there are large differences in the calculation accuracy of different angular positions.
The signal segment amplification module is used to amplify the original analog signal in segments, and the analog-digital conversion module is used to quickly judge the analog signal segment without changing the ADC resolution, which improves the voltage signal resolution and improves the angular accuracy of the encoder.
Without changing the ADC resolution, the angular accuracy of the encoder is improved, and the encoder circuit board area is reduced by integrating into the chip to achieve miniaturization of the encoder.
Smart Images
Figure CN223246572U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of electronic technology, in particular to an analog signal sampling circuit and an encoder chip. Background Art
[0002] The encoder position is calculated by collecting the analog signal output by the sensor to obtain the angle. When the encoder rotates at a constant speed, the analog signal is a standard sine waveform.
[0003] In the existing sampling technology, the analog signal output by the sensor is amplified to 0~VREF+ by an operational amplifier and then directly input to the ADC for sampling. Figure 1 As shown, taking a 0~3.3V sinusoidal signal and a 12-bit ADC resolution as an example, the voltage value corresponding to the 0° position is 1.65V, the voltage value corresponding to the 10° position is 2.48V, the voltage value corresponding to the 90° position is 3.2V, and the voltage value corresponding to the 100° position is 3.1V; VREF+ is equal to 3.3V, and one LSB of the 12-bit ADC represents 3.3 / 2^12≈0.0008V; the voltage difference between 0~10° is 0.83V, corresponding to the ADC The average accuracy of the sampled angle is 1 LSB, which means 10 / 1030≈0.0097°. The voltage difference between 90° and 100° is 0.1V, which corresponds to the ADC’s The average accuracy of the sampled angle is 1 LSB, which means 10 / 124≈0.0806°.
[0004] Therefore, the calculation accuracy of different angular positions is different. The smaller the slope of the sinusoidal signal is, the lower the angle accuracy obtained by sampling is. Utility Model Content
[0005] In view of the shortcomings of the existing technology, the purpose of the present invention is to provide an analog signal sampling circuit and an encoder chip to solve the problem that the existing sampling technology cannot guarantee the angular accuracy of the encoder and there are large differences in the calculation accuracy for different angular positions.
[0006] According to a first aspect of the present invention, an analog signal sampling circuit is provided, comprising:
[0007] A signal segmentation amplification module, the signal segmentation amplification module is used to segmentally amplify the received original analog signal to generate at least two amplified analog signals;
[0008] a signal segment detection module, the signal segment detection module being configured to detect the analog signal segment in which the received original analog signal is located and generate a detection result;
[0009] An analog-to-digital conversion module is connected to the signal segment amplification module and the signal segment detection module respectively, and is used to select one of the at least two amplified analog signals for analog-to-digital conversion to generate a digital signal based on the detection result.
[0010] The analog signal sampling circuit of the utility model uses a signal segmentation amplification module to segmentally amplify the original analog signal of the encoder according to the accuracy requirements. Without changing the ADC resolution, the voltage signal resolution is improved, thereby improving the angular accuracy of the encoder. The signal segment detection module quickly determines which analog signal segment the original analog signal is located in, ensuring that the ADC samples the amplified voltage value of the corresponding analog signal segment in real time.
[0011] In some embodiments, the signal segmentation amplification module includes:
[0012] At least two analog voltage subtractors, each configured to perform a voltage subtraction operation on the original analog signal and at least two reference signals in a one-to-one correspondence to generate at least two new analog signal segment signals;
[0013] At least two programmable gain amplifiers, at least two of the programmable gain amplifiers are connected to the at least two analog voltage subtractors in a one-to-one correspondence, and at least two of the programmable gain amplifiers are used to perform voltage amplification on at least two new analog signal segment signals to generate at least two amplified analog signals.
[0014] In some implementations, the analog voltage subtractor includes an operational amplifier.
[0015] In some embodiments, the signal segment detection module includes:
[0016] At least two comparators, the at least two comparators being respectively used to compare the original analog signal with at least two reference signals in a one-to-one correspondence to generate at least two comparison signals;
[0017] A judgment module is connected to at least two of the comparators respectively, and is used to judge the analog signal segment in which the original analog signal is located based on at least two comparison signals to generate the detection result.
[0018] In some embodiments, the judgment module includes at least two XOR gates, the second input terminal of the first XOR gate of the at least two XOR gates is connected to the first input terminal of the second XOR gate, the first input terminals of the at least two XOR gates and the second input terminal of the terminal XOR gate are respectively connected to the at least three comparators in a one-to-one correspondence, the output terminals of the at least two XOR gates and the second input terminal of the terminal XOR gate respectively constitute different detection result output terminals, and the at least two XOR gates perform logical operations according to the at least three comparison signals to output the detection results from different detection result output terminals; or
[0019] An XOR gate, wherein the first input terminal and the second input terminal of the XOR gate are respectively connected to the two comparators in a one-to-one correspondence, the output terminal and the second input terminal of the XOR gate respectively constitute different detection result output terminals, and the XOR gate performs a logical operation according to the two comparison signals to output the detection results from different detection result output terminals.
[0020] In some embodiments, the judgment module includes at least two selection switches connected in series, at least two of the selection switches are respectively connected to at least two of the comparators in a one-to-one correspondence, and at least two of the selection switches perform a selection operation according to at least two of the comparison signals to output the detection results from different selection switches.
[0021] In some embodiments, the selector switch comprises:
[0022] relays;
[0023] MOS transistors, the MOS transistors are respectively connected to the comparator and the relay, and the MOS transistors control the relays to perform a closing operation according to the corresponding comparison signals, so as to output the detection results from different relays.
[0024] In some embodiments, the analog-to-digital conversion module includes at least two conductive switches, at least two of the conductive switches are respectively connected to the judgment module, and at least two of the conductive switches are respectively used to receive at least two of the amplified analog signals. The judgment module is used to select one of the at least two conductive switches to be turned on based on at least two comparison signals, so that the amplified analog signal corresponding to the turned-on conductive switch is transmitted to the analog-to-digital conversion module for analog-to-digital conversion to generate a digital signal.
[0025] In some embodiments, the conductive switch comprises:
[0026] relays;
[0027] MOS transistors, the MOS transistors are respectively connected to the judgment module and the relay, and the judgment module controls the MOS transistor to control the relay to perform a closing operation, so that the amplified analog signal corresponding to the closed relay is transmitted to the analog-to-digital conversion module for analog-to-digital conversion to generate a digital signal.
[0028] In some embodiments, a reference signal module is further included, and the reference signal module is used to generate at least two reference signals.
[0029] In some implementations, each of the reference signals corresponds to a different voltage value.
[0030] According to a second aspect of the present invention, an encoder chip is provided. The encoder chip includes the above-mentioned analog signal sampling circuit.
[0031] Compared with the existing technology, the analog signal sampling circuit and encoder chip of the present invention use a signal segmentation amplification module to segmentally amplify the original analog signal of the encoder according to the accuracy requirements, thereby improving the voltage signal resolution without changing the ADC resolution, thereby improving the angular accuracy of the encoder. The signal segment detection module quickly determines which analog signal segment the original analog signal is located in, ensuring that the ADC samples the amplified voltage value of the corresponding analog signal segment in real time; integrating the analog signal sampling circuit into the chip can reduce the area of the encoder circuit board and realize a miniaturized encoder. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 Schematic diagram of voltage difference at different positions with an angle difference of 10° in the prior art;
[0033] Figure 2 This is a circuit diagram of an encoder chip according to one embodiment of the present invention;
[0034] Figure 3 This is a circuit diagram of an analog voltage subtractor according to one embodiment of the present invention;
[0035] Figure 4 This is a schematic diagram of the operation of an analog voltage subtractor according to one embodiment of the present invention;
[0036] Figure 5 This is a schematic diagram of the function of a programmable gain amplifier according to one embodiment of the present invention;
[0037] Figure 6 This is a first circuit schematic diagram of a judgment module according to an embodiment of the present utility model;
[0038] Figure 7 This is a second circuit principle diagram of the judgment module in one embodiment of the present utility model;
[0039] Figure 8 This is a circuit diagram of an analog-to-digital conversion module according to one embodiment of the present invention;
[0040] Figure 9 This is a schematic diagram of the original analog signal segmentation according to one embodiment of the present invention. DETAILED DESCRIPTION
[0041] The present invention will be further described in detail below with reference to the accompanying drawings.
[0042] The present invention provides an encoder chip 100, such as Figure 2 As shown, the encoder chip 100 is internally integrated with an analog signal sampling circuit 200. Integrating the analog signal sampling circuit 200 into the chip can reduce the area of the encoder circuit board and realize a miniaturized encoder. The analog signal sampling circuit 200 includes a signal segment amplification module 300, a signal segment detection module 400, an analog-to-digital conversion module 500 and a reference signal module 600.
[0043] like Figure 2 As shown, the signal segmented amplification module 300 is used to segmentally amplify the received original analog signal to generate at least two amplified analog signals; specifically, the signal segmented amplification module 300 includes analog voltage subtractors 311, 312, ..., 31n and programmable gain amplifiers (PGAs) 321, 322, ..., 32n, where n is an integer greater than or equal to 1; the first input ends of the analog voltage subtractors 311, 312, ..., 31n are respectively used to receive the original analog signals, and the second input ends of the analog voltage subtractors 311, 312, ..., 31n are respectively used to receive reference signals 1, 2, ..., n, and the analog voltage subtractors 311, 312, ..., 31n perform voltage subtraction operations on the original analog signals and the reference signals 1, 2, ..., n in a one-to-one correspondence to generate new analog signal segment signals 1, 2, ..., n, and output them from their respective output ends. The encoder chip 100 implements sampling of one analog signal through the signal segmentation amplification module 300 , and divides the original analog signal into n segments through the signal segmentation amplification module 300 , thereby implementing high-precision sampling of multiple segments of signals.
[0044] In an optional embodiment, the analog voltage subtractors 311, 312, ..., 31n respectively include operational amplifiers 311, 312, ..., 31n, the operational amplifiers 311, 312, ..., 31n are the same, and the reference signals 1, 2, ..., n are reference voltages 1, 2, ..., n. Figure 3As shown, the non-inverting input terminals of the operational amplifiers 311, 312, ..., 31n are respectively grounded via a first resistor R1, and the non-inverting input terminals of the operational amplifiers 311, 312, ..., 31n are respectively connected in series with a second resistor R2. The original analog signals are respectively transmitted to the non-inverting input terminals of the operational amplifiers 311, 312, ..., 31n via the second resistor R2; the inverting input terminals of the operational amplifiers 311, 312, ..., 31n are respectively connected in series with a third resistor R3, and the reference voltages 1, 2, ..., n are respectively transmitted to the inverting input terminals of the operational amplifiers 311, 312, ..., 31n via the third resistor R3. The inverting input terminals and output terminals of the operational amplifiers 311, 312, ..., 31n are respectively connected via a fourth resistor R4, wherein R1=R2=R3=R4, and the voltages of the new analog signal segments 1, 2, ..., n are equal to the voltages of the original analog signals minus the voltages of the reference voltages 1, 2, ..., n. The purpose of the analog voltage subtractors 311, 312, ..., 31n is to reduce the overall voltage of the original analog signal segment signal in the original analog signal to generate new analog signal segment signals 1, 2, ..., n, and output them from their respective output terminals. Figure 4 As shown, the voltage range of the original analog signal segment signal in the original analog signal is After passing through the analog voltage subtractors 311, 312, ..., 31n, the original analog signal segment signals are shifted downward as a whole to form new analog signal segment signals 1, 2, ..., n. The voltage range of the new analog signal segment signals 1, 2, ..., n is .
[0045] like Figure 2 As shown, the input terminals of the programmable gain amplifiers 321, 322, ..., 32n are connected to the output terminals of the analog voltage subtractors 311, 312, ..., 31n in a one-to-one correspondence. Specifically, the input terminals of the programmable gain amplifiers 321, 322, ..., 32n are connected to the output terminals of the operational amplifiers 311, 312, ..., 31n in a one-to-one correspondence. The programmable gain amplifiers 321, 322, ..., 32n respectively amplify the voltage of the new analog signal segments 1, 2, ..., n to generate amplified analog signals 1, 2, ..., n. The voltage amplification factor can be configured to be 1, 2, 3, 4, etc. according to actual needs. Taking 2 times as an example, Figure 4 The waveforms of the new analog signal segments 1, 2, ..., n after being amplified by programmable gain amplifiers 321, 322, ..., 32n by a factor of 2 are shown in FIG. Figure 5 As shown, the voltage range of the new analog signal segment signals 1, 2, ..., n is determined by become .
[0046] like Figure 2As shown, the signal segment detection module 400 is used to detect the analog signal segment of the received original analog signal and generate a detection result. Specifically, the signal segment detection module 400 includes comparators (CMP) 411, 412, ..., 41n and a judgment module 420. The first input terminals of the comparators 411, 412, ..., 41n are respectively used to receive the original analog signal, and the second input terminals of the comparators 411, 412, ..., 41n are respectively used to receive reference signals 1, 2, ..., n. The comparators 411, 412, ..., 41n are respectively used to receive reference signals 1, 2, ..., n. n are respectively used to compare the original analog signal with the reference signals 1, 2, ..., n one by one to generate comparison signals 1, 2, ..., n, and output them from their respective output terminals; wherein, when the original analog signal is greater than the reference signals 1, 2, ..., n, the comparison signals 1, 2, ..., n output by the comparators 411, 412, ..., 41n are high-level signals; and when the original analog signal is less than the reference signals 1, 2, ..., n, the comparison signals 1, 2, ..., n output by the comparators 411, 412, ..., 41n are low-level signals.
[0047] like Figure 2 As shown, the input end of the judgment module 420 is connected to the output ends of the comparators 411, 412, ..., 41n respectively. The judgment module 420 is used to judge the analog signal segment of the original analog signal according to the comparison signals 1, 2, ..., n to generate a detection result.
[0048] In an optional embodiment, as Figure 2 and Figure 6As shown, the judgment module 420 includes XOR gates 1, 2, ..., n-1. The number of XOR gates 1, 2, ..., n-1 is one less than the number of comparators 411, 412, ..., 41n. Therefore, the connection situations of the XOR gates 1, 2, ..., n-1 can be divided into two types. The first situation is that when the number of XOR gates 1, 2, ..., n-1 is not less than two, the XOR gates 1, 2, ..., n-1 are arranged in sequence, wherein the second input terminal of the previous XOR gate among the XOR gates 1, 2, ..., n-1 is connected to the first input terminal of the next XOR gate, that is, The second input terminal of XOR gate 1 is connected to the first input terminal of XOR gate 2, and the second input terminal of XOR gate 2 is connected to the first input terminal of XOR gate 3. Similarly, the second input terminal of XOR gate n-2 is connected to the first input terminal of XOR gate n-1. The first input terminals Cout1, Cout2, ..., Coutn-1 of XOR gates 1, 2, ..., n-1 and the second input terminal Coutn of the terminal XOR gate n-1 (i.e., XOR gate n-1) are connected to comparators 411, 412, ..., 41n respectively in a one-to-one correspondence. XOR gates 1 and 2 The output terminals Cont1, Cont2, ..., Contn-1 of the comparator 1 and the second input terminal Contn of the XOR gate n-1 at the end respectively constitute different detection result output terminals Cont1, Cont2, ..., Contn. The XOR gates 1, 2, ..., n-1 perform a logic operation according to the comparison signals 1, 2, ..., n to output the detection results from the different detection result output terminals Cont1, Cont2, ..., Contn, i.e., the comparison signal 1 output by the comparator 1 and the comparison signal output by the comparator 2. The calculation result after passing through the XOR gate 1 is output from the detection result output terminal Cont1; the calculation result after passing through the XOR gate 2 of the comparison signal 2 output by comparator 2 and the comparison signal 3 output by comparator 3 is output from the detection result output terminal Cont2; similarly, the calculation result after passing through the XOR gate n-1 of the comparison signal n-1 output by comparator n and the comparison signal n output by comparator n is output from the detection result output terminal Contn-1. In addition, the comparison signal n output by comparator n is also directly output from the detection result output terminal Contn.Exemplarily, when the comparison signal 1 is a high-level signal and the comparison signals 2, ..., n are low-level signals, the XOR gate 1 outputs a high-level signal, the XOR gates 2, ..., n-1 output a low-level signal, and the second input terminal Contn of the XOR gate n-1 is also a low-level signal. When the comparison signals 1 and 2 are high-level signals and the comparison signals 3, ..., n are low-level signals, the XOR gate 2 outputs a high-level signal, the XOR gates 1, 3, ..., n-1 output a low-level signal, and the second input terminal Contn of the XOR gate n-1 is also a low-level signal. Similarly, when the comparison signals 1, 2, ..., n-1 are high-level signals and the comparison signal n is a low-level signal When the comparison signals 1, 2, ..., n are high-level signals, the XOR gates n-1 output a high-level signal, the XOR gates 1, 2, ..., n-2 output a low-level signal, and the second input terminal Contn of the XOR gate n-1 is also a low-level signal. When the comparison signals 1, 2, ..., n are high-level signals, the XOR gates 1, 2, 3, ..., n-1 output a low-level signal, and the second input terminal Contn of the XOR gate n-1 is a high-level signal. The detection results (i.e., high and low-level signals) output by the detection result output terminals Cont1, Cont2, ..., Contn are corresponding to the comparison signals 1, 2, ..., n (corresponding to Cout1~n) one by one to form a table. The specific table is shown in Table 1 below:
[0049] Table 1
[0050]
[0051] Among them, the number "1" in the table represents a high-level signal, and the number "0" represents a low-level signal; the second case is an XOR gate 1, the first input terminal and the second input terminal of the XOR gate 1 are respectively connected to the comparators 1 and 2 in a one-to-one correspondence, and the output terminal and the second input terminal of the XOR gate 1 constitute different detection result output terminals 1 and 2 respectively. The XOR gate 1 performs a logical operation according to the comparison signals 1 and 2 to output the detection results from different detection result output terminals Cont1 and Cont2.
[0052] In an optional embodiment, as Figure 7As shown, the judgment module 420 includes selection switches 421, 422, ..., 42n connected in series, and the selection switches 421, 422, ..., 42n are respectively connected to the output terminals of the comparators 411, 412, ..., 41n in a one-to-one correspondence. The selection switches 421, 422, ..., 42n perform a gating operation according to the comparison signals 1, 2, ..., n to output the detection results from different selection switches 421, 422, ..., 42n. Specifically, the selection switches 421, 422, ..., 42n respectively include grounded relays K1, K2, ..., Kn, and MOS transistors D1, D2, ..., Dn driven by the relays K1, K2, ..., Kn and respectively connected thereto. The MOS transistors D1, D2, ..., Dn are also respectively connected to the VCC terminal. The first terminal of the relay K1 serves as the input terminal of the high-level signal, and the first terminal of the relay K2 serves as the input terminal of the high-level signal. The first end is connected to the third end of the relay K1, and the second end of the relay K2 serves as the detection result output terminal Cont1. The first end of the relay K3 is connected to the third end of the relay K2, and the second end of the relay K3 serves as the detection result output terminal Cont2. Similarly, the first end of the relay Kn is connected to the third end of the relay Kn-1, the second end of the relay Kn serves as the detection result output terminal Contn-1, and the third end of the relay Kn serves as the detection result output terminal Contn. The control ends of the MOS transistors D1, D2, ..., Dn are respectively connected to the comparators 411, 412, ..., 41n in a one-to-one correspondence. The MOS transistors D1, D2, ..., Dn control the relays K1, K2, ..., Kn to perform conduction operations according to the corresponding comparison signals 1, 2, ..., n, so as to output the detection results from different relays K1, K2, ..., Kn;For example, when the comparison signal 1 is a high-level signal and the comparison signals 2, ..., n are low-level signals, the relay K1 performs a closing operation, and the relays K2, K3, ..., Kn do not perform a closing operation, the detection result output terminal Cont1 outputs a high-level signal, and the detection result output terminals Cont2, Cont3 ..., Contn output low-level signals. When the comparison signals 1 and 2 are high-level signals and the comparison signals 3, ..., n are low-level signals, the relays K1 and K2 perform a closing operation, and the relays K3, K4, ..., Kn do not perform a closing operation, the detection result output terminal Cont2 outputs a high-level signal, and the detection result output terminals Cont1, Cont3 ..., Contn output low-level signals. Similarly, when the comparison signals 1, 2, ..., n-1 are high-level signals and the comparison signal n is a low-level signal, the relays K1, K2, K3, ..., Kn-1 perform a closing operation, relay Kn does not perform a closing operation, detection result output terminal Contn-1 outputs a high-level signal, and detection result output terminals Cont1, Cont2, ..., Contn-2, and Contn output low-level signals. When comparison signals 1, 2, ..., n are high-level signals, relays K1, K2, K3, ..., Kn perform a closing operation, detection result output terminal Contn outputs a high-level signal, and detection result output terminals Cont1, Cont2, ..., Contn-1 output low-level signals. The one-to-one correspondence between the detection results (i.e., high and low-level signals) output by the detection result output terminals Cont1, Cont2, ..., Contn and the comparison signals 1, 2, ..., n (corresponding to Cout1-n) is consistent with the correspondence shown in Table 1.
[0053] like Figure 2 and Figure 6As shown, the analog-to-digital conversion module (ADC) 500 is respectively connected to the signal segment amplification module 300 and the signal segment detection module 400. The analog-to-digital conversion module 500 is used to select one of the amplified analog signals 1, 2, ..., n for analog-to-digital conversion to generate a digital signal according to the detection result. Specifically, the analog-to-digital conversion module 500 includes channels CH1, CH2, ..., CHn. The input ends of the channels CH1, CH2, ..., CHn of the analog-to-digital conversion module 500 are respectively connected to the output ends of the programmable gain amplifiers 321, 322, ..., 32n. The analog-to-digital conversion module 500 selects a corresponding sampling channel from the channels CH1, CH2, ..., CHn for signal sampling according to the high-level signal output from any output end of the detection result output ends Cont1, Cont2, ..., Contn in the judgment module 420. For example, when the detection result output end Cont1 outputs a high-level signal, the analog-to-digital conversion module 500 selects a corresponding sampling channel from the channels CH1, CH2, ..., CHn for signal sampling. The module 500 selects channel CH1 for signal sampling to perform analog-to-digital conversion on the amplified analog signal 1 received by channel CH1 to generate a digital signal. When the detection result output terminal Cont2 outputs a high-level signal, the analog-to-digital conversion module 500 selects channel CH2 for signal sampling to perform analog-to-digital conversion on the amplified analog signal 2 received by channel CH2 to generate a digital signal. Similarly, when the detection result output terminal Contn outputs a high-level signal, the analog-to-digital conversion module 500 selects channel CHn for signal sampling to perform analog-to-digital conversion on the amplified analog signal n received by channel CHn to generate a digital signal; thereby achieving the purpose of segmented improvement of the encoder analog signal sampling accuracy, wherein the detection results (i.e., high and low level signals) output by the detection result output terminals Cont1, Cont2, ..., Contn are corresponded to channels CH1, CH2, ..., CHn one by one to form a table, and the specific table is shown in Table 1.
[0054] In an optional embodiment, as Figure 6 and Figure 8As shown, the analog-to-digital conversion module 500 includes conduction switches 511, 512, ..., 51n. The control ends of the conduction switches 511, 512, ..., 51n are respectively connected to the judgment module 420. The input ends of the conduction switches 511, 512, ..., 51n are respectively used to receive the amplified analog signals. The judgment module 420 is used to select one of the conduction switches 511, 512, ..., 51n to be turned on based on the comparison signals 1, 2, ..., n, so that the amplified analog signals 1, 2, ..., corresponding to the turned-on conduction switch are turned on. , n are transmitted to the analog-to-digital conversion module 500 for analog-to-digital conversion to generate digital signals. Specifically, the input ends of the conduction switches 511, 512, ..., 51n are respectively connected to the output ends of the channels CH1, CH2, ..., CHn of the analog-to-digital conversion module 500, and the control ends of the conduction switches 511, 512, ..., 51n are respectively connected to the detection result output ends Cont1, Cont2, ..., Contn in a one-to-one correspondence. When the detection result output end Cont1 outputs a high-level signal, the conduction switches When the switch 511 is turned on, the analog-to-digital conversion module 500 selects channel CH1 for signal sampling to perform analog-to-digital conversion on the amplified analog signal 1 received by channel CH1 to generate a digital signal. When the detection result output terminal Cont2 outputs a high-level signal, the conduction switch 512 is turned on, and the analog-to-digital conversion module 500 selects channel CH2 for signal sampling to perform analog-to-digital conversion on the amplified analog signal 2 received by channel CH2 to generate a digital signal. Similarly, when the detection result output terminal Contn outputs a high-level signal, the conduction switch 51n is turned on, and the analog-to-digital conversion module 500 selects channel CHn for signal sampling to perform analog-to-digital conversion on the amplified analog signal n received by channel CHn to generate a digital signal. This achieves the purpose of segmented improvement of the encoder analog signal sampling accuracy. The detection results (i.e., high and low level signals) output by the detection result output terminals Cont1, Cont2, ..., Contn are corresponding to the channels CH1, CH2, ..., CHn to form a table. The specific table is shown in Table 1.
[0055] In an optional embodiment, as Figure 8As shown, the conducting switches 511, 512, ..., 51n respectively include grounded relays K11, K12, ..., K1n, and MOS transistors D11, D12, ..., D1n driven by and respectively connected to the relays K11, K12, ..., K1n. The MOS transistors D11, D12, ..., D1n are also respectively connected to the VCC terminal. The first terminal of the relay K11 is connected to the channel CH1, the first terminal of the relay K12 is connected to the channel CH2, and the third terminal of the relay K12 is connected to the third terminal of the relay K11. Similarly, the first terminal of the relay K1n is connected to the channel CHn, and the third terminal of the relay K1n is connected to the third terminal of the relay K1n-1. The third terminals of K11, K12, ..., and K1n are connected to form an analog signal input terminal (Ain). The control terminals of the MOS transistors D11, D12, ..., and D1n are connected to the detection result output terminals Cont1, Cont2, ..., and Contn respectively. The MOS transistors D11, D12, ..., and D1n control the relays K11, K12, ..., and K1n to perform a conduction operation according to the high-level signals output by the corresponding detection result output terminals Cont1, Cont2, ..., and Contn, so that the amplified analog signals in the channels CH1, CH2, ..., and CHn corresponding to the closed relays K11, K12, ..., and K1n are transmitted to the analog-to-digital conversion module 50. 0 performs analog-to-digital conversion to generate a digital signal; illustratively, when the detection result output terminal Cont1 outputs a high-level signal, the relay K11 performs a closing operation, and the relays K12, K13, ..., K1n do not perform a closing operation, and the analog-to-digital conversion module 500 selects channel CH1 for signal sampling to perform analog-to-digital conversion on the amplified analog signal 1 received by channel CH1 to generate a digital signal; when the detection result output terminal Cont2 outputs a high-level signal, the relay K12 performs a closing operation, and the relays K11, K13, ..., K1n do not perform a closing operation, and the analog-to-digital conversion module 500 selects channel CH2 for signal sampling to perform analog-to-digital conversion on the amplified analog signal 2 received by channel CH2 to generate a digital signal. Analog-to-digital conversion generates a digital signal. Similarly, when the detection result output terminal Contn outputs a high-level signal, the relay K1n performs a closing operation, and the relays K11, K13, ..., K1n-1 do not perform a closing operation. The analog-to-digital conversion module 500 selects channel CHn for signal sampling to perform analog-to-digital conversion on the amplified analog signal n received by channel CHn to generate a digital signal; thereby achieving the purpose of segmented improvement of the encoder analog signal sampling accuracy. Among them, the detection results (i.e., high and low-level signals) output by the detection result output terminals Cont1, Cont2, ..., Contn are corresponding to the channels CH1, CH2, ..., CHn to form a table. The specific table is shown in Table 1.
[0056] like Figure 2As shown, the reference signal module 600 is used to generate reference signals 1, 2, ..., n. Specifically, the reference signal module 600 includes a digital-to-analog converter (DAC) 600. The digital-to-analog converter 600 has n output terminals, and the n output terminals are respectively connected to the second input terminals of the analog voltage subtractors 311, 312, ..., 31n in a one-to-one correspondence. The n output terminals are also respectively connected to the second input terminals of the comparators 411, 412, ..., 41n. To meet the requirements of different precisions, the original analog signal is divided into n segments, and each segment corresponds to a different reference voltage, such as Figure 9 As shown, the n output terminals of the digital-to-analog converter 600 output reference signals 1, 2, ..., n respectively, and the voltage values corresponding to the reference signals 1, 2, ..., n are different.
[0057] The analog signal sampling circuit 200 of this embodiment uses a signal segmentation amplification module 300 to segmentally amplify the encoder's original analog signal according to accuracy requirements. This improves the voltage signal resolution without changing the ADC resolution, thereby enhancing the encoder's angular accuracy. The signal segment detection module 400 quickly determines the analog signal segment in which the original analog signal resides, ensuring that the ADC samples the amplified voltage value of the corresponding analog signal segment in real time. Integrating the analog signal sampling circuit 200 into the chip 100 reduces the encoder's circuit board area, enabling a miniaturized encoder. This optimized design enables high-precision sampling of multiple analog signal segments, significantly improving the encoder's sampling accuracy and overall performance.
[0058] The above descriptions are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.
Claims
1. An analog signal sampling circuit, characterized in that: include: A signal segmentation amplification module, the signal segmentation amplification module is used to segmentally amplify the received original analog signal to generate at least two amplified analog signals; a signal segment detection module, the signal segment detection module being configured to detect the analog signal segment in which the received original analog signal is located and generate a detection result; An analog-to-digital conversion module is connected to the signal segment amplification module and the signal segment detection module respectively, and is used to select one of the at least two amplified analog signals for analog-to-digital conversion to generate a digital signal based on the detection result.
2. The analog signal sampling circuit according to claim 1, characterized in that: The signal segment amplification module includes: At least two analog voltage subtractors, each configured to perform a voltage subtraction operation on the original analog signal and at least two reference signals in a one-to-one correspondence to generate at least two new analog signal segment signals; At least two programmable gain amplifiers, at least two of the programmable gain amplifiers are connected to the at least two analog voltage subtractors in a one-to-one correspondence, and at least two of the programmable gain amplifiers are used to perform voltage amplification on at least two new analog signal segment signals to generate at least two amplified analog signals.
3. The analog signal sampling circuit according to claim 2, characterized in that: The analog voltage subtractor includes an operational amplifier.
4. The analog signal sampling circuit according to claim 1, wherein: The signal segment detection module includes: At least two comparators, the at least two comparators being respectively used to compare the original analog signal with at least two reference signals in a one-to-one correspondence to generate at least two comparison signals; A judgment module is connected to at least two of the comparators respectively, and is used to judge the analog signal segment in which the original analog signal is located based on at least two comparison signals to generate the detection result.
5. The analog signal sampling circuit according to claim 4, characterized in that: The judgment module includes at least two XOR gates, the second input terminal of the first XOR gate of the at least two XOR gates is connected to the first input terminal of the second XOR gate, the first input terminals of the at least two XOR gates and the second input terminal of the XOR gate at the end are respectively connected to the at least three comparators in a one-to-one correspondence, the output terminals of the at least two XOR gates and the second input terminal of the XOR gate at the end respectively constitute different detection result output terminals, and the at least two XOR gates perform a logic operation according to the at least three comparison signals to output the detection results from different detection result output terminals; or An XOR gate, wherein the first input terminal and the second input terminal of the XOR gate are respectively connected to the two comparators in a one-to-one correspondence, the output terminal and the second input terminal of the XOR gate respectively constitute different detection result output terminals, and the XOR gate performs a logical operation according to the two comparison signals to output the detection results from different detection result output terminals.
6. The analog signal sampling circuit according to claim 4, characterized in that: The judgment module includes at least two selection switches connected in series, and the at least two selection switches are respectively connected to the at least two comparators in a one-to-one correspondence. The at least two selection switches perform a gating operation according to the at least two comparison signals to output the detection results from different selection switches.
7. The analog signal sampling circuit according to claim 4, characterized in that: The analog-to-digital conversion module includes at least two conductive switches, at least two of which are respectively connected to the judgment module, and at least two of which are respectively used to receive at least two amplified analog signals. The judgment module is used to select one of the at least two conductive switches to be turned on based on at least two comparison signals, so that the amplified analog signal corresponding to the turned-on conductive switch is transmitted to the analog-to-digital conversion module for analog-to-digital conversion to generate a digital signal.
8. The analog signal sampling circuit according to claim 2 or 4, characterized in that: The system further includes a reference signal module configured to generate at least two reference signals.
9. The analog signal sampling circuit according to claim 8, characterized in that: The voltage value corresponding to each of the reference signals is different.
10. An encoder chip, characterized in that: The analog signal sampling circuit comprises the analog signal sampling circuit according to any one of claims 1 to 9.