Instrument communication transmission circuit

Abstract

The utility model provides an instrument communication transmission circuit which comprises an MCU chip, an SOC chip, a CAN chip, a CVBS chip, a TFT screen and a Bluetooth WIFI chip. The data transmission end of the SOC chip is connected with the data transmission end of the MCU chip, the data transmission end of the TFT screen, the data transmission end of the Bluetooth WIFI chip, the data transmission end of the CVBS chip and the MIC. The enabling control end of the SOC chip is connected with the control end of the Bluetooth WIFI chip; the data transmission end of the MCU chip is connected with the data transmission end of the CAN chip, and the enabling control end of the MCU chip is connected with the control end of the TFT screen. According to the instrument communication transmission circuit designed by the utility model, the communication efficiency among components in a vehicle is greatly improved, and real-time transmission and accuracy of information are ensured. Besides, the TFT screen and other functional hardware are integrated on the instrument panel, so that the functionality of the instrument panel is enriched, and the safety risk caused by frequent sight transfer of a driver in the operation process of the central control system is obviously reduced.

Description

Technical Field

[0001] The utility model relates to the field of instrument communication, in particular to an instrument communication transmission circuit. Background Art

[0002] As the core of vehicle infotainment and control, the central control system integrates multiple functions, including communication transmission. These features provide drivers with a rich driving experience and convenient operation. However, because in-vehicle communications involve multiple hardware and software components, compatibility between these components is a significant issue. Different vehicle brands and models may utilize varying hardware and software standards, leading to integration and compatibility challenges for central control systems. Furthermore, the excessive number of integrated functions in central control systems makes them more susceptible to electromagnetic interference. Utility Model Content

[0003] The utility model aims to at least solve the technical problems existing in the prior art, and particularly innovatively proposes an instrument communication transmission circuit.

[0004] In order to achieve the above-mentioned purpose of the utility model, the utility model provides an instrument communication transmission circuit, including: an MCU chip, a SOC chip, a CAN chip, a CVBS chip, a TFT screen and a Bluetooth WIFI chip;

[0005] The data transmission end of the SOC chip is connected to the data transmission end of the MCU chip, the data transmission end of the TFT screen, the data transmission end of the Bluetooth WIFI chip, the data transmission end of the CVBS chip, and the MIC (microphone).

[0006] The enabling control terminal of the SOC chip is connected to the control terminal of the Bluetooth WIFI chip;

[0007] The data transmission end of the MCU chip is connected to the data transmission end of the CAN chip, and the enable control end of the MCU chip is connected to the control end of the TFT screen.

[0008] The data transmission between the SOC chip and the Bluetooth WIFI chip is realized through the UART interface and SDIO interface, and the data transmission between the SOC chip and the TFT screen is realized through LVDS (low voltage differential signal).

[0009] Furthermore, it also includes: AMP chip, DSP chip;

[0010] The control terminal of the AMP chip is connected to the enable control terminal of the MCU chip;

[0011] The communication and data transmission terminal of the DSP chip is connected to the communication and data transmission terminal of the SOC chip;

[0012] The audio data input terminal of the DSP chip is connected to the audio data output terminal of the SOC chip, and the audio data output terminal of the DSP chip is connected to the audio data input terminal of the AMP chip.

[0013] Furthermore, the data transmission end of the SOC chip is connected to the data transmission end of the Bluetooth WIFI chip; the enable control end of the SOC chip is connected to the control end of the Bluetooth WIFI chip, including:

[0014] The RF signal transmission terminal WL_BT_ANT of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB54 and the first end of the capacitor CB11. The second end of the capacitor CB11 is connected to the power ground. The second end of the resistor RB54 is connected to the antenna interface JB1 and the first end of the capacitor CB12. The second end of the capacitor CB12 is connected to the power ground.

[0015] The power input terminal VBAT of the Bluetooth WIFI chip UB1 is connected to the first end of the capacitor CB8, the first end of the capacitor CB10, the first end of the capacitor CB7, and the first end of the inductor LB1. The second end of the inductor LB1 is connected to the power supply VCC_3V3.

[0016] The crystal oscillator input terminal XTAL_IN of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB60.

[0017] The crystal oscillator output terminal XTAL_OUT of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB61, the first end of the capacitor CB16, and the first end of the crystal oscillator XB2. The second end of the resistor RB60, the second end of the resistor RB61, the second end of the crystal oscillator XB2 are connected to the first end of the capacitor CB15. The second end of the capacitor CB15, the second end of the capacitor CB16, and the ground end of the crystal oscillator XB2 are connected to the power ground.

[0018] The internal regulator start terminal WL_REG_ON of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB51 and the first end of the resistor RB52. The second end of the resistor RB51 is connected to the enable terminal of the SOC chip; the second end of the resistor RB52 is connected to the power ground;

[0019] The power input terminal VDDIO of the Bluetooth WIFI chip UB1, the first terminal of the capacitor C84, and the first terminal of the capacitor C83 are connected to the power supply VCC_3V3, and the second terminal of the capacitor C84 and the second terminal of the capacitor C83 are connected to the power ground;

[0020] An internal step-down terminal VIN_LDO of the Bluetooth WIFI chip UB1 is connected to a first end of a capacitor CB19 and a first end of an inductor LB2. A second end of the capacitor CB19 is connected to a power ground. A second end of the inductor LB2 is connected to an internal step-down terminal VIN_LDO_OUT of the Bluetooth WIFI chip UB1.

[0021] The PCM data output terminal LPO of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB62, the first end of the resistor RB63, and the first end of the resistor RB64. The second end of the resistor RB62 is connected to the power ground, the second end of the resistor RB64 is connected to the power supply VCC_3V3, the second end of the resistor RB63 is connected to the first end of the capacitor CB20 and the third end of the external crystal oscillator XB1, the second end of the capacitor CB20 and the second end of the external crystal oscillator XB1 are connected to the power ground; the first end of the external crystal oscillator XB1 is connected to the first end of the resistor RB67, the first end of the resistor RB68, the fourth end of the external crystal oscillator XB1, and the first end of the capacitor CB43. The second end of the capacitor CB43 is connected to the power ground, and the second end of the resistor RB68 is connected to the power supply VCC_3V3;

[0022] The ground terminal GND of the Bluetooth WIFI chip UB1 is connected to the power ground;

[0023] An internal regulator start-up terminal BT_REG_ON of the Bluetooth WIFI chip UB1 is connected to a first terminal of a resistor RB57 and a first terminal of a resistor RB58, and a second terminal of the resistor RB58 is connected to a power ground;

[0024] The UART signal transmitting terminal UART_TXD of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB25 and the first end of the resistor RB55. The second end of the resistor RB25 is connected to the power ground. The second end of the resistor RB55 is connected to the UART signal receiving terminal of the SOC chip.

[0025] The UART signal receiving terminal UART_RXD of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB23 and the first end of the resistor RB56. The second end of the resistor RB23 is connected to the power ground. The second end of the resistor RB56 is connected to the UART signal sending terminal of the SOC chip.

[0026] Furthermore, the Bluetooth WIFI chip UB1 also includes an external crystal oscillator circuit:

[0027] The PCM data output terminal LPO of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB63, the first end of the capacitor CB20, and the third end of the external crystal oscillator XB1. The second end of the capacitor CB20 and the second end of the external crystal oscillator XB1 are connected to the power ground. The first end of the external crystal oscillator XB1 is connected to the first end of the resistor RB67, the first end of the resistor RB68, the fourth end of the external crystal oscillator XB1, and the first end of the capacitor CB43. The second end of the capacitor CB43 is connected to the power ground. The second end of the resistor RB68 is connected to the power supply VCC_3V3.

[0028] Connecting a Bluetooth module to an external clock can improve communication accuracy and reliability and may help reduce power consumption. When selecting an external clock source, if the system requires high clock frequency accuracy and hardware cost and space allow, an external crystal oscillator can be used as the external clock source. If the system requires less precise clock frequency or needs to save hardware cost and space, the clock from the SoC can be used as the external clock source.

[0029] Furthermore, it also includes the power supply circuit of the Bluetooth WIFI chip:

[0030] The power supply +3.3VSW is connected to the first end of capacitor CB509, the first end of resistor RB34, and the source of the P-MOS transistor. The gate of the P-MOS transistor is connected to the second end of capacitor CB509, the second end of resistor RB34, and the first end of resistor RB35. The drain of the P-MOS transistor outputs the power supply VCC_3V3 and is connected to the first end of resistor RB36. The second end of resistor RB36 is connected to the power ground.

[0031] The second end of resistor RB35 is connected to the collector of transistor QB4; the base of transistor QB4 is connected to the first end of resistor RB43 and the first end of resistor RB44; the second end of resistor RB43 is connected to the WiFi enable terminal of the SOC chip; the second end of resistor RB44 is connected to the power ground; and the emitter of transistor QB4 is connected to the power ground.

[0032] Furthermore, the data transmission end of the MCU chip is connected to the data transmission end of the CAN chip, including:

[0033] The data transmitting terminal TXD of the CAN chip U1 is connected to the data receiving terminal of the MCU chip; the ground terminal GND of the CAN chip U1 is connected to the power ground; the power terminal VCC of the CAN chip U1, the first end of the resistor R280, the first end of the capacitor C144, and the first end of the capacitor C142 are connected to the power supply +5VCAN; the data receiving terminal RXD of the CAN chip U1 is connected to the second end of the resistor R280 and the data transmitting terminal of the MCU chip;

[0034] The standby mode control input terminal STB of the CAN chip U1 is connected to the control signal terminal of the MCU chip;

[0035] The high-level signal terminal CANH of the CAN chip U1 is connected to the first end of the resistor R102, the first end of the resistor R104, and the first end of the inductor L5; the second end of the resistor R102 is connected to the first end of the resistor R297, the first end of the resistor R103, and the first end of the capacitor C79; the second end of the capacitor C79 is connected to the power ground;

[0036] The second end of the resistor R297 is connected to the first end of the resistor R296, the first end of the capacitor C145, and the power-to-frequency conversion voltage terminal VIO of the CAN chip U1; the second end of the resistor R296 is connected to the power supply +5VCAN; the second end of the capacitor C145 is connected to the power ground;

[0037] The second end of the resistor R103 is connected to the low-level signal terminal CANL of the CAN chip U1, the first end of the resistor R149, and the fourth end of the inductor L5; the second end of the resistor R149 and the third end of the inductor L5 output a low-level signal; the second end of the resistor R104 is connected to the second end of the inductor L5, and the second end of the inductor L5 outputs a high-level signal.

[0038] Resistors R102 and R103 are used for terminal matching, improving the electronic device's resistance to electromagnetic interference and reducing its own external electromagnetic radiation, thereby ensuring the communication quality and stability of the CAN bus system. Inductor L5 is used to improve electromagnetic compatibility (EMC). EMC and terminal matching of CAN chips are key factors in ensuring the stable and reliable operation of the CAN bus system.

[0039] Furthermore, the data transmission end of the SOC chip is connected to the data transmission end of the CVBS chip, including:

[0040] The digital power supply terminal DVDDIO of the CVBS chip UI1 is connected to the first end of the capacitor CI4, the first end of the capacitor CI3, the first end of the capacitor CI5, and the first end of the isolation chip LI3 (used to solve EMC problems). The second end of the capacitor CI4, the second end of the capacitor CI3, and the second end of the capacitor CI5 are connected to the power ground; the second end of the isolation chip LI3 is connected to the power supply +3.3VSW; the power supply terminal DVDD of the CVBS chip UI1 is connected to the first end of the capacitor CI24, the first end of the capacitor CI25, the first end of the capacitor CI9, the first end of the capacitor CI8, the first end of the capacitor CI7, and the first end of the isolation chip LI1; the second end of the capacitor CI24, the second end of the capacitor CI25, the second end of the capacitor CI9, the second end of the capacitor CI8, and the second end of the capacitor CI7 are connected to the power ground; the second end of the isolation chip LI3 is connected to the power supply +1.8V;

[0041] The power supply terminal AVDD of the CVBS chip UI1, the PLL Supply Voltage terminal PVDD of the (18) CVBS chip UI1, the first end of the capacitor CI23, the first end of the capacitor CI22, the first end of the capacitor CI11, the first end of the capacitor CI21, the first end of the capacitor CI10, the first end of the isolation chip LI2 are connected to the power supply AVDD_1.8V, and the second end of the isolation chip LI2 is connected to the power supply +1.8V; the second end of the capacitor CI23, the second end of the capacitor CI22, the second end of the capacitor CI11, the second end of the capacitor CI21, and the second end of the capacitor CI10 are connected to the power ground; the filter terminal ELPF of the CVBS chip UI1 is connected to the first end of the capacitor CI5, the second end of the capacitor CI5 is connected to the first end of the resistor RI1, the first end of the resistor RI2, and the second end of the resistor RI2 is connected to the power ground; the second end of the resistor RI1 and the first end of the transient diode LTVS4 are connected to the interface J1; the second end of the transient diode LTVS4 is connected to the power ground;

[0042] The analog video input terminal AIN1 of the CVBS chip UI1 is connected to the first end of the capacitor CI6, the ground terminal AGND of the CVBS chip UI1 is connected to the first end of the capacitor CI18, the second end of the capacitor CI6 and the second end of the capacitor CI18 are connected to the power ground; the internal voltage reference output terminal VREFP of the CVBS chip UI1 is connected to the first end of the capacitor CI20, the first end of the resistor RI7, and the reset control terminal of the SOC chip, the second end of the capacitor CI20 is connected to the power ground, and the second end of the resistor RI7 is connected to the power supply +3.3VSW; the ground terminal AGND of the CVBS chip UI1 is connected to the capacitor C The first end of I19 is connected, the power supply terminal PVDD of the CVBS chip UI1 is connected to the second end of the capacitor CI19, the crystal oscillator terminal XTAL of the CVBS chip UI1 is connected to the first end of the resistor RI12, the second end of the resistor RI12 is connected to the first end of the crystal oscillator XI1, the first end of the resistor RI13, and the first end of the capacitor CI15, the clock signal terminal XTAL1 of the CVBS chip UI1 is connected to the second end of the resistor RI13, the second end of the crystal oscillator XI1, and the first end of the capacitor CI16, the ground end of the crystal oscillator XI1, the second end of the capacitor CI15, and the second end of the capacitor CI16 are connected to the power ground;

[0043] The internal voltage reference output terminal VREFN of the CVBS chip UI1 is connected to the first end of the resistor RI20 and the first end of the resistor RI21, the second end of the resistor RI20 is connected to the power ground, and the second end of the resistor RI21 is connected to the power supply +3.3VSW; the ground terminal AGND of the CVBS chip UI1 is connected to the first end of the resistor RI22, and the second end of the resistor RI22 is connected to the serial clock of the SOC chip; the power supply terminal AVDD of the CVBS chip UI1 is connected to the first end of the resistor RI23, and the second end of the resistor RI23 is connected to the serial data of the SOC chip; the data transmission terminal of the CVBS chip UI1 is connected to the video data transmission terminal of the SOC chip, the output pixel data terminal LLC interrupt terminal of the CVBS chip UI1 is connected to the first end of the capacitor CI17 and the first end of the capacitor RI8, the second end of the capacitor CI17 is connected to the power ground, and the second end of the capacitor RI8 is connected to the power supply +3.3VSW; the video pixel output terminal P0 of the CVBS chip UI1 is connected to the first end of the resistor RI24 and the first end of the capacitor CI26; the resistor R The second end of I24 is connected to the first end of capacitor CI27; the second end of capacitor CI26 and the second end of capacitor CI27 are connected to the power supply AVDD_1.8V.

[0044] In summary, by employing the aforementioned technical solutions, the instrument cluster communication transmission circuit designed in this utility model shortens the physical distance over which data must be transmitted, thereby reducing communication latency and significantly improving communication efficiency between components within the vehicle. It also mitigates, to a certain extent, the integration and compatibility challenges and electromagnetic interference issues faced by the central control system, thereby largely ensuring the real-time and accurate transmission of information. Furthermore, the innovative integration of the TFT screen and other functional hardware into the instrument cluster not only enriches the functionality of the instrument cluster but also significantly reduces the safety risks associated with the driver frequently shifting their gaze while operating the central control system.

[0045] Additional aspects and advantages of the present invention will be given in part in the following description and will become apparent from the following description or learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0047] Figure 1 It is a connection diagram of the present utility model.

[0048] Figure 2 This is a circuit connection diagram of the CAN chip of the utility model.

[0049] Figure 3This is a circuit connection diagram of the Bluetooth WIFI chip of the utility model.

[0050] Figure 4 This is a schematic diagram of the power supply circuit connection of the Bluetooth WIFI chip of the utility model.

[0051] Figure 5 This is a circuit connection diagram of the CVBS chip of the utility model. DETAILED DESCRIPTION

[0052] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0053] This utility model proposes an instrument communication transmission circuit, such as Figure 1 As shown, it includes: MCU chip, SOC chip, CAN chip, AMP chip, DSP chip, CVBS chip, TFT screen, Bluetooth WIFI chip, MIC (microphone);

[0054] The SOC chip is connected to the MCU chip, TFT screen, Bluetooth WIFI chip, MIC (microphone), DSP chip, and CVBS chip respectively;

[0055] The MCU chip is also connected to the CAN chip, AMP chip, and TFT screen respectively; the CAN chip is used to receive car signals;

[0056] In addition, the DSP chip is connected to the AMP chip.

[0057] This embodiment integrates the central control's imaging and Bluetooth WIFI functions into the instrument panel. The specific implementation is as follows:

[0058] 1. Imaging function implementation: When the CAN chip receives a signal from the vehicle's interior, it transmits the signal to the MCU chip via CAN_TX / RX. The MCU transmits the signal to the SoC chip via UART. The SoC chip controls the CVBS chip, which decodes the vehicle's current video signal and transmits the data to the SoC chip. The SoC chip performs image processing and other operations on the video data before outputting the data to the TFT screen via LVDS. Imaging function usage scenarios include: reversing imaging, 360-degree panoramic imaging, driver monitoring, and interior monitoring.

[0059] 2. Implementation of Bluetooth WIFI function:

[0060] (1) Implementation of Bluetooth function:

[0061] Implementation Path 1: When the Bluetooth WIFI chip receives the data signal from the mobile phone, it transmits the data signal to the SOC chip via UART for decoding and other related processing; then the processed data is transmitted to the DSP chip via I2S for signal processing; the digital signal processed data is transmitted to the AMP chip (audio power amplifier chip, i.e., power amplifier). Usage scenarios include: the mobile phone is connected to the vehicle via Bluetooth, and the vehicle plays music or calls out loud.

[0062] Implementation path two: Receive voice data through the MIC and transmit it to the SoC chip via the ADC for decoding and other related processing. The processed voice data is then transmitted to the Bluetooth WiFi chip via the UART, and the Bluetooth WiFi chip transmits the voice data to the mobile phone. Usage scenarios include: connecting a vehicle to a mobile phone via Bluetooth and making voice calls through the vehicle's MIC.

[0063] (2) Implementation of WIFI function:

[0064] When the Bluetooth Wi-Fi chip receives data signals from the mobile phone, it transmits them to the SoC chip via SDIO. After processing, the SoC chip outputs the data via LVDS to the TFT screen for display. Usage scenarios include: connecting a mobile phone to a vehicle via Wi-Fi and projecting the vehicle's navigation screen.

[0065] The specific circuit diagram of the specific embodiment is as follows Figures 2 to 5 shown.

[0066] The circuit connection of CAN chip is as follows Figure 2 shown.

[0067] The data transmitting terminal TXD of the CAN chip U1 is connected to the data receiving terminal of the MCU chip; the ground terminal GND of the CAN chip U1 is connected to the power ground; the power terminal VCC of the CAN chip U1, the first end of the resistor R280, the first end of the capacitor C144, and the first end of the capacitor C142 are connected to the power supply +5VCAN; the data receiving terminal RXD of the CAN chip U1 is connected to the second end of the resistor R280 and the data transmitting terminal of the MCU chip;

[0068] The standby mode control input terminal STB of the CAN chip U1 is connected to the control signal terminal of the MCU chip;

[0069] The high-level signal terminal CANH of the CAN chip U1 is connected to the first end of the resistor R102, the first end of the resistor R104, and the first end of the inductor L5; the second end of the resistor R102 is connected to the first end of the resistor R297, the first end of the resistor R103, and the first end of the capacitor C79; the second end of the capacitor C79 is connected to the power ground;

[0070] The second end of the resistor R297 is connected to the first end of the resistor R296, the first end of the capacitor C145, and the power-to-frequency conversion voltage terminal VIO of the CAN chip U1; the second end of the resistor R296 is connected to the power supply +5VCAN; the second end of the capacitor C145 is connected to the power ground;

[0071] The second end of the resistor R103 is connected to the low-level signal terminal CANL of the CAN chip U1, the first end of the resistor R149, and the fourth end of the inductor L5; the second end of the resistor R149 and the third end of the inductor L5 output a low-level signal; the second end of the resistor R104 is connected to the second end of the inductor L5, and the second end of the inductor L5 outputs a high-level signal.

[0072] The model of CAN chip U1 is SIT1044.

[0073] The circuit connection of Bluetooth WIFI chip is as follows Figure 3 As shown. The RF signal transmission terminal WL_BT_ANT of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB54 and the first end of the capacitor CB11. The second end of the capacitor CB11 is connected to the power ground. The second end of the resistor RB54 is connected to the antenna interface JB1 and the first end of the capacitor CB12. The second end of the capacitor CB12 is connected to the power ground.

[0074] The power input terminal VBAT of the Bluetooth WIFI chip UB1 is connected to the first end of the capacitor CB8, the first end of the capacitor CB10, the first end of the capacitor CB7, and the first end of the inductor LB1. The second end of the inductor LB1 is connected to the power supply VCC_3V3.

[0075] The crystal oscillator input terminal XTAL_IN of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB60.

[0076] The crystal oscillator output terminal XTAL_OUT of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB61, the first end of the capacitor CB16, and the first end of the crystal oscillator XB2. The second end of the resistor RB60, the second end of the resistor RB61, the second end of the crystal oscillator XB2 are connected to the first end of the capacitor CB15. The second end of the capacitor CB15, the second end of the capacitor CB16, and the ground end of the crystal oscillator XB2 are connected to the power ground.

[0077] The internal regulator start terminal WL_REG_ON of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB51 and the first end of the resistor RB52. The second end of the resistor RB51 is connected to the enable terminal of the SOC chip; the second end of the resistor RB52 is connected to the power ground;

[0078] The power input terminal VDDIO of the Bluetooth WIFI chip UB1, the first terminal of the capacitor C84, and the first terminal of the capacitor C83 are connected to the power supply VCC_3V3, and the second terminal of the capacitor C84 and the second terminal of the capacitor C83 are connected to the power ground;

[0079] An internal step-down terminal VIN_LDO of the Bluetooth WIFI chip UB1 is connected to a first end of a capacitor CB19 and a first end of an inductor LB2. A second end of the capacitor CB19 is connected to a power ground. A second end of the inductor LB2 is connected to an internal step-down terminal VIN_LDO_OUT of the Bluetooth WIFI chip UB1.

[0080] The PCM data output terminal LPO of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB62, the first end of the resistor RB63, and the first end of the resistor RB64. The second end of the resistor RB62 is connected to the power ground, the second end of the resistor RB64 is connected to the power supply VCC_3V3, the second end of the resistor RB63 is connected to the first end of the capacitor CB20 and the third end of the external crystal oscillator XB1, the second end of the capacitor CB20 and the second end of the external crystal oscillator XB1 are connected to the power ground; the first end of the external crystal oscillator XB1 is connected to the first end of the resistor RB67, the first end of the resistor RB68, the fourth end of the external crystal oscillator XB1, and the first end of the capacitor CB43. The second end of the capacitor CB43 is connected to the power ground, and the second end of the resistor RB68 is connected to the power supply VCC_3V3;

[0081] The ground terminal GND of the Bluetooth WIFI chip UB1 is connected to the power ground;

[0082] An internal regulator start-up terminal BT_REG_ON of the Bluetooth WIFI chip UB1 is connected to a first terminal of a resistor RB57 and a first terminal of a resistor RB58, and a second terminal of the resistor RB58 is connected to a power ground;

[0083] The UART signal transmitting terminal UART_TXD of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB25 and the first end of the resistor RB55. The second end of the resistor RB25 is connected to the power ground. The second end of the resistor RB55 is connected to the UART signal receiving terminal of the SOC chip.

[0084] The UART signal receiving terminal UART_RXD of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB23 and the first end of the resistor RB56. The second end of the resistor RB23 is connected to the power ground. The second end of the resistor RB56 is connected to the UART signal transmitting terminal of the SOC chip.

[0085] The model of the Bluetooth WIFI chip UB1 is AP6256.

[0086] The power supply circuit of Bluetooth WIFI chip is as follows Figure 4 As shown. The power supply +3.3VSW is connected to the first end of capacitor CB509, the first end of resistor RB34, and the source of the P-MOS. The gate of the P-MOS is connected to the second end of capacitor CB509, the second end of resistor RB34, and the first end of resistor RB35. The drain of the P-MOS outputs the power supply VCC_3V3 and is connected to the first end of resistor RB36. The second end of resistor RB36 is connected to the power ground.

[0087] The second end of resistor RB35 is connected to the collector of transistor QB4; the base of transistor QB4 is connected to the first end of resistor RB43 and the first end of resistor RB44; the second end of resistor RB43 is connected to the WiFi enable terminal of the SOC chip; the second end of resistor RB44 is connected to the power ground; and the emitter of transistor QB4 is connected to the power ground.

[0088] The SOC chip controls the voltage level at the WiFi enable pin to turn transistor QB4 on and off, which in turn controls the P-MOS transistor on and off, turning the power supply circuit for the Bluetooth WiFi chip on and off. This way, when the instrument cluster goes into sleep mode, the SOC chip can shut down the power supply to the Bluetooth WiFi chip to save energy.

[0089] The circuit connection of CVBS chip is as follows Figure 5 shown.

[0090] The digital power supply terminal DVDDIO of the CVBS chip UI1 is connected to the first end of the capacitor CI4, the first end of the capacitor CI3, the first end of the capacitor CI5, and the first end of the isolation chip LI3 (used to solve EMC problems). The second end of the capacitor CI4, the second end of the capacitor CI3, and the second end of the capacitor CI5 are connected to the power ground; the second end of the isolation chip LI3 is connected to the power supply +3.3VSW; the power supply terminal DVDD of the CVBS chip UI1 is connected to the first end of the capacitor CI24, the first end of the capacitor CI25, the first end of the capacitor CI9, the first end of the capacitor CI8, the first end of the capacitor CI7, and the first end of the isolation chip LI1; the second end of the capacitor CI24, the second end of the capacitor CI25, the second end of the capacitor CI9, the second end of the capacitor CI8, and the second end of the capacitor CI7 are connected to the power ground; the second end of the isolation chip LI3 is connected to the power supply +1.8V;

[0091] The power supply terminal AVDD of the CVBS chip UI1, the PLL Supply Voltage terminal PVDD of the (18) CVBS chip UI1, the first end of the capacitor CI23, the first end of the capacitor CI22, the first end of the capacitor CI11, the first end of the capacitor CI21, the first end of the capacitor CI10, the first end of the isolation chip LI2 are connected to the power supply AVDD_1.8V, and the second end of the isolation chip LI2 is connected to the power supply +1.8V; the second end of the capacitor CI23, the second end of the capacitor CI22, the second end of the capacitor CI11, the second end of the capacitor CI21, and the second end of the capacitor CI10 are connected to the power ground; the filter terminal ELPF of the CVBS chip UI1 is connected to the first end of the capacitor CI5, the second end of the capacitor CI5 is connected to the first end of the resistor RI1, the first end of the resistor RI2, and the second end of the resistor RI2 is connected to the power ground; the second end of the resistor RI1 and the first end of the transient diode LTVS4 are connected to the interface J1; the second end of the transient diode LTVS4 is connected to the power ground;

[0092] The analog video input terminal AIN1 of the CVBS chip UI1 is connected to the first end of the capacitor CI6, the ground terminal AGND of the CVBS chip UI1 is connected to the first end of the capacitor CI18, the second end of the capacitor CI6 and the second end of the capacitor CI18 are connected to the power ground; the internal voltage reference output terminal VREFP of the CVBS chip UI1 is connected to the first end of the capacitor CI20, the first end of the resistor RI7, and the reset control terminal of the SOC chip, the second end of the capacitor CI20 is connected to the power ground, and the second end of the resistor RI7 is connected to the power supply +3.3VSW; the ground terminal AGND of the CVBS chip UI1 is connected to the capacitor C The first end of I19 is connected, the power supply terminal PVDD of the CVBS chip UI1 is connected to the second end of the capacitor CI19, the crystal oscillator terminal XTAL of the CVBS chip UI1 is connected to the first end of the resistor RI12, the second end of the resistor RI12 is connected to the first end of the crystal oscillator XI1, the first end of the resistor RI13, and the first end of the capacitor CI15, the clock signal terminal XTAL1 of the CVBS chip UI1 is connected to the second end of the resistor RI13, the second end of the crystal oscillator XI1, and the first end of the capacitor CI16, the ground end of the crystal oscillator XI1, the second end of the capacitor CI15, and the second end of the capacitor CI16 are connected to the power ground;

[0093] The internal voltage reference output terminal VREFN of the CVBS chip UI1 is connected to the first end of the resistor RI20 and the first end of the resistor RI21, the second end of the resistor RI20 is connected to the power ground, and the second end of the resistor RI21 is connected to the power supply +3.3VSW; the ground terminal AGND of the CVBS chip UI1 is connected to the first end of the resistor RI22, and the second end of the resistor RI22 is connected to the serial clock of the SOC chip; the power supply terminal AVDD of the CVBS chip UI1 is connected to the first end of the resistor RI23, and the second end of the resistor RI23 is connected to the serial data of the SOC chip; the data transmission terminal of the CVBS chip UI1 is connected to the video data transmission terminal of the SOC chip, the output pixel data terminal LLC interrupt terminal of the CVBS chip UI1 is connected to the first end of the capacitor CI17 and the first end of the capacitor RI8, the second end of the capacitor CI17 is connected to the power ground, and the second end of the capacitor RI8 is connected to the power supply +3.3VSW; the video pixel output terminal P0 of the CVBS chip UI1 is connected to the first end of the resistor RI24 and the first end of the capacitor CI26; the resistor R The second end of I24 is connected to the first end of capacitor CI27; the second end of capacitor CI26 and the second end of capacitor CI27 are connected to the power supply AVDD_1.8V.

[0094] The model of CVBS chip UI1 is ADV7180.

[0095] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and purpose of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. An instrument communication transmission circuit, characterized in that: Including: MCU chip, SOC chip, CAN chip, CVBS chip, TFT screen and Bluetooth WIFI chip; The data transmission end of the SOC chip is connected to the data transmission end of the MCU chip, the data transmission end of the TFT screen, the data transmission end of the Bluetooth WIFI chip, the data transmission end of the CVBS chip, and the MIC respectively; The enabling control terminal of the SOC chip is connected to the control terminal of the Bluetooth WIFI chip; The data transmission end of the MCU chip is connected to the data transmission end of the CAN chip, and the enable control end of the MCU chip is connected to the control end of the TFT screen.

2. The instrument communication transmission circuit according to claim 1, characterized in that: Also includes: AMP chip, DSP chip; The control terminal of the AMP chip is connected to the enable control terminal of the MCU chip; The communication and data transmission terminal of the DSP chip is connected to the communication and data transmission terminal of the SOC chip; The audio data input terminal of the DSP chip is connected to the audio data output terminal of the SOC chip, and the audio data output terminal of the DSP chip is connected to the audio data input terminal of the AMP chip.

3. The instrument communication transmission circuit according to claim 1, characterized in that: The data transmission end of the SOC chip is connected to the data transmission end of the Bluetooth WIFI chip; the enable control end of the SOC chip is connected to the control end of the Bluetooth WIFI chip, including: The RF signal transmission terminal WL_BT_ANT of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB54 and the first end of the capacitor CB11. The second end of the capacitor CB11 is connected to the power ground. The second end of the resistor RB54 is connected to the antenna interface JB1 and the first end of the capacitor CB12. The second end of the capacitor CB12 is connected to the power ground. The power input terminal VBAT of the Bluetooth WIFI chip UB1 is connected to the first end of the capacitor CB8, the first end of the capacitor CB10, the first end of the capacitor CB7, and the first end of the inductor LB1. The second end of the inductor LB1 is connected to the power supply VCC_3V3. The crystal oscillator input terminal XTAL_IN of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB60. The crystal oscillator output terminal XTAL_OUT of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB61, the first end of the capacitor CB16, and the first end of the crystal oscillator XB2. The second end of the resistor RB60, the second end of the resistor RB61, the second end of the crystal oscillator XB2 are connected to the first end of the capacitor CB15. The second end of the capacitor CB15, the second end of the capacitor CB16, and the ground end of the crystal oscillator XB2 are connected to the power ground. The internal regulator start terminal WL_REG_ON of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB51 and the first end of the resistor RB52. The second end of the resistor RB51 is connected to the enable terminal of the SOC chip; the second end of the resistor RB52 is connected to the power ground; The power input terminal VDDIO of the Bluetooth WIFI chip UB1, the first terminal of the capacitor C84, and the first terminal of the capacitor C83 are connected to the power supply VCC_3V3, and the second terminal of the capacitor C84 and the second terminal of the capacitor C83 are connected to the power ground; An internal step-down terminal VIN_LDO of the Bluetooth WIFI chip UB1 is connected to a first end of a capacitor CB19 and a first end of an inductor LB2. A second end of the capacitor CB19 is connected to a power ground. A second end of the inductor LB2 is connected to an internal step-down terminal VIN_LDO_OUT of the Bluetooth WIFI chip UB1. The PCM data output terminal LPO of the Bluetooth WIFI chip UB1, the first end of the resistor RB62, and the first end of the resistor RB64 are connected to the power supply VCC_3V3, the second end of the resistor RB62 is connected to the power ground, and the second end of the resistor RB64 is connected to the power supply VCC_3V3. The ground terminal GND of the Bluetooth WIFI chip UB1 is connected to the power ground; An internal regulator start-up terminal BT_REG_ON of the Bluetooth WIFI chip UB1 is connected to a first terminal of a resistor RB57 and a first terminal of a resistor RB58, and a second terminal of the resistor RB58 is connected to a power ground; The UART signal transmitting terminal UART_TXD of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB25 and the first end of the resistor RB55. The second end of the resistor RB25 is connected to the power ground. The second end of the resistor RB55 is connected to the UART signal receiving terminal of the SOC chip. The UART signal receiving terminal UART_RXD of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB23 and the first end of the resistor RB56. The second end of the resistor RB23 is connected to the power ground. The second end of the resistor RB56 is connected to the UART signal sending terminal of the SOC chip.

4. The instrument communication transmission circuit according to claim 1, characterized in that: The Bluetooth WIFI chip UB1 also includes an external crystal oscillator circuit: The PCM data output terminal LPO of the Bluetooth WIFI chip UB1 is connected to the first end of the resistor RB63, the first end of the capacitor CB20, and the third end of the external crystal oscillator XB1. The second end of the capacitor CB20 and the second end of the external crystal oscillator XB1 are connected to the power ground. The first end of the external crystal oscillator XB1 is connected to the first end of the resistor RB67, the first end of the resistor RB68, the fourth end of the external crystal oscillator XB1, and the first end of the capacitor CB43. The second end of the capacitor CB43 is connected to the power ground. The second end of the resistor RB68 is connected to the power supply VCC_3V3.

5. The instrument communication transmission circuit according to claim 1, characterized in that: It also includes the power supply circuit of the Bluetooth WIFI chip: The power supply +3.3VSW is connected to the first end of capacitor CB509, the first end of resistor RB34, and the source of the P-MOS transistor. The gate of the P-MOS transistor is connected to the second end of capacitor CB509, the second end of resistor RB34, and the first end of resistor RB35. The drain of the P-MOS transistor outputs the power supply VCC_3V3 and is connected to the first end of resistor RB36. The second end of resistor RB36 is connected to the power ground. The second end of resistor RB35 is connected to the collector of transistor QB4; the base of transistor QB4 is connected to the first end of resistor RB43 and the first end of resistor RB44; the second end of resistor RB43 is connected to the WiFi enable terminal of the SOC chip; the second end of resistor RB44 is connected to the power ground; and the emitter of transistor QB4 is connected to the power ground.

6. The instrument communication transmission circuit according to claim 1, characterized in that: The data transmission end of the MCU chip is connected to the data transmission end of the CAN chip, including: The data transmitting terminal TXD of the CAN chip U1 is connected to the data receiving terminal of the MCU chip; the ground terminal GND of the CAN chip U1 is connected to the power ground; the power terminal VCC of the CAN chip U1, the first end of the resistor R280, the first end of the capacitor C144, and the first end of the capacitor C142 are connected to the power supply +5VCAN; the data receiving terminal RXD of the CAN chip U1 is connected to the second end of the resistor R280 and the data transmitting terminal of the MCU chip; The standby mode control input terminal STB of the CAN chip U1 is connected to the control signal terminal of the MCU chip; The high-level signal terminal CANH of the CAN chip U1 is connected to the first end of the resistor R102, the first end of the resistor R104, and the first end of the inductor L5; the second end of the resistor R102 is connected to the first end of the resistor R297, the first end of the resistor R103, and the first end of the capacitor C79; the second end of the capacitor C79 is connected to the power ground; The second end of the resistor R297 is connected to the first end of the resistor R296, the first end of the capacitor C145, and the power-to-frequency conversion voltage terminal VIO of the CAN chip U1; the second end of the resistor R296 is connected to the power supply +5VCAN; the second end of the capacitor C145 is connected to the power ground; The second end of the resistor R103 is connected to the low-level signal terminal CANL of the CAN chip U1, the first end of the resistor R149, and the fourth end of the inductor L5; the second end of the resistor R149 and the third end of the inductor L5 output a low-level signal; the second end of the resistor R104 is connected to the second end of the inductor L5, and the second end of the inductor L5 outputs a high-level signal.

7. The instrument communication transmission circuit according to claim 1, characterized in that: The data transmission end of the SOC chip is connected to the data transmission end of the CVBS chip, including: The digital power supply terminal DVDDIO of the CVBS chip UI1 is connected to the first end of the capacitor CI4, the first end of the capacitor CI3, the first end of the capacitor CI5, and the first end of the isolation chip LI3. The second end of the capacitor CI4, the second end of the capacitor CI3, and the second end of the capacitor CI5 are connected to the power ground; the second end of the isolation chip LI3 is connected to the power supply +3.3VSW; the power supply terminal DVDD of the CVBS chip UI1 is connected to the first end of the capacitor CI24, the first end of the capacitor CI25, the first end of the capacitor CI9, the first end of the capacitor CI8, the first end of the capacitor CI7, and the first end of the isolation chip LI1; the second end of the capacitor CI24, the second end of the capacitor CI25, the second end of the capacitor CI9, the second end of the capacitor CI8, and the second end of the capacitor CI7 are connected to the power ground; the second end of the isolation chip LI3 is connected to the power supply +1.8V; The power supply terminal AVDD of the CVBS chip UI1, the PLL Supply Voltage terminal PVDD of the (18) CVBS chip UI1, the first end of the capacitor CI23, the first end of the capacitor CI22, the first end of the capacitor CI11, the first end of the capacitor CI21, the first end of the capacitor CI10, the first end of the isolation chip LI2 are connected to the power supply AVDD_1.8V, and the second end of the isolation chip LI2 is connected to the power supply +1.8V; the second end of the capacitor CI23, the second end of the capacitor CI22, the second end of the capacitor CI11, the second end of the capacitor CI21, and the second end of the capacitor CI10 are connected to the power ground; the filter terminal ELPF of the CVBS chip UI1 is connected to the first end of the capacitor CI5, the second end of the capacitor CI5 is connected to the first end of the resistor RI1, the first end of the resistor RI2, and the second end of the resistor RI2 is connected to the power ground; the second end of the resistor RI1 and the first end of the transient diode LTVS4 are connected to the interface J1; the second end of the transient diode LTVS4 is connected to the power ground; The analog video input terminal AIN1 of the CVBS chip UI1 is connected to the first end of the capacitor CI6, the ground terminal AGND of the CVBS chip UI1 is connected to the first end of the capacitor CI18, the second end of the capacitor CI6 and the second end of the capacitor CI18 are connected to the power ground; the internal voltage reference output terminal VREFP of the CVBS chip UI1 is connected to the first end of the capacitor CI20, the first end of the resistor RI7, and the reset control terminal of the SOC chip, the second end of the capacitor CI20 is connected to the power ground, and the second end of the resistor RI7 is connected to the power supply +3.3VSW; the ground terminal AGND of the CVBS chip UI1 is connected to the capacitor C The first end of I19 is connected, the power supply terminal PVDD of the CVBS chip UI1 is connected to the second end of the capacitor CI19, the crystal oscillator terminal XTAL of the CVBS chip UI1 is connected to the first end of the resistor RI12, the second end of the resistor RI12 is connected to the first end of the crystal oscillator XI1, the first end of the resistor RI13, and the first end of the capacitor CI15, the clock signal terminal XTAL1 of the CVBS chip UI1 is connected to the second end of the resistor RI13, the second end of the crystal oscillator XI1, and the first end of the capacitor CI16, the ground end of the crystal oscillator XI1, the second end of the capacitor CI15, and the second end of the capacitor CI16 are connected to the power ground; The internal voltage reference output terminal VREFN of the CVBS chip UI1 is connected to the first end of the resistor RI20 and the first end of the resistor RI21, the second end of the resistor RI20 is connected to the power ground, and the second end of the resistor RI21 is connected to the power supply +3.3VSW; the ground terminal AGND of the CVBS chip UI1 is connected to the first end of the resistor RI22, and the second end of the resistor RI22 is connected to the serial clock of the SOC chip; the power supply terminal AVDD of the CVBS chip UI1 is connected to the first end of the resistor RI23, and the second end of the resistor RI23 is connected to the serial data of the SOC chip; the data transmission terminal of the CVBS chip UI1 is connected to the video data transmission terminal of the SOC chip, the output pixel data terminal LLC interrupt terminal of the CVBS chip UI1 is connected to the first end of the capacitor CI17 and the first end of the capacitor RI8, the second end of the capacitor CI17 is connected to the power ground, and the second end of the capacitor RI8 is connected to the power supply +3.3VSW; the video pixel output terminal P0 of the CVBS chip UI1 is connected to the first end of the resistor RI24 and the first end of the capacitor CI26; the resistor R The second end of I24 is connected to the first end of capacitor CI27; the second end of capacitor CI26 and the second end of capacitor CI27 are connected to the power supply AVDD_1.8V.

Images