Clock device controlled by line frequency phase-locked loop of graphic wafer defect detection camera

Abstract

The utility model belongs to the technical field of electronic circuits, and particularly relates to a clock device controlled by a line frequency phase-locked loop of a graphic wafer defect detection camera. The clock device comprises a coding circuit, a frequency halving circuit, a first filter circuit, a signal processing circuit, a first frequency dividing circuit, a second filter circuit, an analog quantity peak adjusting circuit, a bidirectional comparator level conditioning circuit and a phase-locked loop circuit. According to the utility model, sine and cosine analog quantity positions or digital quantity signals in a motion process are obtained through the coding circuit and are uniformly converted into analog quantities, and then the analog quantities are subjected to linear processing, digital filtering, angle interpolation subdivision, frequency division, band-pass filtering, gain threshold control, digital square wave shaping, phase locking and camera line frequency clock adjustment through the signal processing circuit; and finally, a digital trigger signal meeting practical application is obtained, the camera line frequency clock can be randomly adjusted on line, the motion position and the line frequency clock phase are always kept in a locked state, and the wafer defect detection accuracy is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of electronic circuits, and specifically relates to a device for automatic frequency or phase control, and in particular to a clock device for line frequency phase-locked loop control of a pattern wafer defect detection camera. Background Art

[0002] During wafer defect inspection, the XY motion translation stage carries the wafer stage along a "bow"-shaped trajectory to scan the wafer at a constant speed for imaging and defect detection.

[0003] Since the XY motion translation stage can be configured with multiple scanning speeds, and traditional image inspection equipment collects data with a fixed line frequency clock, the position of the XY motion translation stage does not match the phase of the line frequency clock, affecting the accuracy of wafer defect detection.

[0004] Therefore, it is urgent to develop a new clock device controlled by the line frequency phase-locked loop of the graphic wafer defect inspection camera to solve the technical problem of how to overcome the mismatch between the motion position and the line frequency clock phase.

[0005] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Utility Model Content

[0006] The embodiments of the present disclosure at least provide a clock device for controlling a line-frequency phase-locked loop of a pattern wafer defect inspection camera.

[0007] In the first aspect, an embodiment of the present disclosure provides a clock device controlled by a line frequency phase-locked loop of a graphic wafer defect detection camera, which includes: an encoding circuit, a two-frequency division circuit, a first filtering circuit, a signal processing circuit, a first frequency division circuit, a second filtering circuit, an analog peak adjustment circuit, a bidirectional comparator level conditioning circuit and a phase-locked loop circuit electrically connected in sequence; the encoding circuit is suitable for obtaining a signal from device one, and the signal is sent to device two via the two-frequency division circuit, the first filtering circuit, the signal processing circuit, the first frequency division circuit, the second filtering circuit, the analog peak adjustment circuit, the bidirectional comparator level conditioning circuit and the phase-locked loop circuit.

[0008] In an optional embodiment, the encoding circuit includes: an analog encoder and / or a digital encoder; the analog encoder and the digital encoder are electrically connected to device one to respectively obtain corresponding electrical signals and digital signals to be sent to the binary frequency division circuit.

[0009] In an optional embodiment, the two-way frequency division circuit includes: a first digital-to-analog converter, an analog switch and a dual-channel rising-edge triggered D-type trigger; the input end of the first digital-to-analog converter is electrically connected to the encoding circuit, the first digital-to-analog converter, the analog switch, and the dual-channel rising-edge triggered D-type trigger are electrically connected in sequence, and the dual-channel rising-edge triggered D-type trigger is electrically connected to the first filtering circuit; the first digital-to-analog converter is suitable for converting the input signal into a digital signal, and the digital signal is divided into two after being sent to the first filtering circuit by the analog switch and the dual-channel rising-edge triggered D-type trigger.

[0010] In an optional embodiment, the first filtering circuit includes: a first bandpass filter; the first bandpass filter is electrically connected to the binary frequency division circuit and the signal processing circuit; the first bandpass filter is suitable for filtering the signal to send it to the signal processing circuit.

[0011] In an optional embodiment, the signal processing circuit includes: two second analog-to-digital converters, a processor and a PI filter; the two second analog-to-digital converters, the PI filter and the processor are electrically connected, and the processor is electrically connected to the first frequency division circuit; the two second analog-to-digital converters are suitable for performing analog-to-digital conversion on the signal respectively to send it to the processor, so that the signal is sent to the first frequency division circuit after being subjected to inverse tangent, filtering and difference processing by the processor and the PI filter.

[0012] In an optional embodiment, the first frequency dividing circuit includes: a first frequency divider; the first frequency divider is electrically connected to the signal processing circuit and the second filtering circuit; the first frequency divider is suitable for dividing the signal by several times to send it to the second filtering circuit.

[0013] In an optional embodiment, the second filtering circuit includes: a second bandpass filter; the second bandpass filter is electrically connected to the first frequency division circuit and the analog peak adjustment circuit; the second bandpass filter is suitable for filtering the signal to send it to the analog peak adjustment circuit.

[0014] In an optional embodiment, the analog value peak adjustment circuit includes: a potentiometer; the potentiometer is electrically connected to the second filtering circuit and the bidirectional comparator level conditioning circuit; the potentiometer is suitable for adjusting the analog value peak threshold of the signal to send it to the bidirectional comparator level conditioning circuit.

[0015] In an optional embodiment, the bidirectional comparator level conditioning circuit includes: an inverter; the inverter is electrically connected to the analog peak adjustment circuit and the phase-locked loop circuit; the inverter is suitable for shaping the signal to convert the analog signal into a digital signal and send it to the phase-locked loop circuit.

[0016] In an optional embodiment, the phase-locked loop circuit includes: a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a second frequency divider; the phase detector, charge pump, loop filter, and voltage-controlled oscillator are electrically connected in sequence, the input end of the second frequency divider is electrically connected to the voltage-controlled oscillator, and the output end of the second frequency divider is electrically connected to the phase detector; the phase detector is electrically connected to a bidirectional comparator level conditioning circuit, and the voltage-controlled oscillator is electrically connected to an image acquisition system.

[0017] In a second aspect, an embodiment of the present disclosure also provides a dark field pattern wafer defect detection system, which includes: a motion control device and an image acquisition device; the input end of the encoding circuit is electrically connected to the motion control device, and the output end of the phase-locked loop circuit is electrically connected to the image acquisition device.

[0018] The beneficial effect of the present invention is that the present invention obtains the sine and cosine analog position or digital signal during the movement process through the encoding circuit, and after being uniformly converted into analog quantity by the two-frequency division circuit and the first filtering circuit, the signal processing circuit performs linearization processing, digital filtering, and angle interpolation subdivision, and the first frequency division circuit, the second filtering circuit, the analog quantity peak adjustment circuit, the bidirectional comparator level conditioning circuit and the phase-locked loop circuit perform re-frequency division, bandpass filtering, gain threshold control, digital square wave shaping, phase locking, and camera line frequency clock adjustment in sequence, and finally obtains a digital trigger signal that meets practical applications, realizes that the camera line frequency clock can be adjusted online arbitrarily, and the movement position and line frequency clock phase always remain in a locked state, thereby improving the accuracy of wafer defect detection.

[0019] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The objectives and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1A block diagram showing the principle of a clock device controlled by a line-rate phase-locked loop for a pattern wafer defect inspection camera according to an embodiment of the present disclosure;

[0023] Figure 2 A structural block diagram of a clock device for line-frequency phase-locked loop control of a pattern wafer defect inspection camera provided by an embodiment of the present disclosure;

[0024] Figure 3 A waveform diagram of signal inverse tangent processing by a processor provided in an embodiment of the present disclosure;

[0025] Figure 4 A waveform diagram of the initial filtering process of a signal by a PI filter provided in an embodiment of the present disclosure;

[0026] Figure 5 This is a waveform diagram of the final filtering processing of a signal by a PI filter provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic structural diagram of a clock device controlled by a line-rate phase-locked loop for a pattern wafer defect inspection camera provided in an embodiment of the present disclosure.

[0028] 1. Laser illumination unit; 2. Laser refraction light intensity collection unit; 3. Wafer scattered light collection unit; 4. Tray; 5. X-direction linear motor stator; 6. Y-direction linear motor stator. DETAILED DESCRIPTION

[0029] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0030] The terms used herein are only used to describe specific exemplary configurations and are not intended to be limiting. As used herein, the singular articles "a", "an" and "the" may also be intended to include plural forms, unless otherwise clearly indicated herein. The terms "comprise", "include" and "have" are inclusive and therefore specify the presence of features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the particular order discussed or shown, unless specifically identified as an execution order. Additional or alternative steps may be adopted.

[0031] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Thus, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, such that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations, aspects, or designs. Instead, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0032] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0033] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0034] like Figure 1 To, 6, at least one embodiment provides a clock device controlled by a line frequency phase-locked loop of a graphic wafer defect detection camera, which includes: an encoding circuit, a two-frequency division circuit, a first filtering circuit, a signal processing circuit, a first frequency division circuit, a second filtering circuit, an analog peak value adjustment circuit, a bidirectional comparator level conditioning circuit and a phase-locked loop circuit electrically connected in sequence; the encoding circuit is suitable for obtaining a signal from device one, and the signal is sent to device two via the two-frequency division circuit, the first filtering circuit, the signal processing circuit, the first frequency division circuit, the second filtering circuit, the analog peak value adjustment circuit, the bidirectional comparator level conditioning circuit and the phase-locked loop circuit.

[0035] In at least one embodiment, the sine and cosine analog position or digital signal during the motion process is obtained through an encoding circuit, and is uniformly converted into analog quantity by a two-frequency division circuit and a first filtering circuit. Then, the signal processing circuit performs linearization processing, digital filtering, and angle interpolation subdivision. The first frequency division circuit, the second filtering circuit, the analog peak adjustment circuit, the bidirectional comparator level conditioning circuit, and the phase-locked loop circuit sequentially perform re-frequency division, band-pass filtering, gain threshold control, digital square wave shaping, phase locking, and camera line frequency clock adjustment, and finally obtains a digital trigger signal that meets the actual application, so that the camera line frequency clock can be adjusted online arbitrarily, and the motion position and line frequency clock phase are always kept in a locked state, thereby improving the accuracy of wafer defect detection.

[0036] In at least one embodiment, the encoding circuit includes: an analog encoder and / or a digital encoder; the analog encoder and the digital encoder are electrically connected to device one to respectively obtain corresponding electrical signals and digital signals to be sent to the binary frequency division circuit.

[0037] Specifically, the segmented impedance matching network is designed to be 480 ohms, which can better match digital and analog quantities.

[0038] In at least one embodiment, the two-way frequency division circuit includes: a first digital-to-analog converter, an analog switch and a dual-channel rising-edge-triggered D-type trigger; the input end of the first digital-to-analog converter is electrically connected to the encoding circuit, the first digital-to-analog converter, the analog switch, and the dual-channel rising-edge-triggered D-type trigger are electrically connected in sequence, and the dual-channel rising-edge-triggered D-type trigger is electrically connected to the first filtering circuit; the first digital-to-analog converter is suitable for converting the input signal into a digital signal, and the digital signal is divided into two after being sent to the first filtering circuit by the analog switch and the dual-channel rising-edge-triggered D-type trigger.

[0039] Specifically, the first digital-to-analog converter adopts TI's AM26LV32EIDR converter, which uses a single-pole double-throw analog switch, and the analog switch can use the ADG1634BRUZ chip to complete the switching of high and low speed modes. In high-speed mode, the signal is passed to a dual-channel rising edge triggered D-type trigger, and the dual-channel rising edge triggered D-type trigger can use an SN74LVC74APW trigger.

[0040] In at least one embodiment, the first filtering circuit includes: a first bandpass filter; the first bandpass filter is electrically connected to the binary frequency division circuit and the signal processing circuit; the first bandpass filter is suitable for filtering the signal to send it to the signal processing circuit.

[0041] Specifically, the first bandpass filter adopts an 8th-order Butterworth bandpass filter with a center frequency of 525Khz, a passband of -0.1db@350Khz, and a bandstop of -12db@700Khz. It is only effective at high speed. The first bandpass filter is designed using the Analog Devices high-speed operational amplifier ADA4807-4 with a GBP-gain bandwidth of 200MHz. According to the Nyquist sampling theorem, it can effectively restore a 10Mhz sine wave.

[0042] In at least one embodiment, the signal processing circuit includes: two second analog-to-digital converters, a processor and a PI filter; the two second analog-to-digital converters, the PI filter and the processor are electrically connected, and the processor is electrically connected to the first frequency division circuit; the two second analog-to-digital converters are suitable for performing analog-to-digital conversion on the signal respectively to send it to the processor, so that the signal is sent to the first frequency division circuit after being subjected to inverse tangent, filtering and difference processing by the processor and the PI filter.

[0043] Specifically, based on the translation stage's X-axis speed, typically less than 600 mm / s, and assuming a 0.512 μm positional accuracy for the encoder circuit, the maximum SIN / COS frequency output by the encoder circuit will be less than 1.2 MHz. The second ADC, with a sampling rate of 20 MHz and a sampling depth of 12 bits, can accurately capture and restore a 1.2 MHz sine wave signal, providing better signal restoration quality, reduced distortion, and greater flexibility in subsequent signal processing.

[0044] Specifically, see Figure 3 The processor linearizes the angle relationship and converts the sine (SIN) and cosine (COS) signals of the encoding circuit into inverse tangent graphs. The formula is as follows:

[0045] Rotation radian: A=arctan(sin(x),cos(x)); Rotation angle: α=A*180° / π=±180°

[0046] The ARCTAN function can help linearize certain nonlinear characteristics, particularly when the angle approaches 90 degrees (π / 2 radians) or 270 degrees (3π / 2 radians). The rate of change of the sin and cos functions becomes very small, while the arctan function exhibits a more linear behavior in these regions. Angle (or phase) information is crucial. The tangent function (ARCTAN) is mathematically directly related to angle calculation, and the arctan function can be used to directly determine the angle. This is more direct than calculating the angle from sin and cos signals, especially when rapid angle changes are required. Using the ARCTAN signal can improve angle measurement resolution within specific angular ranges, particularly near 0° and 90°. This is because the ARCTAN function's rate of change is larger in these regions, amplifying angular changes. Converting sin and cos signals to ARCTAN signals improves signal noise immunity. Since the ARCTAN signal tends to infinity when both sin and cos are close to zero (i.e., when the signal amplitude is very small), it can overcome the effects of noise on angle calculations.

[0047] Specifically, the PI filter Figure 3In the example, SIN and COS are superimposed with 3% differential mode signals and 5% common mode signals. After superposition, the common mode signal becomes smaller and the differential mode signal cannot be eliminated. Moreover, large jitter occurs when SIN changes from positive to negative. Figure 4 .

[0048] Specifically, the original sin and cos signals may contain noise and various nonlinearities and uncertainties. After arctan conversion, these noises are more significant in the phase domain. The PI filter can effectively further smooth the error compensation of these signals, reduce the impact of noise on system performance, and ensure that the system can still operate on the expected track when there is external interference or system parameter changes. The PI filter is used to reduce errors and improve the response performance of the system. For a linear signal, applying a PI filter can help smooth the signal and reduce noise. The output of the PI filter can be expressed as: u(t)=Kp*e(t)+∫Ki*e(t)*dt, where u(t) is the output of the filter, e(t) is the error between the input signal and the reference signal, Kp is the proportional gain, and Ki is the integral gain. The filtering effect is as follows: Figure 5 As shown in the figure, within the angle range of ±180°, for ±5° differential mode noise and 10° common mode noise, after filtering, the overall differential mode noise is controlled within 0.1%, and the common mode noise is also effectively smoothed.

[0049] Specifically, the processor interpolates the phase angle change between phases A and B, using the inverse tangent (arctan) function to accurately calculate radians from the sine and cosine signals. Resolution is then increased through radian subdivision. The angle is subdivided from 1 to 1024 steps, with a minimum angular resolution of 0.352°, sufficient for both high- and low-speed applications.

[0050] In at least one embodiment, the first frequency dividing circuit includes: a first frequency divider; the first frequency divider is electrically connected to the signal processing circuit and the second filtering circuit; the first frequency divider is suitable for dividing the signal by several times to send it to the second filtering circuit.

[0051] Specifically, the first frequency divider performs 1 to 8 frequency division on the digital signal after radian interpolation, which further increases the flexibility of the system and can also neutralize part of the position error.

[0052] In at least one embodiment, the second filtering circuit includes: a second bandpass filter; the second bandpass filter is electrically connected to the first frequency division circuit and the analog peak adjustment circuit; the second bandpass filter is suitable for filtering the signal to send it to the analog peak adjustment circuit.

[0053] Specifically, the second bandpass filter used for radian interpolation improves resolution, but also introduces some imbalance errors that require further compensation, thereby improving output signal stability. This second bandpass filter utilizes a 6th-order Butterworth active bandpass filter. The LTC6244 dual 50MHz, low offset drift (2.5µV / °C), 0.1Hz to 10Hz noise (1.5µV / P), CMOS rail-to-rail operational amplifier is selected. Its passband is 200kHz at 1.5625MHz, providing excellent filtering performance and improving device stability.

[0054] In at least one embodiment, the analog value peak adjustment circuit includes: a potentiometer; the potentiometer is electrically connected to the second filtering circuit and the bidirectional comparator level conditioning circuit; the potentiometer is suitable for adjusting the analog value peak threshold of the signal to send it to the bidirectional comparator level conditioning circuit.

[0055] Specifically, the potentiometer is used to adjust the analog peak threshold after the bandpass filter, and a signal with a jitter within a bandwidth of 100Khz above and below the target rate can be obtained.

[0056] In at least one embodiment, the bidirectional comparator level conditioning circuit includes: an inverter; the inverter is electrically connected to the analog peak adjustment circuit and the phase-locked loop circuit; the inverter is suitable for shaping the signal to convert the analog signal into a digital signal and send it to the phase-locked loop circuit.

[0057] Specifically, the digital signal is converted into an analog signal through the second bandpass filter. The inverter shapes the analog signal and converts the analog quantity into a standard digital output. The N74AHC1G14DBVR inverter is used, which is a single 2V to 5.5V inverter with Schmitt trigger input, which can meet actual usage requirements.

[0058] In at least one embodiment, the phase-locked loop circuit includes: a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a second frequency divider; the phase detector, charge pump, loop filter, and voltage-controlled oscillator are electrically connected in sequence, the input end of the second frequency divider is electrically connected to the voltage-controlled oscillator, and the output end of the second frequency divider is electrically connected to the phase detector; the phase detector is electrically connected to a bidirectional comparator level conditioning circuit, and the voltage-controlled oscillator is electrically connected to an image acquisition system.

[0059] Specifically, the standard digital signal is input into a phase-locked loop circuit, frequency-multiplied, and then frequency-reduced to obtain a predefined frequency.

[0060] Specifically, the ADF4150 PLL chip integrates a phase detector, charge pump, loop filter, and second frequency divider. The HMC388 voltage-controlled oscillator operates in the 3.15-3.4 GHz range, with 3.276 GHz selected as the center frequency. This frequency is further divided by integers and fractional numbers, resulting in a highly flexible and convenient output for real-time adjustment of the laser scanning cycle and image acquisition time. It also locks the phase of the encoder's output digital signal in real time and serves as a real-time diagnostic tool for the stability of horizontal-frequency motion systems. If the frequency of the radian interpolation output is significantly disturbed, the phase-locked loop circuit loses lock, instantly notifying the host computer software.

[0061] In at least one embodiment, see Figure 6 The clock device controlled by the line frequency phase-locked loop of the graphic wafer defect detection camera also includes: a motion control device and an image acquisition device; the input end of the encoding circuit is electrically connected to the motion control device, and the output end of the phase-locked loop circuit is electrically connected to the image acquisition device.

[0062] See also Figure 6 The motion control device includes: an X-motion direction linear motor stator 5, a Y-motion direction linear motor stator 6 and a tray 4. The X-motion direction linear motor stator 5 is movably connected to the Y-motion direction linear motor stator 6, and the tray 4 is movably connected to the X-motion direction linear motor stator 5, and a wafer is placed on the tray 4. The image acquisition device includes: a laser illumination unit 1, a laser refraction light intensity acquisition unit 2, and a wafer scattered light acquisition unit 3. Therefore, the encoding circuit is electrically connected to the X-motion direction linear motor stator 5 and the Y-motion direction linear motor stator 6, and the phase-locked loop circuit is electrically connected to the laser refraction light intensity acquisition unit 2 and the wafer scattered light acquisition unit 3, which can achieve real-time adjustment of the line frequency trigger frequency output when responding to multiple gears with different X-direction motion speeds.

[0063] In summary, the present invention obtains the sine and cosine analog position or digital signal during the motion process through the encoding circuit, and after being uniformly converted into analog signals by the two-frequency division circuit and the first filtering circuit, the signal processing circuit performs linearization processing, digital filtering, and angle interpolation subdivision. The first frequency division circuit, the second filtering circuit, the analog peak adjustment circuit, the bidirectional comparator level conditioning circuit and the phase-locked loop circuit sequentially perform re-frequency division, band-pass filtering, gain threshold control, digital square wave shaping, phase locking, and camera line frequency clock adjustment, and finally obtains a digital trigger signal that meets practical applications, so that the camera line frequency clock can be adjusted online at will, and the motion position and line frequency clock phase are always kept locked. state, improving the accuracy of wafer defect detection; breaking through the limitation of traditional subdivision input frequency that cannot exceed 700Khz, making the original subdivision frequency of the encoder as high as 1.4Mhz, corresponding to a higher scanning speed; realizing online switching of high and low speeds through I / O control signals; being compatible with analog encoders and digital encoders; the camera line frequency clock can be adjusted arbitrarily online, and the position of the translation stage and the line frequency clock phase are always kept locked; eliminating the traditional angle interpolation calibration process to achieve online configuration of scanning speed in a larger range; performing ultra-narrow bandpass filtering on the phase-locked frequency to remove interference signals outside the bandpass; providing online feedback and diagnostic functions on the locking status of the motion translation stage.

[0064] The disclosure and other solutions, examples, embodiments, modules, and functional operations described in this document can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this document and their structural equivalents, or any combination thereof. The disclosure and other embodiments can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible, non-volatile computer-readable medium, for execution by a data processing apparatus or to control the operation of the data processing apparatus. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a storage device, a composition of matter that effects a machine-readable propagated signal, or any combination thereof. The term "data processing unit" or "data processing apparatus" includes all devices, equipment, and machines for processing data, including, for example, a programmable processor, a computer, or a plurality of processors or computers. In addition to hardware, the apparatus may also include code that creates an execution environment for a computer program, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or any combination thereof. A propagated signal is an artificially generated signal, such as a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to a suitable receiver device.

[0065] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language (including compiled or interpreted languages) and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or portions of code). A computer program may be deployed for execution on one or more computers, located at one site or distributed across multiple sites and interconnected by a communications network.

[0066] The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special-purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0067] For example, processors suitable for executing computer programs include general-purpose and special-purpose microprocessors, as well as any one or more of any type of digital computer. Typically, a processor will receive instructions and data from read-only memory or random access memory, or both. The essential components of a computer are a processor that executes instructions and one or more memory devices that store instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as magnetic, magneto-optical, or optical disks, or be operatively coupled to receive data from or transfer data to a mass storage device, or both. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media, and storage devices, including, for example, semiconductor memory devices, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and compact disk read-only memory (CD ROM) and digital versatile disk read-only memory (DVD-ROM) disks. The processor and memory may be supplemented by, or incorporated into, special-purpose logic circuitry.

[0068] While this patent document contains many details, they should not be interpreted as limitations on the scope of any invention or the claims, but rather as descriptions of features of particular embodiments of particular inventions. Certain features described in this patent document in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various functions described in the context of a single embodiment may also be implemented separately in multiple embodiments, or in any suitable subcombination. Furthermore, while the features described above may be described as working in certain combinations, or even initially claimed to be so, in some cases one or more features in a claim combination may be removed from the combination, and a claim combination may be directed to a subcombination or a variation of a subcombination.

[0069] Likewise, while operations may be depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, in order to achieve desired results. Furthermore, the separation of various system components in the embodiments of this patent document should not be understood as requiring such separation in all embodiments.

[0070] Only a few implementations and examples are described, and other implementations, enhancements, and variations can be made based on what is described and illustrated in this patent document.

[0071] A first component is directly coupled to a second component when there are no intervening components other than a line, trace, or another medium between the first and second components. A first component is indirectly coupled to a second component when there are intervening components other than a line, trace, or another medium between the first and second components. The term "coupled" and its variations encompass both direct and indirect couplings. Unless otherwise specified, the use of the term "about" is intended to include a range of 10% above and below the value.

[0072] Although several embodiments are provided in this disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered illustrative rather than restrictive, and the present invention is not to be construed as being limited to the details given. For example, various elements or components may be combined or integrated into another system, or certain features may be omitted or not implemented.

[0073] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a portion of code, and the module, program segment, or a portion of code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0074] In addition, without departing from the scope of the present disclosure, the discrete or separate techniques, systems, subsystems, and methods described and illustrated in the various embodiments may be combined or integrated with other systems, modules, techniques, or methods. Other items shown or discussed as coupled may be directly connected, or may be indirectly coupled or communicated through some interface, device, or intermediate component in an electrical, mechanical, or other manner. Other examples of changes, substitutions, and modifications may be determined by those skilled in the art without departing from the spirit and scope disclosed herein.

Claims

1. A clock device controlled by a line frequency phase-locked loop for a pattern wafer defect inspection camera, characterized in that: include: An encoding circuit, a two-frequency dividing circuit, a first filtering circuit, a signal processing circuit, a first frequency dividing circuit, a second filtering circuit, an analog value peak value adjustment circuit, a bidirectional comparator level conditioning circuit, and a phase-locked loop circuit electrically connected in sequence; The encoding circuit is suitable for obtaining the signal of device one, and the signal is sent to device two through the two-frequency division circuit, the first filtering circuit, the signal processing circuit, the first frequency division circuit, the second filtering circuit, the analog peak adjustment circuit, the bidirectional comparator level conditioning circuit, and the phase-locked loop circuit.

2. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: The encoding circuit includes: an analog encoder and / or a digital encoder; The two-frequency divider circuit includes: a first digital-to-analog converter, an analog switch and a dual-channel rising-edge-triggered D-type flip-flop; The analog encoder and the digital encoder are electrically connected to device 1 to respectively obtain corresponding electrical signals and digital signals to be sent to the first digital-to-analog converter; The first digital-to-analog converter, the analog switch, and the dual-channel rising-edge-triggered D-type flip-flop are electrically connected in sequence, and the dual-channel rising-edge-triggered D-type flip-flop is electrically connected to the first filtering circuit; The first digital-to-analog converter is suitable for converting an input signal into a digital signal, and the digital signal is divided into two by the analog switch and the dual-channel rising-edge-triggered D-type flip-flop before being sent to the first filtering circuit.

3. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: The first filtering circuit includes: a first bandpass filter; The first bandpass filter is electrically connected to the two-frequency dividing circuit and the signal processing circuit; The first bandpass filter is adapted to filter the signal for sending to the signal processing circuit.

4. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: The signal processing circuit includes: two second analog-to-digital converters, a processor and a PI filter; The second analog-to-digital converter and the PI filter are electrically connected to the processor, and the processor is electrically connected to the first frequency dividing circuit; The two second analog-to-digital converters are suitable for performing analog-to-digital conversion on the signal respectively to send it to the processor, so that the signal is sent to the first frequency dividing circuit after being processed by the processor and the PI filter for arc tangent, filtering and difference.

5. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: The first frequency dividing circuit includes: a first frequency divider; The first frequency divider is electrically connected to the signal processing circuit and the second filtering circuit; The first frequency divider is adapted to divide the frequency of the signal by several times so as to send the signal to the second filtering circuit.

6. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: The second filtering circuit includes: a second bandpass filter; The second bandpass filter is electrically connected to the first frequency dividing circuit and the analog value peak adjustment circuit; The second bandpass filter is adapted to filter the signal so as to send the signal to the analog peak value adjustment circuit.

7. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: The analog value peak value adjustment circuit includes: a potentiometer; The potentiometer is electrically connected to the second filter circuit and the bidirectional comparator level conditioning circuit; The potentiometer is suitable for adjusting the analog peak value threshold of the signal so as to send the signal to the bidirectional comparator level conditioning circuit.

8. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: The bidirectional comparator level conditioning circuit includes: an inverter; The inverter is electrically connected to the analog peak value adjustment circuit and the phase-locked loop circuit; The inverter is suitable for shaping the signal to convert the analog signal into a digital signal and send it to the phase-locked loop circuit.

9. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: The phase-locked loop circuit includes: a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a second frequency divider; The phase detector, the charge pump, the loop filter, and the voltage-controlled oscillator are electrically connected in sequence, the input end of the second frequency divider is electrically connected to the voltage-controlled oscillator, and the output end of the second frequency divider is electrically connected to the phase detector; The phase detector is electrically connected to the bidirectional comparator level conditioning circuit, and the voltage-controlled oscillator is electrically connected to the image acquisition system.

10. The clock device controlled by a line frequency phase-locked loop of a pattern wafer defect inspection camera according to claim 1, wherein: Also includes: motion control device and image acquisition device; The input end of the encoding circuit is electrically connected to the motion control device, and the output end of the phase-locked loop circuit is electrically connected to the image acquisition device.

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