Out-of-band management cascade circuit and electronic equipment

Abstract

The utility model relates to the technical field of communication circuit design, in particular to an out-of-band management cascade circuit and electronic equipment. Comprising a controller, a front-stage module, a middle-stage module and a rear-stage module, the first group of input ends of the preceding-stage module are connected with the first group of output ends of an external controller, and the first group of output ends of the preceding-stage module are connected with the first group of input ends of the controller; the first group of input ends of the intermediate module are connected with the second group of output ends of the preceding module, and the first group of output ends of the intermediate module are connected with the second group of input ends of the preceding module; the first group of input ends of the rear-stage module are connected with the second group of output ends of the middle-stage module, and the first group of output ends of the rear-stage module are connected with the second group of input ends of the middle-stage module. The size and the area of the PCB and the shell are reduced by reducing the management ports of the out-of-band management design, so that the beneficial effect of reducing the cost is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of communication circuit design, and in particular to an out-of-band management cascade circuit and electronic equipment. Background Art

[0002] In multi-port high-speed communication circuit designs, management ports can be managed in-band or out-of-band. In-band management implements both data transmission and management functions over the same physical connection within a communication circuit design. In this mode, management data and service data share the same transmission channel, necessitating the separation of management information and service information within the data stream. Out-of-band management separates management functions from data transmission within a communication circuit design, implementing them over independent physical connections or dedicated management channels. In this mode, management data and service data are transmitted over separate channels without interfering with each other.

[0003] Among them, each port of out-of-band management is configured with a management port. This design not only increases the number of interfaces and occupies more controller resources, but also increases the size and area of ​​the PCB and the shell, which in turn increases the production design cost. Obviously, this is not conducive to industrial production. Based on this, how to reduce the management ports of the out-of-band management design, and then reduce the size and area of ​​the PCB and the shell, thereby reducing costs, is a technical problem that needs to be solved urgently. Utility Model Content

[0004] In order to overcome the shortcomings of the existing technology, the present application provides an out-of-band management cascade circuit and electronic equipment, which can reduce the size and area of ​​the PCB and the housing by reducing the management port of the out-of-band management design, thereby achieving the beneficial effect of reducing costs.

[0005] The technical solution adopted by this application to solve its technical problems is:

[0006] In a first aspect, the present application provides an out-of-band management cascade circuit, comprising a controller, a front-stage module, a mid-stage module, and a back-stage module;

[0007] The first group of input terminals of the front-stage module is connected to the first group of output terminals of the external controller, and the first group of output terminals of the front-stage module is connected to the first group of input terminals of the controller;

[0008] The first group of input terminals of the intermediate module is connected to the second group of output terminals of the previous module, and the first group of output terminals of the intermediate module is connected to the second group of input terminals of the previous module;

[0009] The first group of input terminals of the rear-stage module is connected to the second group of output terminals of the intermediate-stage module, and the first group of output terminals of the rear-stage module is connected to the second group of input terminals of the intermediate-stage module.

[0010] Optionally, the front-stage module includes a first communication chip, a first capacitor group, and a second capacitor group;

[0011] The first group of input terminals of the first communication chip and one end of the first capacitor group are connected, and the other end of the first capacitor group is connected to the first group of output terminals of the controller, and the first group of output terminals of the first communication chip are connected to the first group of input terminals of the controller;

[0012] The second group of output terminals of the first communication chip is connected to the first group of input terminals of the intermediate module, the second group of input terminals of the first communication chip is connected to one end of the second capacitor group, and the other end of the second capacitor group is connected to the first group of output terminals of the intermediate module.

[0013] Optionally, the intermediate module includes a second-level unit and a third-level unit;

[0014] The first group of input terminals of the second stage unit is connected to the second group of output terminals of the first communication chip, and the first group of output terminals of the second stage unit is connected to the other end of the second capacitor group;

[0015] The second group of output terminals of the second stage unit is connected to the first group of input terminals of the third stage unit, and the second group of input terminals of the second stage unit is connected to the first group of output terminals of the third stage unit;

[0016] The second group of output terminals of the third-stage unit is connected to the first group of input terminals of the subsequent-stage module, and the second group of input terminals of the third-stage unit is connected to the first group of output terminals of the subsequent-stage module.

[0017] Optionally, the second-stage unit includes a second communication chip, a third capacitor group, and a fourth capacitor group;

[0018] The first group of input terminals of the second communication chip is connected to one end of the third capacitor group, and the other end of the third capacitor group is connected to the second group of output terminals of the first communication chip;

[0019] The second group of output ends of the second communication chip is connected to the first group of input ends of the third-stage unit, the second group of input ends of the second communication chip is connected to one end of the fourth capacitor group, and the other end of the fourth capacitor group is connected to the first group of output ends of the third-stage unit.

[0020] Optionally, the third-level unit includes a third communication chip, a fifth capacitor group, and a sixth capacitor group;

[0021] The first group of input terminals of the third communication chip is connected to one end of the fifth capacitor, the other end of the fifth capacitor is connected to the second group of output terminals of the second communication chip, and the first group of output terminals of the third communication chip is connected to the other end of the fourth capacitor group;

[0022] The second group of output ends of the third communication chip is connected to the first group of input ends of the subsequent module, the second group of input ends of the third communication chip is connected to one end of the sixth capacitor group, and the other end of the sixth capacitor group is connected to the first group of output ends of the subsequent module.

[0023] Optionally, the post-stage module includes a fourth communication chip and a seventh capacitor group;

[0024] The first group of input terminals of the fourth communication chip is connected to one end of the seventh capacitor group, and the other end of the seventh capacitor group is connected to the second group of output terminals of the third communication chip;

[0025] The first output terminal of the fourth communication chip is connected to the other end of the sixth capacitor group;

[0026] The second group of output terminals and the second group of input terminals of the fourth communication chip are left floating.

[0027] Optionally, the first communication chip, the second communication chip, the third communication chip and the fourth communication chip are all of model VN1083.

[0028] Optionally, the first capacitor group, the second capacitor group, the third capacitor group, the fourth capacitor group, the fifth capacitor group, the sixth capacitor group and the sixth capacitor group serve as coupling capacitors on high-speed differential lines, used to isolate the DC component of high-speed signals between connected communication chips.

[0029] Optionally, the controller is a network switching chip of model 98DX336S-A1.

[0030] In a second aspect, the present application provides an electronic device equipped with the above-mentioned out-of-band management cascade circuit.

[0031] The beneficial effects of the present application are: the front-stage module is connected to the controller, and the intermediate module and the rear-stage module are cascaded. The controller sends management information through its first group of output ports. The frame header of the management information contains the ID information of the communication chip. The management information is first input into the communication chip in the front-stage module to determine whether the ID information contained in the management chip is consistent with the chip. If the ID does not match, the front-stage module acts as a transparent transmission and does not execute the controller's instructions, and sends it to the next-level module; if the ID matches, the communication chip of the ID executes the controller's instructions, and the instruction content includes but is not limited to querying the current working status of the return port, the current temperature of the communication chip, etc., that is, using one management port to manage multiple ports, which neither occupies data bandwidth nor increases the number of management ports, thereby reducing the size of the device and the PCB and the casing, thereby achieving the beneficial effect of saving device costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of module connections of an out-of-band management cascade circuit provided in an embodiment of the present application;

[0033] Figure 2 This is a circuit schematic diagram of a four-port out-of-band management cascade circuit provided in an embodiment of the present application;

[0034] Figure 3 Schematic diagram of a controller used in a four-port out-of-band management cascade circuit provided in an embodiment of the present application;

[0035] Figure numerals: 1, front-stage module; 2, middle-stage module; 3, back-stage module. DETAILED DESCRIPTION

[0036] The present application is further described below with reference to the accompanying drawings and examples.

[0037] The following will clearly and completely describe the concept, specific structure and technical effects of this application in combination with the embodiments and drawings, so as to fully understand the purpose, characteristics and effects of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application. In addition, all the connection / connection relationships involved in the patent do not refer to the direct connection of components, but refer to the formation of a better connection structure by adding or reducing connection accessories according to the specific implementation situation. The various technical features created in this application can be combined interactively without conflicting with each other.

[0038] Reference Figure 1 , Figure 1 The module connection diagram of the out-of-band management cascade circuit provided in the embodiment of the present application includes a controller US1A, a front-stage module 1, a mid-stage module 2, and a back-stage module 3, which are described in detail below:

[0039] Regarding the front-end module 1: the first group of input terminals of the front-end module 1 is connected to the first group of output terminals of the external controller US1A, and the first group of output terminals of the front-end module 1 is connected to the first group of input terminals of the controller US1A.

[0040] Regarding the intermediate module 2 : the first group of input terminals of the intermediate module 2 is connected to the second group of output terminals of the front-stage module 1 , and the first group of output terminals of the intermediate module 2 is connected to the second group of input terminals of the front-stage module 1 .

[0041] Regarding the rear-stage module 3 : the first group of input terminals of the rear-stage module 3 is connected to the second group of output terminals of the intermediate module 2 , and the first group of output terminals of the rear-stage module 3 is connected to the second group of input terminals of the intermediate module 2 .

[0042] Specifically, the front-stage module 1 is connected to the controller US1A, and is cascaded with the intermediate module 2 and the rear-stage module 3. The controller US1A sends management information through its first group of output ports. The frame header of the management information contains the ID information of the communication chip. The management information is first input into the communication chip in the front-stage module 1 to determine whether the ID information contained in the management chip is consistent with the chip. If the ID does not match, the front-stage module 1 acts as a transparent transmission and does not execute the instructions of the controller US1A, and sends it to the next-level module; if the ID matches, the communication chip of the ID executes the instructions of the controller US1A. The instruction content includes but is not limited to querying the current working status of the return port, the current temperature of the communication chip, etc., that is, using one management port to manage multiple ports, which neither occupies data bandwidth nor increases the number of management ports, thereby reducing the size of the device as well as the PCB and the casing, thereby achieving the beneficial effect of saving device costs.

[0043] The intermediate module 2 includes multiple levels of units, each of which includes a communication chip. This application uses a four-port example, with the front-stage module 1 representing the first level, the intermediate module including the second and third levels, and the rear-stage module 3 representing the fourth level. Within the range of the number of ports corresponding to the management port rate of the controller US1A, the system can be adjusted to eight or sixteen cascade levels based on actual needs, i.e., by expanding the number of cascade chips included in the intermediate module.

[0044] Reference Figure 2 , Figure 2 This is a circuit schematic diagram of a four-port out-of-band management cascade circuit provided in an embodiment of the present application. The four ports include four-stage units. In the embodiment of the present application, the front-stage module 1 includes the first stage, the middle-stage module 2 includes the second and third stages, and the back-stage module 3 includes the fourth stage. Figure 2 To explain in detail:

[0045] Optionally, the front-stage module 1 includes a first communication chip U1B, a first capacitor group (VC1 and VC2) and a second capacitor group (VC3 and VC4);

[0046] The first group of input terminals of the first communication chip U1B is connected to one end of the first capacitor group (VC1 and VC2), and the other end of the first capacitor group (VC1 and VC2) is connected to the first group of output terminals of the controller US1A, and the first group of output terminals of the first communication chip U1B is connected to the first group of input terminals of the controller US1A;

[0047] The second group of output terminals of the first communication chip U1B is connected to the first group of input terminals of the intermediate module 2, the second group of input terminals of the first communication chip U1B is connected to one end of the second capacitor group (VC3 and VC4), and the other end of the second capacitor group (VC3 and VC4) is connected to the first group of output terminals of the intermediate module 2.

[0048] Optionally, the intermediate module 2 includes a second-level unit and a third-level unit;

[0049] The first group of input terminals of the second stage unit is connected to the second group of output terminals of the first communication chip U1B, and the first group of output terminals of the second stage unit is connected to the other end of the second capacitor group (VC3 and VC4);

[0050] The second group of output terminals of the second stage unit is connected to the first group of input terminals of the third stage unit, and the second group of input terminals of the second stage unit is connected to the first group of output terminals of the third stage unit;

[0051] The second group of output terminals of the third-stage unit is connected to the first group of input terminals of the subsequent-stage module 3 , and the second group of input terminals of the third-stage unit is connected to the first group of output terminals of the subsequent-stage module 3 .

[0052] Optionally, the second-stage unit includes a second communication chip U2B, a third capacitor group (VC5 and VC6), and a fourth capacitor group (VC7 and VC8);

[0053] The first group of input terminals of the second communication chip U2B is connected to one end of the third capacitor group (VC5 and VC6), and the other end of the third capacitor group (VC5 and VC6) is connected to the second group of output terminals of the first communication chip U1B;

[0054] The second group of output ends of the second communication chip U2B is connected to the first group of input ends of the third-stage unit, the second group of input ends of the second communication chip U2B is connected to one end of the fourth capacitor group (VC7 and VC8), and the other end of the fourth capacitor group (VC7 and VC8) is connected to the first group of output ends of the third-stage unit.

[0055] Optionally, the third-level unit includes a third communication chip U3B, a fifth capacitor group (VC9 and VC10) and a sixth capacitor group (VC11 and VC12);

[0056] The first group of input terminals of the third communication chip U3B is connected to one end of the fifth capacitor, the other end of the fifth capacitor is connected to the second group of output terminals of the second communication chip U2B, and the first group of output terminals of the third communication chip U3B is connected to the other end of the fourth capacitor group (VC7 and VC8);

[0057] The second group of output terminals of the third communication chip U3B is connected to the first group of input terminals of the subsequent module 3, the second group of input terminals of the third communication chip U3B is connected to one end of the sixth capacitor group (VC11 and VC12), and the other end of the sixth capacitor group (VC11 and VC12) is connected to the first group of output terminals of the subsequent module 3.

[0058] Optionally, the post-stage module 3 includes a fourth communication chip U4B and a seventh capacitor group (VC13 and VC14);

[0059] The first group of input terminals of the fourth communication chip U4B is connected to one end of the seventh capacitor group (VC13 and VC14), and the other end of the seventh capacitor group (VC13 and VC14) is connected to the second group of output terminals of the third communication chip U3B;

[0060] The first output terminal of the fourth communication chip U4B is connected to the other end of the sixth capacitor group (VC11 and VC12);

[0061] The second group of output terminals and the second group of input terminals of the fourth communication chip U4B are left floating.

[0062] Specifically, the front-stage module 1, the mid-stage module 2 and the rear-stage module 3 include multiple levels of units, each level of unit includes a communication chip, and each communication chip is provided with corresponding ID information; except that the last level unit corresponding to the rear-stage module 3 includes a group of capacitors (in this application, a capacitor group includes two capacitors), each level of unit includes two groups of capacitors, which are used as coupling capacitors on high-speed differential lines to isolate the DC component of high-speed signals between connected communication chips.

[0063] In the embodiment of the present application, in order to improve the solution, it is further disclosed that the first communication chip U1B, the second communication chip U2B, the third communication chip U3B and the fourth communication chip U4B are all model VN1083.

[0064] Reference Figure 3 , Figure 3 This is a schematic diagram of a controller used in a four-port out-of-band management cascade circuit provided in an embodiment of the present application. The controller US1A used is a network switching chip model 98DX336S-A1.

[0065] Specifically, the management rate of the controller US1A with model 98DX336S-A1 is 2.5Gbps. If the rate of each management port is required to be 100Mbps, then theoretically up to 25 ports can be cascaded. Relevant personnel can adjust the management port rate requirements or the controller US1A management rate according to actual needs, and there is no limit here.

[0066] In a second aspect, the present application provides an electronic device equipped with the above-mentioned out-of-band management cascade circuit.

[0067] The above is a specific description of the preferred implementation of the present application, but the invention of the present application is not limited to the described embodiments. Technical personnel familiar with the art can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. An out-of-band management cascade circuit, characterized in that: Including controller, front-end module, middle-end module and back-end module; The first group of input terminals of the front-stage module is connected to the first group of output terminals of the external controller, and the first group of output terminals of the front-stage module is connected to the first group of input terminals of the controller; The first group of input terminals of the intermediate module is connected to the second group of output terminals of the previous module, and the first group of output terminals of the intermediate module is connected to the second group of input terminals of the previous module; The first group of input terminals of the rear-stage module is connected to the second group of output terminals of the intermediate-stage module, and the first group of output terminals of the rear-stage module is connected to the second group of input terminals of the intermediate-stage module.

2. The out-of-band management cascade circuit according to claim 1, characterized in that: The front-stage module includes a first communication chip, a first capacitor group and a second capacitor group; The first group of input terminals of the first communication chip and one end of the first capacitor group are connected, and the other end of the first capacitor group is connected to the first group of output terminals of the controller, and the first group of output terminals of the first communication chip are connected to the first group of input terminals of the controller; The second group of output terminals of the first communication chip is connected to the first group of input terminals of the intermediate module, the second group of input terminals of the first communication chip is connected to one end of the second capacitor group, and the other end of the second capacitor group is connected to the first group of output terminals of the intermediate module.

3. The out-of-band management cascade circuit according to claim 2, wherein: The intermediate module includes a second-level unit and a third-level unit; The first group of input terminals of the second stage unit is connected to the second group of output terminals of the first communication chip, and the first group of output terminals of the second stage unit is connected to the other end of the second capacitor group; The second group of output terminals of the second stage unit is connected to the first group of input terminals of the third stage unit, and the second group of input terminals of the second stage unit is connected to the first group of output terminals of the third stage unit; The second group of output terminals of the third-stage unit is connected to the first group of input terminals of the subsequent-stage module, and the second group of input terminals of the third-stage unit is connected to the first group of output terminals of the subsequent-stage module.

4. The out-of-band management cascade circuit according to claim 3, wherein: The second-stage unit includes a second communication chip, a third capacitor group and a fourth capacitor group; The first group of input terminals of the second communication chip is connected to one end of the third capacitor group, and the other end of the third capacitor group is connected to the second group of output terminals of the first communication chip; The second group of output ends of the second communication chip is connected to the first group of input ends of the third-stage unit, the second group of input ends of the second communication chip is connected to one end of the fourth capacitor group, and the other end of the fourth capacitor group is connected to the first group of output ends of the third-stage unit.

5. The out-of-band management cascade circuit according to claim 4, characterized in that: The third-level unit includes a third communication chip, a fifth capacitor group and a sixth capacitor group; The first group of input terminals of the third communication chip is connected to one end of the fifth capacitor, the other end of the fifth capacitor is connected to the second group of output terminals of the second communication chip, and the first group of output terminals of the third communication chip is connected to the other end of the fourth capacitor group; The second group of output ends of the third communication chip is connected to the first group of input ends of the subsequent module, the second group of input ends of the third communication chip is connected to one end of the sixth capacitor group, and the other end of the sixth capacitor group is connected to the first group of output ends of the subsequent module.

6. The out-of-band management cascade circuit according to claim 5, characterized in that: The post-stage module includes a fourth communication chip and a seventh capacitor group; The first group of input terminals of the fourth communication chip is connected to one end of the seventh capacitor group, and the other end of the seventh capacitor group is connected to the second group of output terminals of the third communication chip; The first output terminal of the fourth communication chip is connected to the other end of the sixth capacitor group; The second group of output terminals and the second group of input terminals of the fourth communication chip are left floating.

7. The out-of-band management cascade circuit according to claim 6, characterized in that: The first communication chip, the second communication chip, the third communication chip and the fourth communication chip are all of model VN1083.

8. The out-of-band management cascade circuit according to claim 6, wherein: The first capacitor group, the second capacitor group, the third capacitor group, the fourth capacitor group, the fifth capacitor group, the sixth capacitor group and the sixth capacitor group serve as coupling capacitors on high-speed differential lines, and are used to isolate the DC component of high-speed signals between connected communication chips.

9. The out-of-band management cascade circuit according to claim 6, characterized in that: The controller is a network switching chip of model 98DX336S-A1.

10. An electronic device, characterized in that: The device is equipped with the out-of-band management cascade circuit according to any one of claims 1 to 9.

Images