Automatic memory testing device

Abstract

The utility model discloses an automatic testing device for a memory. The automatic testing device comprises an upper computer, HUB equipment, power supply equipment and a plurality of control devices, wherein the HUB equipment is used for expanding a communication path of the upper computer and a power supply path of the power supply equipment; each expanded communication path and each expanded power supply path are electrically connected with a control device together, each control device can further expand the communication path and the power supply path, and the further expanded paths are respectively connected with the corresponding to-be-tested memories. Through the connection of the devices and the equipment, the function that a single upper computer can automatically test a plurality of memories at the same time is realized, the dependence on manpower is greatly reduced, the complete program control in the test process and the automatic switching of the tested memory equipment in the test process are realized, and the test efficiency is improved. The test efficiency and the test capacity are greatly improved, the operation error rate is reduced, and the reliability of a test result is improved.

Description

Technical Field

[0001] The utility model relates to the field of memory testing, in particular to an automatic memory testing device. Background Art

[0002] Memory ICs are electronic components used for storing and transmitting data and are widely used in various electronic products, including computers, mobile phones, and servers. After memory IC production is complete, they need to be mounted on the complete equipment of various control platforms for comprehensive verification, including functional testing, performance testing, and reliability testing. Because verification results require a large amount of verification data to support them, data collection and analysis are required across a large number of devices to reach a verification conclusion. Currently, memory testing can almost only be performed manually, resulting in low memory testing efficiency, low test capacity, high test error rates, low data reliability, and high testing costs. In this technological context, automated testing of memory ICs is particularly important. Utility Model Content

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an automated memory test device that can simultaneously perform automated testing of hundreds of memory devices on a single computer, as well as automatically switch between the memory devices under test during testing. This significantly improves test efficiency, test capacity, and test reliability, significantly reduces reliance on manual labor, and lowers manual testing costs.

[0004] The memory automatic testing device according to an embodiment of the present invention includes:

[0005] Host computer;

[0006] A HUB device, the HUB device being electrically connected to the host computer and used to extend the communication path of the host computer;

[0007] A power supply device, the power supply device being electrically connected to the HUB device and configured to supply power to the HUB device, and the HUB device being further configured to extend a power supply path of the power supply device;

[0008] Several control devices are provided, each of which is provided with a power supply input interface and several power supply output interfaces. Each of the control devices is also provided with a communication input interface and several communication output interfaces. The power supply input interface and the communication input interface are both electrically connected to the HUB device, and each of the power supply output interface and each of the communication output interfaces are used to electrically connect to the corresponding memory to be tested.

[0009] According to some embodiments of the present invention, it is characterized in that the control device includes:

[0010] a control chip, the control chip being electrically connected to the communication input interface;

[0011] A plurality of load voltage switches, wherein the plurality of load voltage switches correspond one to one with the plurality of power output interfaces;

[0012] The input end of each load voltage switch is electrically connected to the power supply input interface, the output end of each load voltage switch is electrically connected to the corresponding power supply output interface, and the control end of each load voltage switch is electrically connected to the control chip.

[0013] According to some embodiments of the present invention, it is characterized in that the control device further includes:

[0014] A plurality of communication signal switches, wherein the input end of each communication signal switch is electrically connected to the communication input interface, the output end of each communication signal switch is electrically connected to the corresponding communication output interface, and the control end of each communication signal switch is electrically connected to the control chip.

[0015] According to some embodiments of the present invention, the number of the communication signal switches is half the number of the communication output interfaces, and each of the communication signal switches corresponds to two of the communication output interfaces.

[0016] According to some embodiments of the present invention, it is characterized in that the control device further includes:

[0017] a plurality of voltage feedback circuits, wherein the plurality of voltage feedback circuits correspond one-to-one to the plurality of power output interfaces;

[0018] The input end of each voltage feedback circuit is electrically connected to the corresponding power supply output interface, and the output end of each voltage feedback circuit is electrically connected to the control chip.

[0019] According to some embodiments of the present invention, it is characterized in that the control device further includes:

[0020] a plurality of signal feedback circuits, wherein the plurality of signal feedback circuits correspond one-to-one to the plurality of communication output interfaces;

[0021] The input end of each of the signal feedback circuits is electrically connected to the communication output interface, and the output end of each of the signal feedback circuits is electrically connected to the control chip.

[0022] According to some embodiments of the present invention, it is characterized in that the control device further includes:

[0023] a plurality of power supply status indicator lights, wherein the plurality of power supply status indicator lights correspond one-to-one to the plurality of voltage feedback circuits;

[0024] Each power supply status indicator light is electrically connected to the corresponding voltage feedback circuit.

[0025] According to some embodiments of the present invention, it is characterized in that the control device further includes:

[0026] a plurality of signal status indicator lights, wherein the plurality of signal status indicator lights correspond one-to-one to the plurality of signal feedback circuits;

[0027] Each signal status indicator light is electrically connected to the corresponding signal feedback circuit.

[0028] According to some embodiments of the present invention, it is characterized in that the voltage feedback circuit and the control chip are connected in an IIC communication manner; the signal feedback circuit and the control chip are connected in an IIC communication manner.

[0029] According to the memory automation testing device of the embodiment of the present utility model, there are at least the following beneficial effects: by adopting a HUB device to expand the communication path of the host computer and the power supply path of the power supply device, and providing a plurality of control devices, each of which controls a communication path and a power supply path respectively, and further expanding the two paths, a single host computer can realize the function of automatically testing multiple memories at the same time, greatly reducing the dependence on manual labor; and by adopting a control chip, complete program control of the test process and automatic switching of the tested memory device during the test process are realized, which greatly improves the test efficiency and test capacity, reduces the operation error rate, and improves the reliability of the test results.

[0030] Additional aspects and advantages of the present invention will be given in part in the following description and will become apparent from the following description or learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0032] Figure 1 This is a module block diagram of a memory automatic test device according to an embodiment of the utility model;

[0033] Figure 2 for Figure 1 The module block diagram of the control device of the memory automatic test device is shown.

[0034] Host computer 100, HUB 200, power supply equipment 300, control device 400, power supply input interface 410, power supply output interface 420, communication input interface 430, communication output interface 440, control chip 450, load voltage switch 460, communication signal switch 470, voltage feedback circuit 480, power supply status indicator light 481, signal feedback circuit 490, signal status indicator light 491, memory 500. DETAILED DESCRIPTION

[0035] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0036] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0037] In the description of this utility model, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and is not to be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0038] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0039] The following is combined with Figure 1-2 , a detailed description of the memory automatic testing device of an embodiment of the present utility model is given.

[0040] Reference Figure 1 and Figure 2In an embodiment of the present invention, a memory automation test device is proposed, comprising: a host computer 100, a HUB device 200, a power supply device 300, and a plurality of control devices 400. The HUB device 200 is electrically connected to the host computer 100 and is used to extend the communication path of the host computer 100; the power supply device 300 is electrically connected to the HUB device 200 and is used to supply power to the HUB device 200, and the HUB device 200 is also used to extend the power supply path of the power supply device 300; each control device 400 is provided with a power input interface 410 and a plurality of power output interfaces 420, and each control device 400 is also provided with a communication input interface 430 and a plurality of communication output interfaces 440. The power input interface 410 and the communication input interface 430 are both electrically connected to the HUB device 200, and each power output interface 420 and each communication output interface 440 are used to connect to a corresponding memory device 500 to be tested. Specifically, in this embodiment, the host computer 100 is used to implement memory test functions such as program downloading, command sending, data transmission, status display, and data recording during the test process, and a computer with the above functions can be used. The HUB device 200 is used to expand a communication path of the host computer 100 and a power supply path of the power supply device 300 into A paths (A≥20), and the HUB device 200 adopts an active HUB, which not only provides a transmission path for data signals, but also has the functions of regenerating, concentrating, and enhancing signals, so that the HUB device 200 can support longer cable transmission distances, ensure the stability and reliability of data transmission, and expand the coverage of the transmission network, that is, it can expand more transmission paths, thereby testing more memory devices 500 at the same time. The power supply device 300 is used to supply power to the HUB device 200 and each power supply path expanded by the HUB device 200. The number of the control device 400, the communication transmission path expanded by the HUB device 200, and the power supply path expanded by the HUB device 200 is A. At the same time, each communication path and each power supply path corresponds to a control device 400, that is, each control device 400 is respectively provided with a communication input interface 430 for connecting to an expanded communication path, and a power supply input interface 410 for connecting to an expanded power supply path; and the control device can further expand each communication path and each power supply path expanded by the HUB device 200 to N (N≥10), that is, in each control device 400, one communication input interface 430 is correspondingly provided with N communication output interfaces 440, and one power supply input interface 410 is correspondingly provided with N power supply output interfaces 420, thereby achieving the effect that one host computer 100 can automatically test A*N memories 500 at the same time, where A≥20 and N≥10, so that one host computer 100 can control and test at least 200 memories 500 at the same time.When this embodiment is running, the host computer first sends the test instructions and test program to the HUB device 200 through a communication path. At the same time, the power supply device supplies power to the HUB device 200 through a power supply path. The HUB device 200 extends a communication path to A and extends a power supply path to A. Then, the test program and power are input to A control devices 400 through the above-mentioned extended communication path and power supply path respectively. Then, each control device 400 expands the input path N times to control the communication and power supply for the test output of N memories to be tested, thereby achieving the technical effect that one host computer 100 can simultaneously control the test of A*N memories 500.

[0041] Reference Figure 2Furthermore, in some embodiments of the present invention, the control device 400 also includes a control chip 450 and a plurality of load voltage switches 460. The control chip 450 is electrically connected to the communication input interface 430; the plurality of load voltage switches 460 correspond one-to-one to the plurality of power output interfaces 420; the input end of each load voltage switch 460 is electrically connected to the power input interface 410, the output end of each load voltage switch 460 is electrically connected to the corresponding power output interface 420, and the control end of each load voltage switch 460 is electrically connected to the control chip 450. Specifically, in this embodiment, the control chip can be a microcontroller unit (MCU), i.e., a single-chip microcomputer, configured to control the opening and closing of each load voltage switch 460 according to a host computer control signal input from the communication input interface 430. In addition, the electrical connection between the communication input interface 430 and the control chip 450 enables the function of downloading programs from the host computer 100 to the control chip 450 for program optimization and upgrading, thereby improving the convenience of program optimization and upgrading. There are N load voltage switches 460 (N ≥ 10), which are controllable switches. That is, the load voltage switches 460 should be able to be controlled to open or close by external signals. Therefore, the load voltage switches 460 are provided with three ports: an input port, an output port, and a control port. The input port of the load voltage switch 460 is electrically connected to the power input interface 410, and the output port of the load voltage switch 460 is electrically connected to the corresponding power output interface 420. Therefore, each load voltage switch 460 can control the connection and disconnection between its corresponding power output interface 420 and the power input interface 410; the control port of the load voltage switch 460 is electrically connected to the IO port on the control chip 450, so that the control chip 450 can control the on / off state of the load voltage switch 460. The above structure can realize the function of automatic power supply switching. When powering, first, the power supply path expanded by the HUB device 200 simultaneously transmits power to N load voltage switches 460 through the power supply input interface 410. After passing through the N load voltage switches 460, N power supply paths that can be controlled by the control chip 450 for IO control are separated. The control chip 450 transmits instructions to the IO port according to the test program downloaded from the communication input interface 430. The instructions are input through the control end of the load voltage switch 460 connected to the IO port, thereby controlling the on and off state of the load voltage switch 460. Subsequently, each power supply path separated by the load voltage switch 460 is supplied to the corresponding memory device 500 through the corresponding power supply output interface 420, so as to realize independent power supply and programmable power supply switching of each memory device 500 during testing.

[0042] Reference Figure 2Furthermore, in some embodiments of the present invention, the control device 400 further includes: a plurality of communication signal switches 470, wherein the input end of each communication signal switch 470 is electrically connected to the communication input interface 430, the output end of each communication signal switch 470 is electrically connected to the corresponding communication output interface 440, and the control end of each communication signal switch 470 is electrically connected to the control chip 450. Specifically, in this embodiment, the control chip 450 can control the communication signal output state of each communication signal switch 470 according to the host computer control signal input by the communication input interface 430. The communication signal output state of the communication signal switch 470 can determine the communication signal transmission state between the corresponding communication output interface 440 and the communication input interface 430, thereby realizing the automatic communication switching function during the memory test process. When transmitting communication signals, first, the communication path expanded by the HUB device 200 transmits the communication signal to the control chip 450 and all communication signal switches 470 simultaneously through the communication input interface 430. After passing through several communication signal switches 470, N communication signals that can be controlled by the control chip for IO are separated. The control chip 450 transmits instructions to the IO port according to the test program downloaded from the communication input interface 430. The instructions are then input through the control end of the communication signal switch 470 connected to the IO port, thereby controlling the communication signal output state of the communication signal switch 470. Subsequently, each communication path separated by the communication signal switch 470 is bidirectionally communicated with the corresponding memory device 500 through the corresponding communication output interface 440, so as to realize independent communication and programmable communication switching of each memory device 500 during testing.

[0043] Reference Figure 2Furthermore, in some embodiments of the present invention, the number of communication signal switches 470 is half the number of communication output interfaces 440, and each communication signal switch 470 corresponds to two communication output interfaces 440. Specifically, in this embodiment, the communication signal switch 470 uses a dual-output communication signal switch (such as CD4066 or RS2102, etc.), which can achieve dual-output through a single input, and simultaneously process and transmit two signals. Since the number of communication output interfaces 440 is N, the number of communication signal switches 470 is N / 2. Each communication signal switch 470 is respectively provided with an input port, two output ports, and a control port, wherein the input port of the communication signal switch 470 is electrically connected to the communication input interface 430, the two output ports of the communication signal switch 470 are respectively electrically connected to the two communication output ports 440, and the control port of the communication signal switch 470 is electrically connected to the IO port of the control chip 450. By adopting the dual-output communication signal switch 470, it has the advantages of realizing multi-channel signal processing, low power consumption, fast response, and improving the overall performance and stability of the system. It is convenient for efficient management and switching of two independent signal paths according to the test program during the test process, thereby ensuring the reliability and stability of signal transmission.

[0044] Reference Figure 2 Furthermore, in some embodiments of the present invention, the control device 400 further includes: a plurality of voltage feedback circuits 480, each corresponding to a plurality of power output interfaces 420; the input end of each voltage feedback circuit 480 is electrically connected to the corresponding power output interface 420, and the output end of each voltage feedback circuit 480 is electrically connected to the control chip 450. Specifically, in this embodiment, since there are N power output interfaces 420, there are also N voltage feedback circuits 480. The voltage feedback circuits 480 are used to collect, monitor, and record the output voltage values ​​of each power output interface 420 in real time, and to feed the collected voltage values ​​back to the control chip 450 in real time. The control chip 450 then combines the obtained feedback voltage values ​​with the test program to further transmit control instructions to the load voltage switch 460, thereby implementing closed-loop negative feedback control of the output voltage values ​​of each power output interface 420, thereby improving the stability and output accuracy of the system.

[0045] Reference Figure 2Furthermore, in some embodiments of the present invention, the control device 400 further includes: a plurality of signal feedback circuits 490, each corresponding to a plurality of communication output interfaces 440; the input end of each signal feedback circuit 490 is electrically connected to the communication output interface 440, and the output end of each signal feedback circuit 490 is electrically connected to the control chip 450. Specifically, in this embodiment, since there are N communication output interfaces 440, there are also N signal feedback circuits 490. The signal feedback circuits 490 are used to collect, monitor, and record the communication signals output by each communication output interface 440 in real time, and to feed back the collected communication signals to the control chip 450 in real time. The control chip 450 then combines the obtained feedback communication signals with the test program to further transmit control instructions to the communication signal switch 470, thereby realizing closed-loop negative feedback control of the output control signals of each communication output interface 440, thereby improving the stability and output accuracy of the system.

[0046] Reference Figure 2Furthermore, in some embodiments of the present invention, the control device 400 further includes: a plurality of power supply status indicator lights 481, each of which corresponds to a plurality of voltage feedback circuits 480 or a plurality of power supply output interfaces 420; each power supply status indicator light 481 is electrically connected to the corresponding voltage feedback circuit 480 or the corresponding communication output interface 440. Specifically, in this embodiment, the power supply status indicator light 481 can be a single light-emitting diode, or a light-emitting circuit composed of a single or multiple light-emitting diodes can be designed to indicate to the operator the current power supply status of the power supply output interface 420 during the test process, that is, whether power is supplied or the power supply is abnormal. For example, if the current power supply output interface 420 is in a normal power supply state, the corresponding power supply status indicator light 481 is always on; if the power supply output interface 420 has no output voltage, the corresponding power supply status indicator light 481 is always off; if the current power supply output interface 420 output voltage is abnormal (the voltage is too high or too low), the corresponding power supply status indicator light 481 flashes. When the power status indicator light 481 is electrically connected to the corresponding voltage feedback circuit 480: When performing a memory function test, the output voltage of the corresponding power output interface 420 is first collected by the voltage feedback circuit 480, and then the collected output voltage is transmitted to the power status indicator light 481 in the form of voltage, current, or a digital signal. The power status indicator light 481 presents different lighting states according to the signal, thereby achieving the technical effect of indicating to the operator the current power status of the power output interface 420. When the power status indicator light 481 is electrically connected to the corresponding power output interface 420: When performing a memory function test, the output voltage of the corresponding power output interface 420 is first collected by the lighting circuit of the power status indicator light 481, and then the collected output voltage is presented in different lighting states, thereby achieving the technical effect of indicating to the operator the current power status of the power output interface 420.

[0047] Reference Figure 2Furthermore, in some embodiments of the present invention, the control device 400 further includes: a plurality of signal status indicator lights 491, each of which corresponds to a plurality of the signal feedback circuits or a plurality of the communication output interfaces 440; each of the signal status indicator lights 491 is electrically connected to a corresponding signal feedback circuit 490 or a corresponding communication output interface 440. Specifically, in this embodiment, the signal status indicator light 491 can be a single light-emitting diode, or a light-emitting circuit composed of a single or multiple light-emitting diodes can be designed to indicate the current communication status of the communication output interface 440 to the operator during the test process, that is, whether the communication is in progress or the communication is abnormal. For example, if the current communication output interface 440 is in a normal communication state, the corresponding communication status indicator light 491 is always on; if the communication output interface 440 does not output a communication signal, the corresponding signal status indicator light 491 is always off; if the current communication signal output by the communication output interface 440 is abnormal, the corresponding signal status indicator light 491 flashes. When the signal status indicator light 491 is electrically connected to the corresponding signal feedback circuit 480: When performing a memory function test, the signal feedback circuit 490 first collects the communication signal output by the corresponding communication output interface 440, and then transmits the collected communication signal to the signal status indicator light 491 in the form of voltage, current, or digital signal. The signal status indicator light 491 presents different lighting states according to the signal, thereby achieving the technical effect of indicating to the operator the current communication status of the communication output interface 440. When the signal status indicator light 491 is electrically connected to the corresponding communication output interface 440: When performing a memory function test, the lighting circuit of the signal status indicator light 481 first collects the communication signal output by the corresponding communication output interface 420, and then presents different lighting states according to the collected communication signal, thereby achieving the technical effect of indicating to the operator the current communication status of the communication output interface 440.

[0048] Reference Figure 2 Furthermore, in some embodiments of the present invention, the voltage feedback circuit 480 and the control chip 450 are connected using IIC communication. Specifically, in this embodiment, the use of IIC communication between the voltage feedback circuit 480 and the control chip 450 can significantly reduce power consumption and cost. Only two lines are required for communication (SDA and SCL), which can greatly reduce the number of pins occupied on the control chip 450 and save hardware resources. In addition, the timing of the IIC protocol is relatively simple, easy to implement and debug, and more simple and flexible, thereby further improving the scalability of the system. At the same time, the IIC bus has functions such as automatic addressing, high-speed and low-speed device synchronization and arbitration, which ensure the reliability and stability of data transmission between the voltage feedback circuit 480 and the control chip 450.

[0049] Reference Figure 2 Furthermore, in some embodiments of the present invention, an IIC communication connection is adopted between the signal feedback circuit 490 and the control chip 450. Specifically, in this embodiment, the IIC communication connection between the signal feedback circuit 490 and the control chip 450 can significantly reduce power consumption and cost. Only two lines are required for communication (SDA and SCL), which can greatly reduce the number of pins occupied on the control chip 450 and save hardware resources. In addition, the timing of the IIC protocol is relatively simple, easy to implement and debug, and more simple and flexible, thereby further improving the scalability of the system. At the same time, the IIC bus has functions such as automatic addressing, high-speed and low-speed device synchronization and arbitration, which ensure the reliability and stability of data transmission between the signal feedback circuit 490 and the control chip 450.

[0050] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the scope of knowledge possessed by ordinary technicians in the technical field without departing from the scope of the present invention.

Claims

1. A memory automatic testing device, characterized in that: include: Host computer; A HUB device, the HUB device being electrically connected to the host computer and used to extend the communication path of the host computer; A power supply device, the power supply device being electrically connected to the HUB device and configured to supply power to the HUB device, and the HUB device being further configured to extend a power supply path of the power supply device; Several control devices, each of which is provided with a power input interface and several power output interfaces, and each of which is also provided with a communication input interface and several communication output interfaces, wherein the power input interface and the communication input interface are both electrically connected to the HUB device, and each of the power output interface and each of the communication output interfaces is used to electrically connect to the corresponding memory to be tested; The control device comprises: a control chip, the control chip being electrically connected to the communication input interface; A plurality of load voltage switches, wherein the plurality of load voltage switches correspond one to one with the plurality of power output interfaces; The input end of each load voltage switch is electrically connected to the power supply input interface, the output end of each load voltage switch is electrically connected to the corresponding power supply output interface, and the control end of each load voltage switch is electrically connected to the control chip.

2. The memory automatic testing device according to claim 1, wherein: The control device further comprises: A plurality of communication signal switches, wherein the input end of each communication signal switch is electrically connected to the communication input interface, the output end of each communication signal switch is electrically connected to the corresponding communication output interface, and the control end of each communication signal switch is electrically connected to the control chip.

3. The memory automatic testing device according to claim 2, wherein: The number of the communication signal switches is half the number of the communication output interfaces, and each communication signal switch corresponds to two communication output interfaces.

4. The memory automatic testing device according to claim 1, wherein: The control device further comprises: a plurality of voltage feedback circuits, wherein the plurality of voltage feedback circuits correspond one-to-one to the plurality of power output interfaces; The input end of each voltage feedback circuit is electrically connected to the corresponding power supply output interface, and the output end of each voltage feedback circuit is electrically connected to the control chip.

5. The memory automatic testing device according to claim 1, wherein: The control device further comprises: a plurality of signal feedback circuits, wherein the plurality of signal feedback circuits correspond one-to-one to the plurality of communication output interfaces; The input end of each of the signal feedback circuits is electrically connected to the communication output interface, and the output end of each of the signal feedback circuits is electrically connected to the control chip.

6. The memory automatic testing device according to claim 4, characterized in that: The control device further comprises: a plurality of power supply status indicator lights, each of the plurality of power supply status indicator lights corresponding one-to-one to the plurality of voltage feedback circuits or to the plurality of power supply output interfaces; Each of the power supply status indicator lights is electrically connected to the corresponding voltage feedback circuit or the corresponding power supply output interface.

7. The memory automatic testing device according to claim 5, characterized in that: The control device further comprises: a plurality of signal status indicator lights, each of the plurality of signal status indicator lights corresponding one-to-one to the plurality of signal feedback circuits or to the plurality of communication output interfaces; Each of the signal status indicator lights is electrically connected to the corresponding signal feedback circuit or the corresponding communication output interface.

8. The memory automatic testing device according to claim 4, characterized in that: The voltage feedback circuit and the control chip are connected in an IIC communication manner.

9. The memory automatic testing device according to claim 5, characterized in that: The signal feedback circuit and the control chip are connected in an IIC communication manner.

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