Display driving chip with laminated wafer bump structure

Abstract

The utility model discloses a display driving chip with a laminated wafer bump structure, which comprises a chip and a plurality of laminated bumps arranged on the chip, and the laminated bumps are made of different metal materials. The laminated bump comprises a first metal layer and a plurality of metal layers arranged above the first metal layer, and a microscopic rough surface is formed on the top surface of the first metal layer. The top surface of the first metal layer is processed into a microscopic rough surface, so that the mechanical occlusion between the first metal layer and other plating layers is increased, and the binding force between the plating layers is improved; the purposes of improving the binding force between different metal coatings, enhancing the reliability and stability between the metal coatings and ensuring the use instruction of the display driving chip are achieved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor chip packaging, in particular to a display driver chip with a stacked wafer bump structure. Background Art

[0002] Bump manufacturing technology is fundamental to the development and evolution of various advanced packaging technologies. Wafer bumping plays a key role in the application of liquid crystal display driver ICs (DDICs). With technological advancements and cost considerations, the industry has begun exploring and using other materials as gold alternatives, such as lead-tin alloys, copper, copper-nickel-gold, tin, and palladium. Research into bumps composed of different metals can address the shortcomings of traditional wire bonding processes at a lower cost. However, different metals have different thermal expansion coefficients due to differences in atomic structure, crystal structure, chemical bond strength, and other factors.

[0003] How to effectively solve the above technical problems is a technical problem that needs to be considered urgently in this technical field at this stage.

[0004] The information disclosed in this background technology section is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to those skilled in the art. Utility Model Content

[0005] In order to solve the above technical problems, the utility model proposes a display driver chip with a stacked wafer bump structure, so as to achieve the purpose of improving the bonding force between different metal coatings, enhancing the reliability and stability between metal coatings and ensuring the use instructions of the display driver chip.

[0006] In order to achieve the above-mentioned purpose, the technical solution of the present utility model is as follows:

[0007] A display driver chip with a stacked wafer bump structure includes a chip and a plurality of stacked bumps arranged on the chip, wherein the stacked bumps are composed of different metal materials;

[0008] The stacked bump includes a first metal layer and a plurality of metal layers arranged above the first metal layer, and a microscopic rough surface is formed on the top surface of the first metal layer.

[0009] The utility model increases the mechanical engagement between the first metal layer and other plating layers by processing the top surface of the first metal layer into a microscopic rough surface, thereby improving the bonding force between the plating layers; thereby achieving the purpose of improving the bonding force between different metal plating layers, enhancing the reliability and stability between the metal plating layers, and ensuring the use instructions of the display driver chip.

[0010] It is further worth noting that, based on a customized photomask, the first metal layer is formed on the chip through a bottom metal deposition, coating and development process, and the first metal layer is used as a connection substrate on the chip.

[0011] It is further worth noting that the second metal layer is electroplated on the rough surface formed on the surface of the first metal layer.

[0012] It is further worth noting that the top surface of the second metal layer is processed to form a microscopic rough surface, and the third metal layer is electroplated on the microscopic rough surface of the second metal layer.

[0013] The utility model has the following advantages:

[0014] 1. The utility model increases the mechanical engagement between the first metal layer and other plating layers by processing the top surface of the first metal layer into a microscopic rough surface, thereby improving the bonding force between the plating layers; thereby achieving the purpose of improving the bonding force between different metal plating layers, enhancing the reliability and stability between the metal plating layers, and ensuring the use instructions of the display driver chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art.

[0016] Figure 1 This is a schematic structural diagram of a display driver chip with a stacked wafer bump structure disclosed in an embodiment of the present utility model;

[0017] Figure 2 The manufacturing state of a display driver chip with a stacked wafer bump structure disclosed in an embodiment of the utility model Figure 1 ;

[0018] Figure 3 The present invention discloses a display driver chip with a stacked wafer bump structure. Figure 2 ;

[0019] Figure 4 The manufacturing state of a display driver chip with a stacked wafer bump structure disclosed in an embodiment of the utility model Figure 3 ;

[0020] The numbers and letters in the figure represent the corresponding component names:

[0021] 1. Chip 21. First metal layer 22. Multiple metal layers. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0023] The utility model provides a display driver chip with a stacked wafer bump structure. Its working principle is to increase the mechanical bite between the first metal layer and other plating layers by processing the top surface of the first metal layer into a microscopic rough surface, thereby improving the bonding force between the plating layers; thereby achieving the purpose of improving the bonding force between different metal plating layers, enhancing the reliability and stability between the metal plating layers, and ensuring the use instructions of the display driver chip.

[0024] The present invention will be further described in detail below with reference to the embodiments and specific implementation methods.

[0025] like Figure 1 As shown, a display driver chip with a stacked wafer bump structure includes a chip 1 and a plurality of stacked bumps arranged on the chip, wherein the stacked bumps are composed of different metal materials;

[0026] The stacked bump includes a first metal layer 21 and a multi-layer metal layer 22 arranged above the first metal layer [the specific number of layers of the multi-layer metal layer is set according to actual needs, and can be 2 layers, 3 layers, or other numbers of layers], and the top surface of the first metal layer is formed with a microscopic rough surface.

[0027] The first metal layer is formed on the chip based on a customized photomask through bottom metal deposition, coating and development processes, and the first metal layer serves as a connection substrate on the chip.

[0028] The second metal layer is electroplated on the rough surface formed on the surface of the first metal layer.

[0029] The top surface of the second metal layer is processed to form a microscopic rough surface, and a third metal layer is electroplated on the microscopic rough surface formed on the top surface of the second metal layer.

[0030] [Other metal layers are processed in the same way, and are plated on the rough surface on top of the previous metal layer]

[0031] The specific steps of using this utility model are as follows: Figure 1 As shown, the chip 1 is used as a substrate, and a certain thickness of metal Au is electroplated on the surface as the first metal layer 21 (such as Figure 2 ); then the upper surface of the first metal layer is roughened by mechanical or chemical methods to increase the surface roughness, that is, the upper surface of the first metal layer is a rough surface (such as Figure 3); then a certain thickness of metal Ni is electroplated on the surface of the first metal layer to form a second metal layer; then the upper surface of the second metal layer [metal Ni layer] is roughened by mechanical or chemical methods to increase the surface roughness (such as Figure 4 ), electroplating a certain thickness of metal Pd on the upper surface of the second metal layer to form a third metal layer [metal Pd layer]; repeating the above steps to sequentially form a fourth metal layer [metal Cu layer], such as Figure 1 .

[0032] By roughening the upper surface of the previous layer, a series of failure problems such as separation, cracking, and decreased conductivity caused by thermal expansion coefficient mismatch between different metal plating layers can be effectively prevented, especially under temperature cycling or extreme temperature environments. Stronger interfacial bonding can reduce the risk of separation between metal layers during temperature cycling, mechanical stress, or long-term use, thereby significantly improving product reliability and lifespan. At the same time, tight interlayer bonding can reduce contact resistance and ensure better current conduction, which is particularly important for high-frequency and high-speed signal transmission. It can reduce signal attenuation and delay, improve circuit efficiency and response speed, and thus improve electrical performance. In the case of external impact or vibration, the high-bonding metal layer can better maintain structural integrity, prevent open circuit or short circuit failures caused by interface separation, and enhance the mechanical stability of the chip. In power semiconductor and high heat flow applications, good intermetallic bonding helps heat be more effectively transferred away from the heat source, avoiding local overheating, protecting sensitive components, and improving the overall thermal management capability of the system, thereby improving thermal conductivity.

[0033] Through the above method, the display driver chip with a stacked wafer bump structure provided by the present invention increases the mechanical bite between the first metal layer and other coatings by processing the top surface of the first metal layer into a microscopic rough surface, thereby improving the bonding force between the coatings; achieving the purpose of improving the bonding force between different metal coatings, enhancing the reliability and stability between the metal coatings, and ensuring the use instructions of the display driver chip.

[0034] The above is only a preferred embodiment of a display driver chip with a stacked wafer bump structure disclosed in the present invention. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A display driver chip having a stacked wafer bump structure, characterized in that: The invention comprises a chip and a plurality of stacked bumps arranged on the chip, wherein the stacked bumps are composed of different metal materials; The stacked bump includes a first metal layer and a plurality of metal layers arranged above the first metal layer, and a microscopic rough surface is formed on the top surface of the first metal layer.

2. The display driver chip with a stacked wafer bump structure according to claim 1, characterized in that: On the chip, based on a customized photomask, the first metal layer is formed through bottom metal deposition, coating and development processes, and the first metal layer is used as a connection substrate on the chip.

3. The display driver chip with a stacked wafer bump structure according to claim 2, characterized in that: A second metal layer is electroplated on the rough surface formed on the surface of the first metal layer.

4. The display driver chip with a stacked wafer bump structure according to claim 3, characterized in that: The top surface of the second metal layer is processed to form a microscopic rough surface, and a third metal layer is electroplated on the microscopic rough surface formed on the top surface of the second metal layer.

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