Data transmission circuit of domestic routing switch

Abstract

The utility model provides a data transmission circuit of a domestic routing switch, which comprises a main controller, an MCU (Microprogrammed Control Unit), a switching chip, a network transformer and a PHY (Physical Layer) transceiver, the data transmission end of the main controller is connected with the first data transmission end of the MCU, and the control end of the main controller is connected with the controlled end of the MCU; the second data transmission end of the MCU is connected with the data transmission end of the exchange chip; the other data transmission end of the switching chip is connected with the data transmission end of the first network transformer, and the other data transmission end of the first network transformer is connected with the terminal equipment; the third data transmission end of the MCU is connected with the data transmission end of the PHY transceiver, the other data transmission end of the PHY transceiver is connected with the data transmission end of the second network transformer, and the other data transmission end of the second network transformer is connected with the terminal equipment. According to the utility model, through the close cooperation of the main controller and the MCU, high-efficiency data transmission is realized; the speed and the stability of data transmission are improved by adopting the switching chip and the network transformer; and the MCU is connected with the PHY transceiver, so that quick transmission and receiving of physical layer data are realized, and the response speed and the data processing capability of the system are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of transmission circuits, in particular to a domestic routing switch data transmission circuit. Background Art

[0002] With the rapid development of information technology, network communications have become an indispensable part of modern society. Routing switches, as core devices in various network communication systems, are responsible for forwarding, routing, and switching data, and are the key to achieving efficient and reliable network communications.

[0003] However, existing domestic routing switch technology still faces several pressing challenges. First, data transmission efficiency and compatibility between different components are key factors affecting system performance. Traditional data transmission methods can suffer from signal attenuation and transmission delays, leading to reduced data transmission efficiency and, in turn, impacting overall network communication quality. Second, the expansion of network scale and the surge in data volumes place higher demands on the data processing capabilities and control accuracy of routing switches. Traditional control methods may fail to meet the requirements for real-time performance, efficiency, and reliability, leading to system performance bottlenecks. Utility Model Content

[0004] The utility model aims to at least solve the technical problems existing in the prior art, and particularly innovatively proposes a domestically produced routing switch data transmission circuit.

[0005] In order to achieve the above-mentioned purpose of the present invention, the present invention provides a domestic routing switch data transmission circuit, which is characterized by comprising: a main controller, an MCU, a switching chip, a network transformer and a PHY transceiver.

[0006] The data transmission end of the main controller is connected to the first data transmission end of the MCU, and the control end of the main controller is connected to the controlled end of the MCU for data transmission and control; the second data transmission end of the MCU is connected to the data transmission end of the switching chip; the other data transmission end of the switching chip is connected to the data transmission end of the first network transformer, and the other data transmission end of the first network transformer is connected to the terminal device;

[0007] The third data transmission end of the MCU is connected to the data transmission end of the PHY transceiver, the other data transmission end of the PHY transceiver is connected to the data transmission end of the second network transformer, and the other data transmission end of the second network transformer is connected to the terminal device.

[0008] The MCU (microcontroller unit) is connected to the switching chip to process various control tasks and data forwarding instructions of the routing switch; it is then connected to the terminal device through a network transformer. The network transformer is used for signal isolation, transmission and matching, ensuring that data signals can be transmitted to the terminal device stably and reliably.

[0009] At the same time, the MCU is also connected to the PHY (physical layer) transceiver, which is used for data transmission and reception at the physical layer; the PHY transceiver is then connected to the external environment through another network transformer to achieve bidirectional data transmission.

[0010] Using network transformers in the data transmission circuits of routing switches can not only isolate electrical signals and protect equipment safety, but also improve data transmission quality and network adaptability.

[0011] Preferably, the number of the switching chips and the number of the first network transformers are the same.

[0012] Preferably, the other data transmission end of the first network transformer is connected to a terminal device; the other data transmission end of the second network transformer is connected to a terminal device. The MCU is sequentially connected to the switching chip, the network transformer, and the external device. However, if the switch has gateway functionality and is configured with the corresponding network protocols and routing tables, it can also support data exchange between the internal and external networks to a certain extent. The MCU is sequentially connected to the PHY transceiver and the network transformer.

[0013] Preferably, the data end of the main controller is connected to the data transmission end of the flash memory, and the other data end of the main controller is connected to the data transmission end of the eMMC memory; the power management end of the MCU is connected to the monitoring end of the power monitoring chip.

[0014] Preferably, the circuit connection between the data terminal of the main controller and the data transmission terminal of the flash memory includes:

[0015] The storage signal terminal of the controller U2 is connected to the data transmission terminal of the flash memory D3.

[0016] The auxiliary power supply terminal VCCAUX_L10 of the controller U2 and the first ends of the plurality of parallel capacitors are connected to the power supply VCC1.8V, and the second ends of the plurality of parallel capacitors are connected to the power ground;

[0017] The auxiliary power supply terminal VCCPAUX_T9 of the controller U2 and the first ends of the plurality of parallel capacitors are connected to the power supply VCC1.8V, and the second ends of the plurality of parallel capacitors are connected to the power ground;

[0018] The phase-locked loop (PLL) power supply terminal VCCPLL_H10 of the controller U2 is connected to the first end of the magnetic bead L19 and the first ends of several parallel capacitors. The second end of the magnetic bead L19 is connected to the power supply VCC1.8V. The second ends of the several parallel capacitors are connected to the power ground.

[0019] The core power supply terminal VCCPINT_R8 of the controller U2, the first terminals of the plurality of parallel capacitors, the positive terminals of the polarized capacitors are connected to the power supply VCC1.05V; the second terminals of the plurality of parallel capacitors and the negative terminals of the polarized capacitors are connected to the power ground;

[0020] The core power supply terminal VCCINT_R14 of the controller U2, the first terminals of the plurality of parallel capacitors, and the positive terminals of the polarized capacitors are connected to the power supply VCC1.05V; the second terminals of the plurality of parallel capacitors and the negative terminals of the polarized capacitors are connected to the power ground;

[0021] The memory power supply terminal VCCBRAM_J10 of the controller U2 and the first ends of several parallel capacitors are connected to the power supply VCC1.05V; the second ends of the several parallel capacitors and the negative electrode of the polarized capacitor are connected to the power ground.

[0022] Preferably, the power management terminal of the controller is connected to the monitoring terminal of the power monitoring chip, and the circuit connection includes:

[0023] The status display terminal of the controller U2 is connected to the cathode of the light emitting diode HL7, the anode of the light emitting diode HL7 is connected to the first terminal of the resistor R171, and the second terminal of the resistor R171 is connected to the power supply VCC3.3V;

[0024] The manual reset input MR of the power monitoring chip D4 is connected to the first end of the capacitor C7 and the first end of the resistor R170. The second end of the capacitor C7 is connected to the power ground. The second end of the resistor R170, the first end of the capacitor C279, the first end of the capacitor C280, the first end of the resistor R176, and the power supply voltage input terminal VCC of the power monitoring chip D4 are connected to the power supply VCC3.3V.

[0025] The reset output terminal RESET of the power monitoring chip D4 is connected to the second end of the resistor R176, the first end of the capacitor C281, and the data transmission end of the flash memory D3, and the second end of the capacitor C281 is connected to the power ground;

[0026] The second end of the capacitor C279 and the ground terminal GND of the power monitoring chip D4 are connected to the power ground.

[0027] Preferably, it also includes a network serial port transparent transmission chip, the data transmission end of the network serial port transparent transmission chip is respectively connected to the data transmission end of the network transformer and the data transmission end of the level conversion chip, the other data transmission end of the level conversion chip is connected to the data transmission end of the USB serial port chip, the other data transmission end of the USB serial port chip is connected to the data transmission end of the common mode filter, the clock signal end of the USB serial port chip is connected to the clock signal end of the crystal oscillator, and the data transmission end of the common mode filter is connected to the data transmission end of the USB connector.

[0028] The network serial port transparent transmission chip converts network data into UART signals for transmission. These UART signals are then fed into the SGM4553 dual-channel high-speed level shifter chip. The SGM4553 adjusts the UART signal levels based on the voltage requirements of the receiving end (in this case, the USB serial port chip) to ensure correct signal reception. The level-shifted UART signals are then passed to the USB serial port chip, which converts them to USB format for communication with a computer or other USB device. Before being sent to the USB connector, the USB signal passes through a common-mode filter to remove common-mode noise that could interfere with signal transmission, thereby improving signal quality and stability. Finally, the cleaned USB signal connects and communicates with external devices through the USB connector. This process completes the complete conversion and transmission chain from network to UART signals, and then to USB signals.

[0029] Preferably, the circuit connection of the switching chip includes:

[0030] The power supply terminal of the switching chip U22 and the first terminals of the plurality of parallel capacitors are connected to the power supply VCC3.3V, and the second terminals of the plurality of parallel capacitors are connected to the power ground;

[0031] An address terminal A0 of the memory D14 is connected to a first end of a resistor R304, an address terminal A1 of the memory D14 is connected to a first end of a resistor R303, an address terminal A2 of the memory D14 is connected to a first end of a resistor R302, and a second end of the resistor R304, a second end of the resistor R303, and a second end of the resistor R302 are connected to a power supply VCC 3.3V.

[0032] A power supply terminal VCC of the memory D14, a first terminal of the capacitor C252, and a first terminal of the capacitor C256 are connected to the power supply VCC 3.3V, and a second terminal of the capacitor C252 and a second terminal of the capacitor C256 are connected to the power ground; a write protection terminal WP of the memory D14 is connected to a first terminal of the resistor R305, and a second terminal of the resistor R305 is connected to the power ground;

[0033] Preferably, the model of the main controller is FMQL45T900, and the model of the MCU is GD32F427ZG.

[0034] The serial clock end SCL of the memory D14 and the clock end of the switching chip U22 are both connected to the clock control end of the MCU, and the serial data end SDA of the memory D14 and the data end of the switching chip U22 are both connected to the data end of the MCU, which are used for slave device communication on the I2C bus.

[0035] In summary, due to the adoption of the above-mentioned technical solution, the utility model proposes a domestic routing switch data transmission circuit, which improves the overall performance of the system by optimizing the data transmission and control methods between components. First, through the close cooperation between the main controller and the MCU, efficient data transmission and the issuance of control instructions are achieved. The cooperation mechanism ensures the accurate execution of control instructions and improves the control accuracy. At the same time, the use of switching chips and network transformers further improves the speed and stability of data transmission. In addition, through the connection between the MCU and the PHY transceiver, the rapid transmission and reception of physical layer data is achieved, thereby improving the response speed and data processing capabilities of the system. These improvement measures work together on the domestic routing switch, effectively solving the data transmission efficiency and compatibility problems in the existing technology, and providing strong support for building an efficient and reliable network communication system.

[0036] Additional aspects and advantages of the present invention will be given in part in the following description and will become apparent from the following description or learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0038] Figure 1 It is a connection diagram of the present utility model.

[0039] Figure 2 This is a circuit connection diagram of the controller, power monitoring chip and flash memory of the utility model.

[0040] Figure 3 This is a circuit connection diagram of the MCU and power monitoring chip of the utility model.

[0041] Figure 4 This is a schematic diagram of the circuit connection between the switching chip and the memory of the utility model.

[0042] Figure 5 This is a circuit connection diagram of the PHY transceiver of the utility model.

[0043] Figure 6This is a circuit connection diagram of the utility model network transformer.

[0044] Figure 7 This is a circuit connection diagram of the network serial port transparent transmission chip of the utility model.

[0045] Figure 8 This is a circuit connection diagram of the level conversion chip and the USB to serial port chip of the utility model.

[0046] Figure 9 This is a circuit connection diagram of the eMMC memory of the utility model. DETAILED DESCRIPTION

[0047] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0048] This utility model proposes a domestic routing switch data transmission circuit, such as Figure 1 As shown. It includes main controller, MCU, switch chip, network transformer and PHY transceiver;

[0049] The main controller's data transmission port is connected to the MCU's data transmission port, while the main controller's control port is connected to the MCU's control port for data transmission and control. The MCU's data transmission port is also connected to the PHY transceiver's data transmission port and the switch chip's data transmission port. The PHY transceiver and switch chip are both connected to a network transformer. Some ports on the switch chip have internal PHYs and can be directly connected to the transformer, while some ports lack internal PHYs and require an external PHY and network transformer. The network transformer may be connected directly to the device's network card or via an RJ45 network port.

[0050] In addition, there is a network serial port transparent transmission chip, which is respectively connected to the network transformer and the level conversion chip. The level conversion chip is connected to the USB-to-serial port chip, and the USB-to-serial port chip is connected to the USB connector through a common-mode filter; thereby realizing the mutual conversion and transmission between network data (data received or sent through the Ethernet interface) and USB data (data communicated with the computer or other USB devices through the USB interface).

[0051] In practice, multiple network chips are used to connect to switch chips, PHY transceivers and other components in order to improve the overall performance, functional scalability, reliability and redundancy of the network communication system, while bypassing hardware limitations to achieve higher data processing capabilities, parallel processing, modular design, multiple interface support, fault isolation, load balancing and cost-effectiveness.

[0052] The data transmission process of the routing switch is as follows:

[0053] (1) Input signal reception:

[0054] Network signals (such as Ethernet packets) enter the routing switch through an RJ45 port or a network card connected directly to a device terminal. These signals first pass through a network transformer, which isolates, enhances, and protects the signal, ensuring stability and interference resistance during transmission.

[0055] (2) Signal conversion and transmission:

[0056] After passing through the network transformer, the signal is sent to the PHY transceiver. This PHY transceiver converts physical layer signals into digital signals, or vice versa, for transmission across the network. The converted digital signals are then sent to the switch chip. The switch chip is the core component of a routing switch, responsible for high-speed data packet switching and routing. It determines the data packet's transmission path based on the packet's destination address and other information.

[0057] (3) Data exchange and processing:

[0058] Within the switch chip, data packets are rapidly processed and switched. If a packet needs to be forwarded to another port or device, the switch chip sends it to the corresponding output channel. Simultaneously, the main controller and MCU monitor and control the entire data transmission process. The MCU receives control commands from the main controller and adjusts data transmission parameters and policies accordingly.

[0059] (4) Output signal transmission:

[0060] The processed data packets pass through the network transformer again to ensure signal stability and anti-interference. The signal is then sent to the target device through an RJ45 network port or a network card directly connected to another device terminal.

[0061] (5) Implementation of special functions (such as network serial port transparent transmission):

[0062] If conversion and transmission between network data and USB data is required, the network serial port transparent transmission chip comes into play. It receives Ethernet data from the network transformer and converts it into a signal suitable for USB transmission through a level conversion chip. The converted signal is purified by a common-mode filter before being output through the USB connector to a computer or other USB device.

[0063] The specific circuit design of the routing switch data transmission circuit is as follows Figures 2 to 9 shown.

[0064] The auxiliary power supply terminal VCCAUX_L10 of the controller U2 and the first ends of the plurality of parallel capacitors are connected to the power supply VCC1.8V, and the second ends of the plurality of parallel capacitors are connected to the power ground;

[0065] The auxiliary power supply terminal VCCPAUX_T9 of the controller U2 and the first ends of the plurality of parallel capacitors are connected to the power supply VCC1.8V, and the second ends of the plurality of parallel capacitors are connected to the power ground;

[0066] The phase-locked loop (PLL) power supply terminal VCCPLL_H10 of the controller U2 is connected to the first end of the magnetic bead L19 and the first ends of several parallel capacitors. The second end of the magnetic bead L19 is connected to the power supply VCC1.8V. The second ends of the several parallel capacitors are connected to the power ground.

[0067] The core power supply terminal VCCPINT_R8 of the controller U2, the first terminals of the plurality of parallel capacitors, the positive terminals of the polarized capacitors are connected to the power supply VCC1.05V; the second terminals of the plurality of parallel capacitors and the negative terminals of the polarized capacitors are connected to the power ground;

[0068] The core power supply terminal VCCINT_R14 of the controller U2, the first terminals of the plurality of parallel capacitors, and the positive terminals of the polarized capacitors are connected to the power supply VCC1.05V; the second terminals of the plurality of parallel capacitors and the negative terminals of the polarized capacitors are connected to the power ground;

[0069] The memory power supply terminal VCCBRAM_J10 of the controller U2 and the first ends of several parallel capacitors are connected to the power supply VCC1.05V; the second ends of the several parallel capacitors and the negative electrode of the polarized capacitor are connected to the power ground.

[0070] The status display terminal of the controller U2 is connected to the cathode of the light emitting diode HL7, the anode of the light emitting diode HL7 is connected to the first terminal of the resistor R171, and the second terminal of the resistor R171 is connected to the power supply VCC3.3V;

[0071] The storage signal terminal of the controller U2 is connected to the data transmission terminal of the flash memory D3.

[0072] The manual reset input MR of the power monitoring chip D4 is connected to the first end of the capacitor C7 and the first end of the resistor R170. The second end of the capacitor C7 is connected to the power ground. The second end of the resistor R170, the first end of the capacitor C279, the first end of the capacitor C280, the first end of the resistor R176, and the power supply voltage input terminal VCC of the power monitoring chip D4 are connected to the power supply VCC3.3V.

[0073] The reset output terminal RESET of the power monitoring chip D4 is connected to the second end of the resistor R176, the first end of the capacitor C281, and the data transmission end of the flash memory D3. The second end of the capacitor C281 is connected to the power ground.

[0074] The second end of the capacitor C279 and the ground terminal GND of the power monitoring chip D4 are connected to the power ground.

[0075] Figure 2 This is a circuit connection diagram of the controller, power monitoring chip and flash memory of the utility model.

[0076] The operating status indication terminal of the MCU U6 is connected to the first terminal of the resistor R56 , the second terminal of the resistor R56 is connected to the anode of the light emitting diode, and the cathode of the light emitting diode is connected to the power ground.

[0077] The power supply terminal of the switching chip U22 and the first terminals of the plurality of parallel capacitors are connected to the power supply VCC3.3V, and the second terminals of the plurality of parallel capacitors are connected to the power ground.

[0078] An address terminal A0 of the memory D14 is connected to a first end of a resistor R304, an address terminal A1 of the memory D14 is connected to a first end of a resistor R303, an address terminal A2 of the memory D14 is connected to a first end of a resistor R302, and a second end of the resistor R304, a second end of the resistor R303, and a second end of the resistor R302 are connected to a power supply VCC 3.3V.

[0079] A power supply terminal VCC of the memory D14, a first terminal of the capacitor C252, and a first terminal of the capacitor C256 are connected to the power supply VCC 3.3V, and a second terminal of the capacitor C252 and a second terminal of the capacitor C256 are connected to the power ground; a write protection terminal WP of the memory D14 is connected to a first terminal of the resistor R305, and a second terminal of the resistor R305 is connected to the power ground;

[0080] The serial clock end SCL of the memory D14 and the clock end of the switching chip U22 are both connected to the clock control end of the MCU, and the serial data end SDA of the memory D14 and the data end of the switching chip U22 are both connected to the data end of the MCU, which are used for slave device communication on the I2C bus.

[0081] The data transmission end of the PHY transceiver D1 is connected to the data transmission end of the network transformer T15, and the control management end of the PHY transceiver D1 is connected to the control end of the MCU U6;

[0082] The RMII interface data receiving end and the MII interface data receiving end of the PHY transceiver D1 are both connected to one end of two resistors, and the other ends of the two resistors are connected to the power supply DVDD33_PHY and the power ground respectively.

[0083] The address signal terminal of the PHY transceiver D1 is connected to one end of two resistors and the cathode of a light-emitting diode. The other ends of the two resistors are connected to the power supply DVDD33_PHY and the power ground respectively. The anode of the light-emitting diode is connected to the power supply DVDD33_PHY. The light-emitting diode is used to indicate that the address signal terminal of the PHY transceiver D1 is in normal working state.

[0084] The Ethernet data transmitter and receiver of network serial port transparent transmission chip U12 are connected to the data receiver and transmitter of network transformer T14, respectively. This enables remote transparent data transmission, signal isolation and protection, and improved data transmission stability and reliability. The asynchronous serial port data input and output of network serial port transparent transmission chip U12 are connected to the data output A2 and data input A1 of level conversion chip U9, respectively. The indicator terminal of network serial port transparent transmission chip U12 is connected to the cathode of a light-emitting diode, while the anode of the light-emitting diode is connected to the 3.3V power supply VCC via a resistor.

[0085] The power supply voltage A terminal VCCA of the level conversion chip U9, the first terminal of the capacitor C453, and the first terminal of the resistor R463 are connected to the power supply VCC3.3V, the second terminal of the capacitor C453 is connected to the power ground, and the second terminal of the resistor R463 is connected to the output enable control terminal OE of the level conversion chip U9; the channel 1 transmission terminal B1 of the level conversion chip U9 is connected to the data transmitting terminal TXD of the USB serial port chip D21, and the channel 2 transmission terminal B2 of the level conversion chip U9 is connected to the data receiving terminal RXD of the USB serial port chip D21; the power supply voltage B terminal VCCB of the level conversion chip U9 is connected to the first terminal of the capacitor C456, the power supply terminal VCC of the USB serial port chip D21, and the USB connector X8; the second terminal of the capacitor C456 is connected to the power ground;

[0086] The reference voltage terminal V3 of the USB serial port chip D21 is connected to the first terminal of the capacitor C455, and the second terminal of the capacitor C455 is connected to the power ground;

[0087] The USB differential signal terminal UDP and the differential signal terminal UDM of the USB serial port chip D21 are respectively connected to the fourth terminal and the third terminal of the common mode filter U8; the first terminal and the second terminal of the common mode filter U8 are connected to the USB connector X8;

[0088] The clock signal input terminal XI of the USB serial port chip D21 is connected to the first terminal of the clock chip G8, and the clock signal output terminal XO is connected to the third terminal of the clock chip G8;

[0089] The network serial port transparent transmission chip U12 is responsible for converting network data from the PHY transceiver and / or switch chip into UART signals for transmission. These UART signals are then sent to the dual-channel high-speed level conversion chip U9. The level conversion chip U9 makes necessary level adjustments to the UART signals based on the voltage requirements of the receiving end (i.e., the USB serial port chip D21) to ensure that the signals can be received correctly. The level-converted UART signals are then passed to the USB serial port chip D21, which is responsible for further converting these signals into USB format for communication with a computer or other USB devices. Before the USB signal is sent to the USB connector X8, it first passes through the common-mode filter U8, which filters out common-mode noise that may interfere with signal transmission, thereby improving the quality and stability of the signal. Finally, the purified USB signal is connected and communicated with external devices through the USB connector X8. This process realizes the complete conversion and transmission link from network to UART signal, and then to USB signal.

[0090] The power supply terminal of the eMMC memory U1 and the first terminals of the three parallel capacitors are connected to the power supply VCC3.3V; the second terminals of the three parallel capacitors are connected to the power ground.

[0091] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and purpose of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A domestic routing switch data transmission circuit, characterized in that: include: Main controller, MCU, switch chip, network transformer and PHY transceiver, The data transmission end of the main controller is connected to the first data transmission end of the MCU, and the control end of the main controller is connected to the controlled end of the MCU; the second data transmission end of the MCU is connected to the data transmission end of the switching chip; the other data transmission end of the switching chip is connected to the data transmission end of the first network transformer, and the other data transmission end of the first network transformer is connected to the terminal device; The third data transmission end of the MCU is connected to the data transmission end of the PHY transceiver, the other data transmission end of the PHY transceiver is connected to the data transmission end of the second network transformer, and the other data transmission end of the second network transformer is connected to the terminal device.

2. A domestic routing switch data transmission circuit according to claim 1, characterized in that: The number of the switching chips and the number of the first network transformers are the same.

3. The data transmission circuit of a domestic routing switch according to claim 1, characterized in that: The other data transmission end of the first network transformer is connected to the terminal device; the other data transmission end of the second network transformer is connected to the terminal device.

4. The data transmission circuit of a domestic routing switch according to claim 1, characterized in that: The data end of the main controller is connected to the data transmission end of the flash memory, and the other data end of the main controller is connected to the data transmission end of the eMMC memory; the power management end of the MCU is connected to the monitoring end of the power monitoring chip.

5. The data transmission circuit of a domestic routing switch according to claim 4, characterized in that: The circuit connection between the data terminal of the main controller and the data transmission terminal of the flash memory includes: The storage signal terminal of the controller U2 is connected to the data transmission terminal of the flash memory D3. The auxiliary power supply terminal VCCAUX_L10 of the controller U2 and the first ends of the plurality of parallel capacitors are connected to the power supply VCC1.8V, and the second ends of the plurality of parallel capacitors are connected to the power ground; The auxiliary power supply terminal VCCPAUX_T9 of the controller U2 and the first ends of the plurality of parallel capacitors are connected to the power supply VCC1.8V, and the second ends of the plurality of parallel capacitors are connected to the power ground; The phase-locked loop (PLL) power supply terminal VCCPLL_H10 of the controller U2 is connected to the first end of the magnetic bead L19 and the first ends of several parallel capacitors. The second end of the magnetic bead L19 is connected to the power supply VCC1.8V. The second ends of the several parallel capacitors are connected to the power ground. The core power supply terminal VCCPINT_R8 of the controller U2, the first terminals of the plurality of parallel capacitors, the positive terminals of the polarized capacitors are connected to the power supply VCC1.05V; the second terminals of the plurality of parallel capacitors and the negative terminals of the polarized capacitors are connected to the power ground; The core power supply terminal VCCINT_R14 of the controller U2, the first terminals of the plurality of parallel capacitors, and the positive terminals of the polarized capacitors are connected to the power supply VCC1.05V; the second terminals of the plurality of parallel capacitors and the negative terminals of the polarized capacitors are connected to the power ground; The memory power supply terminal VCCBRAM_J10 of the controller U2 and the first ends of several parallel capacitors are connected to the power supply VCC1.05V; the second ends of the several parallel capacitors and the negative electrode of the polarized capacitor are connected to the power ground.

6. The domestic routing switch data transmission circuit according to claim 1, characterized in that: The power management terminal of the controller is connected to the monitoring terminal of the power monitoring chip. The circuit connection includes: The status display terminal of the controller U2 is connected to the cathode of the light emitting diode HL7, the anode of the light emitting diode HL7 is connected to the first terminal of the resistor R171, and the second terminal of the resistor R171 is connected to the power supply VCC3.3V; The manual reset input MR of the power monitoring chip D4 is connected to the first end of the capacitor C7 and the first end of the resistor R170. The second end of the capacitor C7 is connected to the power ground. The second end of the resistor R170, the first end of the capacitor C279, the first end of the capacitor C280, the first end of the resistor R176, and the power supply voltage input terminal VCC of the power monitoring chip D4 are connected to the power supply VCC3.3V. The reset output terminal RESET of the power monitoring chip D4 is connected to the second end of the resistor R176, the first end of the capacitor C281, and the data transmission end of the flash memory D3, and the second end of the capacitor C281 is connected to the power ground; The second end of the capacitor C279 and the ground terminal GND of the power monitoring chip D4 are connected to the power ground.

7. The domestic routing switch data transmission circuit according to claim 1, characterized in that: It also includes a network serial port transparent transmission chip, the data transmission end of the network serial port transparent transmission chip is respectively connected to the data transmission end of the network transformer and the data transmission end of the level conversion chip, the other data transmission end of the level conversion chip is connected to the data transmission end of the USB serial port chip, the other data transmission end of the USB serial port chip is connected to the data transmission end of the common mode filter, the clock signal end of the USB serial port chip is connected to the clock signal end of the crystal oscillator, and the data transmission end of the common mode filter is connected to the data transmission end of the USB connector.

8. The domestic routing switch data transmission circuit according to claim 1, characterized in that: The circuit connection of the switching chip includes: The power supply terminal of the switching chip U22 and the first terminals of the plurality of parallel capacitors are connected to the power supply VCC3.3V, and the second terminals of the plurality of parallel capacitors are connected to the power ground; An address terminal A0 of the memory D14 is connected to a first end of a resistor R304, an address terminal A1 of the memory D14 is connected to a first end of a resistor R303, an address terminal A2 of the memory D14 is connected to a first end of a resistor R302, and a second end of the resistor R304, a second end of the resistor R303, and a second end of the resistor R302 are connected to a power supply VCC 3.3V. The power supply terminal VCC of the memory D14, the first end of the capacitor C252, and the first end of the capacitor C256 are connected to the power supply VCC3.3V, and the second end of the capacitor C252 and the second end of the capacitor C256 are connected to the power ground; the write protection terminal WP of the memory D14 is connected to the first end of the resistor R305, and the second end of the resistor R305 is connected to the power ground.

9. The domestic routing switch data transmission circuit according to claim 1, characterized in that: The model of the main controller is FMQL45T900 and the model of the MCU is GD32F427ZG.

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