Piezoelectric printer

Abstract

The utility model discloses a piezoelectric printer, which comprises a printer body and a printer main board in communication connection with the printer body, the printer main board is electrically connected with a trolley board, an SOC chip is arranged in the trolley board, the SOC chip is electrically connected with a matching module, a grating sensor, an acquisition module and a nozzle control module respectively, and the matching module is electrically connected with the grating sensor, the acquisition module and the nozzle control module. The matching module is used for level conversion, the grating sensor is used for judging the position of the spray head according to grating signals collected in real time, the collecting module is used for collecting the remaining ink amount in an ink bottle, and the spray head control module is used for driving the spray head to work. A high-integration-level FPGA chip is adopted, and an SDRAM chip and an ARM chip do not need to be additionally arranged. The single SOC main control chip meets all functional requirements of the trolley board, and the required functions can be completed through the two-layer board design. The design is greatly simplified, the cost is reduced, the system complexity is reduced, and the system reliability is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of printing equipment, in particular to a piezoelectric printer. Background Art

[0002] Piezoelectric printers operate by controlling one or more sets of piezoelectric printheads. Simply put, a piezoelectric printhead applies voltage to a piezoelectric crystal, causing it to deform slightly and rapidly, thereby forcing ink out of the nozzle cavity. Conventional piezoelectric printers, such as inkjet printers, flatbed printers, and printing machines, typically have multiple sets of printheads, with four or eight sets being common. This multi-set of printheads requires multiple DAC channels, necessitating the selection of DAC chips with multiple output channels, which is expensive.

[0003] Currently, existing technologies require the use of multiple main chips for combined design, each requiring separate programming, increasing system complexity and hardware circuit size. Furthermore, the need for an external SDRAM chip complicates hardware design. SDRAM operates at a high frequency, requiring impedance matching and necessitating a four-layer or higher board design, which also increases costs and design risks. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention proposes the following technical solutions:

[0005] In the first aspect, an embodiment of the utility model provides a piezoelectric printer, comprising: a printer body and a printer main board communicatively connected to the printer body, the printer main board being electrically connected to a carriage board, a SOC chip being arranged in the carriage board, the SOC chip being electrically connected to a matching module, a grating sensor, an acquisition module and a nozzle control module respectively, the matching module being used for level conversion, the grating sensor being used for determining the position of the nozzle based on the grating signal acquired in real time, the acquisition module being used for acquiring the remaining amount of ink in the ink bottle, and the nozzle control module being used for driving the nozzle to work.

[0006] In one possible implementation, the SOC chip uses a highly integrated FPGA chip, the FPGA chip has built-in CORTEX-M3 ARM and SDRAM, the FPGA chip is electrically connected to the first end of the matching module through LVDS IO, and the second end of the matching module is electrically connected to the optical fiber module.

[0007] In a possible implementation, when the matching module is used to convert the LVPECL level into the LVDS level, it includes: a PECL DRIVER, wherein a first output end of the PECL DRIVER is electrically connected to the first end of the first resistor and the first end of the second resistor respectively, the second end of the second resistor is electrically connected to the first end of the first terminal resistor, the second end of the first terminal resistor is electrically connected to the first end of the first capacitor, the second end of the first capacitor is electrically connected to the first end of the third resistor and the first input end of the LVDS RECEIVER respectively, the second output end of the PECL DRIVER is electrically connected to the first end of the fourth resistor and the first end of the fifth resistor respectively, the second end of the fifth resistor is electrically connected to the first end of the second terminal resistor, the second end of the second terminal resistor is electrically connected to the first end of the second capacitor, the second end of the second capacitor is electrically connected to the first end of the sixth resistor and the second input end of the LVDS RECEIVER respectively, and the second end of the first resistor, the second end of the third resistor, the second end of the fourth resistor, and the second end of the sixth resistor are grounded.

[0008] In one possible implementation, when the matching module is used to convert the LVDS level into the LVPECL level, it includes: an LVDSDRIVER, a first output end of the LVDSDRIVER is electrically connected to the first end of the third terminal resistor, a second end of the third terminal resistor is electrically connected to the first end of the third capacitor, the second end of the third capacitor is electrically connected to the first end of the seventh resistor, the first end of the eighth resistor and the first input end of the LVPECL RECEIVER respectively, the second output end of the LVDSDRIVER is electrically connected to the first end of the fourth terminal resistor, the second end of the fourth terminal resistor is electrically connected to the first end of the fourth capacitor, the second end of the fourth capacitor is electrically connected to the first end of the ninth resistor, the first end of the tenth resistor and the second input end of the LVPECL RECEIVER respectively, the second end of the seventh resistor and the second end of the ninth resistor are electrically connected to a 3.3V power supply, and the second end of the eighth resistor and the second end of the tenth resistor are grounded.

[0009] In one possible implementation, the nozzle control module adopts the SN74lvc244 chip, the 1A0 port of the SN74lvc244 chip is electrically connected to the first end of the eleventh resistor, the second end of the eleventh resistor is electrically connected to the signal input end, the VCC port of the SN74lvc244 chip is electrically connected to the VCC power supply, the 1Y0 port of the SN74lvc244 chip is electrically connected to the first end of the twelfth resistor, the second end of the twelfth resistor is electrically connected to the signal output end, and the signal output end is connected to the nozzle; the 1OE port and the GND port of the SN74lvc244 chip are grounded.

[0010] In one possible implementation, the acquisition module uses a PC817C chip, a first port of the PC817C chip is electrically connected to the first end of a thirteenth resistor, a second end of the thirteenth resistor is electrically connected to the VDD power supply and the first end of a fourteenth resistor, a second port of the PC817C chip is electrically connected to the cathode of a light-emitting diode and a float switch signal port, a third port of the PC817C chip is grounded, a fourth port of the PC817C chip is electrically connected to the first end of a fifteenth resistor, and a second end of the fifteenth resistor is electrically connected to a 3.3V power supply.

[0011] In one possible implementation, the FPGA chip has built-in ADC interface and SPI interface, the ADC interface is electrically connected to the conditioning module, the conditioning module is used to collect the nozzle voltage in real time, the SPI interface is electrically connected to the voltage control module, and the voltage control module is used to adjust the nozzle driving voltage.

[0012] In one possible implementation, the voltage control module includes a voltage follower, the first input end of the voltage follower is electrically connected to the first end of the sixteenth resistor and the first end of the seventeenth resistor, respectively, the second end of the seventeenth resistor is electrically connected to the output end of the voltage follower, the second input end of the voltage follower is electrically connected to the voltage signal input end and the first end of the fifth capacitor, respectively, the second end of the fifth capacitor and the second end of the sixteenth resistor are grounded.

[0013] In a possible implementation, a power module is further included, wherein the power module adopts an RT7294CGJ6F chip, the VIN port of the RT7294CGJ6F chip is electrically connected to the first end of the eighteenth resistor, the first end of the sixth capacitor and the VIN power supply respectively, the EN port of the RT7294CGJ6F chip is electrically connected to the second end of the eighteenth resistor, the first end of the nineteenth resistor and the first end of the seventh capacitor respectively, the BOOT port of the RT7294CGJ6F chip is electrically connected to the first end of the eighth capacitor, and the SW port of the RT7294CGJ6F chip is electrically connected to the second end of the eighth capacitor and the A first end of the first inductor is electrically connected to the first end of the ninth capacitor, the first end of the twentieth resistor, and the first end of the twenty-first resistor, respectively. A second end of the first inductor is electrically connected to the second end of the ninth capacitor, the second end of the twentieth resistor, the first end of the tenth capacitor, and the first end of the eleventh capacitor, respectively. The second end of the nineteenth resistor, the second end of the seventh capacitor, the second end of the sixth capacitor, a GND port of the RT7294CGJ6F chip, the second end of the twenty-first resistor, the second end of the tenth capacitor, and the second end of the eleventh capacitor are grounded.

[0014] Compared with the prior art, the beneficial effects of the present invention are:

[0015] This new system utilizes a highly integrated FPGA chip, eliminating the need for additional SDRAM and ARM chips. A single SOC master control chip fulfills all the functional requirements of the vehicle board, enabling a two-layer board design to accomplish all required functions. This significantly simplifies the design, reduces costs, and reduces system complexity, improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic structural diagram of a piezoelectric printer provided in an embodiment of the present utility model;

[0017] Figure 2 A circuit schematic diagram of a matching module provided in an embodiment of the present invention for converting LVPECL level to LVDS level;

[0018] Figure 3 A circuit schematic diagram of a matching module provided in an embodiment of the present invention for converting LVDS level to LVPECL level;

[0019] Figure 4 A circuit diagram of a nozzle control module provided in an embodiment of the present utility model;

[0020] Figure 5 A circuit diagram of the acquisition module provided in an embodiment of the present utility model;

[0021] Figure 6 A circuit diagram of a voltage control module provided in an embodiment of the present utility model;

[0022] Figure 7 This is a circuit diagram of the power module provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0023] The present invention will be described below with reference to the accompanying drawings and specific implementation methods.

[0024] Figure 1 This is a schematic diagram of the structure of the piezoelectric printer provided by the embodiment of the utility model, see Figure 1 In this embodiment, a piezoelectric printer includes a printer body and a printer mainboard communicatively connected to the printer body. The printer mainboard is electrically connected to a carriage board. The carriage board includes a system-on-chip (SoC) chip, which is electrically connected to a matching module, a grating sensor, a collection module, and a printhead control module. The matching module is used for level conversion, the grating sensor is used to determine the position of the printhead based on real-time grating signals, the collection module is used to measure the remaining ink level in the ink bottle, and the printhead control module is used to drive the printhead.

[0025] Since there is a certain distance between the carriage board and the printer main board and high-speed communication is required, optical fiber is a good choice. In this embodiment, common optical fiber modules such as 1X9 and SFC can be selected.

[0026] In this embodiment, the SOC chip adopts a highly integrated FPGA chip, which has built-in CORTEX-M3ARM and SDRAM. The FPGA chip is electrically connected to the first end of the matching module through LVDS IO, and the second end of the matching module is electrically connected to the optical fiber module.

[0027] In this embodiment, since the FPGA chip supports LVDS level, the optical module is mostly LVPECL level, and the matching module is used to achieve level conversion. In this embodiment, when the FPGA chip receives data, the LVPECL level is converted to the LVDS level, and when the FPGA chip sends data, the LVDS level is converted to the LVPECL level.

[0028] See also Figure 2 When the matching module is used to convert the LVPECL level into the LVDS level, it includes: a PECL DRIVER, a first output end of the PECL DRIVER is electrically connected to the first end of the first resistor R1 and the first end of the second resistor R2, a second end of the second resistor R2 is electrically connected to the first end of the first terminal resistor R3, a second end of the first terminal resistor R3 is electrically connected to the first end of the first capacitor C1, a second end of the first capacitor C1 is electrically connected to the first end of the third resistor R4 and the first input end of the LVDS receiver, a second output end of the PECL DRIVER is electrically connected to the first end of the fourth resistor R5 and the first end of the fifth resistor R6, a second end of the fifth resistor R6 is electrically connected to the first end of the second terminal resistor R7, a second end of the second terminal resistor R7 is electrically connected to the first end of the second capacitor C2, a second end of the second capacitor C2 is electrically connected to the first end of the sixth resistor R8 and the second input end of the LVDS receiver, and a second end of the first resistor R1, a second end of the third resistor R4, a second end of the fourth resistor R5, and a second end of the sixth resistor R8 are grounded.

[0029] See also Figure 3When the matching module is used to convert the LVDS level into the LVPECL level, it includes: an LVDS DRIVER, a first output end of the LVDSDRIVER is electrically connected to the first end of the third terminal resistor R9, a second end of the third terminal resistor R9 is electrically connected to the first end of the third capacitor C3, a second end of the third capacitor C3 is electrically connected to the first end of the seventh resistor R10, the first end of the eighth resistor R11, and the first input end of the LVPECL receiver, a second output end of the LVDSDRIVER is electrically connected to the first end of the fourth terminal resistor R12, a second end of the fourth terminal resistor R12 is electrically connected to the first end of the fourth capacitor C4, a second end of the fourth capacitor C4 is electrically connected to the first end of the ninth resistor R13, the first end of the tenth resistor R14, and the second input end of the LVPECL receiver, a second end of the seventh resistor R10 and a second end of the ninth resistor R13 are electrically connected to a 3.3V power supply, and a second end of the eighth resistor R11 and a second end of the tenth resistor R14 are grounded.

[0030] See also Figure 4 In this embodiment, the nozzle control module adopts the SN74lvc244 chip, the 1A0 port of the SN74lvc244 chip is electrically connected to the first end of the eleventh resistor R15, the second end of the eleventh resistor R15 is electrically connected to the signal input A0, the VCC port of the SN74lvc244 chip is electrically connected to the VCC power supply, the 1Y0 port of the SN74lvc244 chip is electrically connected to the first end of the twelfth resistor R16, the second end of the twelfth resistor R16 is electrically connected to the signal output end, the signal output end Y0 is connected to the nozzle, and the 1OE port and the GND port of the SN74lvc244 chip are grounded.

[0031] See also Figure 5 In this embodiment, the acquisition module uses a PC817C chip. The first port of the PC817C chip is electrically connected to the first end of a thirteenth resistor R18. The second end of the thirteenth resistor R18 is electrically connected to the VDD power supply and the first end of a fourteenth resistor R17, respectively. The second port of the PC817C chip is electrically connected to the cathode of the light-emitting diode and the float switch signal port X0, respectively. The third port of the PC817C chip is grounded. The fourth port of the PC817C chip is electrically connected to the first end of a fifteenth resistor R19, and the second end of the fifteenth resistor R19 is electrically connected to the 3.3V power supply. In this embodiment, X0 is connected to the float switch signal, which is turned on when ink is low. IN0 is high, and the signal is sent to the FPGA chip.

[0032] In addition, in this embodiment, the FPGA chip has built-in ADC interface and SPI interface, wherein the ADC interface is electrically connected to the conditioning module, the conditioning module is used to collect the nozzle voltage in real time, and the SPI interface is electrically connected to the voltage control module, and the voltage control module is used to adjust the nozzle driving voltage.

[0033] See also Figure 6 In this embodiment, the voltage control module includes a voltage follower IC0, the first input end of the voltage follower IC0 is electrically connected to the first end of the sixteenth resistor R20 and the first end of the seventeenth resistor R21, respectively, the second end of the seventeenth resistor R21 is electrically connected to the output end V0 of the voltage follower, the second input end of the voltage follower is electrically connected to the voltage signal input end Vi and the first end of the fifth capacitor C5, respectively, the second end of the fifth capacitor C5 and the second end of the sixteenth resistor R20 are grounded. The voltage control module has two functions: one is to increase the driving capability of the DAC module, and the other is to achieve a higher voltage output and enhance the voltage regulation capability of the power control sub-loop. This solution adopts a unidirectional proportional amplifier circuit, and the output of V0 is adjustable by adjusting the size of R20 and R21.

[0034] In this embodiment, the piezoelectric printer further includes a power supply module for converting the external power supply voltage into the voltage required by the board. Figure 7 The power module adopts the RT7294CGJ6F chip, the VIN port of the RT7294CGJ6F chip is electrically connected to the first end of the eighteenth resistor R22, the first end of the sixth capacitor C6 and the VIN power supply respectively, the EN port of the RT7294CGJ6F chip is electrically connected to the second end of the eighteenth resistor R22, the first end of the nineteenth resistor R23 and the first end of the seventh capacitor C7 respectively, the BOOT port of the RT7294CGJ6F chip is electrically connected to the first end of the eighth capacitor C8, the SW port of the RT7294CGJ6F chip is electrically connected to the second end of the eighth capacitor C8 and the first end of the first inductor L1 respectively, the RT729 The FB port of the 4CGJ6F chip is electrically connected to the first end of the ninth capacitor C9, the first end of the twentieth resistor R24, and the first end of the twenty-first resistor R25, respectively. The second end of the first inductor L1 is electrically connected to the second end of the ninth capacitor C9, the second end of the twentieth resistor R24, the first end of the tenth capacitor C10, and the first end of the eleventh capacitor C11, respectively. The second end of the nineteenth resistor R23, the second end of the seventh capacitor C7, the second end of the sixth capacitor C6, the GND port of the RT7294CGJ6F chip, the second end of the twenty-first resistor R25, the second end of the tenth capacitor C10, and the second end of the eleventh capacitor C11 are grounded.

[0035] The printer mainboard sends the print data to the carriage board. The FPGA chip connects to the matching module through LVDS IO, converts the LVDS signal into LVPECL signal (LVPECL signal is the level interface of common fiber optic modules), and connects to the fiber optic module. The FPGA chip caches the print data received through the fiber optic module into the internal SDRAM. The M7M12N5 has a built-in 64MbSDRAM and does not require an additional extended SDRAM chip. In addition, the received control signal is executed in real time. The FPGA collects the grating signal in real time to determine the position information, and retrieves the cached data based on the position information to control the nozzle printing. The voltage is collected through the FPGA's built-in CORTEX-M3 hard-core controller ADC module to ensure normal power supply to the driver board, and the DAC module is controlled through the SPI interface to adjust the voltage of the nozzle according to actual needs. Ordinary IO realizes functions such as float signal switch quantity collection.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0037] The above description is merely a specific embodiment of the present invention. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A piezoelectric printer, characterized in that: include: A printer body and a printer mainboard communicatively connected to the printer body, the printer mainboard being electrically connected to a carriage board, a SOC chip being provided in the carriage board, the SOC chip being electrically connected to a matching module, a grating sensor, an acquisition module, and a nozzle control module, respectively; the matching module being used for level conversion; the grating sensor being used for determining the position of the nozzle based on a grating signal acquired in real time; the acquisition module being used for acquiring the remaining amount of ink in the ink bottle; and the nozzle control module being used for driving the nozzle to operate.

2. The piezoelectric printer according to claim 1, wherein: include: The SOC chip adopts a highly integrated FPGA chip, and the FPGA chip has built-in CORTEX-M3 ARM and SDRAM. The FPGA chip is electrically connected to the first end of the matching module through LVDS IO, and the second end of the matching module is electrically connected to the optical fiber module.

3. The piezoelectric printer according to claim 2, wherein: When the matching module is used to convert the LVPECL level into the LVDS level, it includes: a PECL DRIVER, a first output end of the PECL DRIVER is electrically connected to the first end of the first resistor and the first end of the second resistor respectively, the second end of the second resistor is electrically connected to the first end of the first terminal resistor, the second end of the first terminal resistor is electrically connected to the first end of the first capacitor, the second end of the first capacitor is electrically connected to the first end of the third resistor and the first input end of the LVDS RECEIVER respectively, the second output end of the PECL DRIVER is electrically connected to the first end of the fourth resistor and the first end of the fifth resistor respectively, the second end of the fifth resistor is electrically connected to the first end of the second terminal resistor, the second end of the second terminal resistor is electrically connected to the first end of the second capacitor, the second end of the second capacitor is electrically connected to the first end of the sixth resistor and the second input end of the LVDS RECEIVER respectively, and the second end of the first resistor, the second end of the third resistor, the second end of the fourth resistor and the second end of the sixth resistor are grounded.

4. The piezoelectric printer according to claim 3, wherein: When the matching module is used to convert the LVDS level into the LVPECL level, it includes: an LVDSDRIVER, a first output end of the LVDSDRIVER is electrically connected to the first end of the third terminal resistor, a second end of the third terminal resistor is electrically connected to the first end of the third capacitor, the second end of the third capacitor is electrically connected to the first end of the seventh resistor, the first end of the eighth resistor and the first input end of the LVPECL RECEIVER respectively, the second output end of the LVDSDRIVER is electrically connected to the first end of the fourth terminal resistor, the second end of the fourth terminal resistor is electrically connected to the first end of the fourth capacitor, the second end of the fourth capacitor is electrically connected to the first end of the ninth resistor, the first end of the tenth resistor and the second input end of the LVPECL RECEIVER respectively, the second end of the seventh resistor and the second end of the ninth resistor are electrically connected to a 3.3V power supply, and the second end of the eighth resistor and the second end of the tenth resistor are grounded.

5. The piezoelectric printer according to claim 1, wherein: The nozzle control module adopts the SN74lvc244 chip, the 1A0 port of the SN74lvc244 chip is electrically connected to the first end of the eleventh resistor, the second end of the eleventh resistor is electrically connected to the signal input end, the VCC port of the SN74lvc244 chip is electrically connected to the VCC power supply, the 1Y0 port of the SN74lvc244 chip is electrically connected to the first end of the twelfth resistor, the second end of the twelfth resistor is electrically connected to the signal output end, and the signal output end is connected to the nozzle; the 1OE port and GND port of the SN74lvc244 chip are grounded.

6. The piezoelectric printer according to claim 1, wherein: include: The acquisition module uses a PC817C chip, a first port of the PC817C chip is electrically connected to the first end of the thirteenth resistor, the second end of the thirteenth resistor is electrically connected to the VDD power supply and the first end of the fourteenth resistor, respectively, the second port of the PC817C chip is electrically connected to the cathode of the light-emitting diode and the float switch signal port, respectively, the third port of the PC817C chip is grounded, the fourth port of the PC817C chip is electrically connected to the first end of the fifteenth resistor, and the second end of the fifteenth resistor is electrically connected to the 3.3V power supply.

7. The piezoelectric printer according to claim 2, wherein: include: The FPGA chip has built-in ADC interface and SPI interface. The ADC interface is electrically connected to the conditioning module, and the conditioning module is used to collect the nozzle voltage in real time. The SPI interface is electrically connected to the voltage regulation module, and the voltage regulation module is used to adjust the nozzle driving voltage.

8. The piezoelectric printer according to claim 7, wherein: The voltage control module includes a voltage follower, the first input end of the voltage follower is electrically connected to the first end of the sixteenth resistor and the first end of the seventeenth resistor respectively, the second end of the seventeenth resistor is electrically connected to the output end of the voltage follower, the second input end of the voltage follower is electrically connected to the voltage signal input end and the first end of the fifth capacitor respectively, the second end of the fifth capacitor and the second end of the sixteenth resistor are grounded.

9. The piezoelectric printer according to claim 1, wherein: The power supply module further includes a power supply module using an RT7294CGJ6F chip, wherein the VIN port of the RT7294CGJ6F chip is electrically connected to the first end of the eighteenth resistor, the first end of the sixth capacitor, and the VIN power supply, respectively; the EN port of the RT7294CGJ6F chip is electrically connected to the second end of the eighteenth resistor, the first end of the nineteenth resistor, and the first end of the seventh capacitor, respectively; the BOOT port of the RT7294CGJ6F chip is electrically connected to the first end of the eighth capacitor, and the SW port of the RT7294CGJ6F chip is electrically connected to the second end of the eighth capacitor and the first end of the first inductor, respectively. One end of the first inductor is electrically connected to the first end of the ninth capacitor, the first end of the twentieth resistor, and the first end of the twenty-first resistor, respectively. The second end of the first inductor is electrically connected to the second end of the ninth capacitor, the second end of the twentieth resistor, the first end of the tenth capacitor, and the first end of the eleventh capacitor, respectively. The second end of the nineteenth resistor, the second end of the seventh capacitor, the second end of the sixth capacitor, a GND port of the RT7294CGJ6F chip, the second end of the twenty-first resistor, the second end of the tenth capacitor, and the second end of the eleventh capacitor are grounded.

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