Testing system of wireless communication rod

Abstract

The utility model relates to the technical field of wireless communication module testing, in particular to a testing system of a wireless communication rod, which comprises an upper computer module, a USB (Universal Serial Bus)-TTL (Transistor-Transistor Logic) module and a transceiving circuit module, one group of signal transceiving ends of the transceiving circuit module are electrically connected with the upper computer module, the other group of signal transceiving ends of the transceiving circuit module are electrically connected with the USB-TTL module, and the USB-TTL module is electrically connected with the upper computer module. The bidirectional conversion circuit is used for performing bidirectional conversion on the level of the USB interface and the TTL level. According to the utility model, the transceiver circuit module is respectively connected with the upper computer module and the USB-to-TTL module, high and low levels are overturned at any time through the level overturning circuit controlled by the switch, correct input levels are ensured, the performance of the wireless communication equipment can be comprehensively tested and monitored, the communication quality and efficiency are ensured, and the reliability of the wireless communication equipment is improved. And the test can be completed without an additional peripheral circuit.

Description

Technical Field

[0001] The utility model relates to the technical field of wireless communication module testing, in particular to a testing system for a wireless communication stick. Background Art

[0002] During the development and testing of wireless communication sticks, USB signals are typically converted to other communication protocols via a converter circuit to interact with the chip. Only when the peripheral hardware is accessible can the communication module interact with the chip. Therefore, testing the peripheral hardware circuits becomes an essential step in the early stages. During testing, a host computer serial port assistant is used to communicate with the communication module on behalf of the chip. Currently, chip peripheral circuits typically need to be built and supplemented separately; this significantly increases the time and cost of testing for companies, making the testing process cumbersome, limiting the production efficiency of electronic products, and not meeting the requirements of technological development.

[0003] Therefore, in order to solve the problem that the existing testing of wireless communication equipment requires the construction of a separate peripheral circuit to test the hardware path of the wireless communication stick, it is necessary to design a testing system for the wireless communication stick.

[0004] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Utility Model Content

[0005] In order to solve the technical problems mentioned in the background technology, the present disclosure provides at least one testing system for a wireless communication stick, which includes:

[0006] Host computer module, USB to TTL module;

[0007] The transceiver circuit module has one set of signal transceiver ends electrically connected to the host computer module, and another set of signal transceiver ends electrically connected to the USB to TTL module, and is used to perform bidirectional conversion between the USB interface level and the TTL level.

[0008] In an optional embodiment, the transceiver circuit module includes: a first signal transceiver circuit unit and a second signal transceiver circuit unit, respectively corresponding to the corresponding groups of signal transceiver ends to form two bidirectional signal paths;

[0009] Among them, one signal path is when the host computer module is tested as a host, the first signal transceiver circuit unit is used to transmit the sending signal of the host computer module to the USB to TTL module; and

[0010] Another signal path is when testing the host computer module as a slave, the second signal transceiver circuit unit is used to transmit the sending signal of the USB to TTL module to the host computer module.

[0011] In an optional embodiment, the first signal transceiver circuit unit includes: a first level flip circuit, a first shaping circuit, and a first level conversion circuit connected in sequence;

[0012] Wherein, the signal receiving end of the first level flip circuit is electrically connected to the signal output end of the host computer module; and

[0013] The signal sending end of the first level conversion circuit is electrically connected to the signal input end of the USB to TTL module.

[0014] In an optional embodiment, the first level flip circuit includes: an NPN transistor Q1, an input resistor R42, a bias resistor R43 and a collector resistor R44;

[0015] The signal output terminal of the host computer module is electrically connected to the base of the NPN transistor Q1 through the input resistor R42;

[0016] The emitter of the NPN transistor Q1 is grounded, and the bias resistor R43 is electrically connected between the emitter and the base;

[0017] The collector of the NPN transistor Q1 is connected to a 3.3V power supply voltage through the collector resistor R44, and the collector is derived as a first signal access point A; and

[0018] The signal output end of the host computer module serves as the second signal access point B;

[0019] Among them, the first shaping circuit chooses to access the first signal access point A to input the sending signal of the host computer module into the first shaping circuit through the first level flipping circuit; or chooses to access the second signal access point B to directly connect the sending signal of the host computer module to the first shaping circuit.

[0020] In an optional embodiment, the first shaping circuit includes: a single-pole double-throw switch S1, a PNP transistor Q2, an input resistor R6, an output resistor R8 and a voltage divider resistor R10;

[0021] The common terminal of the single-pole double-throw switch S1 is electrically connected to the base of the PNP transistor Q2 through the input resistor R6, and the two contacts of the single-pole double-throw switch S1 correspond to the first signal access point A and the second signal access point B respectively;

[0022] The emitter of the PNP transistor Q2 is connected to a 3.3V power supply voltage;

[0023] The output resistor R8 and the voltage-dividing resistor R10 form a series voltage-dividing circuit to divide the shaped voltage outputted from the collector of the PNP transistor Q2 and output the divided voltage to the first level conversion circuit.

[0024] In an optional embodiment, the first level conversion circuit includes: an NPN transistor Q3, a pull-up resistor R9 and an output resistor R11;

[0025] The shaped voltage after voltage division is input to the base of the NPN transistor Q3;

[0026] The emitter of the NPN transistor Q3 is grounded, and the collector thereof outputs the conversion voltage to the signal input terminal of the USB to TTL module through the pull-up resistor R9 and the output resistor R11.

[0027] In an optional embodiment, the second signal transceiver circuit unit includes: a second level flip circuit, a second shaping circuit, and a second level conversion circuit connected in sequence;

[0028] Wherein, the signal receiving end of the second level flip circuit is electrically connected to the signal output end of the USB to TTL module; and

[0029] The signal sending end of the second level conversion circuit is electrically connected to the signal input end of the host computer module.

[0030] In an optional embodiment, the second level flip circuit includes: an NPN transistor Q4, an input resistor R46, a bias resistor R45 and a collector resistor R47;

[0031] The signal output terminal of the USB to TTL module is electrically connected to the base of the NPN transistor Q4 through the input resistor R46;

[0032] The emitter of the NPN transistor Q4 is grounded, and the bias resistor R45 is electrically connected between the emitter and the base;

[0033] The collector of the NPN transistor Q4 is connected to a 5V power supply voltage through the collector resistor R47, and the collector is derived as a third signal access point C; and

[0034] The signal output end of the USB to TTL module serves as the fourth signal access point D;

[0035] Among them, the second shaping circuit selects to access the third signal access point C to input the sending signal of the USB to TTL module into the second shaping circuit through the second level flip circuit; or selects to access the fourth signal access point D to directly connect the sending signal of the USB to TTL module to the second shaping circuit.

[0036] In an optional embodiment, the second shaping circuit includes: a single-pole double-throw switch S2, a PNP transistor Q5, an input resistor R22, an output resistor R18 and a voltage divider resistor R23;

[0037] The common terminal of the single-pole double-throw switch S2 is electrically connected to the base of the PNP transistor Q5 through the input resistor R22, and the two contacts of the single-pole double-throw switch S2 correspond to the third signal access point C and the fourth signal access point D respectively;

[0038] The emitter of the PNP transistor Q5 is connected to a 5V power supply voltage;

[0039] The output resistor R18 and the voltage-dividing resistor R23 form a series voltage-dividing circuit to divide the shaped voltage outputted from the collector of the PNP transistor Q5 and output the divided voltage to the second level conversion circuit.

[0040] In an optional embodiment, the second level conversion circuit includes: an NPN transistor Q6, a pull-up resistor R17, an output resistor R16 and a filter capacitor C5;

[0041] The shaped voltage after voltage division is input to the base of the NPN transistor Q6;

[0042] The emitter of the NPN transistor Q6 is grounded, and its collector outputs the conversion voltage through the pull-up resistor R17, and is connected to the signal input end of the host computer module through the RC filter circuit composed of the output resistor R16 and the filter capacitor C5.

[0043] The beneficial effects of the utility model are as follows: the utility model is connected to the host computer module and the USB to TTL module respectively through the transceiver circuit module, and the level flipping circuit controlled by the switch flips the high and low levels at any time to ensure the correct input level, and can comprehensively test and monitor the performance of the wireless communication equipment to ensure the quality and efficiency of the communication, and the test can be completed without additional peripheral circuits.

[0044] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 A functional block diagram of a test system according to an embodiment of the present disclosure;

[0048] Figure 2 A circuit schematic diagram of a test system provided in an embodiment of the present disclosure;

[0049] Figure 3 A circuit schematic diagram of a first signal transceiver circuit unit provided in an embodiment of the present disclosure;

[0050] Figure 4 This is a circuit schematic diagram of the second signal transceiver circuit unit provided in an embodiment of the present disclosure.

[0051] In the picture:

[0052] A first level flip circuit 101, a first shaping circuit 102, and a first level conversion circuit 103;

[0053] A second level flip circuit 201 , a second shaping circuit 202 , and a second level conversion circuit 203 . DETAILED DESCRIPTION

[0054] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0055] The terms used herein are intended only to describe specific exemplary configurations and are not intended to be limiting. As used herein, the singular articles "a," "an," and "the" may also be intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprise," "include," and "have" are inclusive and thus specify the presence of features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0056] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Thus, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, such that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations, aspects, or designs. Instead, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0057] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0058] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0059] like Figure 1 As shown, at least one embodiment provides a testing system for a wireless communication stick, comprising a host computer module, a USB-to-TTL module, and a transceiver circuit module. A set of signal transceivers in the transceiver circuit module is electrically connected to the host computer module, and another set of signal transceivers is electrically connected to the USB-to-TTL module, for bidirectional conversion between the USB interface voltage level and the TTL voltage level. Since the transceiver circuit module includes two bidirectional signal paths, a pair of signal receiving and signal transmitting terminals is provided between the module and the host computer module to form a set of signal transceivers. Similarly, a pair of signal receiving and signal transmitting terminals is provided between the module and the USB-to-TTL module to form another set of signal transceivers, corresponding to the first and second signal transceiver circuit units in the transceiver circuit module. This is described in detail in the following embodiments.

[0060] See Figure 2Specifically, the transceiver circuit module includes: a first signal transceiver circuit unit and a second signal transceiver circuit unit, which respectively correspond to the signal transceiver ends of the corresponding groups to form two bidirectional signal paths; wherein, one signal path is when the upper computer module is tested as a host, the first signal transceiver circuit unit is used to transmit the sending signal of the upper computer module to the USB to TTL module; and the other signal path is when the upper computer module is tested as a slave, the second signal transceiver circuit unit is used to transmit the sending signal of the USB to TTL module to the upper computer module. Figure 2 In the diagram, arrows are used to indicate the direction of signal transmission, which can clearly indicate the specific locations of the signal receiving end and the signal sending end.

[0061] As for the specific signal receiving end and signal sending end of the host computer module, they are determined according to its specific model. This embodiment does not limit the specific model of the host computer module. Similarly, the specific signal receiving end and signal sending end of the USB to TTL module are also determined according to its specific model. This embodiment does not limit the specific model of the USB to TTL module. Those skilled in the art can reasonably select the specific models of the above-mentioned host computer module and USB to TTL module according to the specific usage scenario, and can implement the specific solution of this embodiment.

[0062] See Figure 2 and Figure 3 , the figure shows an optional implementation of the first signal transceiver circuit unit. Specifically, the first signal transceiver circuit unit includes: a first level flip circuit 101, a first shaping circuit 102 and a first level conversion circuit 103 connected in sequence; wherein, the signal receiving end of the first level flip circuit 101 is electrically connected to the signal output end of the host computer module; and the signal sending end of the first level conversion circuit 103 is electrically connected to the signal input end of the USB to TTL module.

[0063] The following is based on Figure 2 and Figure 3 As shown, each circuit is described step by step, as follows:

[0064] Some embodiments provide a first level flip circuit 101, which may specifically include: an NPN transistor Q1, an input resistor R42, a bias resistor R43 and a collector resistor R44; wherein the signal output end of the host computer module is electrically connected to the base of the transistor Q1 through the input resistor R42.

[0065] The emitter of the NPN transistor Q1 is grounded, and a bias resistor R43 is electrically connected between the emitter and the base. The collector of the NPN transistor Q1 is connected to a 3.3V power supply voltage via a collector resistor R44, and the collector is derived as a first signal access point A. The signal output end of the host computer module serves as a second signal access point B. The first shaping circuit 102 selects to access the first signal access point A to input the transmit signal of the host computer module into the first shaping circuit 102 via the first level-flipping circuit 101, or selects to access the second signal access point B to directly connect the transmit signal of the host computer module to the first shaping circuit 102. Similarly, in some embodiments, the first level-flipping circuit 101 can also be constructed using a PNP transistor based on the above circuit. This embodiment is merely an exemplary description of the above level-flipping circuit and does not limit its structure.

[0066] The first shaping circuit 102 cooperates with the first level flip circuit 101, please continue to refer to Figure 2 and Figure 3 The first shaping circuit 102 may include a single-pole double-throw switch S1, a PNP transistor Q2, an input resistor R6, an output resistor R8 and a voltage divider resistor R10.

[0067] In some embodiments, the single-pole double-throw switch S1 can be implemented by, but is not limited to, a manual dial switch, or an electronic switch. This embodiment does not limit whether it is manually controlled or electronically controlled.

[0068] Specifically, the common terminal of the single-pole double-throw switch S1 is electrically connected to the base of the PNP transistor Q2 via the input resistor R6, and the two contacts of the single-pole double-throw switch S1 correspond to the first signal access point A and the second signal access point B, respectively; the emitter of the PNP transistor Q2 is connected to the 3.3V power supply voltage; the output resistor R8 and the voltage divider resistor R10 form a series voltage divider circuit to divide the shaped voltage output by the collector of the PNP transistor Q2 and output it to the first level conversion circuit 103.

[0069] like Figure 2 and Figure 3 As shown, in some embodiments, the first level conversion circuit 103 may also include: an NPN transistor Q3, a pull-up resistor R9 and an output resistor R11; wherein the shaped voltage after voltage division is input to the base of the NPN transistor Q3; the emitter of the NPN transistor Q3 is grounded, and its collector outputs the conversion voltage to the signal input end of the USB to TTL module through the pull-up resistor R9 and the output resistor R11.

[0070] In some embodiments, the structures of the first signal transceiver unit and the second signal transceiver unit can be similar, or they can be different, as long as the specific effects of this embodiment are achieved. To better illustrate the specific implementation process of this embodiment, the second signal transceiver unit is described as follows using a structure similar to that of the first signal transceiver unit:

[0071] See Figure 2 and Figure 4 The second signal transceiver circuit unit may include: a second level flip circuit 201, a second shaping circuit 202 and a second level conversion circuit 203 connected in sequence; wherein the signal receiving end of the second level flip circuit 201 is electrically connected to the signal output end of the USB to TTL module; and the signal sending end of the second level conversion circuit 203 is electrically connected to the signal input end of the host computer module.

[0072] As an optional technical solution, the second level-flipping circuit 201 includes: an NPN transistor Q4, an input resistor R46, a bias resistor R45, and a collector resistor R47; wherein the signal output end of the USB-to-TTL module is electrically connected to the base of the NPN transistor Q4 via the input resistor R46; the emitter of the NPN transistor Q4 is grounded, and a bias resistor R45 is electrically connected between the emitter and the base; the collector of the NPN transistor Q4 is connected to a 5V power supply voltage via the collector resistor R47, and the collector is derived as a third signal access point C; and the signal output end of the USB-to-TTL module serves as a fourth signal access point D; wherein the second shaping circuit 202 selects access to the third signal access point C to input the transmit signal of the USB-to-TTL module to the second shaping circuit 202 via the second level-flipping circuit 201; or selects access to the fourth signal access point D to directly connect the transmit signal of the USB-to-TTL module to the second shaping circuit 202.

[0073] See Figure 2 and Figure 4 The second shaping circuit 202 includes a single-pole double-throw switch S2, a PNP transistor Q5, an input resistor R22, an output resistor R18, and a voltage-dividing resistor R23. The common terminal of the single-pole double-throw switch S2 is electrically connected to the base of the PNP transistor Q5 via the input resistor R22, and the two contacts of the single-pole double-throw switch S2 correspond to the third signal access point C and the fourth signal access point D, respectively. The emitter of the PNP transistor Q5 is connected to a 5V power supply voltage. The output resistor R18 and the voltage-dividing resistor R23 form a series voltage-dividing circuit to divide the shaped voltage outputted from the collector of the PNP transistor Q5 and output it to the second level conversion circuit 203.

[0074] See Figure 2 and Figure 4The second level conversion circuit 203 includes: an NPN transistor Q6, a pull-up resistor R17, an output resistor R16, and a filter capacitor C5; wherein the shaped voltage after voltage division is input to the base of the NPN transistor Q6; the emitter of the NPN transistor Q6 is grounded, and its collector outputs the conversion voltage through the pull-up resistor R17, and is connected to the signal input end of the host computer module through the RC filter circuit composed of the output resistor R16 and the filter capacitor C5.

[0075] The RC filter circuit is an optional circuit that can remove noise (such as ripple) in the conversion voltage and improve voltage stability.

[0076] In this embodiment, the power supply voltage is divided into 3.3V and 5V. The selection of the above power supply voltage can be adjusted according to the specific model of the transistor, for example, such as silicon tube, germanium tube, NPN, PNP and power size, etc. The above power supply voltage is a reference value.

[0077] In summary, the utility model is connected to the host computer module and the USB to TTL module respectively through the transceiver circuit module, and the level flipping circuit controlled by the switch can flip the high and low levels at any time to ensure the correct input level. It can comprehensively test and monitor the performance of wireless communication equipment to ensure the quality and efficiency of communication, and the test can be completed without additional peripheral circuits.

[0078] In the description of the embodiments of the present invention, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to electrical connection, direct connection, indirect connection through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0079] In the description of the present invention, the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0080] Based on the above-mentioned ideal embodiment of the present invention, and in accordance with the above description, relevant personnel can make various changes and modifications without departing from the technical scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, but must be determined according to the scope of the claims.

Claims

1. A testing system for a wireless communication stick, characterized in that: include: Host computer module, USB to TTL module; The transceiver circuit module has one set of signal transceiver ends electrically connected to the host computer module, and another set of signal transceiver ends electrically connected to the USB to TTL module, and is used to perform bidirectional conversion between the USB interface level and the TTL level.

2. The test system according to claim 1, wherein: The transceiver circuit module includes: a first signal transceiver circuit unit and a second signal transceiver circuit unit, which respectively correspond to the corresponding groups of signal transceiver ends to form two bidirectional signal paths; Among them, one signal path is when the host computer module is tested as a host, the first signal transceiver circuit unit is used to transmit the sending signal of the host computer module to the USB to TTL module; and Another signal path is when testing the host computer module as a slave, the second signal transceiver circuit unit is used to transmit the sending signal of the USB to TTL module to the host computer module.

3. The test system according to claim 2, wherein: The first signal transceiver circuit unit includes: a first level flip circuit, a first shaping circuit and a first level conversion circuit connected in sequence; Wherein, the signal receiving end of the first level flip circuit is electrically connected to the signal output end of the host computer module; and The signal sending end of the first level conversion circuit is electrically connected to the signal input end of the USB to TTL module.

4. The test system according to claim 3, characterized in that The first level flip circuit includes: an NPN transistor Q1, an input resistor R42, a bias resistor R43 and a collector resistor R44; The signal output terminal of the host computer module is electrically connected to the base of the NPN transistor Q1 through the input resistor R42; The emitter of the NPN transistor Q1 is grounded, and the bias resistor R43 is electrically connected between the emitter and the base; The collector of the NPN transistor Q1 is connected to a 3.3V power supply voltage through the collector resistor R44, and the collector is derived as a first signal access point A; and The signal output end of the host computer module serves as the second signal access point B; Among them, the first shaping circuit chooses to access the first signal access point A to input the sending signal of the host computer module into the first shaping circuit through the first level flipping circuit; or chooses to access the second signal access point B to directly connect the sending signal of the host computer module to the first shaping circuit.

5. The test system according to claim 4, characterized in that: The first shaping circuit includes: a single-pole double-throw switch S1, a PNP transistor Q2, an input resistor R6, an output resistor R8 and a voltage divider resistor R10; The common terminal of the single-pole double-throw switch S1 is electrically connected to the base of the PNP transistor Q2 through the input resistor R6, and the two contacts of the single-pole double-throw switch S1 correspond to the first signal access point A and the second signal access point B respectively; The emitter of the PNP transistor Q2 is connected to a 3.3V power supply voltage; The output resistor R8 and the voltage-dividing resistor R10 form a series voltage-dividing circuit to divide the shaped voltage outputted from the collector of the PNP transistor Q2 and output the divided voltage to the first level conversion circuit.

6. The test system according to claim 5, characterized in that: The first level conversion circuit includes: an NPN transistor Q3, a pull-up resistor R9 and an output resistor R11; The shaped voltage after voltage division is input to the base of the NPN transistor Q3; The emitter of the NPN transistor Q3 is grounded, and the collector thereof outputs the conversion voltage to the signal input terminal of the USB to TTL module through the pull-up resistor R9 and the output resistor R11.

7. The test system according to claim 2, wherein: The second signal transceiver circuit unit includes: a second level flip circuit, a second shaping circuit and a second level conversion circuit connected in sequence; Wherein, the signal receiving end of the second level flip circuit is electrically connected to the signal output end of the USB to TTL module; and The signal sending end of the second level conversion circuit is electrically connected to the signal input end of the host computer module.

8. The test system according to claim 7, characterized in that: The second level flip circuit includes: an NPN transistor Q4, an input resistor R46, a bias resistor R45 and a collector resistor R47; The signal output terminal of the USB to TTL module is electrically connected to the base of the NPN transistor Q4 through the input resistor R46; The emitter of the NPN transistor Q4 is grounded, and the bias resistor R45 is electrically connected between the emitter and the base; The collector of the NPN transistor Q4 is connected to a 5V power supply voltage through the collector resistor R47, and the collector is derived as a third signal access point C; and The signal output end of the USB to TTL module serves as the fourth signal access point D; Among them, the second shaping circuit selects to access the third signal access point C to input the sending signal of the USB to TTL module into the second shaping circuit through the second level flip circuit; or selects to access the fourth signal access point D to directly connect the sending signal of the USB to TTL module to the second shaping circuit.

9. The test system according to claim 8, characterized in that: The second shaping circuit includes: a single-pole double-throw switch S2, a PNP transistor Q5, an input resistor R22, an output resistor R18 and a voltage divider resistor R23; The common terminal of the single-pole double-throw switch S2 is electrically connected to the base of the PNP transistor Q5 through the input resistor R22, and the two contacts of the single-pole double-throw switch S2 correspond to the third signal access point C and the fourth signal access point D respectively; The emitter of the PNP transistor Q5 is connected to a 5V power supply voltage; The output resistor R18 and the voltage-dividing resistor R23 form a series voltage-dividing circuit to divide the shaped voltage outputted from the collector of the PNP transistor Q5 and output the divided voltage to the second level conversion circuit.

10. The test system according to claim 9, characterized in that: The second level conversion circuit includes: an NPN transistor Q6, a pull-up resistor R17, an output resistor R16 and a filter capacitor C5; The shaped voltage after voltage division is input to the base of the NPN transistor Q6; The emitter of the NPN transistor Q6 is grounded, and its collector outputs the conversion voltage through the pull-up resistor R17, and is connected to the signal input end of the host computer module through the RC filter circuit composed of the output resistor R16 and the filter capacitor C5.

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