Packaging chip, circuit board assembly and electronic equipment
By setting a surrounding edge at the edge of the substrate and forming a heat conduction path, the problems of mechanical deformation and thermal warping of the substrate are solved, the rigidity and welding reliability of the substrate are improved, and efficient heat dissipation is achieved, reducing costs.
Patent Information
- Application Number
- CN202422366806.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2034-09-26
AI Technical Summary
In integrated circuits, substrates with large areas and small thickness are prone to mechanical deformation and thermal warpage at high temperatures, resulting in poor soldering and poor connection reliability.
A surrounding edge is set at the edge of the substrate and fixedly connected to the substrate by welding or bonding to enhance the rigidity of the substrate. A heat conduction path is formed through the stratum and the surrounding edge, and efficient heat dissipation is achieved by combining the heat sink and the thermal interface material layer.
It effectively reduces the mechanical deformation of the substrate and thermal warpage at high temperatures, improves the mechanical reliability and soldering yield of the substrate, and at the same time achieves efficient heat dissipation and reduces overall costs.
Smart Images
Figure CN223308994U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a packaged chip, a circuit board assembly, and an electronic device. Background Art
[0002] In integrated circuit technology, substrates (such as grid array boards) are used to transfer electronic components to circuit structures (such as motherboards), achieving electrical connections between the intended electronic components and the circuit structure. The greater the number of electronic components on a substrate, the larger the substrate area. Due to the limited thickness of electronic devices, substrates must be thin. Large, thin substrates have low rigidity and are prone to mechanical deformation and thermal warping at high temperatures, leading to poor soldering and connection reliability between the substrate and the circuit structure. Utility Model Content
[0003] The embodiments of the present application provide a packaged chip, a circuit board assembly, and an electronic device, so that a packaged chip substrate with a large area and a small thickness is not easily subject to mechanical deformation and thermal warping deformation under high temperature.
[0004] The embodiments of this application adopt the following technical solutions:
[0005] In a first aspect, embodiments of the present application provide a packaged chip, comprising: a substrate, a first electronic device, and a surround. The substrate has a first surface, a second surface, and a side surface. The first and second surfaces are disposed opposite each other along the thickness direction of the substrate, and the side surface is connected between the first and second surfaces. The first electronic device is mounted on the first surface. The second surface has a plurality of pins. The surround is connected to at least a portion of an edge of the first surface and / or is connected to at least a portion of the side surface.
[0006] In the packaged chip provided in the embodiment of the present application, the first electronic device is mounted on the first surface of the substrate, and the second surface of the substrate has a plurality of pins. The surrounding edge can be connected to the edge of the first surface and the side of the substrate to improve the rigidity of the packaged chip. Even for a substrate with a large area and a small thickness, after the surrounding edge is set at the edge of the substrate, the mechanical deformation and thermal warping deformation of the substrate under high temperature can be reduced, thereby improving the mechanical reliability and welding yield of the substrate. Compared with the related art of thickening the substrate or changing the substrate material to reduce the amount of deformation, the present embodiment sets a surrounding edge on the substrate to reduce the amount of deformation, which can reduce the overall cost.
[0007] In an optional implementation, the surrounding edge and the base plate are welded or bonded together, which can achieve a reliable and fixed connection between the surrounding edge and the base plate and is easy to implement.
[0008] In one optional implementation, the surrounding edge is metal, and the substrate has a ground layer within it. The ground layer is connected to the first electronic device, enabling heat conduction between the two. Even if a high-heat-generating first electronic device is installed on a large substrate, the heat generated by the first electronic device can be conducted to the surrounding edge through the ground layer, achieving efficient heat dissipation.
[0009] In one optional implementation, the surrounding edge is metal, and heat conduction between the first electronic device and the surrounding edge is achieved through the substrate's ground layer. The packaged chip also includes a heat sink, which is in contact with the surrounding edge, with a thermal interface material layer disposed between the heat sink and the surrounding edge. Heat generated by the first electronic device is sequentially conducted through the ground layer, the surrounding edge, and the thermal interface material layer to the heat sink, where it is dissipated into the surrounding space, thereby improving heat dissipation capacity. The thermal interface material layer reduces the contact thermal resistance between the heat sink and the surrounding edge, thereby improving heat dissipation performance.
[0010] In an optional implementation, the heat sink may include a heat conductor, a heat pipe, and a fan. The heat conductor may be a metal structure, with a thermal interface material layer provided between one end of the heat conductor and the surrounding edge, and the other end of the heat conductor in contact with the heat pipe. The heat conductor is used to transfer heat from the surrounding edge to the heat pipe. The heat pipe is a vacuum cavity with a microstructure on the inner wall, and the heat pipe has an evaporation zone and a condensation zone. When heat is transferred to the evaporation zone, the liquid cooling medium in the cavity is heated and vaporized. After absorbing heat, the liquid cooling medium rapidly expands in volume, and the gaseous cooling medium quickly fills the entire cavity. When the gaseous cooling medium contacts the relatively cold condensation zone, it condenses and releases the heat accumulated during evaporation. The condensed liquid cooling medium returns to the evaporation zone through the microstructured capillary tube. This process is cyclical, transferring heat from the evaporation zone to the condensation zone. The airflow from the fan removes the heat from the evaporation zone of the heat pipe.
[0011] In an optional implementation, the heat sink may include a heat conductor and a fan. The heat conductor may be a heat sink fin assembly. Heat from the peripheral edge is transferred to the heat sink fin assembly, and the airflow from the fan removes the heat from the heat sink fin assembly.
[0012] In one optional implementation, the perimeter includes a first side portion, which faces and connects to the edge of the first surface. Securing the first side portion to the edge of the first surface of the substrate can enhance the strength and rigidity of the substrate, reduce mechanical deformation and thermal warpage at high temperatures, and improve the mechanical reliability and soldering yield of the substrate. The first side portion and the edge of the first surface can be connected by welding, bonding, or other methods.
[0013] In one optional implementation, the thickness of the first side portion is less than or equal to the thickness of the first electronic device. If the overall thickness of the packaged chip does not increase even if the substrate surrounds the chip, the thickness of the first side portion can be increased by fully utilizing the thickness space at the edge of the substrate. This can improve the strength of the surround, better control the flatness of the substrate, and enhance the strength and rigidity of the packaged chip.
[0014] In one optional implementation, a first spacing is formed between the inner edge of the first side portion and the first electronic device adjacent to the first side portion on the plane of the first surface, and the width of the first side portion is greater than or equal to the first spacing. By maximizing the area of the first side portion, the connection area between the first side portion and the edge of the first surface is increased, ensuring a secure connection between the first side portion and the edge of the first surface, thereby reducing the risk of separation between the edge and the substrate in a drop impact scenario.
[0015] In an optional implementation, when the first side portion and the first surface are welded, the larger area of the first side portion can increase the amount of solder, so that the first side portion and the first surface are reliably connected, and the risk of desoldering of the edge and the substrate in a drop impact scenario is reduced.
[0016] In an optional implementation, when the first side portion and the first surface are bonded, the larger area of the first side portion can increase the amount of glue, so that the first side portion and the first surface are reliably connected, reducing the risk of debonding of the edge and the substrate in a drop impact scenario.
[0017] In an optional implementation, the first surface has a plurality of ground holes at the corresponding surrounding edge, the ground layer extends to the ground holes, the first surface is provided with a soldering pad, the soldering pad is at least partially located in the ground hole and connected to the ground layer, and the soldering pad is connected to the surrounding edge. The substrate and the surrounding edge are connected by the soldering pad, so that a portion of the soldering pad is located in the ground hole of the substrate. The substrate and the surrounding edge are reliably connected by the larger soldering pad, thereby improving the bonding strength and reducing the risk of separation of the surrounding edge and the substrate in a drop impact scenario. The ground layer and the surrounding edge of the substrate are connected by the soldering pad, and the heat generated by the first electronic device can be conducted in sequence along the ground layer, soldering pad, surrounding edge, thermal interface material layer and heat sink of the substrate, and dissipated from the heat sink to the surrounding space, thereby achieving efficient heat dissipation.
[0018] In one optional implementation, the substrate is rectangular or another shape, the perimeter extends along the edge of the substrate, and multiple ground holes are provided along the edge of the first surface of the substrate, with the ground layer of the substrate extending to the ground holes. Different portions of the pads are filled in the multiple ground holes, and the perimeter is fixed to the pads of the substrate, ensuring a reliable connection between the perimeter and the substrate.
[0019] In one optional implementation, the perimeter edge includes a first side portion that faces and connects to an edge of the first surface, and a second side portion that connects to the first side portion and faces and connects to the side surface. This can further enhance the strength and rigidity of the substrate, reduce mechanical deformation and thermal warpage at high temperatures, and improve the mechanical reliability and soldering yield of the substrate.
[0020] In an optional implementation, the first side portion and the edge of the first surface, and the second side portion and the side surface of the substrate may be connected by welding, bonding or other methods.
[0021] In an optional implementation, the surrounding edge is a hard metal surrounding edge, and the surrounding edge includes a first side portion and a second side portion, and welding is adopted between the first side portion and the edge of the first surface, and between the second side portion and the side surface of the substrate.
[0022] In an optional implementation, the edge is a hard metal edge, including a first side portion and a second side portion, and the first side portion is bonded to the edge of the first surface, and the second side portion is bonded to the side of the substrate. Glue can be applied to the substrate by dispensing.
[0023] In an optional implementation, the first side portion and the second side portion are an integral structure, and the first side portion and the second side portion can be formed by bending a metal piece. Using a metal piece to form the first side portion and the second side portion by bending is easy to form and can better control the flatness of the surrounding edge.
[0024] In one optional implementation, the perimeter includes a first side portion that faces and connects to an edge of the first surface. The perimeter also includes a positioning post connected to a side of the first side portion that faces the substrate. The substrate has a positioning hole, the ground layer extends to the positioning hole, and the positioning post is disposed within the positioning hole and connected to the ground layer. This can further enhance the strength and rigidity of the substrate, reduce mechanical deformation and thermal warpage at high temperatures, and improve the mechanical reliability and soldering yield of the substrate.
[0025] In one optional implementation, the first side portion and the edge of the first surface, and the positioning posts and the wall of the positioning hole, can be connected by welding, bonding, or other methods. The substrate's base layer, the surrounding positioning posts, and the first side portion are sequentially connected. Heat generated by the first electronic device is sequentially conducted along the substrate's base layer, the surrounding positioning posts and the first side portion, the thermal interface material layer, and the heat sink, and is dissipated from the heat sink to the surrounding space, achieving efficient heat dissipation.
[0026] In one optional implementation, the substrate is rectangular or otherwise shaped, the perimeter extends along the edge of the substrate, and a plurality of positioning holes are defined at the edge of the substrate, with the substrate ground layer extending to the positioning holes. A first side portion of the perimeter is secured to the edge of the first surface of the substrate, and a plurality of positioning posts are respectively secured to the positioning holes, providing a secure connection between the perimeter and the substrate.
[0027] In one optional implementation, the first side portion and the positioning post are assembled, with the positioning post riveted or welded to the first side portion. This allows for secure attachment of the positioning post to the first side portion, facilitating reliable connection between the surrounding edge and the substrate edge. It also allows for heat conduction between the positioning post and the first side portion. The positioning post and the first side portion, combined with the substrate's ground layer, thermal interface material layer, and heat sink, effectively dissipate heat from the first electronic device.
[0028] In an optional implementation, the first side portion and the positioning column are an integrated structure, and the first side portion and the positioning column can be formed by bending a metal piece. The first side portion and the positioning column are formed by bending a metal piece, which is easy to form.
[0029] In one optional implementation, the substrate is rectangular or otherwise shaped, the first side portion of the perimeter extends along an edge of the substrate, and a plurality of positioning posts are formed on the outer edge of the first side portion. The first side portion is secured to an edge of the first surface of the substrate, and the plurality of positioning posts are respectively secured to the positioning holes, providing a secure connection between the perimeter and the substrate.
[0030] In one optional implementation, the perimeter edge does not have a first side portion, but instead includes a second side portion, which faces and connects to the side surface of the substrate. Securing the second side portion to the side surface of the substrate can enhance the substrate's strength and rigidity, reduce mechanical deformation and thermal warpage at high temperatures, and improve the substrate's mechanical reliability and soldering yield. The second side portion can be connected to the side surface of the substrate by welding, bonding, or other methods.
[0031] In one optional implementation, the heat sink contacts the second side of the surround, with a thermal interface material layer disposed between the heat sink and the surround. The second side is connected to the ground layer of the substrate to facilitate heat conduction between the two. Heat generated by the first electronic device during operation is sequentially conducted to the ground layer, the surround, the thermal interface material layer, and the heat sink, where it is then dissipated to the surrounding space, thereby enhancing heat dissipation capacity.
[0032] In an optional implementation, the substrate is polygonal, such as a rectangle, a pentagon, etc.
[0033] In an optional implementation, at least a portion of an edge of the substrate is arc-shaped.
[0034] In an optional implementation, the substrate has a notch, and the notch area is used to avoid predetermined components. The shape of the substrate can be set as needed.
[0035] In one optional implementation, the perimeter is a closed-loop structure. A closed-loop structure means the perimeter extends around the edge of the substrate without openings. A substrate with a perimeter can increase the strength and rigidity of the overall structure, reduce mechanical deformation and thermal warpage at high temperatures, and improve the mechanical reliability and soldering yield of the substrate.
[0036] In one optional implementation, the perimeter is an open ring structure. An open ring structure extends around the edge of the substrate and has an opening. A substrate with a perimeter can increase the strength and rigidity of the overall structure, reduce mechanical deformation and thermal warpage at high temperatures, and improve the mechanical reliability and soldering yield of the substrate.
[0037] In an optional implementation, the substrate is rectangular, and the surrounding edge is a closed ring structure and extends substantially along the four sides of the rectangle.
[0038] In an optional implementation, the substrate is in the shape of a combination of a rectangle and an arc, and the surrounding edge is an open ring structure and extends substantially along three sides of the rectangle.
[0039] In an optional implementation, the substrate is in the shape of a rectangle with a notch provided at one corner, the surrounding edge is an open ring structure and extends substantially along the four sides of the rectangle, and no surrounding edge is provided at the edge of the notch.
[0040] In an optional implementation, the substrate is rectangular, and the surrounding edge is an open ring structure and extends substantially along three sides of the rectangle.
[0041] In an optional implementation, a border may be provided on one or more edges of the substrate, both of which may enhance the strength and rigidity of the substrate.
[0042] In an optional implementation, the packaged chip may be a grid array packaged chip, the pins of which may be metal contacts, and the connection ends of the circuit structure are connected to the metal contacts of the grid array packaged chip to achieve electrical connection.
[0043] In a second aspect, an embodiment of the present application provides a circuit board assembly, comprising a circuit structure and the aforementioned packaged chip, wherein the pins of the packaged chip are connected to the circuit structure to achieve conduction between the packaged chip and the circuit structure.
[0044] In an optional implementation, the circuit structure can be a circuit board, and the packaged chip and the circuit board can be assembled to form a circuit board assembly to achieve electrical connection between the packaged chip and the circuit board. The pins of the packaged chip and the circuit board can be connected via multiple conductive bumps or pins.
[0045] In a third aspect, an embodiment of the present application provides an electronic device, comprising the aforementioned packaged chip or the aforementioned circuit board assembly. The packaged chip or the circuit board assembly may be disposed in a device housing. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Figure 1 (a) to (c) are schematic diagrams of different circuit board assemblies in the related art;
[0047] Figure 2A three-dimensional exploded view of a packaged chip provided in an embodiment of the present application;
[0048] Figure 3 for Figure 2 A three-dimensional assembly drawing of the packaged chip;
[0049] Figure 4 for Figure 3 A cross-sectional view of the packaged chip along line AA;
[0050] Figure 5 for Figure 2 A schematic diagram of a substrate in a packaged chip;
[0051] Figure 6 for Figure 4 Schematic diagram of the packaged chip after the heat sink is set;
[0052] Figure 7 A three-dimensional exploded view of a packaged chip provided in another embodiment of the present application;
[0053] Figure 8 for Figure 7 A three-dimensional assembly drawing of the packaged chip;
[0054] Figure 9 for Figure 8 A cross-sectional view of the packaged chip along line BB;
[0055] Figure 10 for Figure 7 A schematic diagram of a substrate in a packaged chip;
[0056] Figure 11 for Figure 9 Schematic diagram of the packaged chip after the heat sink is set;
[0057] Figure 12 A three-dimensional exploded view of a packaged chip provided in another embodiment of the present application;
[0058] Figure 13 for Figure 12 A three-dimensional assembly drawing of the packaged chip;
[0059] Figure 14 for Figure 13 A cross-sectional view of the packaged chip along line CC;
[0060] Figure 15 for Figure 12 A schematic diagram of a substrate in a packaged chip;
[0061] Figure 16 for Figure 14 Schematic diagram of the packaged chip after the heat sink is set;
[0062] Figure 17A schematic diagram of a packaged chip provided in another embodiment of the present application;
[0063] Figures 18 to 21 Schematic diagrams of packaged chips provided in different embodiments of the present application;
[0064] Figure 22 A schematic diagram of a circuit board assembly provided in an embodiment of the present application.
[0065] Description of reference numerals:
[0066] 1-PCB assembly; 1a-substrate; 1b-electronic device; 1d-conductive bump; 2-circuit structure;
[0067] 10-packaged chip; 11-substrate; 11a-first surface; 11b-second surface; 11c-side; 111-ground layer; 112-ground hole; 113-solder pad; 114-positioning hole; 115-notch; 12-first electronic device; 13-surrounding edge; 131-first side; 132-second side; 133-positioning column; 14-heat sink; 141-heat conducting member; 15-thermal interface material layer; 20-circuit structure; 21-conductive bump; 100-circuit board assembly. DETAILED DESCRIPTION
[0068] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application. Although the description of this application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to this embodiment. On the contrary, the purpose of introducing the application in conjunction with the embodiment is to cover other options or modifications that may be extended based on the claims of this application. In order to provide an in-depth understanding of the application, the following description will contain many specific details. This application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of this application, some specific details will be omitted in the description. It should be noted that the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict.
[0069] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.
[0070] It should be understood that in the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. The orientation or positional relationship indicated by the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.
[0071] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.
[0072] In the embodiments of this application, "and / or" is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.
[0073] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0074] See Figure 1In (a), a circuit board assembly 1 of the related art can use a substrate 1a (such as a grid array board) to transfer some electronic devices 1b to a circuit structure 1c (such as a motherboard). The pins of the substrate 1a are connected to the circuit structure 1c to achieve electrical connection between the predetermined electronic devices 1b and the circuit structure 1c. The warpage tolerance range L1 of the substrate 1a can be less than or equal to 100 microns (μm), and deformation of the substrate 1a within the above-mentioned warpage tolerance range L1 is acceptable. The left and right ends of the substrate 1a exceed the above-mentioned warpage tolerance range L1, and the pins of the substrate 1a separate the conductive bumps 1d of the circuit structure 1c, causing empty soldering. Moreover, a high-heat-generating electronic device 1b is provided on the substrate 1a, and the heat of the electronic device 1b is difficult to be effectively released, which may cause damage to the function of the electronic device 1b and affect the working performance.
[0075] See Figure 1 In (b), another circuit board assembly 1 of the related art can improve the rigidity of the substrate 1a by increasing the thickness L2 of the substrate 1a, thereby reducing mechanical deformation and thermal warping deformation under high temperature. This method is not conducive to the overall thinness of the structure. After the area of the substrate 1a increases to a certain size, such as a length and width of more than 50 mm, it is difficult to effectively reduce the high-temperature deformation caused by welding of the substrate 1a by increasing the thickness L2 of the substrate 1a. It is also difficult to effectively improve the external release of heat from the electronic device 1b.
[0076] See Figure 1 (c) in the related art, another circuit board assembly 1 can change the material of the substrate 1a. For example, the substrate 1a is made of a material with a higher glass transition temperature (glass transition temperature, Tg) to improve the thermal deformation problem of the substrate 1a, which will increase the cost of the substrate 1a. After the area of the substrate 1a increases to a certain size, such as more than 50 mm in length and width, it is difficult to effectively reduce the high-temperature deformation of the substrate 1a caused by welding by changing the material of the substrate 1a. Alternatively, the substrate 1a uses a plate with a higher thermal conductivity to improve the heat dissipation capacity of the substrate 1a, which will increase the cost of the substrate 1a.
[0077] See Figures 2 to 5 An embodiment of the present application provides a packaged chip 10, comprising: a substrate 11, a first electronic device 12, and a surround 13. The substrate 11 has a first surface 11a, a second surface 11b, and a side surface 11c. The first surface 11a and the second surface 11b are arranged in back-to-back relationship along the thickness direction Z of the substrate 11, and the side surface 11c is connected between the first surface 11a and the second surface 11b. The first electronic device 12 is mounted on the first surface 11a. The second surface 11b has a plurality of pins. The surround 13 is connected to at least a portion of the edge of the first surface 11a, and / or, the surround 13 is connected to at least a portion of the side surface 11c.
[0078] Among them, the first electronic device 12 can be a high-heat-generating device such as a system on chip (SoC), a double data rate (DDR) memory, a metal-oxide-semiconductor field-effect transistor (MOSFET), etc. The first electronic device 12 can also be a resistor, a capacitor, etc.
[0079] The edge 13 is connected to at least a portion of the edge of the first surface 11a and to at least a portion of the side surface 11c. One or both of the two methods can be used. The following embodiments will describe this in detail.
[0080] In the packaged chip 10 provided in the embodiment of the present application, the first electronic device 12 is mounted on the first surface 11a of the substrate 11, and the second surface 11b of the substrate 11 has a plurality of pins. The border 13 can be connected to the edge of the first surface 11a and the side 11c of the substrate 11 to improve the rigidity of the packaged chip 10. Even for a substrate 11 with a large area and a small thickness, after the border 13 is provided at the edge of the substrate 11, the mechanical deformation and thermal warping deformation of the substrate 11 at high temperature can be reduced, thereby improving the mechanical reliability and welding yield of the substrate 11. Compared with the related art of thickening the substrate or changing the substrate material to reduce the amount of deformation, the present embodiment provides a border 13 on the substrate 11 to reduce the amount of deformation, which can reduce the overall cost.
[0081] For example, the substrate 11 is rectangular, with a length and width of 50 mm. A border 13 is provided along the edge of the substrate 11 to increase its rigidity and reduce mechanical deformation and thermal warping at high temperatures. Compared to a substrate 11 without a border 13, the substrate 11 with the border 13 in this embodiment reduces deformation by over 40%, improving the mechanical reliability and soldering yield of the substrate 11. It is understood that the substrate 11 can also be provided in other shapes and sizes.
[0082] In some embodiments, see Figure 3 、 Figure 4 , the surrounding edge 13 and the base plate 11 are welded or bonded. A reliable fixed connection between the surrounding edge 13 and the base plate 11 can be achieved, and it is easy to achieve.
[0083] In some embodiments, see Figure 4The surrounding edge 13 is a metal surrounding edge. The substrate 11 has a ground layer 111 inside. The ground layer 111 and the first electronic device 12 are connected to form heat conduction between the two. The ground layer 111 and the surrounding edge 13 are connected to form heat conduction between the two. The ground layer 111 can be arranged in one or more layers. The material of the ground layer 111 can be silver, copper and other materials. The material of the metal surrounding edge can be silver, copper, tungsten, aluminum and other metal materials with fast thermal conductivity and high hardness. Even if a high-heat-generating first electronic device 12 is set on a large-area substrate 11, the heat generated by the first electronic device 12 can be conducted to the surrounding edge 13 through the ground layer 111, which can achieve efficient heat dissipation.
[0084] In some embodiments, see Figure 6 On the basis that the surrounding edge 13 is a metal surrounding edge and the first electronic device 12 and the surrounding edge 13 achieve heat conduction through the ground layer 111 of the substrate 11, the packaged chip 10 also includes a heat sink 14, the heat sink 14 is in contact with the surrounding edge 13, and a thermal interface material (TIM) layer 15 is provided between the heat sink 14 and the surrounding edge 13. The heat generated by the operation of the first electronic device 12 passes through the ground layer 111, the surrounding edge 13 and the thermal interface material layer 15 in sequence, and then is conducted to the heat sink 14, and the heat is dissipated to the surrounding space by the heat sink 14, thereby improving the heat dissipation capacity. The thermal interface material layer 15 can reduce the contact thermal resistance between the heat sink 14 and the surrounding edge 13, thereby improving the heat dissipation performance. The thermal interface material layer 15 can be made of materials such as silicone grease, silica gel, and thermal conductive glue.
[0085] In some embodiments, see Figure 6 The heat sink 14 may include a heat conductor 141, a heat pipe, and a fan. The heat conductor 141 may be a metal structure (such as a copper block). A thermal interface material layer 15 is provided between one end of the heat conductor 141 and the surrounding edge 13. The other end of the heat conductor 141 contacts the heat pipe. The heat conductor 141 is used to transfer heat from the surrounding edge 13 to the heat pipe. A heat pipe is a vacuum cavity with a microstructured inner wall. The heat pipe has an evaporation zone and a condensation zone. The vacuum cavity is filled with water or other cooling medium. When heat is transferred to the evaporation zone, the liquid cooling medium in the cavity is heated and vaporizes. After absorbing heat, the liquid cooling medium rapidly expands in volume, quickly filling the entire cavity. When the gaseous cooling medium contacts the relatively cold condensation zone, it condenses and releases the heat accumulated during evaporation. The condensed liquid cooling medium returns to the evaporation zone through the microstructured capillary channels. This process repeats continuously, transferring heat from the evaporation zone to the condensation zone. The airflow from the fan removes the heat from the evaporation zone of the heat pipe.
[0086] In some embodiments, see Figure 6 The heat sink 14 may include a heat conducting member 141 and a fan. The heat conducting member 141 may be a heat dissipation fin group. The heat of the surrounding edge 13 is transferred to the heat dissipation fin group, and the airflow of the fan removes the heat from the heat dissipation fin group.
[0087] In some embodiments, see Figures 2 to 4 The surrounding edge 13 includes a first side portion 131, which faces and connects to the edge of the first surface 11a. Securing the first side portion 131 to the edge of the first surface 11a of the substrate 11 can enhance the strength and rigidity of the substrate 11, reduce mechanical deformation and thermal warpage at high temperatures, and improve the mechanical reliability and soldering yield of the substrate 11. The first side portion 131 and the edge of the first surface 11a can be connected by welding, bonding, or other methods.
[0088] In some embodiments, see Figure 4 The thickness D1 of the first side portion 131 is less than or equal to the thickness D2 of the first electronic device 12. The thickness D1 of the first side portion 131 is the dimension of the first side portion 131 in the thickness direction Z of the substrate 11. The thickness D2 of the first electronic device 12 is the dimension of the first electronic device 12 at its thickest point in the thickness direction Z of the substrate 11.
[0089] When the substrate 11 is provided with a peripheral edge 13 without increasing the overall thickness of the packaged chip 10, the thickness space at the edge of the substrate 11 is fully utilized to increase the thickness of the first side portion 131, thereby improving the strength of the peripheral edge 13, better controlling the flatness of the substrate 11, and improving the strength and rigidity of the packaged chip 10.
[0090] In some embodiments, see Figure 4 On the plane of the first surface 11a, a first spacing D3 is formed between the inner edge of the first side portion 131 and the first electronic device 12 adjacent to the first side portion 131, and the width D4 of the first side portion 131 is greater than or equal to the first spacing D3. The inner edge of the first side portion 131 is the edge of the first side portion 131 close to the first electronic device 12. The inner edge of the first side portion 131 is positioned close to the adjacent first electronic device 12 to maximize the area of the first side portion 131, thereby increasing the connection area between the first side portion 131 and the edge of the first surface 11a, and reliably connecting the first side portion 131 to the edge of the first surface 11a, thereby reducing the risk of separation between the edge 13 and the substrate 11 in a drop impact scenario.
[0091] When the first side portion 131 and the first surface 11a are welded, the larger area of the first side portion 131 can increase the amount of solder, so that the first side portion 131 and the first surface 11a are reliably connected, reducing the risk of desoldering of the edge 13 and the substrate 11 in a drop impact scenario.
[0092] When the first side portion 131 and the first surface 11a are bonded, the larger area of the first side portion 131 can increase the amount of glue, so that the first side portion 131 and the first surface 11a are reliably connected, reducing the risk of debonding between the edge 13 and the substrate 11 in a drop impact scenario.
[0093] In some embodiments, see Figure 2 、 Figure 4 、 Figure 5 , the first surface 11a has a plurality of ground holes 112 corresponding to the surrounding edge 13, the ground layer 111 extends to the ground holes 112, the first surface 11a is provided with a pad 113, the pad 113 is at least partially located in the ground hole 112 and connected to the ground layer 111, and the pad 113 is connected to the surrounding edge 13. The substrate 11 and the surrounding edge 13 are connected through the pad 113, so that a part of the pad 113 is located in the ground hole 112 of the substrate 11. The larger pad 113 is used to achieve a reliable connection between the substrate 11 and the surrounding edge 13, thereby improving the bonding strength and reducing the risk of separation of the surrounding edge 13 and the substrate 11 in a drop impact scenario. The ground layer 111 and the surrounding edge 13 of the substrate 11 are connected through the pad 113, and the bonding is Figure 6 The heat generated by the first electronic device 12 can be conducted in sequence along the ground layer 111 of the substrate 11, the pad 113, the edge 13, the thermal interface material layer 15 and the heat sink 14, and dissipated to the surrounding space by the heat sink 14 to achieve efficient heat dissipation.
[0094] For example, see Figure 2 、 Figure 3 The substrate 11 is rectangular or in another shape, and the edge 13 extends along the edge of the substrate 11. A plurality of ground holes 112 are provided at the edge of the first surface 11a of the substrate 11, and the ground layer 111 of the substrate 11 extends to the ground holes 112. Different portions of the solder pads 113 are filled in the plurality of ground holes 112, and the edge 13 is fixed to the solder pads 113 of the substrate 11, ensuring a reliable connection between the edge 13 and the substrate 11.
[0095] In some embodiments, see Figures 2 to 4 The edge 13 includes a first side portion 131, which faces and is connected to the edge of the first surface 11a. The edge 13 also includes a second side portion 132, which is connected to the first side portion 131 and the second side portion 132, and which faces and is connected to the side surface 11c.
[0096] Securing the first side portion 131 to the edge of the first surface 11a of the substrate 11 and the second side portion 132 to the side surface 11c of the substrate 11 further enhances the strength and rigidity of the substrate 11, reduces mechanical deformation and thermal warpage of the substrate 11 at high temperatures, and improves the mechanical reliability and soldering yield of the substrate 11. The first side portion 131 and the edge of the first surface 11a, and the second side portion 132 and the side surface 11c of the substrate 11, can be connected by welding, bonding, or other methods.
[0097] Exemplarily, the surrounding edge 13 is a hard metal surrounding edge, and the surrounding edge 133 includes a first side portion 131 and a second side portion 132 . The first side portion 131 and the edge of the first surface 11 a , and the second side portion 132 and the side surface 11 c of the substrate 11 are both welded.
[0098] Exemplarily, the edge 13 is a hard metal edge and includes a first side portion 131 and a second side portion 132. Adhesion is employed between the first side portion 131 and the edge of the first surface 11a, and between the second side portion 132 and the side surface 11c of the substrate 11. Glue can be applied to the substrate 11 by dispensing. The glue can be structural adhesive or other highly adhesive adhesive.
[0099] In some embodiments, see Figures 2 to 4 The first side portion 131 and the second side portion 132 are integrally formed and can be formed by bending metal parts. Using metal parts to form the first side portion 131 and the second side portion 132 by bending facilitates forming and effectively controls the flatness of the surrounding edge 13. Adjacent first side portions 131 and second side portions 132 can be perpendicular to each other.
[0100] In some embodiments, see Figures 7 to 11 The edge 13 includes a first side portion 131, which faces and connects to the edge of the first surface 11a. The edge 13 also includes a positioning post 133, which is connected to the side of the first side portion 131 facing the substrate 11. The substrate 11 has a positioning hole 114, and the ground layer 111 extends to the positioning hole 114. The positioning post 133 is disposed in the positioning hole 114 and connected to the ground layer 111.
[0101] Fixing the first side portion 131 to the edge of the first surface 11a of the substrate 11 and the positioning post 133 within the positioning hole 114 of the substrate 11 can further enhance the strength and rigidity of the substrate 11, reduce mechanical deformation and thermal warping deformation of the substrate 11 at high temperatures, and improve the mechanical reliability and soldering yield of the substrate 11. The first side portion 131 and the edge of the first surface 11a, and the positioning post 133 and the wall of the positioning hole 114, can be connected by welding, bonding, or other methods. The base layer 111 of the substrate 11, the positioning post 133 of the surrounding edge 13, and the first side portion 131 are sequentially connected. Heat generated by the first electronic device 12 is sequentially conducted along the base layer 111 of the substrate 11, the positioning post 133 of the surrounding edge 13, the first side portion 131, the thermal interface material layer 15, and the heat sink 14, and is dissipated from the heat sink 14 to the surrounding space, achieving efficient heat dissipation.
[0102] For example, see Figures 7 to 10The substrate 11 is rectangular or in another shape, and the edge 13 extends along the edge of the substrate 11. A plurality of positioning holes 114 are provided at the edge of the substrate 11, and the ground layer 111 of the substrate 11 extends to the positioning holes 114. A first side portion 131 of the edge 13 is fixed to the edge of the first surface 11a of the substrate 11, and a plurality of positioning posts 133 are respectively fixed to the positioning holes 114, ensuring a secure connection between the edge 13 and the substrate 11.
[0103] In some embodiments, see Figure 7 and Figure 9 The first side portion 131 and the positioning post 133 form an assembled structure, with the positioning post 133 riveted or welded to the first side portion 131. This allows the positioning post 133 to be securely fixed to the first side portion 131, facilitating a reliable connection between the edge of the surround 13 and the substrate 11. This allows for heat conduction between the positioning post 133 and the first side portion 131. The positioning post 133 and the first side portion 131, combined with the ground layer 111 of the substrate 11, the thermal interface material layer 15, and the heat sink 14, achieve efficient heat dissipation for the first electronic device 12.
[0104] In some embodiments, see Figure 12 and Figure 14 The first side portion 131 and the positioning post 133 are integrally formed. The first side portion 131 and the positioning post 133 can be formed by bending metal parts. Forming the first side portion 131 and the positioning post 133 using metal parts by bending facilitates forming. Adjacent first side portions 131 and positioning posts 133 can be perpendicular to each other.
[0105] Exemplarily, the substrate 11 is rectangular or in another shape, and the first side portion 131 of the peripheral edge 13 extends along the edge of the substrate 11. A plurality of positioning posts 133 are formed on the outer edge of the first side portion 131. The first side portion 131 is fixed to the edge of the first surface 11a of the substrate 11, and the plurality of positioning posts 133 are respectively fixed to the positioning holes 114, ensuring a secure connection between the peripheral edge 13 and the substrate 11.
[0106] In some embodiments, see Figure 17 The surrounding edge 13 does not have a first side portion. Instead, the surrounding edge 13 includes a second side portion 132. The second side portion 132 faces and is connected to the side surface 11c of the substrate 11. Securing the second side portion 132 to the side surface 11c of the substrate 11 can enhance the strength and rigidity of the substrate 11, reduce mechanical deformation and thermal warpage at high temperatures, and improve the mechanical reliability and soldering yield of the substrate 11. The second side portion 132 can be connected to the side surface 11c of the substrate 11 by welding, bonding, or other methods.
[0107] In some embodiments, see Figure 17The heat sink 14 contacts the second side portion 132 of the surround 13, with a thermal interface material layer 15 disposed between the heat sink 14 and the surround 13. The second side portion 132 is connected to the ground layer 111 of the substrate 11 to facilitate heat conduction between the two. Heat generated by the first electronic device 12 is sequentially conducted to the ground layer 111, the surround 13, the thermal interface material layer 15, and the heat sink 14, where it is dissipated into the surrounding space, thereby improving heat dissipation capacity.
[0108] In some embodiments, see Figure 2 、 Figure 5 、 Figure 18 , the substrate 11 is polygonal, such as rectangular, pentagonal, etc. Or, refer to Figure 19 , at least part of the edge of the substrate 11 is arc-shaped. Or, refer to Figure 20 The substrate 11 has a notch 115, and the notch 115 area is used to avoid predetermined components. The shape of the substrate 11 is set as needed.
[0109] In some embodiments, see Figure 2 、 Figure 18 The surrounding edge 13 is a closed loop structure. The closed loop structure means that the surrounding edge 13 extends around the edge of the substrate 11 and has no openings.
[0110] In some embodiments, see Figure 19 、 Figure 20 The surrounding edge 13 is an open ring structure. The open ring structure means that the surrounding edge 13 extends around the edge of the substrate 11 and has an opening.
[0111] The substrate 11 equipped with the surrounding edge 13 can increase the strength and rigidity of the overall structure, reduce the mechanical deformation and thermal warping deformation of the substrate 11 at high temperatures, and improve the mechanical reliability and welding yield of the substrate 11.
[0112] For example, see Figure 2 、 Figure 18 The substrate 11 is rectangular, and the surrounding edge 13 is a closed ring structure and extends roughly along the four sides of the rectangle.
[0113] For example, see Figure 19 The shape of the substrate 11 is a combination of a rectangle and an arc, and the surrounding edge 13 is an open ring structure and extends roughly along three sides of the rectangle.
[0114] For example, see Figure 20 The substrate 11 is in the shape of a rectangle with a notch set at one corner. The surrounding edge 13 is an open ring structure and extends roughly along the four sides of the rectangle. No surrounding edge 13 is set at the edge of the notch.
[0115] For example, see Figure 21 The substrate 11 is rectangular, and the surrounding edge 13 is an open ring structure and extends roughly along three sides of the rectangle.
[0116] It is understandable that the surrounding edge 13 can be provided on one or more edges of the substrate 11 , both of which can improve the strength and rigidity of the substrate 11 .
[0117] In some embodiments, see Figures 2 to 4 The packaged chip 10 may be a land grid array (LGA) chip. The pins of the LGA chip 10 may be metal contacts. Figure 22 , the connection end of the circuit structure 20 (such as a motherboard) is connected to the metal contact of the grid array package chip 10 to achieve electrical connection.
[0118] See Figure 22 The embodiment of the present application provides a circuit board assembly 100, including a circuit structure 20 and the above-mentioned packaged chip 10, wherein the pins of the packaged chip 10 are connected to the circuit structure 20 to achieve conduction between the packaged chip 10 and the circuit structure 20.
[0119] For example, the circuit structure 20 can be a circuit board, and the packaged chip 10 and the circuit board can be assembled to form a circuit board assembly 100, thereby achieving electrical connection between the packaged chip 10 and the circuit board. The pins of the packaged chip 10 and the circuit board can be connected via a plurality of conductive bumps 21 or pins.
[0120] An embodiment of the present application provides an electronic device, including the aforementioned packaged chip 10 or the aforementioned circuit board assembly 100. The packaged chip 10 or the circuit board assembly 100 may be disposed in a device housing.
[0121] Among them, the electronic devices can be mobile phones, tablet computers, laptops, super mobile personal computers, e-book readers, netbooks, personal digital assistants, wearable devices, augmented reality (AR) devices, virtual reality (VR) devices, televisions, drones, sports cameras, driving recorders, vehicle-mounted equipment, robots, ATMs, etc.
[0122] When confirming the packaged chip 10, circuit board assembly 100 and electronic device of the embodiment of the present application, the packaged chip 10 or the circuit board assembly 100 can be disassembled and analyzed to confirm that the packaged chip 10 includes a substrate 11, a first electronic device 12 and a surround 13, and the surround 13 is connected to at least a portion of the edge of the first surface 11a of the substrate 11, and / or, the surround 13 is connected to at least a portion of the side 11c of the substrate 11.
[0123] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.
Claims
1. A packaged chip, characterized in that: include: a substrate, a first electronic device, and a surrounding edge; The substrate has a first surface, a second surface and a side surface, the first surface and the second surface are arranged back to back along the thickness direction of the substrate, and the side surface is connected between the first surface and the second surface; The first electronic device is mounted on the first surface; The second surface has a plurality of pins; The surrounding edge is connected to at least a portion of an edge of the first surface, and / or the surrounding edge is connected to at least a portion of the side surface.
2. The packaged chip according to claim 1, wherein: The surrounding edge is a metal surrounding edge, and a ground layer is provided inside the substrate. The ground layer is connected to the first electronic device, and the ground layer is connected to the surrounding edge.
3. The packaged chip according to claim 2, wherein: It also includes a heat sink, which is in contact with the surrounding edge, and a thermal interface material layer is provided between the heat sink and the surrounding edge.
4. The packaged chip according to claim 2 or 3, characterized in that: The surrounding edge includes a first side portion, and the first side portion faces and is connected to an edge of the first surface.
5. The packaged chip according to claim 4, wherein: The thickness of the first side portion is less than or equal to the thickness of the first electronic device; And / or, on the plane where the first surface is located, a first distance is formed between an inner edge of the first side portion and the first electronic device adjacent to the first side portion, and a width of the first side portion is greater than or equal to the first distance; And / or, the first surface has multiple ground holes corresponding to the surrounding edge, the ground layer extends to the ground holes, the first surface is provided with a pad, the pad is at least partially located in the ground hole and connected to the ground layer, and the pad is connected to the surrounding edge.
6. The packaged chip according to claim 4 or 5, characterized in that: The surrounding edge further includes a second side portion, the first side portion and the second side portion are connected, and the second side portion faces and is connected to the side surface.
7. The packaged chip according to claim 6, wherein: The first side portion and the second side portion are an integrated structure, and the first side portion and the second side portion are formed by bending metal parts.
8. The packaged chip according to claim 4 or 5, characterized in that: The surrounding edge also includes a positioning column, which is connected to the side of the first side portion facing the substrate. The substrate has a positioning hole, the ground layer extends to the positioning hole, and the positioning column is arranged in the positioning hole and connected to the ground layer.
9. The packaged chip according to claim 8, wherein: The positioning column is riveted to the first side portion; Alternatively, the positioning column is welded to the first side portion; Alternatively, the first side portion and the positioning post are an integrated structure, and the first side portion and the positioning post are formed by bending metal parts.
10. The packaged chip according to any one of claims 1 to 9, characterized in that: The substrate is polygonal, or at least part of the edge of the substrate is arc-shaped; And / or, the substrate has a notch; And / or, the surrounding edge is a closed ring structure or an open ring structure; and / or, the surrounding edge and the substrate are welded or bonded; And / or, the packaged chip is a grid array packaged chip.
11. A circuit board assembly, characterized in that: It comprises a circuit structure and a packaged chip according to any one of claims 1 to 10, wherein the pins of the packaged chip are connected to the circuit structure.
12. An electronic device, characterized in that: The method comprises the packaged chip according to any one of claims 1 to 10 or the circuit board assembly according to claim 11.