Low-voltage UVLO layout structure
By introducing an isolated ground ring and high-precision matching design into the UVLO circuit layout, the problems of large area and weak anti-interference ability of the existing UVLO circuit layout are solved, and high low-voltage undervoltage lockout accuracy and improved chip stability are achieved.
Patent Information
- Application Number
- CN202421587413.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-06
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2034-07-06
AI Technical Summary
The existing UVLO circuit layout design has the disadvantages of large chip area, poor internal component matching, and incomplete isolation and shielding, resulting in weak anti-interference ability and affecting module accuracy and performance.
A low-voltage UVLO layout structure is adopted, including an isolated ground ring, N-type and P-type differential pair areas, a voltage divider resistor area, a capacitor area, a digital layout area, and a current mirror matching area. Through high-precision matching and isolation ring design, parasitic resistance and capacitance are reduced, thereby improving the stability and anti-interference ability of the chip.
The low voltage undervoltage lockout has high precision, the chip area is reduced, the production cost is reduced, the reliability and stability of the chip are improved, and the anti-interference ability is enhanced.
Smart Images
Figure CN223322359U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electrical components, in particular to a low-voltage UVLO layout structure. Background Art
[0002] With the rapid development of integrated circuits, power supply chips are becoming increasingly versatile. In the practical application of electronic devices, it is difficult to maintain a very stable input voltage. Therefore, a UVLO module can be designed into the circuit layout.
[0003] UVLO stands for undervoltage lockout. During device operation, if the supply voltage falls below the IC's turn-on threshold voltage, UVLO causes the internal circuitry to enter a semi-standby state to prevent malfunctions. When the supply voltage reaches the IC's turn-on threshold voltage, the lockout is released and operation resumes.
[0004] The existing UVLO circuit layout design has the following disadvantages:
[0005] 1. The layout structure is complex and the chip area is large, which increases the chip production cost.
[0006] 2. The internal components are not well matched, the isolation and shielding are not perfect, and the anti-interference ability is weak, which affects the accuracy and performance of the module. Summary of the Invention
[0007] This utility model aims to address issues such as UVLO circuit layout matching and accuracy by providing a low-voltage UVLO layout structure with high undervoltage lockout accuracy, achieving a low-voltage undervoltage lockout function, improving the chip's own reliability and stability, and extending the device's service life. Based on integrated process technology, the module design adheres to a compact structure, strictly matching important components, adding a shielding ring to ensure sufficient substrate contact, reducing interference caused by parasitic resistance and parasitic capacitance, reducing chip area, and saving chip manufacturing costs.
[0008] The utility model provides a low-voltage UVLO layout structure, comprising an isolation ground ring with a PW located at the outermost periphery, an N-type differential pair area located on the left side of the isolation ground ring, a voltage divider resistor area and a P-type differential pair area located on the right side of the N-type differential pair area and arranged vertically, a capacitor area located on the right side of the voltage divider resistor area and the P-type differential pair area, a digital layout area and a current mirror matching area located on the right side of the capacitor area and arranged vertically, and a power line VDD and a ground line GND located inside the isolation ground ring. The N-type differential pair area, the voltage divider resistor area, the P-type differential pair area, the capacitor area, the digital layout area, and the current mirror matching area are all connected inside the isolation ground ring.
[0009] The N-type differential pair area and the P-type differential pair area are the feedback circuit, the voltage divider resistor area and the capacitor C1 in the capacitor area are the sampling circuit, the digital layout area is the output buffer, and the current mirror matching area is the comparator;
[0010] The N-type differential pair area includes CMOS transistors M6 and M7 that are co-centroidally matched and arranged in two rows and two columns, and virtual transistors in the N-type differential pair area located on the left and right sides of the co-centroidally matched transistors M6 and M7. The gate of transistor M6 is connected to the bandgap reference voltage VREF, and the gate of transistor M7 is connected to the voltage divider resistor area and the digital layout area.
[0011] The voltage divider resistor area includes series resistors R0, R1, and R2 that are matched with each other and arranged in a single row, and a resistor R3 connected in parallel at the right end. The other end of the resistor R0 is connected to the ground line GND. A sampling voltage VC is output between the resistor R0 and the resistor R1. The other end of the resistor R2 is connected to the power line VDD. One end of the resistor R3 is connected to the power line VDD.
[0012] The P-type differential pair region includes CMOS transistors M0, M1, M2, M3, M4, and M5, which are matched in 4 rows and 5 columns. The P-type differential pair region is connected to the N-type differential pair region and the voltage divider resistor region. The P-type differential pair region and the N-type differential pair region form a feedback circuit. The other end of the P-type differential pair region is connected to the power supply VDC.
[0013] The capacitor area includes capacitors C0 and C1. One end of capacitor C0 is connected to voltage V02 and the other end is connected to ground GND. One end of capacitor C1 is connected to VDC and the other end is connected to ground GND.
[0014] The current mirror matching region includes CMOS transistors M10 and M11 for current mirror matching, and CMOS transistors M8, M9, and M13 for current mirror matching. The current mirror matching region is arranged in two rows with the same substrate potential and a common substrate ring. Transistors M10 and M11 are connected to the P-type differential pair region, and the drain of transistor M11 is connected to voltage V01. Transistors M8, M9, and M13 are connected to the N-type differential pair region, and the drain of transistor M8 is connected to IBN7, and the drain of transistor M13 is connected to voltage V02.
[0015] The gate of the transistor M6 inputs the bandgap reference voltage VREF, and the power supply sampling voltage VC is output between the resistors R1 and R0. The current mirror matching area compares the power supply sampling voltage VC with the bandgap reference voltage VREF to control UVLO.
[0016] In the low-voltage UVLO layout structure described in the present invention, as a preferred embodiment, the minimum channel lengths of the virtual transistors in the N-type differential pair region and the common centroid matching transistors M6 and M7 are of the same type.
[0017] In the low-voltage UVLO layout structure described in the present invention, as a preferred embodiment, the double-hole ground ring in the N-type differential pair area serves as the substrate ring and the isolation ring.
[0018] In the low-voltage UVLO layout structure described in the present invention, as a preferred embodiment, a dummy tube of the same type is connected to the left and right sides of the voltage divider resistor area.
[0019] The low-voltage UVLO layout structure described in the present invention is preferably configured such that the left and right ends of the P-type differential pair region are each connected to a dummy tube of the same type with a minimum channel length, and the double-hole power ring serves as the substrate ring and the isolation ring.
[0020] In the low-voltage UVLO layout structure described in the present invention, as a preferred embodiment, the transistors M0, M1, M2, M3, M4 and M5 are all P-type 5V CMOS transistors.
[0021] In the low-voltage UVLO layout structure described in the present invention, as a preferred embodiment, the capacitor C0 and the capacitor C1 are placed adjacent to each other.
[0022] The low-voltage UVLO layout structure described in the present invention is preferably configured such that dummy tubes of the same type with minimum channel length are added to the left and right ends of the current mirror matching region, and a single-hole ground ring serves as a substrate ring and an isolation ring.
[0023] In the low-voltage UVLO layout structure described in the present invention, as a preferred embodiment, the transistors M8, M9, M10, M11 and M13 are all N-type 5V CMOS transistors.
[0024] In the low-voltage UVLO layout structure described in the present invention, as a preferred embodiment, the line widths of the ground line GND and the power line VDD are 3 μm.
[0025] The utility model has the following advantages:
[0026] (1) The utility model rationally plans the layout signals, the layout structure is compact, the chip area utilization rate is improved, and the production cost is reduced;
[0027] (2) According to the layout design rules, the internal components of the utility model, such as current mirrors, differential pairs, and matching resistors, are matched with high precision to ensure the consistency of the surrounding environment; an isolation protection ring is added to the periphery to increase its anti-interference ability and improve its accuracy and performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 This is a device distribution block diagram of a low-voltage UVLO layout structure;
[0029] Figure 2aThis is a schematic diagram of a low-voltage UVLO layout structure;
[0030] Figure 2b The left side is an enlarged diagram of a low-voltage UVLO layout structure diagram;
[0031] Figure 2c This is an enlarged view of the middle part of a low-voltage UVLO layout structure diagram;
[0032] Figure 2d The right side of the schematic diagram of a low-voltage UVLO layout structure is enlarged;
[0033] Figure 3a A circuit diagram of a low-voltage UVLO layout structure;
[0034] Figure 3b The left side of the circuit diagram is an enlarged view of a low-voltage UVLO layout structure;
[0035] Figure 3c The right side of the circuit diagram is an enlarged view of a low-voltage UVLO layout structure;
[0036] Figure 4 A schematic diagram of the substrate structure of a low-voltage UVLO layout structure.
[0037] Reference numerals:
[0038] 100, isolation ground ring; 110, N-type differential pair area; 120, voltage divider resistor area; 130, P-type differential pair area; 140, capacitor area; 150, digital layout area; 160, current mirror matching area. DETAILED DESCRIPTION
[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.
[0040] Example 1
[0041] like Figure 1 、 2a Figures 2d, 3a-3c, and 4 show a low-voltage UVLO layout structure consisting of 5V CMOS, poly resistors, NW capacitors, and other components.
[0042] The device includes an isolation ground ring 100 with a PW located at the outermost periphery, an N-type differential pair region 110 located on the left side of the isolation ground ring 100, a voltage divider resistor region 120 and a P-type differential pair region 130 located on the right side of the N-type differential pair region 110 and arranged vertically, a capacitor region 140 located on the right side of the voltage divider resistor region 120 and the P-type differential pair region 130, a digital layout region 150 and a current mirror matching region 160 located on the right side of the capacitor region 140 and arranged vertically, and a power line VDD and a ground line GND located inside the isolation ground ring 100. The N-type differential pair region 110, the voltage divider resistor region 120, the P-type differential pair region 130, the capacitor region 140, the digital layout region 150, and the current mirror matching region 160 are all connected inside the isolation ground ring 100.
[0043] The N-type differential pair area 110 and the P-type differential pair area 130 are feedback circuits, the voltage divider resistor area 120 and the capacitor C1 of the capacitor area 140 are sampling circuits, the digital layout area 150 is an output buffer, and the current mirror matching area 160 is a comparator;
[0044] The N-type differential pair region 110 includes CMOS transistors M6 and M7 that are co-centroidally matched and arranged in two rows and two columns, and N-type differential pair region dummy transistors located on the left and right sides of the co-centroidally matched transistors M6 and M7. The gate of transistor M6 is connected to the bandgap reference voltage VREF, and the gate of transistor M7 is connected to the voltage divider resistor region 120 and the digital layout region 150.
[0045] The voltage divider resistor area 120 includes series resistors R0, R1, and R2 arranged in a single row with a common centroid, and a resistor R3 connected in parallel at the right end. The other end of the resistor R0 is connected to the ground line GND. A sampling voltage VC is output between the resistor R0 and the resistor R1. The other end of the resistor R2 is connected to the power line VDD. One end of the resistor R3 is connected to the power line VDD.
[0046] The P-type differential pair region 130 includes CMOS transistors M0, M1, M2, M3, M4, and M5, which are matched in differential pairs in four rows and five columns. The P-type differential pair region 130 is connected to the N-type differential pair region 110 and the voltage divider resistor region 120. The P-type differential pair region 130 and the N-type differential pair region 110 form a feedback circuit. The other end of the P-type differential pair region 130 is connected to the power supply VDC.
[0047] The capacitor area 140 includes capacitors C0 and C1. One end of the capacitor C0 is connected to the voltage V02 and the other end is connected to the ground line GND. One end of the capacitor C1 is connected to VDC and the other end is connected to the ground line GND.
[0048] The current mirror matching region 160 includes CMOS transistors M10 and M11 for current mirror matching, and CMOS transistors M8, M9, and M13 for current mirror matching. The current mirror matching region 160 is arranged in two rows with the same substrate potential and a common substrate ring. The transistors M10 and M11 are connected to the P-type differential pair region 130, and the drain of the transistor M11 is connected to the voltage V01. The transistors M8, M9, and M13 are connected to the N-type differential pair region 110, and the drain of the transistor M8 is connected to IBN7, and the drain of the transistor M13 is connected to the voltage V02.
[0049] The gate of the transistor M6 inputs the bandgap reference voltage VREF, and the power supply sampling voltage VC is output between the resistors R1 and R0. The current mirror matching area 160 compares the power supply sampling voltage VC with the bandgap reference voltage VREF to control UVLO.
[0050] 1. Such as Figure 2a As shown in the figure, an isolation ground ring with PW is added to the outermost periphery of the overall module layout.
[0051] 2. Such as Figure 2a As shown, the line width of the two buses (power line VDD and ground line GND) is 3μm to ensure its overcurrent capability.
[0052] 3. Such as Figure 2b As shown, in area 110, the differential pair composed of N-type 5V CMOS transistors (M6 and M7) are matched with the same centroid and arranged in 2 rows and 2 columns. A dummy transistor of the same type with the minimum channel length is added at the left and right ends, and a double-hole ground ring is used as the substrate ring and isolation ring.
[0053] 4. Such as Figure 2b 、 2c As shown, in the 120 area, the voltage divider resistors (R0, R1, R2) are arranged in a single row with common centroid matching. R3 is placed on the right end, and a dummy resistor of the same type is added on each side.
[0054] 5. Such as Figure 2c As shown, in area 130, P-type 5V CMOS transistors (M0, M1, M2, M3, M4, M5) are differentially matched into 4 rows and 5 columns, and dummy transistors of the same type with the minimum channel length are added at both ends. The double-hole power ring serves as the substrate ring and isolation ring.
[0055] 6. Such as Figure 2c As shown, in the 140 area, capacitors C1 and C0 are placed close to each other to meet the minimum spacing requirement.
[0056] 7. Such as Figure 2d As shown, area 150 is the digital part of the map.
[0057] 8. Such as Figure 2dAs shown, in area 160, two current mirrors composed of N-type 5V CMOS transistors (M10, M11 and M8, M9, M13) are matched, with the same substrate potential and a common substrate ring. They are arranged in two rows, and dummy transistors of the same type with the minimum channel length are added at both ends. A single-hole ground ring serves as the substrate ring and isolation ring.
[0058] This embodiment has the following advantages:
[0059] (1) MOS transistors have their own substrate ring and isolated ground ring, which greatly increases the chip area. In this embodiment, PMOS transistors of the same type and substrate potential share the NW double-hole substrate ring, and NMOS transistors of the same type and substrate potential share the PW double-hole substrate ring, achieving the same potential well sharing.
[0060] (2) MOS devices require high-precision matching when used in current mirrors and differential pairs. The current direction should be consistent, and common-centroid matching should be achieved whenever possible to reduce proportional mismatch and ensure matching consistency, symmetry, dispersion, compactness, and directionality. Common-centroid matching is superior to interdigital matching.
[0061] (3) Add dummy devices of the same type with the minimum channel length on both sides of the matching MOS tube to maintain environmental consistency and prevent excessive etching of the polysilicon.
[0062] (4) The substrate is made into a double-hole ring, which not only ensures that the internal devices have sufficient substrate contact, prevents the latch effect, reduces the parasitic resistance, but also effectively isolates them from the outside world. The specific structure is as follows Figure 4 shown.
[0063] (5) For MOS tubes, the source and drain can be reasonably merged to save chip area.
[0064] Regarding the voltage divider resistor part, it is necessary to ensure that the matching devices are interdigitated or have a common centroid, and add the same type of dummy devices on both sides as dummies to maintain environmental consistency and prevent excessive etching of the polysilicon.
[0065] Do not route traces on analog circuit devices that require high-precision matching to avoid parasitic resistance.
[0066] The key points of this utility model are:
[0067] 1. The overall layout is compact and reasonable, making the chip more integrated.
[0068] 2. Make an isolation protection ring for the analog part of the device, make a double-hole substrate as much as possible, widen the metal wire of the substrate as much as possible, increase the substrate contact, and use capacitors to isolate the analog part and the digital logic part with high-precision matching to reduce the crosstalk caused by the high-frequency signal of the digital part.
[0069] 3. High-precision matching of current mirror, differential pair, and voltage divider resistors to reduce the impact of thermal gradient effects.
[0070] 4. During the layout and routing process, the metal line width should be increased for large currents, the module input and output signal lines should avoid crossing, and the symmetrical signal lines in the matching parts should be as similar as possible to reduce the impact of parasitic resistance and parasitic capacitance on the chip.
[0071] The utility model simulates and verifies the design based on the HG 0.35um BCD process, and the results show that the maximum value of the voltage flip threshold is 2.67V and the minimum value is 2.23V.
[0072] This embodiment is based on the process manufacturing requirements of the Foundry. The circuit block diagram is as follows: Figures 3a to 3c As shown, the UVLO circuit is divided into four parts, namely the voltage divider sampling circuit ( Figure 3a The left side box area 210), the feedback circuit ( Figure 3a The upper middle box area 220), the comparator ( Figure 3a The lower middle box area 230) and the output buffer ( Figure 3a right frame area 240).
[0073] In this embodiment, the voltage-dividing sampling circuit includes a voltage-dividing resistor area 110, a capacitor C1 of a capacitor area 140, a digital layout area 150 (tubes M22, 23, 24, 25), and a comparator inv1_p1; wherein, resistors R0, R1, and R2 are connected in series and then in parallel with R3, the other ends of the resistors R2 and R3 are connected to the power supply voltage VDD, one end of the resistor R0 is grounded, the sampling voltage VC is between the other end of the resistor R1, one end of the resistor R0 and the source of the tube M22 and the drain of the tube M23, and the drain of the tube M25 is connected to one end of the resistor R1 and the source Connect one end of resistor R2, and the gate is connected to the gate of transistor M22. The source of transistor M22 is connected to the drain of transistor M23, and the drain is connected to voltage V01 and the gate of transistor M12. The gates of transistors M25 and M22 are connected to the output end of comparator inv1_p1. One end of comparator inv1_p1 is connected to voltage VDC. Voltage VDC is connected between resistor R3 and the drain of transistor M24. The gate and source of transistor M23 are both grounded. The gate and source of transistor M24 are both grounded. The drain is connected to one end of resistor R3 and one end of capacitor C1. The other end of capacitor C1 is grounded.
[0074] The feedback circuit includes the layout 110 area and the layout 130 area. The sources of transistors M0, M1, M2, M3, M4, and M5 are all connected to the power supply voltage VDC. The gate of transistor M0 is connected to the gate of transistor M1, and the drain of transistor M0 is connected to the drain of transistor M10. The gate and drain of transistor M1 are connected and then connected to the drain of transistor M2, the gate of transistor M3, and the drain of transistor M6. The gate of transistor M2 is connected to the drain of transistor M3, the gate and drain of transistor M4, and then connected to the drain of transistor M7. The gate of transistor M4 is connected to the gate of transistor M5. The drain of transistor M5 is connected to the voltage V01, the drain of transistor M11, and the drain of transistor M22. The gate of transistor M6 inputs the reference voltage VREF, and the source is connected to the source of transistor M7 and the drain of transistor M9. The gate of transistor M7 is connected to the sampling voltage VC, the source of transistor M22, and the drain of transistor M23.
[0075] The comparator includes tubes M9, M10, and M11. The gate of tube M9 is connected to the gate of tube M8, and the source is grounded. The gate and drain of tube M10 are connected to the drain of tube M0, and the source is grounded. The gate of tube M10 is connected to the gate of tube M11. The drain of tube M11 is connected to voltage V01, and the drain and source of tube M5 are grounded.
[0076] The output buffer includes transistors M8, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M26 and comparators inv2_p1 and inv2_p2; the gate of transistor M12 is connected to voltage V01, the source is connected to the source of transistor M5, the drain is connected to voltage V02, and the drain of transistor M13; the gate of transistor M26 is input to UVLO_ENN, the source is grounded, and the drain is connected to voltage VC; the gate of transistor M8 is connected to voltage VC, the gate and drain are connected to input IBN7, and the source is grounded; the gate of transistor M13 is connected to the drain of transistor M8, the source is grounded, and the drain is connected to the drain of M12 The drains and sources of the P-type CMOS transistors M14, M16, and M17, and the N-type CMOS transistors M19, M18, and M15 are connected in sequence, and their gates are all connected. The source of the transistor M21 is connected to the source of the transistor M15, and its drain is connected to the source of the transistor M19. One end of the comparator inv2_p1 is connected between the drain of the transistor M17 and the drain of the transistor M19. One end of the comparator inv2_p2 is connected to the gate of the transistor M20, the gate of the transistor M21, and the output end of the comparator inv2_p1. The output of the comparator inv2_p2 is the control end of the UVLO.
[0077] In the present invention, the power supply sampling voltage VC and the bandgap reference voltage VREF are compared by a voltage comparator:
[0078] At the beginning, when the sampling voltage VC < VREF, the drain voltage of M7 in region 220 is high, the gate voltages of M4 and M5 are also high, the drain voltage of M5 is low, that is, the VO1 voltage is low, the drain voltage of M12 in region 240 is high, that is, VO2 is high, the drain voltage of M17 is low. Through the action of inverter inv1_p1 and inverter inv_p2, the output voltage is low, and the UVLO output is at a low level. Through the logic control circuit, some internal circuits of the chip are turned off.
[0079] When the VDD voltage gradually rises from zero, the sampling voltage VC also gradually rises from zero. When the sampling voltage VC gradually rises but is less than VREF, the drain voltage of M7 in region 220 gradually decreases. Therefore, the gate voltages of M4 and M5 gradually decrease, the drain voltage of M5 gradually increases, the gate voltage of M12 in region 240 gradually increases, and the drain voltage of M12 gradually decreases.
[0080] When VC increases to be greater than VREF, this causes the drain voltage of M17 in region 240 to change from a low level to a high level. Through the action of inverter inv1_p1 and inverter inv2_p2, the output voltage UVLO is at a high level. This high level is connected to other modules in the chip to control the switches of other modules, and thus control the working state of the chip. The system re-enters the normal working mode.
[0081] The utility model conducts simulation verification on this design based on the HG 0.35um BCD process. The results show that the maximum value of the voltage flip threshold is 2.67V and the minimum value is 2.23V.
[0082] The above is only the preferred specific implementation mode of the utility model, but the protection scope of the utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the utility model, according to the technical solution of the utility model and its inventive concept, makes equivalent substitutions or changes, and should be covered within the protection scope of the utility model.
Claims
1. A low-voltage UVLO layout structure, characterized by: The invention comprises an isolation ground ring (100) with a PW located at the outermost periphery, an N-type differential pair area (110) located on the left side inside the isolation ground ring (100), a voltage divider resistor area (120) and a P-type differential pair area (130) located on the right side of the N-type differential pair area (110) and arranged vertically, a capacitor area (140) located on the right side of the voltage divider resistor area (120) and the P-type differential pair area (130), a digital layout area (150) located on the right side of the capacitor area (140) and arranged vertically, a current mirror matching area (160), and a power line VDD and a ground line GND located inside the isolation ground ring (100); the N-type differential pair area (110), the voltage divider resistor area (120), the P-type differential pair area (130), the capacitor area (140), the digital layout area (150), and the current mirror matching area (160) are all connected inside the isolation ground ring (100); The N-type differential pair area (110) and the P-type differential pair area (130) are feedback circuits, the voltage divider resistor area (120) and the capacitor C1 of the capacitor area (140) are sampling circuits, the digital layout area (150) is an output buffer, and the current mirror matching area (160) is a comparator; The N-type differential pair region (110) includes a CMOS transistor M6 and a CMOS transistor M7 that are matched with a common centroid and arranged in two rows and two columns, and N-type differential pair region virtual transistors located on the left and right sides of the transistors M6 and M7, the gate of the transistor M6 being connected to a bandgap reference voltage VREF, and the gate of the transistor M7 being connected to the voltage divider resistor region (120) and the digital layout region (150); The voltage dividing resistor area (120) includes series resistors R0, R1, and R2 that are matched with a common centroid and arranged in a single row, and a resistor R3 located at the right end and connected in parallel, the other end of the resistor R0 is connected to the ground line GND, a sampling voltage VC is output between the resistor R0 and the resistor R1, the other end of the resistor R2 is connected to the power line VDD, and one end of the resistor R3 is connected to the power line VDD; The P-type differential pair region (130) includes CMOS transistors M0, M1, M2, M3, M4, and M5, which are matched in differential pairs in 4 rows and 5 columns; the P-type differential pair region (130) is connected to the N-type differential pair region (110) and the voltage divider resistor region (120); the P-type differential pair region (130) and the N-type differential pair region (110) form a feedback circuit; the other end of the P-type differential pair region (130) is connected to a power supply VDC; The capacitor area (140) includes capacitors C0 and C1, one end of the capacitor C0 is connected to the voltage V02 and the other end is connected to the ground line GND, and one end of the capacitor C1 is connected to VDC and the other end is connected to the ground line GND; The current mirror matching area (160) includes CMOS transistors M10 and M11 for current mirror matching and CMOS transistors M8, M9, and M13 for current mirror matching; the current mirror matching area (160) is arranged in two rows with the same substrate potential and a common substrate ring; transistors M10 and M11 are connected to the P-type differential pair area (130), the drain end of transistor M11 is connected to voltage V01, and transistors M8, M9, and M13 are connected to the N-type differential pair area (110), the drain end of transistor M8 is connected to IBN7, and the drain end of transistor M13 is connected to voltage V02; The gate of the tube M6 inputs a bandgap reference voltage VREF, and the power supply sampling voltage VC is output between the resistors R1 and R0. The current mirror matching area (160) compares the power supply sampling voltage VC with the bandgap reference voltage VREF to control UVLO.
2. The low-voltage UVLO layout structure according to claim 1, characterized in that: The N-type differential pair region virtual transistor has the same minimum channel length as the transistors M6 and M7.
3. The low-voltage UVLO layout structure according to claim 1, characterized in that: The double-hole ground ring of the N-type differential pair region (110) serves as a substrate ring and an isolation ring.
4. The low-voltage UVLO layout structure according to claim 1, wherein: The left and right sides of the voltage-dividing resistor area (120) are each connected to a dummy tube of the same type.
5. The low-voltage UVLO layout structure according to claim 1, characterized in that: The left and right ends of the P-type differential pair region (130) are each connected to a dummy tube of the same type with a minimum channel length, and a double-hole power ring serves as a substrate ring and an isolation ring.
6. The low-voltage UVLO layout structure according to claim 1, characterized in that: The transistors M0, M1, M2, M3, M4 and M5 are all P-type 5VCMOS transistors.
7. The low-voltage UVLO layout structure according to claim 1, characterized in that: Capacitor C0 and capacitor C1 are placed adjacent to each other.
8. The low-voltage UVLO layout structure according to claim 1, characterized in that: The left and right ends of the current mirror matching region (160) are each provided with a dummy tube of the same type with a minimum channel length, and a single-hole ground ring is used as a substrate ring and an isolation ring.
9. The low-voltage UVLO layout structure according to claim 1, characterized in that: The transistors M8, M9, M10, M11 and M13 are all N-type 5V CMOS transistors.
10. The low-voltage UVLO layout structure according to claim 1, characterized in that: The line width of the ground line GND and the power line VDD is 3 μm.