Time service circuit, system and rail transit vehicle

Abstract

The utility model relates to a time service circuit and system and a rail transit vehicle, the time service circuit comprises a signal receiving circuit and a main control circuit, the signal receiving circuit receives satellite signals, analyzes the satellite signals, obtains and sends initial time and second pulse signals to the main control circuit, the main control circuit receives the initial time and second pulse signals, and sends the initial time and second pulse signals to the main control circuit; according to the train operation monitoring and recording device and the train operation monitoring and recording system, a main control circuit receives a pulse per second signal and calibrates initial time according to the pulse per second signal, the calibrated time is obtained and sent to a peripheral circuit, and the peripheral circuit comprises a train operation monitoring and recording device and circuits in other vehicle-mounted equipment. The main control circuit directly sends the calibrated time to the train operation monitoring and recording device and the other vehicle-mounted equipment; therefore, the time error among the devices in the rail transit vehicle can be effectively reduced, and the influence of the time error on the unified management and troubleshooting of the devices in the rail transit vehicle can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of rail transit vehicles, and in particular to a timing circuit, system and rail transit vehicle. Background Art

[0002] At present, the time used by rail transit vehicles is the time of the train operation monitoring and recording device. The time on the train operation monitoring and recording device is forwarded to the main controller through the network interface board, and then sent to other on-board equipment (control network, monitoring network, tail device, etc.) in a periodic manner.

[0003] Since the time on the train operation monitoring and recording device is forwarded to the main controller via the network interface board, and the transmission of electrical signals via the network interface board causes a large time delay, the time received by the main controller has a large error relative to the time on the operation monitoring and recording device. This in turn causes the time received by other on-board equipment to have a large error (in seconds) relative to the time on the operation monitoring and recording device. This large time error will have a significant impact on the unified management and troubleshooting of equipment in rail transit vehicles.

[0004] Therefore, how to reduce the time error between various devices in rail transit vehicles is a technical problem that needs to be solved urgently by those skilled in the art. Utility Model Content

[0005] In order to solve the above technical problems, the purpose of this application is to provide a timing circuit, system and rail transit vehicle; the timing circuit, system and rail transit vehicle provided by this application can effectively reduce the time error between various devices in the rail transit vehicle, and can effectively reduce the impact of time error on the unified management and troubleshooting of equipment in the rail transit vehicle.

[0006] The technical solutions provided in this application are as follows:

[0007] A timing circuit comprises: a signal receiving circuit and a main control circuit;

[0008] The output end of the signal receiving circuit is connected to the first input end of the main control circuit;

[0009] The output end of the main control circuit is connected to the peripheral circuit;

[0010] The signal receiving circuit is used to receive satellite signals, analyze the satellite signals, obtain initial time and pulse-second signal, and send the initial time and pulse-second signal to the main control circuit;

[0011] The main control circuit is used to receive the initial time and the second pulse signal, calibrate the initial time according to the second pulse signal to obtain the calibrated time, and send the calibrated time to the peripheral circuit.

[0012] Optionally, the signal receiving circuit includes: an antenna and a signal receiver;

[0013] The output end of the antenna is connected to the input end of the signal receiver;

[0014] The output end of the signal receiver is connected to the first input end of the main control circuit;

[0015] The antenna is used to receive and output satellite signals;

[0016] The signal receiver is used to receive the satellite signal, analyze the satellite signal, obtain the initial time and the second pulse signal, and send the initial time and the second pulse signal to the main control circuit.

[0017] Optionally, the signal receiving circuit further includes: a first filtering circuit;

[0018] The output end of the antenna is connected to the input end of the first filtering circuit;

[0019] The output end of the first filter circuit is connected to the input end of the signal receiver;

[0020] The first filtering circuit is configured to receive the satellite signal, filter the satellite signal, and send the filtered satellite signal to the signal receiver.

[0021] Optionally, it further includes: an auxiliary timing circuit;

[0022] The output end of the auxiliary timing circuit is connected to the second input end of the main control circuit;

[0023] The auxiliary timing circuit is used to send the backup time to the main control circuit.

[0024] Optionally, the auxiliary timing circuit includes a backup power supply circuit and a clock circuit;

[0025] The output end of the backup power supply circuit is connected to the input end of the clock circuit;

[0026] The output end of the clock circuit is connected to the second input end of the main control circuit;

[0027] The backup power supply circuit is used to output a backup power supply voltage signal when the external power supply fails to supply power;

[0028] The clock circuit is used to send the backup time to the main control circuit when the external power supply is supplied or the backup power supply voltage signal is received.

[0029] Optionally, the auxiliary timing circuit further includes a second filtering circuit;

[0030] The output end of the backup power supply circuit is connected to the input end of the second filter circuit;

[0031] The output end of the second filter circuit is connected to the input end of the clock circuit;

[0032] The second filtering circuit is configured to receive the backup power supply voltage signal, filter the backup power supply voltage signal, and send the filtered backup power supply voltage signal to the clock circuit.

[0033] Optionally, the first filtering circuit includes: a transient diode, a first resistor, a second resistor, a first capacitor, a second capacitor, an inductor and a magnetic bead;

[0034] The first end of the transient diode and the first end of the first resistor are connected to the output end of the antenna;

[0035] The second end of the first resistor is connected to the first end of the second resistor and the first end of the first capacitor;

[0036] The second end of the first capacitor is connected to the first end of the inductor and the first end of the signal receiver;

[0037] The second end of the inductor is connected to the first end of the second capacitor and the first end of the magnetic bead;

[0038] The second end of the transient diode, the second end of the second resistor, and the second end of the second capacitor are grounded;

[0039] The second end of the magnetic bead is connected to a power source.

[0040] Optionally, the main control circuit includes a main control chip;

[0041] The second end of the signal receiver is connected to the first end of the main control chip;

[0042] The third end of the signal receiver is connected to the second end of the main control chip;

[0043] The third terminal and the fourth terminal of the main control chip are connected to the output terminal of the clock circuit;

[0044] The fifth terminal of the main control chip is connected to the peripheral circuit.

[0045] Optionally, the backup power supply circuit includes: a diode and a supercapacitor;

[0046] The positive electrode of the diode is connected to the power supply;

[0047] The cathode of the diode, the anode of the supercapacitor and the input end of the second filter circuit are connected;

[0048] The negative electrode of the supercapacitor is grounded.

[0049] Optionally, the second filtering circuit includes a third resistor and a third capacitor;

[0050] The first end of the third resistor is connected to the output end of the backup power supply circuit;

[0051] The second end of the third resistor is connected to the first end of the third capacitor and the input end of the clock circuit;

[0052] A second terminal of the third capacitor is grounded.

[0053] Optionally, the second filtering circuit further includes: a fourth capacitor and a fifth capacitor, and the clock circuit includes: a clock chip, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a sixth capacitor, a seventh capacitor and an eighth capacitor;

[0054] The first end of the clock chip is connected to the first end of the fourth capacitor and a power supply;

[0055] The second end of the clock chip is connected to the first end of the fifth capacitor and a power supply;

[0056] The third end of the clock chip, the second end of the third resistor, and the first end of the third capacitor;

[0057] The fourth terminal of the clock chip is connected to the first terminal of the fourth resistor;

[0058] The fifth terminal of the clock chip is connected to the first terminal of the sixth capacitor, the first terminal of the fifth resistor and the third terminal of the main control chip;

[0059] The sixth terminal of the clock chip is connected to the first terminal of the seventh capacitor, the first terminal of the sixth resistor, and the fourth terminal of the main control chip;

[0060] The seventh terminal of the clock chip is connected to the first terminal of the seventh resistor;

[0061] The eighth terminal of the clock chip is connected to the first terminal of the eighth capacitor;

[0062] The second end of the fourth capacitor, the second end of the fifth capacitor, the second end of the fourth resistor, the second end of the sixth capacitor, the second end of the seventh capacitor, the second end of the eighth capacitor and the ninth end of the clock chip are grounded;

[0063] The second end of the fifth resistor, the second end of the sixth resistor, and the second end of the seventh resistor are connected to a power supply.

[0064] Optionally, the signal receiving circuit is a Beidou signal receiving circuit;

[0065] The Beidou signal receiving circuit is used to receive Beidou satellite signals, analyze the Beidou satellite signals, obtain initial time and second pulse signal, and send the initial time and second pulse signal to the main control circuit.

[0066] The present application also provides a timing system, comprising any of the above timing circuits and peripheral circuits;

[0067] The output end of the main control circuit in the timing circuit is connected to the peripheral circuit based on the Train Real-Time Data Protocol TRDP communication.

[0068] A rail transit vehicle comprises the timing system described above.

[0069] Compared with the prior art, the present application provides a timing circuit comprising: a signal receiving circuit and a main control circuit, wherein the output end of the signal receiving circuit is connected to the first input end of the main control circuit, and the output end of the main control circuit is communicatively connected to a peripheral circuit. The signal receiving circuit is configured to receive and parse satellite signals to obtain an initial time and a pulse-second signal, and transmit the initial time and pulse-second signal to the main control circuit. The main control circuit is configured to receive the initial time and pulse-second signal, calibrate the initial time based on the pulse-second signal, obtain the calibrated time, and transmit the calibrated time to the peripheral circuit. In the present application, the peripheral circuit includes circuits in a train operation monitoring and recording device and other on-board equipment (control network, monitoring network, tail-of-train device, etc.). Because the main control circuit directly transmits the calibrated time to the train operation monitoring and recording device and other on-board equipment without forwarding it through a network interface board, the time error between various devices in a rail transit vehicle can be effectively reduced, thereby effectively reducing the impact of the time error on the unified management and troubleshooting of equipment in a rail transit vehicle. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0071] Figure 1 A circuit block diagram of a timing circuit provided in an embodiment of the present application;

[0072] Figure 2 A circuit diagram of a timing circuit provided in an embodiment of the present application;

[0073] Figure 3 A circuit block diagram of a timing system provided in an embodiment of the present application;

[0074] Reference numerals: 100 - timing circuit; 110 - signal receiving circuit; 120 - main control circuit; 130 - auxiliary timing circuit; 200 - peripheral circuit;

[0075] X1-antenna; U1-signal receiver; 111-first filtering circuit;

[0076] 131- backup power supply circuit; 132- clock circuit; 133- second filter circuit;

[0077] TVS1-transient voltage diode; R1-first resistor; R2-second resistor; C1-first capacitor; C2-second capacitor; L1-inductor; Z1-ferrite bead;

[0078] U2-main control chip;

[0079] D1-diode; 1311-supercapacitor;

[0080] R3-third resistor; C3-third capacitor; C4-fourth capacitor; C5-fifth capacitor;

[0081] U3 - clock chip; R4 - fourth resistor; R5 - fifth resistor; R6 - sixth resistor; R7 - seventh resistor; C6 - sixth capacitor; C7 - seventh capacitor; C8 - eighth capacitor. DETAILED DESCRIPTION

[0082] In order to help those skilled in the art better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0083] It should be noted that when an element is referred to as being “fixed on” or “set on” another element, it can be directly on the other element or indirectly set on the other element; when an element is referred to as being “connected to” another element, it can be directly connected to the other element or indirectly connected to the other element.

[0084] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" or "several" means two or more, unless otherwise specifically defined.

[0086] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which this application can be implemented. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application.

[0087] like Figure 1 As shown, an embodiment of the present application provides a timing circuit 100, including: a signal receiving circuit 110 and a main control circuit 120; the output end of the signal receiving circuit 110 is connected to the first input end of the main control circuit 120; the output end of the main control circuit 120 is connected to the peripheral circuit 200; the signal receiving circuit 110 is used to receive satellite signals, parse the satellite signals, obtain initial time and second pulse signals, and send the initial time and second pulse signals to the main control circuit 120; the main control circuit 120 is used to receive the initial time and second pulse signals, calibrate the initial time according to the second pulse signal, obtain the calibrated time, and send the calibrated time to the peripheral circuit 200.

[0088] In this embodiment, the peripheral circuit 200 may include circuits in a train operation monitoring and recording device and other on-board equipment (control network, monitoring network, tail device, etc.); the satellite signal may be a Beidou satellite signal or a GPS satellite signal, preferably a Beidou satellite signal; the output end of the main control circuit 120 and the peripheral circuit 200 may be communicatively connected or electrically connected, preferably the output end of the main control circuit 120 and the peripheral circuit 200 are communicatively connected; the signal receiving circuit 110 receives the satellite signal transmitted by the satellite, analyzes the satellite signal, obtains the initial time and second pulse signal, and sends the initial time and second pulse signal to the main control circuit 120, and the main control circuit 120 receives the initial time and second pulse signal. The main control circuit 120 directly sends the calibrated time to the train operation monitoring and recording device and other on-board equipment (control network, monitoring network, tail device, etc.) without forwarding it once through the network interface board, so that the time error between the main control circuit 120, other on-board equipment (control network, monitoring network, tail device, etc.) and the train operation monitoring and recording device is within 100ms.

[0089] Compared with the prior art, the present application provides a timing circuit 100, comprising: a signal receiving circuit 110 and a main control circuit 120, wherein the output end of the signal receiving circuit 110 is connected to the first input end of the main control circuit 120, and the output end of the main control circuit 120 is in communication with the peripheral circuit 200, the signal receiving circuit 110 is used to receive satellite signals, parse the satellite signals, obtain the initial time and second pulse signal, and send the initial time and second pulse signal to the main control circuit 120, the main control circuit 120 is used to receive the initial time and second pulse signal, and adjust the initial time according to the second pulse signal. The time is calibrated to obtain the calibrated time, and the calibrated time is sent to the peripheral circuit 200. In this application, the peripheral circuit includes the circuits in the train operation monitoring and recording device and other on-board equipment (control network, monitoring network, tail device, etc.). Since the main control circuit 120 directly sends the calibrated time to the train operation monitoring and recording device and other on-board equipment without forwarding it once through the network interface board, it can effectively reduce the time error between various devices in the rail transit vehicle, and can effectively reduce the impact of the time error on the unified management and troubleshooting of equipment in the rail transit vehicle.

[0090] like Figure 2As shown, as an implementation method, in an embodiment of the present application, the signal receiving circuit 110 includes: an antenna X1 and a signal receiver U1; the output end of the antenna X1 is connected to the input end of the signal receiver U1; the output end of the signal receiver U1 is connected to the first input end of the main control circuit 120; the antenna X1 is used to receive and output satellite signals; the signal receiver U1 is used to receive satellite signals and parse the satellite signals to obtain initial time and second pulse signals, and send the initial time and second pulse signals to the main control circuit 120.

[0091] In this embodiment, the antenna X1 receives and outputs the satellite signal transmitted by the satellite, the signal receiver U1 receives the satellite signal, and parses the received satellite signal to obtain the parsed initial time and second pulse signal, and sends the initial time and second pulse signal to the main control circuit 120.

[0092] like Figure 2 As shown, as an implementation method, in the embodiment of the present application, the signal receiving circuit 110 also includes: a first filtering circuit 111; the output end of the antenna X1 is connected to the input end of the first filtering circuit 111; the output end of the first filtering circuit 111 is connected to the input end of the signal receiver U1; the first filtering circuit 111 is used to receive satellite signals, filter the satellite signals, and send the filtered satellite signals to the signal receiver U1.

[0093] In this embodiment, the first filtering circuit 111 receives the satellite signal sent by the antenna X1, filters the received satellite signal to obtain a filtered satellite signal, and sends the filtered satellite signal to the signal receiver U1. By filtering the satellite signal through the first filtering circuit 111, the interference signal in the satellite signal can be effectively filtered out.

[0094] like Figure 2 As shown, as an implementation method, the embodiment of the present application also includes: an auxiliary timing circuit 130; the output end of the auxiliary timing circuit 130 is connected to the second input end of the main control circuit 120; the auxiliary timing circuit 130 is used to send the backup time to the main control circuit 120.

[0095] In this embodiment, the auxiliary timing circuit 130 sends the backup time to the main control circuit 120 , so that the main control circuit 120 can send the received backup time to the peripheral circuit 200 when it does not receive the initial time and second pulse signal sent by the signal receiving circuit 110 .

[0096] like Figure 2As shown, as an implementation method, in an embodiment of the present application, the auxiliary timing circuit 130 includes a backup power supply circuit 131 and a clock circuit 132; the output end of the backup power supply circuit 131 is connected to the input end of the clock circuit 132; the output end of the clock circuit 132 is connected to the second input end of the main control circuit 120; the backup power supply circuit 131 is used to output a backup power supply voltage signal when the external power supply cannot supply power; the clock circuit 132 is used to send the backup time to the main control circuit 120 when the external power supply supplies power or receives the backup power supply voltage signal.

[0097] In this embodiment, by providing a backup power supply circuit 131 in the auxiliary timing circuit 130, when the train is out of power for a long time, that is, when the clock circuit 132 is unable to be supplied by an external power supply, the backup power supply circuit 131 can supply power to the clock circuit 132 for a long time, so that the clock circuit 132 can continue to operate even when the external power supply is unable to supply power, and continue to provide backup time to the main control circuit 120, so that the main control circuit 120 can have a higher time accuracy when it is powered on for the first time after a long power outage.

[0098] like Figure 2 As shown, as an implementation method, in an embodiment of the present application, the auxiliary timing circuit 130 also includes a second filtering circuit 133; the output end of the backup power supply circuit 131 is connected to the input end of the second filtering circuit 133; the output end of the second filtering circuit 133 is connected to the input end of the clock circuit 132; the second filtering circuit 133 is used to receive the backup power supply voltage signal, filter the backup power supply voltage signal, and send the filtered backup power supply voltage signal to the clock circuit 132.

[0099] In this embodiment, the second filtering circuit 133 filters the backup power voltage signal output by the backup power supply circuit 131 , thereby effectively filtering out interference signals in the backup power voltage signal.

[0100] like Figure 2 As shown, as an implementation manner, in the embodiment of the present application, the first filtering circuit 111 includes: a transient diode TVS1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, an inductor L1 and a magnetic bead Z1; the first end of the transient diode TVS1 and the first end of the first resistor R1 are connected to the output end of the antenna X1; the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the first end of the first capacitor C1; the second end of the first capacitor C1 and the first end of the inductor L1 are connected to the first end of the signal receiver U1; the second end of the inductor L1 is connected to the first end of the second capacitor C2 and the first end of the magnetic bead Z1; the second end of the transient diode TVS1, the second end of the second resistor R2 and the second end of the second capacitor C2 are grounded; and the second end of the magnetic bead Z1 is connected to the power supply.

[0101] In this embodiment, the transient diode TVS1 is preferably a bidirectional transient diode.

[0102] like Figure 2 As shown, as an implementation, in this embodiment of the present application, the main control circuit 120 includes a main control chip U2; the second end of the signal receiver U1 is connected to the first end of the main control chip U2; the third end of the signal receiver U1 is connected to the second end of the main control chip U2; the third and fourth ends of the main control chip U2 are connected to the output end of the clock circuit 132; and the fifth end of the main control chip U2 is connected to the peripheral circuit 200. In this embodiment, pin 5 of the main control chip U2 is connected to the peripheral circuit 200, which is not shown in the figure.

[0103] In this embodiment, the model of the main control chip U2 may be LS1403A, and the model of the signal receiver U1 may be R930BD.

[0104] like Figure 2 As shown, as an implementation method, in an embodiment of the present application, the backup power supply circuit 131 includes: a diode D1 and a super capacitor 1311; the positive electrode of the diode D1 is connected to the power supply; the negative electrode of the diode D1 and the positive electrode of the super capacitor 1311 are connected to the input end of the second filter circuit 133; and the negative electrode of the super capacitor 1311 is grounded.

[0105] In this embodiment, when the train is powered off for a long time, that is, when the external power supply is unable to supply power, the super capacitor 1311 can supply power to the clock circuit 132 for a long time through the second filter circuit 133.

[0106] like Figure 2 As shown, as an implementation method, in an embodiment of the present application, the second filtering circuit 133 includes a third resistor R3 and a third capacitor C3; the first end of the third resistor R3 is connected to the output end of the backup power supply circuit 131; the second end of the third resistor R3 is connected to the first end of the third capacitor C3 and the input end of the clock circuit 132; the second end of the third capacitor C3 is grounded.

[0107] like Figure 2As shown, as an implementation manner, in the embodiment of the present application, the second filtering circuit 133 further includes: a fourth capacitor C4 and a fifth capacitor C5, and the clock circuit 132 includes: a clock chip U3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8; the first end of the clock chip U3 is connected to the first end of the fourth capacitor C4 and the power supply; the second end of the clock chip U3 is connected to the first end of the fifth capacitor C5 and the power supply; the third end of the clock chip U3 is connected to the second end of the third resistor R3 and the first end of the third capacitor C3; the fourth end of the clock chip U3 is connected to the first end of the fourth resistor R4; the fifth end of the clock chip U3 is connected to the sixth capacitor C 6, the first end of the fifth resistor R5 and the third end of the main control chip U2 are connected; the sixth end of the clock chip U3 is connected to the first end of the seventh capacitor C7, the first end of the sixth resistor R6 and the fourth end of the main control chip U2; the seventh end of the clock chip U3 is connected to the first end of the seventh resistor R7; the eighth end of the clock chip U3 is connected to the first end of the eighth capacitor C8; the second end of the fourth capacitor C4, the second end of the fifth capacitor C5, the second end of the fourth resistor R4, the second end of the sixth capacitor C6, the second end of the seventh capacitor C7, the second end of the eighth capacitor C8 and the ninth end of the clock chip U3 are grounded; the second end of the fifth resistor R5, the second end of the sixth resistor R6 and the second end of the seventh resistor R7 are connected to the power supply.

[0108] In this embodiment, the model of the clock chip U3 can be RX8111CE, and the power supply can be a 3.3V power supply. The backup time is sent to the main control chip U2 in the main control circuit 120 through the clock chip U3 in the auxiliary timing circuit 130, so that when the main control chip U2 does not receive the initial time and second pulse signal sent by the signal receiving circuit 110, the received backup time can be sent to the peripheral circuit 200; in the case that the train is out of power for a long time, that is, when the external power supply cannot supply power, the supercapacitor 1311 can supply power to the clock chip U3 for a long time through the third resistor R3 in the second filter circuit 133, so that when the external power supply (such as a 3.3V power supply) cannot supply power, the clock chip U3 can also continue to run and continue to provide backup time to the main control chip U2.

[0109] As an implementation method, in an embodiment of the present application, the signal receiving circuit 110 is a Beidou signal receiving circuit 110; the Beidou signal receiving circuit 110 is used to receive Beidou satellite signals, parse the Beidou satellite signals, obtain initial time and second pulse signals, and send the initial time and second pulse signals to the main control circuit 120.

[0110] In this embodiment, the signal receiving circuit 110 is a Beidou signal receiving circuit 110, that is, the signal receiver U1 is a Beidou signal receiver U1 that receives Beidou satellite signals transmitted by Beidou satellites. Since the GPS satellite signals transmitted by GPS satellites are easily interfered with by signals with similar frequency points such as GPS, by adopting the Beidou signal receiving circuit 110 including the Beidou signal receiver U1, it is possible to effectively avoid interference from signals with similar frequency points such as GPS.

[0111] like Figure 3 As shown, the present application also provides a timing system, comprising any one of the timing circuits 100 and peripheral circuits 200 described above; the output end of the main control circuit 120 in the timing circuit 100 is connected to the peripheral circuit 200 based on the train real-time data protocol TRDP.

[0112] In this embodiment, TRDP adopts a time-triggered mechanism based on hard real-time time slots to ensure the transmission and processing of communication data, so that the communication delay is low (within 50ms).

[0113] A rail transit vehicle comprises the above-mentioned timing system.

[0114] The embodiments in this specification are described in a progressive manner, and each embodiment focuses on the following

[0115] For other differences between the embodiments, reference may be made to the same or similar parts between the embodiments.

[0116] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A timing circuit, characterized in that: include: Signal receiving circuit and main control circuit; The output end of the signal receiving circuit is connected to the first input end of the main control circuit; The output end of the main control circuit is connected to the peripheral circuit; The signal receiving circuit is used to receive satellite signals, analyze the satellite signals, obtain initial time and pulse-second signal, and send the initial time and pulse-second signal to the main control circuit; The main control circuit is used to receive the initial time and the second pulse signal, calibrate the initial time according to the second pulse signal to obtain the calibrated time, and send the calibrated time to the peripheral circuit.

2. The timing circuit according to claim 1, characterized in that: The signal receiving circuit includes: an antenna and a signal receiver; The output end of the antenna is connected to the input end of the signal receiver; The output end of the signal receiver is connected to the first input end of the main control circuit; The antenna is used to receive and output satellite signals; The signal receiver is used to receive the satellite signal, analyze the satellite signal, obtain the initial time and the second pulse signal, and send the initial time and the second pulse signal to the main control circuit.

3. The timing circuit according to claim 2, characterized in that: The signal receiving circuit further includes: a first filtering circuit; The output end of the antenna is connected to the input end of the first filtering circuit; The output end of the first filter circuit is connected to the input end of the signal receiver; The first filtering circuit is configured to receive the satellite signal, filter the satellite signal, and send the filtered satellite signal to the signal receiver.

4. The timing circuit according to claim 3, characterized in that: Also includes: Auxiliary timing circuit; The output end of the auxiliary timing circuit is connected to the second input end of the main control circuit; The auxiliary timing circuit is used to send the backup time to the main control circuit.

5. The timing circuit according to claim 4, characterized in that: The auxiliary timing circuit includes a backup power supply circuit and a clock circuit; The output end of the backup power supply circuit is connected to the input end of the clock circuit; The output end of the clock circuit is connected to the second input end of the main control circuit; The backup power supply circuit is used to output a backup power supply voltage signal when the external power supply fails to supply power; The clock circuit is used to send the backup time to the main control circuit when the external power supply is supplied or the backup power supply voltage signal is received.

6. The timing circuit according to claim 5, characterized in that: The auxiliary timing circuit also includes a second filtering circuit; The output end of the backup power supply circuit is connected to the input end of the second filter circuit; The output end of the second filter circuit is connected to the input end of the clock circuit; The second filtering circuit is configured to receive the backup power supply voltage signal, filter the backup power supply voltage signal, and send the filtered backup power supply voltage signal to the clock circuit.

7. The timing circuit according to claim 6, characterized in that: The first filtering circuit includes: a transient diode, a first resistor, a second resistor, a first capacitor, a second capacitor, an inductor and a magnetic bead; The first end of the transient diode and the first end of the first resistor are connected to the output end of the antenna; The second end of the first resistor is connected to the first end of the second resistor and the first end of the first capacitor; The second end of the first capacitor is connected to the first end of the inductor and the first end of the signal receiver; The second end of the inductor is connected to the first end of the second capacitor and the first end of the magnetic bead; The second end of the transient diode, the second end of the second resistor, and the second end of the second capacitor are grounded; The second end of the magnetic bead is connected to a power source.

8. The timing circuit according to claim 7, characterized in that: The main control circuit includes a main control chip; The second end of the signal receiver is connected to the first end of the main control chip; The third end of the signal receiver is connected to the second end of the main control chip; The third terminal and the fourth terminal of the main control chip are connected to the output terminal of the clock circuit; The fifth terminal of the main control chip is connected to the peripheral circuit.

9. The timing circuit according to claim 8, characterized in that: The backup power supply circuit includes: a diode and a super capacitor; The positive electrode of the diode is connected to the power supply; The cathode of the diode, the anode of the supercapacitor and the input end of the second filter circuit are connected; The negative electrode of the supercapacitor is grounded.

10. The timing circuit according to claim 9, characterized in that: The second filtering circuit includes a third resistor and a third capacitor; The first end of the third resistor is connected to the output end of the backup power supply circuit; The second end of the third resistor is connected to the first end of the third capacitor and the input end of the clock circuit; A second terminal of the third capacitor is grounded.

11. The timing circuit according to claim 10, characterized in that: The second filtering circuit further includes: a fourth capacitor and a fifth capacitor, and the clock circuit includes: a clock chip, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a sixth capacitor, a seventh capacitor and an eighth capacitor; The first end of the clock chip is connected to the first end of the fourth capacitor and a power supply; The second end of the clock chip is connected to the first end of the fifth capacitor and a power supply; The third end of the clock chip, the second end of the third resistor, and the first end of the third capacitor; The fourth terminal of the clock chip is connected to the first terminal of the fourth resistor; The fifth terminal of the clock chip is connected to the first terminal of the sixth capacitor, the first terminal of the fifth resistor and the third terminal of the main control chip; The sixth terminal of the clock chip is connected to the first terminal of the seventh capacitor, the first terminal of the sixth resistor, and the fourth terminal of the main control chip; The seventh terminal of the clock chip is connected to the first terminal of the seventh resistor; The eighth terminal of the clock chip is connected to the first terminal of the eighth capacitor; The second end of the fourth capacitor, the second end of the fifth capacitor, the second end of the fourth resistor, the second end of the sixth capacitor, the second end of the seventh capacitor, the second end of the eighth capacitor and the ninth end of the clock chip are grounded; The second end of the fifth resistor, the second end of the sixth resistor, and the second end of the seventh resistor are connected to a power supply.

12. The timing circuit according to any one of claims 1 to 11, characterized in that: The signal receiving circuit is a Beidou signal receiving circuit; The Beidou signal receiving circuit is used to receive Beidou satellite signals, analyze the Beidou satellite signals, obtain initial time and second pulse signal, and send the initial time and second pulse signal to the main control circuit.

13. A timing system, characterized in that: A timing circuit and a peripheral circuit comprising any one of claims 1 to 12; The output end of the main control circuit in the timing circuit is connected to the peripheral circuit based on the Train Real-Time Data Protocol TRDP communication.

14. A rail transit vehicle, characterized in that: Including the timing system described in claim 13.

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