Shift register unit, gate drive circuit and display device

Abstract

The utility model provides a shift register unit, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register unit comprises a plurality of control circuits and an output circuit. Under the mutual cooperation of a plurality of control circuits, the potential of the pull-up node and the potential of the pull-down node can be stabilized by flexibly setting clock signals, and then it is ensured that the output capacity of the shifting register unit is good. Besides, on the basis that the output circuit responds to the potential of the pull-up node and the potential of the pull-down node and outputs cascade signals to other cascaded shift register units and outputs driving signals to pixels through different output ends, the cascade load can be reduced, so that the cascade function is prevented from being affected by the load, and it is ensured that the cascade function is good. Therefore, by adopting the shift register unit, the pixels can be driven to emit light reliably, the phenomenon of poor display is avoided, and a relatively good display effect is ensured.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, and a display device. Background Art

[0002] The gate drive circuit is one of the essential circuits in a display device, and is mostly used to transmit gate drive signals to pixels in the display device to drive the pixels to emit light.

[0003] Currently, to meet the demand for narrow bezel designs, gate drive on array (GOA) technology is often used to integrate gate drive circuits onto the array substrate of a display device. Accordingly, gate drive circuits are also called GOA circuits. Furthermore, a GOA circuit generally includes multiple cascaded shift register units (also called GOA units). These multiple GOA units are connected to multiple rows of pixels to output gate drive signals row by row, achieving progressive scanning.

[0004] However, due to the influence of structure or connection mode, the reliability of the gate driving signal output by the current GOA unit is poor, which can easily cause abnormal display and poor display, resulting in poor display effect of the display device. Utility Model Content

[0005] Provided are a shift register unit, a gate drive circuit, and a display device, which can solve the problem in related technologies of display abnormalities and poor display quality caused by poor reliability of the gate drive signal output by the GOA unit. The technical solution is as follows:

[0006] In one aspect, a shift register unit is provided, comprising:

[0007] a first control circuit, connected to the first input terminal, the second input terminal, the first control terminal, the second control terminal, the first power terminal, the pull-down node, and the pull-up node, respectively, and configured to control the connection and disconnection between the first control terminal and the pull-up node in response to a first input signal provided by the first input terminal, control the connection and disconnection between the second control terminal and the pull-up node in response to a second input signal provided by the second input terminal, and control the connection and disconnection between the first power terminal and the pull-up node in response to a potential of the pull-down node;

[0008] a second control circuit, connected to the first control terminal, the second control terminal, the first clock terminal, the second clock terminal, and the intermediate node, respectively, and configured to control the connection and disconnection between the first clock terminal and the intermediate node in response to a first control signal provided by the first control terminal, and to control the connection and disconnection between the second clock terminal and the intermediate node in response to a second control signal provided by the second control terminal;

[0009] a third control circuit, connected to the second power supply terminal, the pull-up node, the intermediate node, and the pull-down node, respectively, and configured to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the potential of the pull-up node, and to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the intermediate node;

[0010] The output circuit is respectively connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal, the shift output terminal and the drive output terminal, and is used to control the on-off connection between the third clock terminal and the shift output terminal and the third clock terminal and the drive output terminal in response to the potential of the pull-up node, and to control the on-off connection between the first power supply terminal and the shift output terminal and the first power supply terminal and the drive output terminal in response to the potential of the pull-down node; wherein the shift output terminal is used to be connected to other stages of cascaded shift register units, and the drive output terminal is used to be connected to pixels in a display panel.

[0011] Optionally, the output circuit includes:

[0012] a first output sub-circuit, connected to the pull-up node, the pull-down node, the third clock terminal, the first power terminal, and the driving output terminal, respectively, and configured to control the connection and disconnection between the third clock terminal and the driving output terminal in response to the potential of the pull-up node, and to control the connection and disconnection between the first power terminal and the driving output terminal in response to the potential of the pull-down node;

[0013] The second output sub-circuit is respectively connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal and the shift output terminal, and is used to control the connection and disconnection of the third clock terminal and the shift output terminal in response to the potential of the pull-up node, and to control the connection and disconnection of the first power supply terminal and the shift output terminal in response to the potential of the pull-down node.

[0014] Optionally, the first output sub-circuit includes: a first transistor and a second transistor; the second output sub-circuit includes: a third transistor and a fourth transistor;

[0015] The gate of the first transistor is connected to the pull-up node, the first electrode of the first transistor is connected to the third clock terminal, and the second electrode of the first transistor is connected to the driving output terminal;

[0016] The gate of the second transistor is connected to the pull-down node, the first electrode of the second transistor is connected to the first power supply terminal, and the second electrode of the second transistor is connected to the driving output terminal;

[0017] The gate of the third transistor is connected to the pull-up node, the first electrode of the third transistor is connected to the third clock terminal, and the second electrode of the third transistor is connected to the shift output terminal;

[0018] A gate of the fourth transistor is connected to the pull-down node, a first electrode of the fourth transistor is connected to the first power supply terminal, and a second electrode of the fourth transistor is connected to the shift output terminal.

[0019] Optionally, a channel width-to-length ratio of the third transistor is different from a channel width-to-length ratio of the first transistor; and / or a channel width-to-length ratio of the fourth transistor is different from a channel width-to-length ratio of the second transistor.

[0020] Optionally, the ratio of the channel width-to-length ratio of the third transistor to the channel width-to-length ratio of the first transistor is greater than 80%; and the ratio of the channel width-to-length ratio of the fourth transistor to the channel width-to-length ratio of the second transistor is greater than 80%.

[0021] Optionally, the first control circuit, the third control circuit, the output circuit and the second control circuit are sequentially arranged along a first direction and in a direction close to the driving output end;

[0022] Furthermore, the third transistor and the first transistor in the output circuit are arranged in sequence along the second direction, and the fourth transistor and the second transistor are arranged in sequence along the first direction, wherein the first direction intersects with the second direction.

[0023] Optionally, the third control circuit includes:

[0024] a first control subcircuit, connected to the pull-up node, the first power supply terminal, and the pull-down node, respectively, and configured to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the potential of the pull-up node;

[0025] The second control subcircuit is connected to the intermediate node, the second power supply terminal and the pull-down node respectively, and is used to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the intermediate node.

[0026] Optionally, the first control subcircuit includes: a fifth transistor; the second control subcircuit includes: a sixth transistor;

[0027] The gate of the fifth transistor is connected to the pull-up node, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the pull-down node;

[0028] A gate of the sixth transistor is connected to the intermediate node, a first electrode of the sixth transistor is connected to the second power supply terminal, and a second electrode of the sixth transistor is connected to the pull-down node.

[0029] Optionally, the second control circuit includes: a seventh transistor and an eighth transistor;

[0030] The gate of the seventh transistor is connected to the first control terminal, the first electrode of the seventh transistor is connected to the first clock terminal, and the second electrode of the seventh transistor is connected to the intermediate node;

[0031] A gate of the eighth transistor is connected to the second control terminal, a first electrode of the eighth transistor is connected to the second clock terminal, and a second electrode of the eighth transistor is connected to the intermediate node.

[0032] Optionally, the first control circuit includes: a ninth transistor, a tenth transistor, and an eleventh transistor;

[0033] The gate of the ninth transistor is connected to the first input terminal, the first electrode of the ninth transistor is connected to the first control terminal, and the second electrode of the ninth transistor is connected to the pull-up node;

[0034] The gate of the tenth transistor is connected to the second input terminal, the first electrode of the tenth transistor is connected to the second control terminal, and the second electrode of the tenth transistor is connected to the pull-up node;

[0035] A gate of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the first power supply terminal, and a second electrode of the eleventh transistor is connected to the pull-up node.

[0036] Optionally, the pull-up node includes: a first pull-up node and a second pull-up node, the first control circuit, the second control circuit, and the third control circuit are all connected to the first pull-up node, and the output circuit is connected to the second pull-up node; and the shift register unit further includes:

[0037] a fourth control circuit, connected to the second power supply terminal, the first pull-up node, and the second pull-up node, respectively, and configured to control the on / off switching of the first pull-up node and the second pull-up node in response to a second power supply signal provided by the second power supply terminal;

[0038] Optionally, the shift register unit further includes at least one of the following circuits:

[0039] a first reset circuit, connected to a reset control terminal, the first power terminal, and the first pull-up node, respectively, and configured to control the connection and disconnection between the first power terminal and the first pull-up node in response to a reset control signal provided by the reset control terminal;

[0040] a second reset circuit, connected to the touch enable terminal, the first power supply terminal, and the drive output terminal, respectively, and configured to control the on / off connection between the first power supply terminal and the drive output terminal in response to a touch enable signal provided by the touch enable terminal;

[0041] a first storage circuit connected between the second pull-up node and the driving output terminal and configured to control the potential of the second pull-up node;

[0042] The second storage circuit is connected between the pull-down node and the first power supply terminal and is used to control the potential of the pull-down node.

[0043] Optionally, the fourth control circuit includes a twelfth transistor; the first reset circuit includes a thirteenth transistor; the second reset circuit includes a fourteenth transistor; the first storage circuit includes a first capacitor; and the second storage circuit includes a second capacitor.

[0044] The gate of the twelfth transistor is connected to the second power supply terminal, the first electrode of the twelfth transistor is connected to the first pull-up node, and the first electrode of the twelfth transistor is connected to the second pull-up node;

[0045] The gate of the thirteenth transistor is connected to the reset control terminal, the first electrode of the thirteenth transistor is connected to the first power supply terminal, and the second electrode of the thirteenth transistor is connected to the first pull-up node;

[0046] The gate of the fourteenth transistor is connected to the touch enable terminal, the first electrode of the fourteenth transistor is connected to the first power supply terminal, and the second electrode of the fourteenth transistor is connected to the driving output terminal;

[0047] One end of the first capacitor is connected to the driving output end, and the other end of the first capacitor is connected to the second pull-up node;

[0048] One end of the second capacitor is connected to the first power supply end, and the other end of the first capacitor is connected to the pull-down node.

[0049] In another aspect, a gate driving circuit is provided, the gate driving circuit comprising: a plurality of shift register units as described in the above aspect connected in cascade;

[0050] The shift output end of each shift register unit is connected to the second input end of the cascaded previous shift register unit, and the driving output end of each shift register unit is connected to the first input end of the cascaded subsequent shift register unit.

[0051] In another aspect, a display device is provided, comprising: a display panel, and the gate driving circuit according to the above-mentioned further aspect; the display panel comprises a plurality of pixels;

[0052] The gate driving circuit is connected to the plurality of pixels via a driving output terminal and is used for transmitting a gate driving signal to the plurality of pixels to drive the plurality of pixels to emit light.

[0053] In summary, the beneficial effects brought about by the technical solution provided by this application may include at least:

[0054] Provided are a shift register unit, a gate drive circuit, and a display device. The shift register unit includes multiple control circuits and an output circuit. The multiple control circuits cooperate with each other to stabilize the potentials of the pull-up and pull-down nodes by flexibly setting clock signals, thereby ensuring a good output capability of the shift register unit. Furthermore, the output circuit responds to the potentials of the pull-up and pull-down nodes, outputting cascade signals to other cascaded shift register units and drive signals to pixels via different output terminals. This reduces the cascade load, thereby preventing the cascade function from being affected by the load and ensuring a good cascade function. Thus, the shift register unit can be used to drive pixels to emit light reliably, avoiding display defects and ensuring a good display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] Figure 1 This is a structural diagram of a shift register unit provided in an embodiment of the present application;

[0057] Figure 2 is a structural diagram of another shift register unit provided in an embodiment of the present application;

[0058] Figure 3 This is a structural diagram of another shift register unit provided in an embodiment of the present application;

[0059] Figure 41 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present application;

[0060] Figure 5 This is a schematic diagram of a circuit structure of multiple shift register units provided in an embodiment of the present application;

[0061] Figure 6 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of the present application;

[0062] Figure 7 This is a schematic diagram of the structural layout of multiple shift register units provided in an embodiment of the present application;

[0063] Figure 8 This is a flow chart of a driving method of a shift register unit provided in an embodiment of the present application;

[0064] Figure 9 This is a timing simulation diagram of a shift register unit provided in an embodiment of the present application;

[0065] Figure 10 This is a timing simulation diagram of another shift register unit provided in an embodiment of the present application;

[0066] Figure 11 This is a timing simulation diagram of another shift register unit provided in an embodiment of the present application;

[0067] Figure 12 This is a timing simulation diagram of another shift register unit provided in an embodiment of the present application;

[0068] Figure 13 1 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0069] Figure 14 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0071] It is understood that the transistors used in the embodiments of the present application can all be thin-film transistors or field-effect transistors or other devices with the same characteristics, such as metal-oxide-semiconductor (MOS) field-effect transistors, also known as MOS transistors. According to their functions in the circuit, the transistors used in the embodiments of the present application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present application, the source is referred to as the first electrode and the drain is referred to as the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the control electrode, which can also be referred to as the gate, the signal input end is the source electrode, and the signal output end is the drain electrode. In addition, the switching transistors used in the embodiments of the present application can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is low and turned off when the gate is high, and the N-type switching transistor is turned on when the gate is high and turned off when the gate is low. In addition, the multiple signals in each embodiment of the present application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not mean that the first potential or the second potential has a specific value in the full text.

[0072] In some embodiments, among the multiple shift register units in cascade, each shift register unit outputs a driving signal and a cascade signal to the pixel and the other shift register units in the cascade through an output terminal, respectively, to drive the pixel to emit light and drive the other shift register units to work. That is, each shift register unit will simultaneously assume the driving function of turning on the connected pixels in the row and the cascade function of turning on the shift register units in other stages. In this way, when the size of the display panel is large, the load connected to one output terminal is large, which will cause the cascade function to be affected and the shift register units in the other stages of the cascade cannot be fully turned on. This will further cause the shift register units in other stages to be unable to reliably drive the connected pixels to emit light, resulting in poor display phenomena such as flowery screen display or split screen display on the display panel, and poor display effect.

[0073] In addition, in some embodiments, due to the connection method, a competitive relationship may be formed between the pull-up node and the pull-down node of each shift register unit. For example, the pull-up node and the pull-down node may be charged simultaneously at a certain moment, resulting in an unnecessary DC path between the transistor that controls the potential of the pull-down node based on the potential of the pull-up node and the transistor that controls the potential of the pull-up node based on the potential of the pull-down node. This will cause the potential of the pull-up node and the potential of the pull-down node to be unable to reach the desired potential, thereby causing the shift register unit to be unable to reliably output the desired drive signal and cascade signal, that is, the output capacity of the shift register unit is poor, which will also lead to poor display effects. Based on this, in other embodiments, it is also considered to improve the output capacity of the shift register unit by increasing the channel width-to-length ratio of the above-mentioned transistors, such as setting the channel width-to-length ratio of the transistor that controls the potential of the pull-down node based on the potential of the pull-up node and the transistor that controls the potential of the pull-up node based on the potential of the pull-down node to 1 / 4. However, increasing the channel width-to-length ratio of the transistors will increase the size of the shift register unit, which is not conducive to the narrow frame design of the display device. Furthermore, the formation of a DC path will additionally increase the operating power consumption of the shift register unit, and there is also a risk of transistor damage, resulting in reduced operating reliability of the display panel.

[0074] Based on this, the embodiment of the present application provides a new shift register unit to ensure that the output capacity of the shift register unit is good, reliably drive the pixels to emit light, and achieve better display effects, while also facilitating the design of a narrow frame and ensuring better working reliability of the display panel.

[0075] Figure 1 Schematic diagram of the structure of a shift register unit provided in an embodiment of the present application. Figure 1 As shown, the shift register unit includes: a first control circuit 01 , a second control circuit 02 , a third control circuit 03 and an output circuit 04 .

[0076] The first control circuit 01 is connected to the first input terminal CAS1, the second input terminal CAS2, the first control terminal CN, the second control terminal CNB, the first power supply terminal VGL_G, the pull-down node PD, and the pull-up node PU, respectively. The first control circuit 01 is configured to control the connection and disconnection between the first control terminal CN and the pull-up node PU in response to a first input signal provided by the first input terminal CAS1, control the connection and disconnection between the second control terminal CNB and the pull-up node PU in response to a second input signal provided by the second input terminal CAS2, and control the connection and disconnection between the first power supply terminal VGL_G and the pull-up node PU in response to the potential of the pull-down node PD.

[0077] For example, when the potential of the first input signal provided by the first input terminal CAS1 is a first potential, the first control terminal CN can be controlled to be conductive with the pull-up node PU, so that the first control signal provided by the first control terminal CN can be transmitted to the pull-up node PU, and when the potential of the first input signal provided by the first input terminal CAS1 is a second potential, the first control terminal CN can be controlled to be disconnected from the pull-up node PU. Similarly, when the potential of the second input signal provided by the second input terminal CAS2 is a first potential, the first control circuit 01 can be controlled to be conductive with the second control terminal CNB and the pull-up node PU, so that the second control signal provided by the second control terminal CNB can be transmitted to the pull-up node PU, and when the potential of the second input signal provided by the second input terminal CAS2 is a second potential, the second control terminal CNB can be controlled to be disconnected from the pull-up node PU. Furthermore, the first control circuit 01 can control the first power terminal VGL_G to be conductive with the pull-up node PU when the potential of the pull-down node PD is at a first potential, so that the first power signal provided by the first power terminal VGL_G can be transmitted to the pull-up node PU. Furthermore, the first control circuit 01 can control the first power terminal VGL_G to be disconnected from the pull-up node PU when the potential of the pull-down node PD is at a second potential. In other words, the first control circuit 01 can control the potential of the pull-up node PU.

[0078] Optionally, in an embodiment of the present application, the first potential may be a higher potential relative to the second potential. That is, the first potential may be a high potential, and the second potential may be a low potential. Of course, in some other embodiments, the first potential may also be a lower potential relative to the second potential. Furthermore, for an N-type transistor, the effective potential may be a high potential, and the invalid potential may be a low potential. For a P-type transistor, the effective potential may be a low potential, and the invalid potential may be a high potential.

[0079] Optionally, the first input terminal CAS1 can be connected to the cascaded upper shift register unit, and the second input terminal CAS2 can be connected to the cascaded lower shift register unit to support forward and reverse scanning functions. Accordingly, the first control terminal CN and the second control terminal CNB can be control terminals that support the forward scanning function and the reverse scanning function, respectively. Of course, the first input terminal CAS1 of the first-stage shift register unit can be connected to the start signal terminal STV to operate based on the start signal provided by the start signal terminal STV. Among them, the forward scanning function can refer to sequential scanning from the first row to the last row of the display panel; the reverse scanning function can refer to sequential scanning from the last row to the first row of the display panel, and scanning is to drive the pixels to emit light.

[0080] The second control circuit 02 is connected to the first control terminal CN, the second control terminal CNB, the first clock terminal CK1, the second clock terminal CK2, and the intermediate node P0, respectively. The second control circuit 02 is configured to control the connection between the first clock terminal CK1 and the intermediate node P0 in response to a first control signal provided by the first control terminal CN, and to control the connection between the second clock terminal CK2 and the intermediate node P0 in response to a second control signal provided by the second control terminal CNB.

[0081] For example, when the potential of the first control signal provided by the first control terminal CN is a first potential, the second control circuit 02 can control the first clock terminal CK1 to be conductive with the intermediate node P0, so that the first clock signal provided by the first clock terminal CK1 can be transmitted to the intermediate node P0, and can control the first clock terminal CK1 to be disconnected from the intermediate node P0 when the potential of the first control signal provided by the first control terminal CN is a second potential. Similarly, when the potential of the second control signal provided by the second control terminal CNB is a first potential, the second control circuit 02 can control the second clock terminal CK2 to be conductive with the intermediate node P0, so that the second clock signal provided by the second clock terminal CK2 can be transmitted to the intermediate node P0, and can control the second clock terminal CK2 to be disconnected from the intermediate node P0 when the potential of the second control signal provided by the second control terminal CNB is a second potential. In other words, the second control circuit 02 can control the potential of the intermediate node P0.

[0082] Based on the above description, it can be known that the first control terminal CN and the second control terminal CNB can be control terminals that support the forward scanning function and the reverse scanning function, respectively. Accordingly, the second control circuit 02 controls the potential of the intermediate node P0 in response to the first control signal provided by the first control terminal CN and the second control signal provided by the second control terminal CNB, and can also support the forward and reverse scanning functions. For example, when the potential of the first control signal provided by the first control terminal CN is the first potential and the potential of the second control signal provided by the second control terminal CNB is the second potential, forward scanning can be achieved. When the potential of the first control signal provided by the first control terminal CN is the second potential and the potential of the second control signal provided by the second control terminal CNB is the first potential, reverse scanning can be achieved.

[0083] The third control circuit 03 is connected to the second power supply terminal VGH_G, the pull-up node PU, the intermediate node P0, and the pull-down node PD. The third control circuit 03 is used to control the connection between the first power supply terminal VGL_G and the pull-down node PD in response to the potential of the pull-up node PU, and to control the connection between the second power supply terminal VGH_G and the pull-down node PD in response to the potential of the intermediate node P0.

[0084] For example, when the potential of the pull-up node PU is at a first potential, the third control circuit 03 can control the first power supply terminal VGL_G to be conductive with the pull-down node PD, so that a first power signal provided by the first power supply terminal VGL_G can be transmitted to the pull-down node PD. Furthermore, when the potential of the pull-up node PU is at a second potential, the third control circuit 03 can control the first power supply terminal VGL_G to be disconnected from the pull-down node PD. Similarly, when the potential of the intermediate node P0 is at a first potential, the third control circuit 03 can control the second power supply terminal VGH_G to be conductive with the pull-down node PD, so that a second power signal provided by the second power supply terminal VGH_G can be transmitted to the pull-down node PD. Furthermore, when the potential of the intermediate node P0 is at a second potential, the third control circuit 03 can control the second power supply terminal VGH_G to be disconnected from the pull-down node PD. In other words, the third control circuit 03 can control the potential of the pull-down node PD.

[0085] Optionally, the potential of the first power signal provided by the first power terminal VGL_G may be a low potential, and the potential of the second power signal provided by the second power terminal VGH_G may be a high potential. Here, low potential and high potential are relative.

[0086] It is understandable that, with the mutual cooperation of the first control circuit 01, the second control circuit 02, and the third control circuit 03, the clock signal provided by the clock terminal can be flexibly set to avoid the formation of a competitive relationship between the pull-down node PD and the pull-up node PU, thereby avoiding the formation of an unnecessary DC path between the transistor in the first control circuit 01 that controls the potential of the pull-up node PU based on the potential of the pull-down node PD and the transistor in the third control circuit 03 that controls the potential of the pull-down node PD based on the potential of the pull-up node PU. In this way, it is not only possible to ensure that the potential of the pull-up node and the potential of the pull-down node can both stably reach the desired potential, ensuring that the output capacity of the shift register unit is good, but also to reduce the operating power consumption of the shift register unit and reduce the risk of transistor damage, thereby improving the operating reliability of the display panel. In addition, since there is no unnecessary DC path, there is no need to increase the channel width-to-length ratio of the above-mentioned transistor to ensure the good output capacity of the shift register unit, which can also facilitate the narrow frame design of the display device.

[0087] Output circuit 04 is connected to a pull-up node PU, a pull-down node PD, a third clock terminal CK3, a first power supply terminal VGL_G, a shift output terminal CR, and a driver output terminal OUT, respectively. Output circuit 04 is configured to control the connection between the third clock terminal CK3 and the shift output terminal CR, and the connection between the third clock terminal CK3 and the driver output terminal OUT, in response to the potential of the pull-up node PU. It is also configured to control the connection between the first power supply terminal VGL_G and the shift output terminal CR, and the connection between the first power supply terminal VGL_G and the driver output terminal OUT, in response to the potential of the pull-down node PD.

[0088] For example, when the potential of the pull-up node PU is at a first potential, the output circuit 04 can control the third clock terminal CK3 to be conductive with the shift output terminal CR, and to be conductive with the drive output terminal OUT, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the shift output terminal CR and the drive output terminal OUT. When the potential of the pull-up node PU is at a second potential, the output circuit 04 can control the third clock terminal CK3 to be disconnected from the shift output terminal CR, and to be disconnected from the drive output terminal OUT. Similarly, when the potential of the pull-down node PD is at a first potential, the output circuit 04 can control the first power supply terminal VGL_G to be conductive with the shift output terminal CR, and to be conductive with the drive output terminal OUT, so that the first power supply signal provided by the first power supply terminal VGL_G can be transmitted to the shift output terminal CR and the drive output terminal OUT. When the potential of the pull-down node PD is at a second potential, the output circuit 04 can control the first power supply terminal VGL_G to be disconnected from the shift output terminal CR, and to be disconnected from the drive output terminal OUT. That is, the output circuit 04 can output signals via the driving output terminal OUT and the shift output terminal CR respectively.

[0089] Among them, the shift output terminal CR is used to connect to other levels of shift register units in the cascade, and the drive output terminal OUT is used to connect to the pixels in the display panel. Accordingly, the signal output by the shift register unit through the shift output terminal CR can be used as a cascade signal to drive other levels of shift register units to work. The signal output by the shift register unit through the drive output terminal OUT can be used as a drive signal to drive the pixel to emit light. That is, in the embodiment of the present application, the cascade signal and the drive signal can be output independently through different output terminals, and the cascade function and the drive function can be executed independently. In this way, compared with the above-mentioned embodiment in which the drive signal and the cascade signal are output through the same output terminal (that is, the shift output terminal CR and the drive output terminal OUT are shared), the load of the pixel originally connected to the cascade output terminal CR can be eliminated, thereby avoiding the cascade function from being affected by the large load and ensuring a better cascade function. In addition, the shift register units at all levels can reliably drive the connected pixels to emit light, avoiding poor display of the display panel and ensuring a better display effect.

[0090] Alternatively, the shift register units of the other stages may be, for example, the shift register units of the next stage adjacent to the current stage, i.e., the two adjacent stages of shift register units may be cascaded via the shift output terminal CR. Furthermore, multiple stages of shift register units may be connected to multiple rows of pixels in a one-to-one correspondence, i.e., each stage of shift register units may be connected to a corresponding row of pixels via the drive output terminal OUT. Of course, the connection method described here is merely illustrative. For example, in some other embodiments, an odd number of stages of shift register units may be cascaded, and each stage of shift register units may be connected to multiple rows of pixels.

[0091] Optionally, in combination with the above description, the cascade output terminal CR of each stage of the shift register unit can be connected to the first input terminal CAS1 of the cascaded subsequent stage shift register unit, and can be connected to the second input terminal CAS2 of the cascaded previous stage shift register unit to support the forward and reverse scanning functions through the first input terminal CAS1 and the second input terminal CAS2.

[0092] In summary, an embodiment of the present application provides a shift register unit. The shift register unit includes: a first control circuit, a second control circuit, a third control circuit, and an output circuit. With the mutual cooperation of the first control circuit to the third control circuit, the potential stability of the pull-up node and the pull-down node can be ensured by flexibly setting the clock signal provided by the clock terminal, thereby ensuring that the output capacity of the shift register unit is good. In addition, on the basis of the output circuit responding to the potential of the pull-up node and the potential of the pull-down node, outputting cascade signals to other stages of shift register units and outputting drive signals to pixels through different output terminals respectively, the load connected to the cascade output terminal can be reduced, thereby avoiding the cascade function being affected by the load and ensuring a better cascade function. In this way, the use of this shift register unit can drive pixels to emit light reliably, avoid poor display on the display panel, and ensure a better display effect.

[0093] Optionally, Figure 2 Schematic diagram of another shift register unit provided in an embodiment of the present application. Figure 2 As shown, the pull-up node PU may include: a first pull-up node PU1 and a second pull-up node PU2; the first control circuit 01, the second control circuit 02, and the third control circuit 03 may all be connected to the first pull-up node PU1; the output circuit 04 may be connected to the second pull-up node PU2; and the shift register unit may further include: a fourth control circuit 05.

[0094] The fourth control circuit 05 can be connected to the second power supply terminal VGH_G, the first pull-up node PU1 and the second pull-up node PU2 respectively. The fourth control circuit 05 can be used to control the on and off of the first pull-up node PU1 and the second pull-up node PU2 in response to the second power signal provided by the second power supply terminal VGH_G.

[0095] For example, the fourth control circuit 05 can control the first pull-up node PU1 and the second pull-up node PU2 to be turned on when the potential of the second power signal provided by the second power terminal VGH_G is the first potential, so that the signal transmitted to the first pull-up node PU1 can be further transmitted to the second pull-up node PU2.

[0096] It can be understood that by setting up the fourth control circuit 05, the purpose of isolating the first pull-up node PU1 and the second pull-up node PU2 can be achieved, avoiding the problem of unstable potential of the first pull-up node PU1 caused by the voltage backflow of the output circuit 04, and protecting the transistor that controls the potential of the first pull-up node PU1, thereby also ensuring better output stability of the shift register unit.

[0097] And / or, continue to refer to Figure 2 It can be seen that, in some embodiments, the shift register unit may further include: a first reset circuit 06 , a second reset circuit 07 , a first storage circuit 08 and a second storage circuit 09 .

[0098] The first reset circuit 06 can be connected to the reset control terminal RESET, the first power terminal VGL_G and the first pull-up node PU1 respectively. The first reset circuit 06 can be used to control the connection between the first power terminal VGL_G and the first pull-up node PU1 in response to a reset control signal provided by the reset control terminal RESET.

[0099] For example, when the potential of the reset control signal provided by the reset control terminal RESET is a first potential, the first reset circuit 06 can control the first power supply terminal VGL_G to be conductive with the first pull-up node PU1, so that the first power signal provided by the first power supply terminal VGL_G can be transmitted to the first pull-up node PU1. Furthermore, when the potential of the reset control signal provided by the reset control terminal RESET is a second potential, the first reset circuit 06 can control the first power supply terminal VGL_G to be disconnected from the first pull-up node PU1. In other words, the first reset circuit 06 can control the potential of the first pull-up node PU1 to reset the first pull-up node PU1. In this way, signal noise can be reduced and the accuracy of the output signal of the shift register unit can be improved.

[0100] The second reset circuit 07 can be connected to the touch enable terminal EN_TOUCH, the first power terminal VGL_G and the driver output terminal OUT respectively. The second reset circuit 07 can be used to control the connection and disconnection of the first power terminal VGL_G and the driver output terminal OUT in response to the touch enable signal provided by the touch enable terminal EN_TOUCH.

[0101] For example, when the potential of the touch enable signal provided by the touch enable terminal EN_TOUCH is a first potential, the second reset circuit 07 can control the first power supply terminal VGL_G to be connected to the drive output terminal OUT, so that the first power supply signal provided by the first power supply terminal VGL_G can be transmitted to the drive output terminal OUT, and when the potential of the touch enable signal provided by the touch enable terminal EN_TOUCH is a second potential, the first power supply terminal VGL_G can be disconnected from the drive output terminal OUT. In other words, the second reset circuit 07 can output a signal through the drive output terminal OUT, which here refers to a reset signal, to reset the signal output through the drive output terminal OUT. In this way, signal noise can also be reduced and the accuracy of the output signal of the shift register unit can be improved. The second reset circuit 07 mainly realizes the reset of the output signal of the drive output terminal OUT during the touch process, that is, the shift register unit can also support touch function to meet various user needs.

[0102] The first storage circuit 08 may be connected between the second pull-up node PU2 and the driving output terminal OUT. The first storage circuit 08 may be used to control the potential of the second pull-up node PU2.

[0103] For example, the first storage circuit 08 can control the potential of the second pull-up node PU2 through coupling to stabilize the potential of the second pull-up node PU2, thereby achieving the purpose of storing the node potential.

[0104] The second storage circuit 09 may be connected between the pull-down node PD and the first power supply terminal VGL_G and may be used to control the potential of the pull-down node PD.

[0105] For example, the second storage circuit 09 can control the potential of the pull-down node PD through coupling to stabilize the potential of the pull-down node PD, thereby achieving the purpose of storing the node potential.

[0106] Optionally, Figure 3 This is a structural diagram of another shift register unit provided in an embodiment of the present application. Figure 3 As shown, the output circuit 04 may include: a first output sub-circuit 041 and a second output sub-circuit 042 .

[0107] The first output sub-circuit 041 can be connected to the pull-up node PU, the pull-down node PD, the third clock terminal CK3, the first power supply terminal VGL_G and the driving output terminal OUT respectively. The first output sub-circuit 041 can be used to control the connection and disconnection between the third clock terminal CK3 and the driving output terminal OUT in response to the potential of the pull-up node PU, and control the connection and disconnection between the first power supply terminal VGL_G and the driving output terminal OUT in response to the potential of the pull-down node PD. Optionally, based on the division of the pull-up node PU into the first pull-up node PU1 and the second pull-up node PU2, as shown in FIG. Figure 3 As shown, the first output sub-circuit 041 may be connected to the second pull-up node PU2.

[0108] For example, when the potential of the second pull-up node PU2 is at a first potential, the first output sub-circuit 041 can control the third clock terminal CK3 to be conductively connected to the driving output terminal OUT, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the driving output terminal OUT. Furthermore, when the potential of the second pull-up node PU2 is at a second potential, the first output sub-circuit 041 can control the third clock terminal CK3 to be disconnected from the driving output terminal OUT. Similarly, when the potential of the pull-down node PD is at a first potential, the first output sub-circuit 041 can control the first power supply terminal VGL_G to be conductively connected to the driving output terminal OUT, so that the first power supply signal provided by the first power supply terminal VGL_G can be transmitted to the driving output terminal OUT. Furthermore, when the potential of the pull-down node PD is at a second potential, the first output sub-circuit 041 can control the first power supply terminal VGL_G to be disconnected from the driving output terminal OUT. In other words, the first output sub-circuit 041 can output a driving signal to the pixel via the driving output terminal OUT to drive the pixel to emit light.

[0109] The second output sub-circuit 042 can be connected to the pull-up node PU, the pull-down node PD, the third clock terminal CK3, the first power supply terminal VGL_G and the shift output terminal CR respectively. The second output sub-circuit 042 can be used to control the connection and disconnection between the third clock terminal CK3 and the shift output terminal CR in response to the potential of the pull-up node PU, and control the connection and disconnection between the first power supply terminal VGL_G and the shift output terminal CR in response to the potential of the pull-down node PD. Optionally, based on the division of the pull-up node PU into the first pull-up node PU1 and the second pull-up node PU2, as shown in FIG. Figure 3 As shown, the second output sub-circuit 042 may also be connected to the second pull-up node PU2.

[0110] For example, when the potential of the second pull-up node PU2 is at a first potential, the second output sub-circuit 042 can control the third clock terminal CK3 to be conductively connected to the shift output terminal CR, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the shift output terminal CR. Furthermore, when the potential of the second pull-up node PU2 is at a second potential, the second output sub-circuit 042 can control the third clock terminal CK3 to be conductively connected to the shift output terminal CR, so that the first power signal provided by the first power terminal VGL_G can be transmitted to the shift output terminal CR. Furthermore, when the potential of the pull-down node PD is at a first potential, the second output sub-circuit 042 can control the first power terminal VGL_G to be conductively connected to the shift output terminal CR, so that the first power signal provided by the first power terminal VGL_G can be transmitted to the shift output terminal CR. Furthermore, when the potential of the pull-down node PD is at a second potential, the second output sub-circuit 042 can control the first power terminal VGL_G to be conductively connected to the shift output terminal CR, so that the first power signal provided by the first power terminal VGL_G can be transmitted to the shift output terminal CR. Furthermore, when the potential of the pull-down node PD is at a second potential, the second output sub-circuit 042 can control the first power terminal VGL_G to be disconnected from the shift output terminal CR. In other words, the second output sub-circuit 042 can output a cascade signal to other stages of the cascaded shift register units via the shift output terminal CR to drive the other stages of the shift register units to operate. In this way, by arranging different output sub-circuits to independently output the driving signal and the cascade signal via different output terminals, the cascade function and the driving function can be reliably and independently executed.

[0111] Optionally, continue to refer to Figure 3 It can be seen that the third control circuit 03 may include: a first control sub-circuit 031 and a second control sub-circuit 032 .

[0112] The first control sub-circuit 031 can be connected to the pull-up node PU, the first power supply terminal VGL_G and the pull-down node PD respectively. The first control sub-circuit 031 can be used to control the connection and disconnection of the first power supply terminal VGL_G and the pull-down node PD in response to the potential of the pull-up node PU. Optionally, based on the division of the pull-up node PU into the first pull-up node PU1 and the second pull-up node PU2, as shown in FIG. Figure 3 As shown, the first control sub-circuit 031 may be connected to the first pull-up node PU1.

[0113] For example, when the potential of the first pull-up node PU is a first potential, the first control sub-circuit 031 can control the first power terminal VGL_G to be conductive with the pull-down node PD, so that the first power signal provided by the first power terminal VGL_G can be transmitted to the pull-down node PD. Furthermore, when the potential of the first pull-up node PU is a second potential, the first control sub-circuit 031 can control the first power terminal VGL_G to be disconnected from the pull-down node PD. In other words, the potential of the pull-down node PD can be controlled by the first control sub-circuit 031 based on the potential of the first pull-up node PU.

[0114] The second control subcircuit 032 can be connected to the middle node P0, the second power supply terminal VGH_G and the pull-down node PD respectively. The second control subcircuit 032 can be used to control the connection between the second power supply terminal VGH_G and the pull-down node PD in response to the potential of the middle node P0.

[0115] For example, when the potential of the intermediate node P0 is at a first potential, the second control sub-circuit 032 can control the second power supply terminal VGH_G to be conductive with the pull-down node PD, so that the second power supply signal provided by the second power supply terminal VGH_G can be transmitted to the pull-down node PD. Furthermore, when the potential of the intermediate node P0 is at a second potential, the second control sub-circuit 032 can control the second power supply terminal VGH_G to be disconnected from the pull-down node PD. In other words, the potential of the pull-down node PD can be controlled by the second control sub-circuit 032 based on the potential of the intermediate node P0.

[0116] It can be understood that since the potential of the first power signal provided by the first power terminal VGL_G is a low potential and the potential of the second power signal provided by the second power terminal VGH_G is a high potential, the first control sub-circuit 031 and the second control sub-circuit 032 are set to respectively respond to the potential of the pull-up node PU to control the low-potential first power signal to be written into the pull-down node PD, and respond to the potential of the intermediate node PU to control the high-potential second power signal to be written into the pull-down node PD. This can avoid being affected by the clock signal and pulling up the potential of the pull-down node PD of other stages of the shift register unit in the cascade when the current stage shift register unit outputs the driving signal, and avoid forming a competitive relationship between the transistor that controls the potential of the pull-down node PD based on the potential of the pull-up node PU (i.e., the transistor included in the first control sub-circuit 031) and the transistor that controls the potential of the pull-up node PU based on the potential of the pull-down node PD (i.e., the transistor included in the first control circuit 01), thereby achieving the purpose of optimizing the potential of the pull-up node PU and the potential of the pull-down node PU.

[0117] Optionally, Figure 4 Schematic diagram of the circuit structure of a shift register unit provided in an embodiment of the present application. Figure 4 As shown, the first output sub-circuit 041 may include: a first transistor T1 and a second transistor T2. The second output sub-circuit 042 may include: a third transistor T3 and a fourth transistor T4.

[0118] The gate of the first transistor T1 can be connected to the pull-up node PU, the first electrode of the first transistor T1 can be connected to the third clock terminal CK3, and the second electrode of the first transistor T1 can be connected to the driving output terminal OUT. Optionally, as described above, the gate of the first transistor T1 can be connected to the second pull-up node PU2 included in the pull-up node PU.

[0119] A gate of the second transistor T2 may be connected to the pull-down node PD, a first electrode of the second transistor T2 may be connected to the first power supply terminal VGL_G, and a second electrode of the second transistor T2 may be connected to the driving output terminal OUT.

[0120] The gate of the third transistor T3 can be connected to the pull-up node PU, the first electrode of the third transistor T3 can be connected to the third clock terminal CK3, and the second electrode of the third transistor T3 can be connected to the shift output terminal CR. Optionally, as described above, the gate of the third transistor T3 can be connected to the second pull-up node PU2 included in the pull-up node PU.

[0121] A gate of the fourth transistor T4 may be connected to the pull-down node PD, a first electrode of the fourth transistor T4 may be connected to the first power supply terminal VGL_G, and a second electrode of the fourth transistor T4 may be connected to the shift output terminal CR.

[0122] Optionally, the channel width-to-length ratio of the third transistor T3 may be different from the channel width-to-length ratio of the first transistor T1 , and / or the channel width-to-length ratio of the fourth transistor T4 may be different from the channel width-to-length ratio of the second transistor T2 .

[0123] Optionally, the ratio of the channel width-to-length ratio of the third transistor T3 to the channel width-to-length ratio of the first transistor T1 can be greater than 80%. The ratio of the channel width-to-length ratio of the fourth transistor T4 to the channel width-to-length ratio of the second transistor T2 can be greater than 80%. For example, the channel width-to-length ratio of the first transistor T1 can be maintained at or above 20, and the channel width-to-length ratio of the third transistor T3 can be greater than 80% of the channel width-to-length ratio of the first transistor T1. In this way, the shift register unit can have good driving capability and cascading capability.

[0124] Optionally, continue to refer to Figure 4 It can be seen that the first control sub-circuit 031 may include: a fifth transistor T5. The second control sub-circuit 032 may include: a sixth transistor T6.

[0125] The gate of the fifth transistor T5 can be connected to the pull-up node PU, the first electrode of the fifth transistor T5 can be connected to the first power supply terminal VGL_G, and the second electrode of the fifth transistor T5 can be connected to the pull-down node PD. Optionally, as described above, the gate of the fifth transistor T5 can be connected to the first pull-up node PU1 included in the pull-up node PU.

[0126] A gate of the sixth transistor T6 may be connected to the middle node P0 , a first electrode of the sixth transistor T6 may be connected to the second power supply terminal VGH_G, and a second electrode of the sixth transistor T6 may be connected to the pull-down node PD.

[0127] Optionally, continue to refer to Figure 4 It can be seen that the second control circuit 02 may include: a seventh transistor T7 and an eighth transistor T8.

[0128] A gate of the seventh transistor T7 may be connected to the first control terminal CN, a first electrode of the seventh transistor T7 may be connected to the first clock terminal CK1 , and a second electrode of the seventh transistor T7 may be connected to the middle node P0 .

[0129] A gate of the eighth transistor T8 may be connected to the second control terminal CNB, a first electrode of the eighth transistor T8 may be connected to the second clock terminal CK2 , and a second electrode of the eighth transistor T8 may be connected to the middle node P0 .

[0130] Optionally, continue to refer to Figure 4 It can be seen that the first control circuit 01 may include: a ninth transistor T9 , a tenth transistor T10 , and an eleventh transistor T11 .

[0131] The gate of the ninth transistor T9 can be connected to the first input terminal CAS1, the first electrode of the ninth transistor T9 can be connected to the first control terminal CN, and the second electrode of the ninth transistor T9 can be connected to the pull-up node PU. Optionally, as described above, the second electrode of the ninth transistor T9 can be connected to the first pull-up node PU1 included in the pull-up node PU.

[0132] The gate of the tenth transistor T10 can be connected to the second input terminal CAS2, the first electrode of the tenth transistor T10 can be connected to the second control terminal CNB, and the second electrode of the tenth transistor T10 can be connected to the pull-up node PU. Optionally, as described above, the second electrode of the tenth transistor T10 can be connected to the first pull-up node PU1 included in the pull-up node PU.

[0133] The gate of the eleventh transistor T11 may be connected to the pull-down node PD, the first electrode of the eleventh transistor T11 may be connected to the first power supply terminal VGL_G, and the second electrode of the eleventh transistor T11 may be connected to the pull-up node PU. Optionally, as described above, the second electrode of the eleventh transistor T11 may be connected to the first pull-up node PU1 included in the pull-up node PU.

[0134] Optionally, the fourth control circuit 05 may include a twelfth transistor T12. The first reset circuit 06 may include a thirteenth transistor T13. The second reset circuit 07 may include a fourteenth transistor T14. The first storage circuit 08 may include a first capacitor C1. The second storage circuit 09 may include a second capacitor C2.

[0135] A gate of the twelfth transistor T12 may be connected to the second power supply terminal VGH_G, a first electrode of the twelfth transistor T12 may be connected to the first pull-up node PU1 , and a first electrode of the twelfth transistor T12 may be connected to the second pull-up node PU2 .

[0136] A gate of the thirteenth transistor T13 may be connected to the reset control terminal RESET, a first electrode of the thirteenth transistor T13 may be connected to the first power supply terminal VGL_G, and a second electrode of the thirteenth transistor T13 may be connected to the first pull-up node PU1.

[0137] A gate of the fourteenth transistor T14 may be connected to the touch enable terminal EN_TOUCH, a first electrode of the fourteenth transistor T14 may be connected to the first power supply terminal VGL_G, and a second electrode of the fourteenth transistor T14 may be connected to the driving output terminal OUT.

[0138] One end of the first capacitor C1 may be connected to the driving output terminal OUT, and the other end of the first capacitor C1 may be connected to the second pull-up node PU2 .

[0139] One end of the second capacitor C2 may be connected to the first power supply terminal VGL_G, and the other end of the first capacitor C1 may be connected to the pull-down node PD.

[0140] It is understandable that Figure 4 The shift register unit shown may include 14 transistors and 2 capacitors. Each transistor may be an N-type transistor, such as an NMOS transistor. In addition, the material of the NMOS transistor may be a low-temperature polycrystalline silicon (LTPS) material. Accordingly, Figure 4 The shift register unit shown can also be called a new type of 14T2C NMOS type LTPS GOA unit. Of course, the shift register unit is not limited to this structure. Figure 4 The circuit structure shown in FIG. 1 is a schematic diagram of the shift register unit according to an embodiment of the present invention.

[0141] First, on the basis of setting the first transistor T1 and the second transistor T2 to be connected to the driving output terminal OUT so as to output the driving signal to the pixel through the driving output terminal OUT to realize the driving function, a third transistor T3 and a fourth transistor T4 are added to be connected to the shift output terminal CR so as to output the cascade signal to the cascaded shift register unit through the shift output terminal CR different from the driving output terminal OUT to realize the cascade function. That is, the driving function and the cascade function are performed separately. In this way, compared with the embodiment in which the driving signal and the cascade signal are simultaneously output through the same output terminal, the load (loading) connected to the driving output terminal OUT and the shift output terminal CR can be reduced, thereby effectively improving the display defects such as the abnormal display of the screen or the abnormal display of the split screen caused by the large loading, and ensuring that the display effect of the display device can be better.

[0142] Secondly, in some embodiments, the sixth transistor T6 is absent, and both the gate and the first electrode of the seventh transistor T7 are connected to the third clock terminal CK3. On this basis, when the current-stage shift register unit outputs a high-potential signal via the output terminal, that is, when the potential of the third clock signal provided by the third clock terminal CK3 is high, the seventh transistor T7 in the cascaded shift register unit is turned on, pulling up the potential of the pull-down node PD. At the same time, the high-potential signal output by the current-stage shift register unit also turns on the ninth transistor T9 in the cascaded shift register unit, pulling up the potential of the first pull-up node PU1, thereby forming a DC path between the transistor that pulls down the potential of the first pull-up node PU1 and the transistor that pulls down the potential of the pull-down node PD, resulting in a competitive relationship between the potential of the first pull-up node PU1 and the potential of the pull-down node PD. This results in a poor output capability of the shift register unit. In the embodiment of the present application, by adding a sixth transistor T6, connecting the gate of the seventh transistor T7 to the first control terminal CN, and simultaneously connecting the eighth transistor T8 to the second control terminal CNB, it is possible to support both forward and reverse scanning functions while avoiding the aforementioned competitive relationship and optimizing the mutual control capability between the first pull-up node PU1 and the pull-down node PD. This ensures greater potential stability of the first pull-up node PU1 and the pull-down node PD, and enhances the output capability of the shift register unit. Furthermore, signal loss caused by the DC path is avoided, the operating power consumption of the shift register unit is reduced, and the aging resistance of the shift register unit is enhanced.

[0143] In some embodiments, when the output capacity of the shift register unit is poor due to the formation of a DC path, the output capacity of the shift register unit can be improved by setting the transistor's channel width-to-length ratio to be larger, as described above. However, this configuration not only increases the operating power consumption of the shift register unit but also hinders the design of a narrow frame. However, the embodiments of the present application avoid the formation of this DC path through the circuit structure and connection relationship, allowing the transistor's channel width-to-length ratio to be flexibly designed according to actual product requirements. This not only reduces the operating power consumption of the shift register unit but also reduces the frame, facilitating a narrow frame design.

[0144] Taking the cascade connection of two adjacent shift register units as an example, Figure 4 On the basis of Figure 5 A schematic diagram of the structure of multiple cascaded shift register units is shown. The multiple cascaded shift register units include an Nth stage shift register unit GOA_N, an N+1th stage shift register unit GOA_N+1, an N+2th stage shift register unit GOA_N+2, and an N+3th stage shift register unit GOA_N+3. Where N can be an integer greater than 1. Figure 4 The shift register unit shown may be an N-th stage shift register unit.

[0145] Combine Figure 4 and Figure 5 It can be seen that the shift output terminal CR_N of the N-th level shift register unit can be connected to the first input terminal CAS1_N+1 of the N+1-th level shift register unit, the shift output terminal CR_N+1 of the N+1-th level shift register unit can be respectively connected to the second input terminal CAS2_N of the N-th level shift register unit and the first input terminal CAS1_N+2 of the N+2-th level shift register unit, the shift output terminal CR_N+2 of the N+2-th level shift register unit can be respectively connected to the second input terminal CAS2_N+1 of the N+1-th level shift register unit and the first input terminal CAS1_N+3 of the N+3-th level shift register unit, and the shift output terminal CR_N+3 of the N+3-th level shift register unit can be connected to the second input terminal CAS2_N+2 of the N+2-th level shift register unit. Accordingly, it can be seen that the first input terminal CAS1_N of the Nth stage shift register unit can be connected to the shift output terminal CR_N-1 of the N-1th stage shift register unit; the second input terminal CAS2_N+3 of the N+3th stage shift register unit can be connected to the shift output terminal CR_N+4 of the N+4th stage shift register unit. The cascade connection method of the other stages of shift register units is similar and will not be repeated here.

[0146] also, Figure 5 The multiple shift register units shown share four clock terminals CLK1 to CLK4, which is a shift register unit using a 4-phase clock. Of course, it is not limited to using a 4-phase clock. For example, an 8-phase clock can be used, sharing eight clock terminals CLK1 to CLK8.

[0147] The first clock terminal CK1 connected to the Nth stage shift register unit is CLK2, the second clock terminal CK2 is CLK4, and the third clock terminal CK3 is CLK1. The first clock terminal CK1 connected to the N+1th stage shift register unit is CLK3, the second clock terminal CK2 is CLK1, and the third clock terminal CK3 is CLK2. The first clock terminal CK1 connected to the N+2th stage shift register unit is CLK4, the second clock terminal CK2 is CLK2, and the third clock terminal CK3 is CLK3. The first clock terminal CK1 connected to the N+3th stage shift register unit is CLK1, the second clock terminal CK2 is CLK3, and the third clock terminal CK3 is CLK4.

[0148] Optionally, in Figure 4 On the basis of Figure 6 A schematic diagram of the layout of a shift register unit is shown. Figure 5 On the basis of Figure 7 A schematic diagram of the layout of another shift register unit is shown.

[0149] Combine Figure 6 and Figure 7 It can be seen that the first control circuit 01 (including the ninth transistor T9 and the tenth transistor T10), the third control circuit 03 (including the fifth transistor T5 and the sixth transistor T6), the output circuit 04 (including the first transistor T1 to the fourth transistor T4) and the second control circuit 02 (including the seventh transistor T7 and the eighth transistor T8) can be arranged in sequence along the first direction X1 and in the direction close to the drive output terminal OUT. In addition, the third transistor T3 and the first transistor T1 in the output circuit 04 can be arranged in sequence along the second direction X2, and the fourth transistor T4 and the second transistor T2 can be arranged in sequence along the first direction X1. Among them, the first direction X1 intersects with the second direction X2. For example, the first direction X1 can be the pixel row direction. The second direction X2 can be the pixel column direction, and the first direction X1 and the second direction X2 can be perpendicular to each other. In addition, with reference to Figure 6 It can also be seen that from the end farthest from the driver output terminal OUT to the end close to the driver output terminal OUT, that is, from left to right:

[0150] First, the ninth transistor T9 and the tenth transistor T10 included in the first control circuit 01 may be located at the leftmost side and arranged along the second direction X2.

[0151] Next, the second power supply terminal VGH_G, the reset control terminal RESET, and the first power supply terminal VGL_G may be arranged in a spaced relationship along the first direction X1 and in a direction close to the driving output terminal OUT. Furthermore, the thirteenth transistor T13 included in the first reset circuit 06 may be located between the second power supply terminal VGH_G and the reset control terminal RESET to be reliably connected to the second power supply terminal VGH_G and the reset control terminal RESET, respectively.

[0152] Next, the twelfth transistor T12 included in the fourth control circuit 05 and the fifth transistor T5 included in the third control circuit 03 can be located on the side of the second power supply terminal VGH_G close to the driving output terminal OUT and arranged in sequence along the second direction X2, and the twelfth transistor T12 establishes a connection between the first pull-up node PU1 and the second pull-up node PU2.

[0153] Next, the eleventh transistor T11 included in the first control circuit 01, the fourth transistor T4 and the second transistor T2 included in the output circuit 04 can be located on the side of the fifth transistor T5 close to the drive output terminal OUT and arranged sequentially in the first direction X1. The sixth transistor T6 included in the third control circuit 03 and the second capacitor C2 included in the second storage circuit 09 can be located on the upper and lower sides of the second transistor T2, respectively. That is, the sixth transistor T6, the second transistor T2 and the second capacitor C2 can be arranged sequentially along the second direction X2. In addition, the second capacitor C2 can extend along the first direction X1.

[0154] Next, the first capacitor C1 included in the first storage circuit 08 can be located on a side of the second transistor T2 close to the driving output terminal OUT, and the first capacitor C1 can extend along the second direction X2. The third transistor T3 and the first transistor T1 included in the output circuit 04 can be located on a side of the first capacitor C1 close to the driving output terminal OUT and can be arranged sequentially along the second direction X2.

[0155] Finally, the eighth transistor T8 and the seventh transistor T7 included in the second control circuit O2 can be located on a side of the third transistor T3 close to the drive output terminal OUT and can be arranged sequentially along the second direction X2. The second control terminal CNB, the first control terminal CN, multiple clock terminals (e.g., eight clock terminals CLK1 to CLK8), and the touch enable terminal EN_TOUCH can be arranged sequentially in a direction away from the eighth transistor T8 and along the first direction X1.

[0156] It is understandable that the layout of the embodiment of the present application can also make full use of the space to reasonably arrange the components, thereby facilitating the design of a narrow frame. Figure 6 It can also be seen that the ninth transistor T9 and the tenth transistor T10 can be arranged symmetrically and can be the same size. The seventh transistor T7 and the eighth transistor T8 can be arranged symmetrically and can be the same size. The size of the fifth transistor T5 can be larger than the sixth transistor T6, and the sizes of the eleventh transistor T11 to the thirteenth transistor T13. The size of the fourth transistor T4 can be smaller than the size of the second transistor T2, and the size of the first transistor T1 can be equal to the size of the third transistor T3. The size here can refer to the area of ​​the orthographic projection on the substrate. This can also facilitate layout and facilitate the design of a narrow frame.

[0157] Optionally, in the film layer structure, the shift register unit may include an active layer, an insulating layer, a gate metal layer, and a source / drain metal layer stacked in sequence. In some embodiments, adjacent transistors may share some film layers to simplify the structure and save costs.

[0158] In summary, an embodiment of the present application provides a shift register unit. The shift register unit includes: a first control circuit, a second control circuit, a third control circuit, and an output circuit. With the mutual cooperation of the first control circuit to the third control circuit, the potential stability of the pull-up node and the pull-down node can be ensured by flexibly setting the clock signal provided by the clock terminal, thereby ensuring that the output capacity of the shift register unit is good. In addition, on the basis of the output circuit responding to the potential of the pull-up node and the potential of the pull-down node, outputting cascade signals to other stages of shift register units and outputting drive signals to pixels through different output terminals respectively, the load connected to the cascade output terminal can be reduced, thereby avoiding the cascade function being affected by the load and ensuring a better cascade function. In this way, the use of this shift register unit can drive pixels to emit light reliably, avoid poor display on the display panel, and ensure a better display effect.

[0159] The embodiment of the present application also provides a driving method of a shift register unit. Figure 8 As shown, the method includes:

[0160] Step 801, in the first stage, the first control circuit controls the first control terminal to be connected to the pull-up node in response to the first input signal provided by the first input terminal; the second control circuit controls the first clock terminal to be connected to the intermediate node in response to the first control signal provided by the first control terminal; the third control circuit controls the first power supply terminal to be connected to the pull-down node in response to the potential of the pull-up node; the output circuit controls the third clock terminal to be connected to both the shift output terminal and the drive output terminal in response to the potential of the pull-up node.

[0161] Step 802, second stage, the first control circuit controls the first control terminal to be connected to the pull-up node in response to the first input signal; the second control circuit controls the first clock terminal to be connected to the intermediate node in response to the first control signal; the third control circuit controls the second power supply terminal to be connected to the pull-down node in response to the potential of the intermediate node; the output circuit controls the first power supply terminal to be connected to both the shift output terminal and the drive output terminal in response to the potential of the pull-down node.

[0162] Optionally, Figure 5 In the structure shown, the transistors included in the shift register unit are all N-type transistors, and accordingly, the first potential is a high potential, the second potential is a low potential, and Figure 4 The shift register unit shown is the Nth stage shift register unit. The Nth stage shift register unit and the N+1th stage shift register unit are cascaded as an example. Figure 9 , the driving method of the shift register unit is described as follows:

[0163] In stage t0, the potential of the cascade signal output by the N-1th stage shift register unit via the cascade output terminal CR_N-1 is a high potential, that is, the potential of the first input signal provided by the first input terminal CAS1_N can be a high potential. For the first-stage shift register unit where N is 1, the cascade output terminal CR_N-1 can be replaced by the start signal terminal STV. That is, the potential of the start signal provided by the start signal terminal STV can be a high potential, and accordingly, for the Nth stage shift register unit, the ninth transistor T9 can be turned on. At this time, the potential of the first control signal provided by the first control terminal CN can be a high potential. In this way, the high-potential first control signal can be transmitted to the first pull-up node PU1 via the turned-on ninth transistor T9, thereby pulling up the potential of the first pull-up node PU1. Furthermore, because the potential of the second power supply signal provided by the second power supply terminal VGH_G is high, the twelfth transistor T12 can be turned on, thereby enabling the high-potential first control signal transmitted to the first pull-up node PU1 to be further transmitted to the second pull-up node PU2, causing the first capacitor C1 to begin charging and enabling both the first transistor T1 and the third transistor T3 to be turned on. Furthermore, the third clock signal provided by the third clock terminal CK3 (e.g., CLK1) can be transmitted to the driver output terminal OUT via the enabled first transistor T1, and to the shift output terminal CR via the enabled third transistor T3. Since the potential of the third clock signal can be low at this time, the potentials of the drive signal output via the driver output terminal OUT and the cascade signal output via the shift output terminal CR can both be low.

[0164] In stage t1, since the potential of the third clock signal provided by the third clock terminal CK3 (i.e., CLK1) is a high potential for the N-th stage shift register unit, the potential of the drive signal output through the drive output terminal OUT and the potential of the cascade signal output through the shift output terminal CR can both be high potentials, that is, the drive signal of this row can be pulled up, and the connected pixels can be charged, and a high potential signal can be output to the first input terminal CAS1 of the N+1-th stage shift register unit, turning on the ninth transistor T9 in the N+1-th stage shift register unit, so that the first capacitor C1 in the N+1-th stage shift register unit starts to charge and the first transistor T1 and the third transistor T3 in the N+1-th stage shift register unit are both turned on. Since the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CLK3) is low for the N+1-stage shift register unit, even if the seventh transistor T7 in the N+1-stage shift register unit is turned on in response to the high-potential first control signal, the twelfth transistor T12 in the N+1-stage shift register unit can be turned off, thereby preventing the high-potential second power supply signal provided by the second power supply terminal VGH_G from being transmitted to the pull-down node PD of the N+1-stage shift register unit. That is, the potential of the pull-down node PD of the N+1-stage shift register unit can be maintained at a low potential. Figure 10 Compared with the timing diagram of the shift register unit without the sixth transistor T6, it can be seen that the potential of the pull-down node PD of the N+1th stage shift register unit will not jump abnormally, thereby achieving the purpose of improving the DC path.

[0165] It is understandable that Figure 10 In a shift register unit in which the sixth transistor T6 is not provided, when the Nth-stage shift register unit outputs a high-potential cascade signal via the shift output terminal CR, causing the ninth transistor T9 of the N+1th-stage shift register unit to turn on and pull up the potential of the first pull-up node PU1, the potential of the first clock signal received by the N+1th-stage shift register unit is pulled up, which in turn causes the pull-down node PD of the N+1th-stage shift register unit to be abnormally raised, thereby reducing the output capability of the shift register unit. In the embodiment of the present application, by adding the sixth transistor T6, abnormal potential jumps of the pull-down node PD of the N+1th-stage shift register unit can be avoided, thereby ensuring better output capability of the shift register unit.

[0166] In stage t2, stage t3 and stage t4, the potential of the third clock signal provided by the third clock terminal CK3 (e.g., CLK2) connected to the N+1-th level shift register unit, the potential of the third clock signal provided by the third clock terminal CK3 (e.g., CLK3) connected to the N+2-th level shift register unit, and the potential of the third clock signal provided by the third clock terminal CK3 (e.g., CLK4) connected to the N+3-th level shift register unit can be high potentials in sequence, so that the N+1-th level shift register unit to the N+3-th level shift register unit can output high-potential driving signals through the driving output terminal OUT in sequence, and output high-potential cascade signal potentials through the shift output terminal CR, thereby realizing cascade driving and ensuring normal display.

[0167] in, Figure 9 The driving output terminals OUT of the Nth to N+3th shift register units are respectively labeled OUT_N, OUT_N+1, OUT_N+2 and OUT_N+3, and the pull-up node PU and the pull-down node PD of the N+1th shift register unit are respectively labeled PU_N+1 and PD_N+1.

[0168] Optionally, based on the embodiment of cascading two adjacent shift register units, taking the example of a shift register unit outputting a cascade signal and a driving signal simultaneously through one output terminal, Figure 11 Schematic diagram showing the signal out outputted by 8 cascaded shift register units via the output terminal OUT <1> to out <8> , and the potential pu of the pull-up node PU of the 8 cascaded shift register units <1> To pu <8> And, taking the shift register unit outputting the cascade signal and the drive signal through the cascade output terminal CR and the drive output terminal OUT as an example, Figure 12 Schematic diagram showing the signal out outputted by 8 cascaded shift register units via the output terminal OUT <1> to out <8> , and the potential pu of the pull-up node PU of the 8 cascaded shift register units <1> To pu <8> Timing simulation diagram.

[0169] contrast Figure 11 and Figure 12It can be seen that in the embodiment of simultaneously outputting the cascade signal and the drive signal through one output terminal, although the first-stage shift register unit can normally output the drive signal through the output terminal OUT, the cascade signal output through the output terminal is abnormal due to the influence of the large cascade load, resulting in the inability to fully pull up the potential of the pull-up node PU of the second-stage shift register unit of the cascade (i.e., too low), thereby causing the potential of the signal output by the next-stage shift register unit of the cascade through the output terminal OUT to be too low, and the signals output by the third to eighth-stage shift register units through the output terminal OUT continue to attenuate. Among them, by the third-stage shift register unit, since the potential of its pull-up node PU can no longer be pulled up, starting from the third-stage shift register unit, the cascade function has actually been lost, causing the display device to be unable to display normally. In the embodiment of the present application, the cascade output terminal CR and the drive output terminal OUT are distinguished to output the cascade signal and the drive signal respectively, so the cascade capability can be improved. Even if the potential of the pull-up node PU of the second-stage shift register unit is slightly attenuated, the potential of the pull-up node PU of each stage of the shift register unit can be ensured to be relatively stable, so that each stage of the shift register unit can output normally, and thus the display device can display normally without being affected by the deterioration of loading or the deterioration of transistor characteristics and causing abnormal display.

[0170] It is understandable that, since the driving method of the shift register unit has substantially the same technical effects as the shift register unit described in the previous embodiment, the technical effects of the driving method will not be repeatedly described here for the purpose of brevity.

[0171] The embodiment of the present application provides a gate drive circuit. Figure 13 As shown, the gate drive circuit includes: a plurality of cascaded Figures 1 to 4 Any of the shift register cells GOA shown.

[0172] The shift output terminal CR of each shift register unit GOA can be connected to the second input terminal CAS2 of the cascaded previous shift register unit GOA, and the driving output terminal of each shift register unit GOA is connected to the first input terminal CAS1 of the cascaded subsequent shift register unit GOA. Figure 5 The contents described in the above embodiments will not be repeated here.

[0173] For example, Figure 13The Nth and N+3th shift register units GOA_N to GOA_N+3 are schematically shown, and the driving output terminals OUT of the Nth shift register unit GOA_N to the N+3th shift register unit GOA_N+3 are respectively identified as OUT_N to OUT_N+3, and the cascade output terminals CR of the Nth shift register unit GOA_N to the N+3th shift register unit GOA_N+3 are respectively identified as CR_N to CR_N+3.

[0174] It is understandable that since the gate driving circuit has substantially the same technical effects as the shift register unit described in the previous embodiment, the technical effects of the gate driving circuit will not be repeatedly described here for the purpose of brevity.

[0175] The embodiment of the present application provides a display device. Figure 14 As shown, the display device includes: a display panel 100, and Figure 13 The gate driving circuit 000 is shown.

[0176] The display panel 000 includes a plurality of pixels ( Figure 14 Not shown). Figure 13 The gate drive circuit 100 is connected to a plurality of pixels via a drive output terminal OUT and is used to transmit a gate drive signal GATE to the plurality of pixels to drive the plurality of pixels to emit light. Of course, the gate drive circuit 100 is not limited to outputting a gate drive signal. For example, a light emission control signal EM can also be output to drive the plurality of pixels to emit light.

[0177] It is understandable that since the display device has substantially the same technical effects as the shift register unit described in the previous embodiment, the technical effects of the display device will not be repeatedly described herein for the purpose of brevity.

[0178] Optionally, the display device described in the embodiments of the present application may be any product or component with a display function, such as an organic light-emitting diode (OLED) display device or a liquid crystal display (LCD). Furthermore, the display device may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation systems, and e-books, and any other product or component with a display function.

[0179] It should be noted that the terms used in the examples of this application are only used to explain the examples and are not intended to limit this application. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this application should have the common meanings understood by people with ordinary skills in the field to which this application belongs.

[0180] For example, the terms "first," "second," or "third," and similar terms used in the patent specification and claims of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprise" include the elements or objects listed after "include" or "comprise," and their equivalents, and do not exclude other elements or objects. Terms such as "upper," "lower," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, or B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0181] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A shift register unit, characterized in that: The shift register unit includes: a first control circuit, connected to the first input terminal, the second input terminal, the first control terminal, the second control terminal, the first power terminal, the pull-down node, and the pull-up node, respectively, and configured to control the connection and disconnection between the first control terminal and the pull-up node in response to a first input signal provided by the first input terminal, control the connection and disconnection between the second control terminal and the pull-up node in response to a second input signal provided by the second input terminal, and control the connection and disconnection between the first power terminal and the pull-up node in response to a potential of the pull-down node; a second control circuit, connected to the first control terminal, the second control terminal, the first clock terminal, the second clock terminal, and the intermediate node, respectively, and configured to control the connection and disconnection between the first clock terminal and the intermediate node in response to a first control signal provided by the first control terminal, and to control the connection and disconnection between the second clock terminal and the intermediate node in response to a second control signal provided by the second control terminal; a third control circuit, connected to the second power supply terminal, the pull-up node, the intermediate node, and the pull-down node, respectively, and configured to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the potential of the pull-up node, and to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the intermediate node; The output circuit is respectively connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal, the shift output terminal and the drive output terminal, and is used to control the on-off connection between the third clock terminal and the shift output terminal and the third clock terminal and the drive output terminal in response to the potential of the pull-up node, and to control the on-off connection between the first power supply terminal and the shift output terminal and the first power supply terminal and the drive output terminal in response to the potential of the pull-down node; wherein the shift output terminal is used to be connected to other stages of cascaded shift register units, and the drive output terminal is used to be connected to pixels in a display panel.

2. The shift register unit according to claim 1, wherein: The output circuit includes: a first output sub-circuit, connected to the pull-up node, the pull-down node, the third clock terminal, the first power terminal, and the driving output terminal, respectively, and configured to control the connection and disconnection between the third clock terminal and the driving output terminal in response to the potential of the pull-up node, and to control the connection and disconnection between the first power terminal and the driving output terminal in response to the potential of the pull-down node; The second output sub-circuit is respectively connected to the pull-up node, the pull-down node, the third clock terminal, the first power supply terminal and the shift output terminal, and is used to control the connection and disconnection of the third clock terminal and the shift output terminal in response to the potential of the pull-up node, and to control the connection and disconnection of the first power supply terminal and the shift output terminal in response to the potential of the pull-down node.

3. The shift register unit according to claim 2, wherein: The first output sub-circuit includes: a first transistor and a second transistor; the second output sub-circuit includes: a third transistor and a fourth transistor; The gate of the first transistor is connected to the pull-up node, the first electrode of the first transistor is connected to the third clock terminal, and the second electrode of the first transistor is connected to the driving output terminal; The gate of the second transistor is connected to the pull-down node, the first electrode of the second transistor is connected to the first power supply terminal, and the second electrode of the second transistor is connected to the driving output terminal; The gate of the third transistor is connected to the pull-up node, the first electrode of the third transistor is connected to the third clock terminal, and the second electrode of the third transistor is connected to the shift output terminal; A gate of the fourth transistor is connected to the pull-down node, a first electrode of the fourth transistor is connected to the first power supply terminal, and a second electrode of the fourth transistor is connected to the shift output terminal.

4. The shift register unit according to claim 3, wherein: The channel width-to-length ratio of the third transistor is different from the channel width-to-length ratio of the first transistor; and / or the channel width-to-length ratio of the fourth transistor is different from the channel width-to-length ratio of the second transistor.

5. The shift register unit according to claim 4, wherein: The ratio of the channel width-to-length ratio of the third transistor to the channel width-to-length ratio of the first transistor is greater than 80%; the ratio of the channel width-to-length ratio of the fourth transistor to the channel width-to-length ratio of the second transistor is greater than 80%.

6. The shift register unit according to claim 3, wherein: The first control circuit, the third control circuit, the output circuit and the second control circuit are sequentially arranged along a first direction and in a direction close to the driving output end; Furthermore, the third transistor and the first transistor in the output circuit are arranged in sequence along a second direction, and the fourth transistor and the second transistor are arranged in sequence along the first direction, wherein the first direction intersects with the second direction.

7. The shift register unit according to any one of claims 1 to 6, characterized in that: The third control circuit includes: a first control subcircuit, connected to the pull-up node, the first power supply terminal, and the pull-down node, respectively, and configured to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the potential of the pull-up node; The second control subcircuit is connected to the intermediate node, the second power supply terminal and the pull-down node respectively, and is used to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the intermediate node.

8. The shift register unit according to claim 7, wherein: The first control subcircuit includes: a fifth transistor; the second control subcircuit includes: a sixth transistor; The gate of the fifth transistor is connected to the pull-up node, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the pull-down node; A gate of the sixth transistor is connected to the intermediate node, a first electrode of the sixth transistor is connected to the second power supply terminal, and a second electrode of the sixth transistor is connected to the pull-down node.

9. The shift register unit according to any one of claims 1 to 6, characterized in that: The second control circuit includes: a seventh transistor and an eighth transistor; The gate of the seventh transistor is connected to the first control terminal, the first electrode of the seventh transistor is connected to the first clock terminal, and the second electrode of the seventh transistor is connected to the intermediate node; A gate of the eighth transistor is connected to the second control terminal, a first electrode of the eighth transistor is connected to the second clock terminal, and a second electrode of the eighth transistor is connected to the intermediate node.

10. The shift register unit according to any one of claims 1 to 6, characterized in that: The first control circuit includes: a ninth transistor, a tenth transistor, and an eleventh transistor; The gate of the ninth transistor is connected to the first input terminal, the first electrode of the ninth transistor is connected to the first control terminal, and the second electrode of the ninth transistor is connected to the pull-up node; The gate of the tenth transistor is connected to the second input terminal, the first electrode of the tenth transistor is connected to the second control terminal, and the second electrode of the tenth transistor is connected to the pull-up node; A gate of the eleventh transistor is connected to the pull-down node, a first electrode of the eleventh transistor is connected to the first power supply terminal, and a second electrode of the eleventh transistor is connected to the pull-up node.

11. The shift register unit according to any one of claims 1 to 6, characterized in that: The pull-up node includes: a first pull-up node and a second pull-up node, the first control circuit, the second control circuit, and the third control circuit are all connected to the first pull-up node, and the output circuit is connected to the second pull-up node; and the shift register unit further includes: The fourth control circuit is connected to the second power supply terminal, the first pull-up node and the second pull-up node respectively, and is used to control the on and off of the first pull-up node and the second pull-up node in response to a second power supply signal provided by the second power supply terminal.

12. The shift register unit according to claim 11, wherein: The shift register unit further includes at least one of the following circuits: a first reset circuit, connected to a reset control terminal, the first power terminal, and the first pull-up node, respectively, and configured to control the connection and disconnection between the first power terminal and the first pull-up node in response to a reset control signal provided by the reset control terminal; a second reset circuit, connected to the touch enable terminal, the first power supply terminal, and the drive output terminal, respectively, and configured to control the on / off connection between the first power supply terminal and the drive output terminal in response to a touch enable signal provided by the touch enable terminal; a first storage circuit connected between the second pull-up node and the driving output terminal and configured to control the potential of the second pull-up node; The second storage circuit is connected between the pull-down node and the first power supply terminal and is used to control the potential of the pull-down node.

13. The shift register unit according to claim 12, wherein: The fourth control circuit includes a twelfth transistor; the first reset circuit includes a thirteenth transistor; the second reset circuit includes a fourteenth transistor; the first storage circuit includes a first capacitor; the second storage circuit includes a second capacitor; The gate of the twelfth transistor is connected to the second power supply terminal, the first electrode of the twelfth transistor is connected to the first pull-up node, and the first electrode of the twelfth transistor is connected to the second pull-up node; The gate of the thirteenth transistor is connected to the reset control terminal, the first electrode of the thirteenth transistor is connected to the first power supply terminal, and the second electrode of the thirteenth transistor is connected to the first pull-up node; The gate of the fourteenth transistor is connected to the touch enable terminal, the first electrode of the fourteenth transistor is connected to the first power supply terminal, and the second electrode of the fourteenth transistor is connected to the driving output terminal; One end of the first capacitor is connected to the driving output end, and the other end of the first capacitor is connected to the second pull-up node; One end of the second capacitor is connected to the first power supply end, and the other end of the first capacitor is connected to the pull-down node.

14. A gate drive circuit, characterized in that: The gate driving circuit comprises: a plurality of cascaded shift register units according to any one of claims 1 to 13; The shift output end of each shift register unit is connected to the second input end of the cascaded previous shift register unit, and the driving output end of each shift register unit is connected to the first input end of the cascaded subsequent shift register unit.

15. A display device, characterized in that: The display device comprises: a display panel, and the gate driving circuit according to claim 14; the display panel comprises a plurality of pixels; The gate driving circuit is connected to the plurality of pixels via a driving output terminal and is used for transmitting a gate driving signal to the plurality of pixels to drive the plurality of pixels to emit light.

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