Data acquisition circuit, data acquisition device and automobile

Abstract

The embodiment of the utility model provides a data acquisition circuit, a data acquisition device and an automobile, belongs to the field of data acquisition, and particularly relates to the data acquisition circuit, the data acquisition device and the automobile, and the circuit comprises a GPIO acquisition interface which is used for receiving an external current signal; the internal balancing module is electrically connected with the GPIO acquisition interface and is used for conducting the external current signal when the external current signal is at a high level or releasing the internal current signal when the external current signal is at a low level; and the current acquisition module is electrically connected with the internal balancing module and is used for acquiring a current signal released by the internal balancing module and determining target data according to the current signal released by the internal balancing module. According to the embodiment, an acquisition circuit with consistent power consumption can be constructed.

Description

Technical Field

[0001] The utility model relates to the field of data acquisition, in particular to a data acquisition circuit, a data acquisition device and a car. Background Art

[0002] Currently, when using multiple AFE chips to collect data, if the number of connected acquisition circuits is inconsistent, each AFE needs to be balanced according to the power consumption of the maximum number of connected acquisition circuits. Otherwise, voltage differences will occur between the battery cells. If the voltage difference is too large, the terminal will report a fault, affecting vehicle operation. Designing the power consumption of each AFE individually increases the complexity of the entire battery management system design. Therefore, how to build acquisition circuits with consistent power consumption has become a pressing issue. Utility Model Content

[0003] The main purpose of the embodiments of the present application is to propose a data acquisition circuit, a data acquisition device and a car, aiming to construct an acquisition circuit with consistent power consumption.

[0004] To achieve the above objectives, a first aspect of an embodiment of the present application provides a data acquisition circuit, comprising:

[0005] GPIO acquisition interface, used to receive external current signals;

[0006] an internal balancing module, electrically connected to the GPIO acquisition interface, and configured to conduct the external current signal when the external current signal is at a high level, or release the internal current signal when the external current signal is at a low level;

[0007] The internal balancing module includes a first control MOS transistor, a second control MOS transistor, a signal control unit, a balancing voltage dividing unit, a first conduction MOS transistor, and a second conduction MOS transistor;

[0008] The source of the first conductive MOS transistor is electrically connected to a power supply, and the drain is electrically connected to the source of the second conductive MOS transistor;

[0009] The drain of the second conduction MOS transistor is grounded and electrically connected to the source of the second control MOS transistor;

[0010] The signal control unit is electrically connected to the gate of the first control MOS transistor and the gate of the second control MOS transistor, and is used to release the internal trim signal when the external current signal is at a low level, so as to turn on the first control MOS transistor and the second control MOS transistor;

[0011] The drain of the second control MOS tube is electrically connected to the trimming voltage dividing unit, and is used for conducting current to the trimming voltage dividing unit after receiving the internal trimming signal;

[0012] The source of the first control MOS transistor is electrically connected to a power supply, and the drain is electrically connected to the trimming voltage divider unit, and is used for conducting current to the trimming voltage divider unit after receiving the internal trimming signal;

[0013] The balancing voltage dividing unit is used to divide the voltage and release the internal current signal;

[0014] The current acquisition module is electrically connected to the internal balancing module and is used to acquire the current signal released by the internal balancing module and determine the target data according to the current signal released by the internal balancing module.

[0015] In some embodiments, the circuit includes at least one GPIO acquisition interface and at least one internal balancing module, and one GPIO acquisition interface is electrically connected to one internal balancing module.

[0016] In some embodiments, the balancing voltage dividing unit includes a first balancing resistor and a second balancing resistor;

[0017] The first balancing resistor is electrically connected to the first control MOS tube and the current acquisition module;

[0018] The second balancing resistor is electrically connected to the second control MOS tube and the current acquisition module.

[0019] In some embodiments, the current acquisition module includes a circuit protection unit and a current acquisition unit;

[0020] The circuit protection unit is electrically connected to the first balancing resistor and the second balancing resistor, and is used to protect the circuit and conduct current;

[0021] The current acquisition unit is electrically connected to the circuit protection unit, and is used to determine the target data according to the current signal released by the internal balancing module.

[0022] In some embodiments, the circuit protection unit includes a first bidirectional breakdown diode and a first diode;

[0023] The first bidirectional breakdown diode is electrically connected to the first balancing resistor, the second balancing resistor and the current acquisition unit;

[0024] The first diode is electrically connected to the first balancing resistor, the second balancing resistor and the current acquisition unit.

[0025] In some embodiments, the circuit further includes a data acquisition module electrically connected to the GPIO acquisition interface, configured to acquire target data and release the external current signal based on the target data.

[0026] In some embodiments, the data acquisition module includes a data acquisition unit and a data voltage dividing unit;

[0027] The data acquisition unit is used to acquire the target data and determine different currents based on the target data;

[0028] The data voltage divider unit is electrically connected to the data acquisition unit and the GPIO acquisition interface, and is used to connect the current and divide the voltage of the data acquisition unit, and output the external current signal representing the target data based on the current released by the data acquisition unit.

[0029] In some embodiments, the data acquisition unit includes a thermistor electrically connected to a power supply and the data voltage divider unit, and the thermistor is used to acquire temperature and determine different resistance values ​​based on the temperature.

[0030] To achieve the above-mentioned purpose, a second aspect of an embodiment of the present application provides a data acquisition device, comprising:

[0031] Data display circuit;

[0032] The data acquisition circuit as described in the first aspect above.

[0033] To achieve the above objectives, a third aspect of the embodiments of the present application provides an automobile, comprising:

[0034] body;

[0035] Car door;

[0036] Battery;

[0037] Vehicle control system, the vehicle control system includes the data acquisition device described in the second aspect above

[0038] The data acquisition circuit, data acquisition device, and automobile illustrated in the embodiments of the present application receive an external current signal via a GPIO acquisition interface and transmit the external current signal to an internal trim module. When the external current signal is at a low level (i.e., the GPIO acquisition interface is not connected to an external circuit), a signal control unit in the internal trim module controls the first and second control MOS transistors to conduct, and releases the internal current signal to the current acquisition module via the first conducting MOS transistor, the second conducting MOS transistor, the first control MOS transistor, the second control MOS transistor, and the trim voltage divider unit, thereby putting the current acquisition module into an operating state. When the external current signal is at a high level (i.e., the GPIO acquisition interface is connected to an external circuit), the signal control unit in the internal trim module controls the first and second control MOS transistors to not conduct, causing current to flow through the internal trim module and the current acquisition module. The current acquisition module determines target data based on the collected current, thereby ensuring that the data acquisition circuit is in an operating state even when no external circuit is connected. This, in turn, controls the power consumption of the AFE. Furthermore, when multiple AFE chips operate together, the power consumption of the multiple AFE chips can be set to be consistent, thereby constructing a data acquisition circuit with consistent power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a module block diagram of a data acquisition circuit provided in an embodiment of the present application;

[0040] Figure 2 yes Figure 1 Circuit diagram of the internal trim module;

[0041] Figure 3 yes Figure 1 A circuit schematic diagram of an internal balancing module provided in another embodiment;

[0042] Figure 4 is a module block diagram of a data acquisition circuit provided in another embodiment of the present application;

[0043] Figure 5 yes Figure 4 Circuit diagram of the medium current protection unit;

[0044] Figure 6 is a module block diagram of a data acquisition circuit provided in another embodiment of the present application;

[0045] Figure 7 is a module block diagram of a data acquisition circuit provided in another embodiment of the present application;

[0046] Figure 8 yes Figure 7 The circuit schematic diagram of the data acquisition unit;

[0047] Figure 9is a circuit schematic diagram of a data acquisition circuit provided in another embodiment of the present application;

[0048] Figure 10 This is a module block diagram of the data acquisition device provided in an embodiment of the present application;

[0049] Figure 11 This is a module block diagram of the automobile provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0051] It should be noted that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and so on, in the specification, claims, and drawings, are used to distinguish similar items and are not necessarily used to describe a specific sequence or precedence.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0053] The data acquisition circuit, data acquisition device, and automobile provided in the embodiments of the present application are specifically illustrated through the following embodiments. First, the data acquisition circuit in the embodiments of the present application is described.

[0054] The data acquisition circuit provided in the embodiments of the present application can be applied to a terminal or a server, or can be software running on a terminal or a server. In some embodiments, the terminal can be a smartphone, tablet computer, laptop computer, desktop computer, etc.; the server can be configured as an independent physical server, or as a server cluster or distributed system composed of multiple physical servers, or as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application that implements the data acquisition circuit, etc., but is not limited to the above forms.

[0055] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments in which tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0056] See also Figure 1 and Figure 2 In some embodiments, the data acquisition circuit includes:

[0057] GPIO acquisition interface 100, used to receive external current signals;

[0058] The internal balancing module 200 is electrically connected to the GPIO acquisition interface 100 and is used to conduct the external current signal when the external current signal is at a high level, or release the internal current signal when the external current signal is at a low level;

[0059] The internal balancing module 200 includes a first control MOS transistor, a second control MOS transistor, a signal control unit, a balancing voltage dividing unit, a first conduction MOS transistor, and a second conduction MOS transistor;

[0060] The source of the first conductive MOS transistor is electrically connected to a power supply, and the drain is electrically connected to the source of the second conductive MOS transistor;

[0061] The drain of the second conduction MOS transistor is grounded and electrically connected to the source of the second control MOS transistor;

[0062] The signal control unit is electrically connected to the gate of the first control MOS transistor and the gate of the second control MOS transistor, and is used to release the internal balancing signal when the external current signal is at a low level, so as to turn on the first control MOS transistor and the second control MOS transistor;

[0063] The drain of the second control MOS tube is electrically connected to the trimming voltage divider unit, and is used for conducting current to the trimming voltage divider unit after receiving the internal trimming signal;

[0064] The source of the first control MOS transistor is electrically connected to the power supply, and the drain is electrically connected to the trimming voltage divider unit, and is used for conducting current to the trimming voltage divider unit after receiving the internal trimming signal;

[0065] The balancing voltage divider unit is used to divide the voltage and release the internal current signal;

[0066] The current acquisition module 300 is electrically connected to the internal balancing module 200 and is used to acquire the current signal released by the internal balancing module 200 and determine target data according to the current signal released by the internal balancing module 200 .

[0067] The beneficial effects of the embodiments of the present application include but are not limited to:

[0068] The external current signal is received through the GPIO acquisition interface 100 and transmitted to the internal balancing module 200. When the external current signal is at a low level, that is, when the GPIO acquisition interface 100 is not connected to an external circuit, the signal control unit of the internal balancing module 200 controls the first control MOS transistor and the second control MOS transistor to be turned on, and releases the internal current signal to the current acquisition module 300 through the first conduction MOS transistor, the second conduction MOS transistor, the first control MOS transistor, the second control MOS transistor and the balancing voltage divider unit, so that the current acquisition module 300 is in a working state. When the voltage is high, that is, when the GPIO acquisition interface 100 is connected to an external circuit, the signal control unit of the internal balancing module 200 controls the first control MOS transistor and the second control MOS transistor to be non-conductive, and the current flows through the internal balancing module 200 and the current acquisition module 300. The current acquisition module 300 determines the target data based on the collected current, thereby ensuring that the data acquisition circuit is in an operating state even when there is no external circuit. In other words, the power consumption of the AFE is controlled, and further, when multiple AFE chips work together, the power consumption of the multiple AFE chips can be set to be consistent, thereby constructing a data acquisition circuit with consistent power consumption.

[0069] See also Figure 1 In some embodiments, the circuit includes at least one GPIO acquisition interface 100 and at least one internal balancing module 200 , and one GPIO acquisition interface 100 is electrically connected to one internal balancing module 200 .

[0070] The advantage of this embodiment is that by equipping each GPIO acquisition interface 100 with an internal balancing module 200, when the acquisition quantities of multiple AFE acquisition chips are inconsistent, the internal balancing module 200 can be used to make the power consumption of each AFE consistent, thereby realizing a data acquisition circuit with consistent power consumption.

[0071] For example, in one embodiment, the first AFE chip needs to collect the temperatures of three battery packs, while the second AFE chip needs to collect the temperature of one battery pack. The first GPIO acquisition interface 100 of the second AFE chip collects the temperatures, while the second and third GPIO acquisition interfaces 100 and 100 do not need to collect temperatures. The internal balancing module 200 of the second GPIO acquisition interface 100 releases the second internal current signal, while the internal balancing module 200 of the third GPIO acquisition interface 100 releases the third internal current signal. This allows the second AFE chip to collect three current signals, consistent with the first AFE chip's operating state. This ensures consistent power consumption for the first and second AFE chips, eliminating the need to set power consumption for each AFE chip separately.

[0072] See also Figure 1 and Figure 3 In some embodiments, the voltage balancing unit includes a first balancing resistor and a second balancing resistor;

[0073] The first balancing resistor is electrically connected to the first control MOS tube and the current acquisition module 300;

[0074] The second balancing resistor is electrically connected to the second control MOS tube and the current acquisition module 300 .

[0075] The advantage of this embodiment is that by controlling the first control MOS tube to be closed, current flows through the first balancing resistor, and by controlling the second control MOS tube to be closed, current flows through the second balancing resistor, the first balancing resistor and the second balancing resistor divide the voltage and release the internal current signal.

[0076] See also Figure 4 , in some embodiments, the current acquisition module 300 includes a circuit protection unit 310 and a current acquisition unit 320;

[0077] The circuit protection unit 310 is electrically connected to the first balancing resistor and the second balancing resistor, and is used to protect the circuit and conduct current;

[0078] The current acquisition unit 320 is electrically connected to the circuit protection unit 310 and is used to determine target data according to the current signal released by the internal balancing module 200 .

[0079] The advantage of this embodiment is that the first balancing resistor and the second balancing resistor are electrically connected to each other and protected by the circuit protection unit 310, so as to limit the current flowing into the current acquisition unit 320, and the current acquisition unit 320 determines the target data based on the acquired current, thereby realizing that the current acquisition unit 320 determines the target data based on the acquired current when protecting the circuit.

[0080] See also Figure 4 and Figure 5 , in some embodiments, the circuit protection unit 310 includes a first bidirectional breakdown diode and a first diode;

[0081] The first bidirectional breakdown diode is electrically connected to the first balancing resistor, the second balancing resistor and the current acquisition unit 320;

[0082] The first diode is electrically connected to the first balancing resistor, the second balancing resistor, and the current acquisition unit 320 .

[0083] The advantage of this embodiment is that the direction of the current flowing into the current collection channel is limited by the first diode, and the circuit is protected from static electricity and surge current by the first bidirectional breakdown diode, thereby protecting the circuit.

[0084] See also Figure 6 In some embodiments, the circuit further includes a data acquisition module 400 electrically connected to the GPIO acquisition interface 100 for acquiring target data and releasing an external current signal based on the target data.

[0085] The advantage of this embodiment is that target data is collected through the data acquisition module 400, and an external current signal is released based on the target data. The external current signal flows through the internal balancing module 200 through the GPIO acquisition interface 100. When the internal balancing module 200 receives a high-level external current signal, the signal control unit controls the first control MOS transistor and the second control MOS transistor to not be closed, thereby allowing the external current signal to flow to the current acquisition unit 320 through the circuit protection unit 310. The current acquisition unit 320 determines the target data based on the external current signal.

[0086] See also Figure 7 ,In some embodiments, the data acquisition module 400 includes a data acquisition unit 410 and a data pressure dividing unit 420;

[0087] The data acquisition unit 410 is used to acquire target data and determine different currents based on the target data;

[0088] The data voltage divider unit 420 is electrically connected to the data acquisition unit 410 and the GPIO acquisition interface 100 , and is used to connect current and divide the voltage of the data acquisition unit 410 , and output an external current signal representing target data based on the current released by the data acquisition unit 410 .

[0089] The advantage of this embodiment is that the data acquisition unit 410 is used to collect target data, and different currents are determined based on the target data, and the data acquisition unit 410 and the GPIO acquisition interface 100 are electrically connected through the data voltage divider unit 420. The data voltage divider unit 420 outputs an external current signal representing the target data based on the current released by the data acquisition unit 410, thereby realizing the conversion of the target data into the external current signal. After the current acquisition unit 320 collects the external current signal, the target data is determined, thereby realizing the collection of the target data.

[0090] See also Figure 1 and Figure 7 In some embodiments, the data acquisition unit 410 includes a thermistor, which is electrically connected to the power supply and the data voltage divider unit 420. The thermistor is used to collect temperature and determine different resistance values ​​based on the temperature.

[0091] The advantage of this embodiment is that different resistance values ​​are determined at different temperatures by the thermistor, and the data voltage divider unit 420 divides different voltages based on the different resistance values, thereby determining the external current signal released to the current acquisition module 300 based on the temperature. After receiving the external current signal, the current acquisition unit 320 determines the target temperature and realizes the acquisition of the target temperature.

[0092] See also Figure 7 and Figure 9 In some embodiments, after the GPIO acquisition interface 100 is electrically connected to the data acquisition module 400, the signal control unit controls the first control MOS tube and the second control MOS tube to not be closed, so that the external current signal flows into the current acquisition unit 320 to realize the acquisition of the target temperature.

[0093] See also Figure 10 , an embodiment of the present application also provides a data acquisition device, including a data display circuit and a data acquisition circuit.

[0094] The specific implementation of the data acquisition circuit in the data acquisition device is basically the same as the specific embodiment of the data acquisition circuit described above, and will not be repeated here.

[0095] See also Figure 11 , an embodiment of the present application also provides a car, including a body, doors, a battery and a vehicle control system, the vehicle control system including a battery collection device.

[0096] The specific implementation of the vehicle control system in the car is basically the same as the specific embodiment of the above-mentioned data acquisition device, and will not be repeated here.

[0097] The data acquisition circuit, data acquisition device and automobile provided in the embodiment of the present application receive an external current signal through the GPIO acquisition interface 100 and transmit the external current signal to the internal balancing module 200. When the external current signal is at a low level, that is, when the GPIO acquisition interface 100 is not connected to an external circuit, the signal control unit of the internal balancing module 200 controls the first control MOS transistor and the second control MOS transistor to be turned on, and releases the internal current signal to the current acquisition module 300 through the first conductive MOS transistor, the second conductive MOS transistor, the first control MOS transistor, the second control MOS transistor and the balancing voltage divider unit, so that the current acquisition module 300 processes the current. In the working state, when the external current signal is at a high level, that is, when the GPIO acquisition interface 100 is connected to an external circuit, the signal control unit of the internal balancing module 200 controls the first control MOS tube and the second control MOS tube to be non-conductive, and the current flows through the internal balancing module 200 and the current acquisition module 300. The current acquisition module 300 determines the target data based on the collected current, thereby ensuring that the data acquisition circuit is in a working state even when there is no external circuit, that is, the power consumption of the AFE is controlled, and further ensuring that the power consumption of the multiple AFE chips can be set to be consistent when the multiple AFE chips work together, that is, a data acquisition circuit with consistent power consumption is constructed.

[0098] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0099] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0100] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0101] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0102] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0103] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0104] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0105] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0106] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A data acquisition circuit, characterized in that: The circuit comprises: GPIO acquisition interface, used to receive external current signals; an internal balancing module, electrically connected to the GPIO acquisition interface, and configured to conduct the external current signal when the external current signal is at a high level, or release the internal current signal when the external current signal is at a low level; The internal balancing module includes a first control MOS transistor, a second control MOS transistor, a signal control unit, a balancing voltage dividing unit, a first conduction MOS transistor, and a second conduction MOS transistor; The source of the first conductive MOS transistor is electrically connected to a power supply, and the drain is electrically connected to the source of the second conductive MOS transistor; The drain of the second conduction MOS transistor is grounded and electrically connected to the source of the second control MOS transistor; The signal control unit is electrically connected to the gate of the first control MOS transistor and the gate of the second control MOS transistor, and is used to release the internal trim signal when the external current signal is at a low level, so as to turn on the first control MOS transistor and the second control MOS transistor; The drain of the second control MOS tube is electrically connected to the trimming voltage dividing unit, and is used for conducting current to the trimming voltage dividing unit after receiving the internal trimming signal; The source of the first control MOS transistor is electrically connected to a power supply, and the drain is electrically connected to the trimming voltage divider unit, and is used for conducting current to the trimming voltage divider unit after receiving the internal trimming signal; The balancing voltage dividing unit is used to divide the voltage and release the internal current signal; The current acquisition module is electrically connected to the internal balancing module and is used to acquire the current signal released by the internal balancing module and determine the target data according to the current signal released by the internal balancing module.

2. The circuit according to claim 1, wherein: The circuit includes at least one GPIO acquisition interface and at least one internal balancing module, and one GPIO acquisition interface is electrically connected to one internal balancing module.

3. The circuit according to claim 1, wherein: The balancing voltage dividing unit includes a first balancing resistor and a second balancing resistor; The first balancing resistor is electrically connected to the first control MOS tube and the current acquisition module; The second balancing resistor is electrically connected to the second control MOS tube and the current acquisition module.

4. The circuit according to claim 3, characterized in that The current acquisition module includes a circuit protection unit and a current acquisition unit; The circuit protection unit is electrically connected to the first balancing resistor and the second balancing resistor, and is used to protect the circuit and conduct current; The current acquisition unit is electrically connected to the circuit protection unit, and is used to determine the target data according to the current signal released by the internal balancing module.

5. The circuit according to claim 4, characterized in that The circuit protection unit includes a first bidirectional breakdown diode and a first diode; The first bidirectional breakdown diode is electrically connected to the first balancing resistor, the second balancing resistor and the current acquisition unit; The first diode is electrically connected to the first balancing resistor, the second balancing resistor and the current acquisition unit.

6. The circuit according to claim 1, wherein: The circuit further includes a data acquisition module electrically connected to the GPIO acquisition interface, configured to acquire target data and release the external current signal based on the target data.

7. The circuit according to claim 6, characterized in that The data acquisition module includes a data acquisition unit and a data pressure dividing unit; The data acquisition unit is used to acquire the target data and determine different currents based on the target data; The data voltage divider unit is electrically connected to the data acquisition unit and the GPIO acquisition interface, and is used to connect current and divide the voltage of the data acquisition unit, and output the external current signal representing the target data based on the current released by the data acquisition unit.

8. The circuit according to claim 7, characterized in that The data acquisition unit includes a thermistor, which is electrically connected to a power supply and the data voltage divider unit. The thermistor is used to acquire temperature and determine different resistance values ​​based on the temperature.

9. A data acquisition device, characterized in that: include: Data display circuit; The data acquisition circuit according to any one of claims 1 to 8.

10. A new energy vehicle, characterized in that: include: body; Car door; Battery; A vehicle control system, comprising the data acquisition device according to claim 9.

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