Configuration switching device and server

Abstract

The utility model discloses a configuration switching device and a server, and relates to the technical field of servers, the configuration switching device comprises a mainboard module, the mainboard module comprises a processor, and the processor is used for processing data; the switch module comprises at least one switch, the switch is connected with the processor, and the switch is used for data transmission; the power supply module is respectively connected with the mainboard module and the switch module and sends a configuration switching signal to the processor and the at least one switch, and the configuration switching signal is generated based on a power line inserted into the power supply module and is used for indicating configuration files of the processor and the at least one switch. The problem that a configuration switching mechanism in the prior art is low in configuration accuracy is solved.

Description

Technical Field

[0001] The present application relates to the field of servers, and in particular to a configuration switching device and a server. Background Art

[0002] Servers often need to support a variety of configuration options to adapt to changing workloads and user needs. For example, during AI training, the high-concurrency communication and data exchange between multiple graphics processing units (GPUs) significantly increases the demand for high-speed Peripheral Component Interconnect Express (PCIe) bus bandwidth. A dual-uplink configuration can provide higher data transfer rates. In some I / O-intensive tasks or those that don't require high-intensity GPU computing, a single-uplink configuration can save costs, reduce power consumption, and reduce heat dissipation. Therefore, fast and flexible configuration switching within the server is necessary.

[0003] Related configuration switching mechanisms typically rely on software-level identification and management, but the accuracy and real-time nature of software identification cannot be guaranteed. Especially in high-load environments, processing delays can lead to configuration switching failures, impacting overall system performance and stability. Existing configuration switching mechanisms suffer from low configuration accuracy. Utility Model Content

[0004] The present application provides a configuration switching device and a server to at least solve the problem of low configuration accuracy in the configuration switching mechanism in the related art.

[0005] The present application provides a configuration switching device, comprising: a mainboard module, the mainboard module including a processor, the processor being configured to process data;

[0006] A switch module includes at least one switch, the switch is connected to the processor, and the switch is used for data transmission;

[0007] The power module is connected to the mainboard module and the switch module respectively, and sends a configuration switching signal to the processor and at least one switch, wherein the configuration switching signal is generated based on the power cord inserted into the power module, and the configuration switching signal is used to indicate the configuration files of the processor and at least one switch.

[0008] The present application also provides a server, comprising a chassis and the above-mentioned configuration switching device, wherein the configuration switching device is arranged in the chassis.

[0009] Through this application, the power module is connected to the mainboard module and the switch module. When the processor and switch are connected via a single link (single uplink), the processor can be connected to an additional board, and then the power module needs to be plugged into an additional power cord. When the processor and switch are connected via two links (dual uplink), the power module does not need to be plugged into an additional power cord. Therefore, the automatic adjustment of the firmware can be triggered by the change of the physical connection status, without relying on complex software detection logic, greatly simplifying the configuration switching process and reducing the error rate in manufacturing and on-site maintenance. Therefore, it can solve the technical problem of low configuration accuracy in the configuration switching mechanism in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 is a schematic diagram of a hardware environment of an optional configuration switching device according to an embodiment of the present application;

[0012] Figure 2 is a schematic diagram of an optional configuration switching device according to an embodiment of the present application;

[0013] Figure 3 is a schematic diagram of another optional configuration switching device according to an embodiment of the present application;

[0014] Figure 4 is a schematic diagram of an optional connection method of a configuration switching device according to an embodiment of the present application;

[0015] Figure 5 is a schematic diagram of another optional connection method of the configuration switching device according to an embodiment of the present application;

[0016] Figure 6 is a schematic diagram of an application example of an optional configuration switching device according to an embodiment of the present application;

[0017] Figure 7 This is a schematic diagram of an application example of another optional configuration switching device according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0019] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0020] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0021] According to one aspect of the embodiments of the present application, a configuration switching device is provided. As an optional implementation, the configuration switching device can be applied to, but is not limited to, Figure 1 In the hardware environment shown in FIG. The server may include but is not limited to one or more ( Figure 1 Only one is shown in the figure) Central Processing Unit (CPU) 11, Root Complex 12, Memory 13 for storing data and Switch 14. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the server side. Figure 1 More or fewer components than shown, or with Figure 1 The host side can be connected to one or more PCI Express devices (PCI Express Endpoint) 21 or a PCI Express-PCI Bridge 22 via a Peripheral Component Interconnect Express (PCIe) interface. Figure 1 The structure and connection method shown are for illustration only and do not limit the structure between the host side and the PCIe device.

[0022] The central processing unit (CPU) 11 is responsible for executing program instructions and processing data. In a PCIe architecture, the CPU is typically connected to the root complex. The CPU is connected to the root complex via a high-speed interconnect, such as a cache coherent interconnect or dedicated PCIe lanes, enabling fast data and instruction transfer.

[0023] The root multiplexer (ROOT Complex) 12 is the top layer of the PCIe bus hierarchy, serving as the interface between the CPU and the PCIe bus. The ROOT Complex may include multiple components, such as processor interfaces, DRAM interfaces, and input / output (I / O) controllers. In some systems, the ROOT Complex may be integrated within the CPU die or placed adjacent to the CPU die as a separate chip. The ROOT Complex manages PCIe bus transactions originating from the CPU, including memory accesses and device communications. In a PCIe system, data flows through the ROOT Complex, passing through a PCIe switch or other bridge device, and finally reaching the target PCIe device.

[0024] The memory 13 is a hardware component for storing data and programs, which can be a random access memory (RAM), a read-only memory (ROM), a static random access memory (SRAM), etc.

[0025] The switch 14 can be used to connect multiple devices and forward data packets. In the PCIe architecture, a switch is a PCIe switch that allows multiple PCIe devices to connect to a single PCIe port, expanding the system's connectivity. A PCIe switch can connect multiple PCIe end devices or root complexes, supporting more complex system topologies while managing the routing and forwarding of data packets between devices.

[0026] A PCIe device (PCI Express Endpoint) 21 is a device connected to the PCIe bus. PCIe endpoints often take the form of cards, such as graphics cards, solid-state drives (SSDs), and network cards. They communicate with the rest of the system through the PCIe interface. PCIe devices can send and receive data and can be either the initiator or the terminator of bus operations.

[0027] The PCI Express-PCI Bridge 22 allows communication between PCIe interfaces and legacy PCI (Peripheral Component Interconnect) or PCI-X (PCI eXtended) interfaces. This allows legacy PCIe devices to be used in newer PCIe systems, while also allowing legacy PCI systems to connect to PCIe devices. It supports compatibility between PCI Express and PCI / PCI-X, allowing PCI devices to be used in PCIe systems.

[0028] In an optional implementation, the switch can connect to the CPU in two different configuration modes. These two modes primarily affect PCIe lane allocation and overall system bandwidth management. They differ in the number of upstream connections the switch makes, and the resulting performance and configuration flexibility.

[0029] Specifically, in a single-uplink configuration, the PCIe switch chip connects to upstream devices (such as the CPU) via a set of PCIe links (a single uplink port). This means that all downstream devices connected through the switch (such as GPUs and NICs) share this set of links to communicate with the host. A single-uplink configuration is typically suitable for scenarios requiring fewer PCIe devices or low PCIe bandwidth requirements. Its advantages include simple configuration and relatively low cost.

[0030] In contrast, a dual-uplink configuration means the PCIe switch chip has two independent uplink ports, each connected to an upstream device via a set of PCIe links. This configuration provides higher bandwidth and improved data transfer capabilities because downstream devices can distribute the load and communicate with the host via two independent uplinks, avoiding the bandwidth bottleneck that can be caused by a single link. Dual-uplink configurations are suitable for high-performance computing, data center servers, and graphics-intensive applications, which often require large amounts of data transfer and processing power.

[0031] Therefore, to improve system flexibility, optimize resource usage, and ensure optimal system performance under both light and heavy loads, it is necessary to change the CPU and switch firmware settings based on the single and dual uplink modes.

[0032] The embodiment of the present application provides a configuration switching device, Figure 2 is a schematic diagram of an optional configuration switching device according to an embodiment of the present application; Figure 2 As shown, the configuration switching device includes:

[0033] Mainboard module 202, the mainboard module includes a processor 204, the processor 204 is used to process data;

[0034] A switch module 206 includes at least one switch 208, the switch 208 is connected to the processor, and the switch is used for data transmission;

[0035] The power supply module 210 is connected to the mainboard module and the switch module respectively, and sends a configuration switching signal to the processor and at least one switch, wherein the configuration switching signal is generated based on the power cord inserted into the power supply module, and the configuration switching signal is used to indicate the configuration file of the processor and at least one switch.

[0036] It should be noted that the motherboard module 202 is the core of the server hardware. It contains multiple key components, such as the processor, memory, and PCIe slots, and is responsible for coordinating and controlling all hardware operations within the server. The processor 204 within the motherboard module is the brain of the system, primarily responsible for data processing, instruction execution, system management, and scheduling. In server scenarios, the processor (CPU) is typically a high-performance multi-core processor capable of processing large amounts of data and running complex applications.

[0037] The switch module 206 is dedicated to PCIe data transmission. It includes at least one switch 208 ( Figure 2 (Only two are shown in the figure.) This switch 208 is connected to processor 204 and is responsible for managing and allocating PCIe links, enabling multiple devices (such as GPUs and network adapters) to efficiently communicate with the processor via the PCIe bus. In high-performance computing and data center environments, the performance and flexibility of PCIe switches are crucial to overall system performance.

[0038] The power module 210 is the server's power supply center, responsible for converting external power to the voltage required by the server's components. The power module not only connects to the motherboard module and switch module but also generates and sends configuration switching signals. These signals are generated based on whether a specific power cord is plugged into the power module. If a power cord is plugged in, the power module generates a configuration switching signal and sends it to the processor 204 and at least one switch 208. The configuration switching signal informs the processor and switch which configuration file to use for operation—single uplink configuration or dual uplink configuration.

[0039] The configuration switching signal, based on the power cable connection status, provides the processor and switch with immediate information about the current system configuration requirements. For example, when no power cable is connected to power module 210, the signal indicates that the system should switch to a dual-uplink configuration. This means that switch 208 will communicate with the processor via two independent PCIe links, providing higher data transmission bandwidth, suitable for high-performance computing and scenarios with a large number of PCIe devices connected. Conversely, when the power cable is connected, the signal indicates that the system should remain in a single-uplink configuration. In this case, the switch communicates with the processor via a single PCIe link, which is suitable for light loads or situations with few PCIe devices connected, thereby optimizing bandwidth usage and avoiding resource waste.

[0040] In an optional embodiment, after receiving the configuration switching signal, the settings of different devices can be switched, for example:

[0041] PCIe Switch firmware: The firmware in the PCIe switch chip manages PCIe link establishment, configuration, and fault recovery. When a configuration switch signal arrives, the PCIe SW adjusts its link configuration parameters, including link speed, width, and which processors or add-in cards to connect to. For example, if the system detects a dual uplink configuration requirement, the PCIe SW firmware automatically adjusts to support independent uplinks for both processors, increasing the transmission bandwidth of the PCIe device.

[0042] Basic Input / Output System (BIOS): The BIOS is the first system program that runs when a server boots up. It is responsible for hardware initialization and loading the operating system. The configuration switch signal affects the BIOS initialization process, enabling it to identify the current PCIe topology (single or dual uplinks) and adjust the boot sequence and other hardware parameters accordingly, ensuring that the server boots and runs according to the correct configuration.

[0043] Baseboard Management Controller (BMC): A BMC is a dedicated microcontroller used to remotely monitor and manage system hardware. Upon receiving a configuration switch signal, the BMC updates its hardware monitoring strategy, such as adjusting the monitoring range of PCIe links and monitoring changes in the power cord insertion status, to ensure that the system remains healthy and efficient in all configurations.

[0044] Complex Programmable Logic Device (CPLD): Commonly used to implement customized logic functions. Configuration switching signals prompt the CPLD firmware to reconfigure its input / output interfaces and possible logic circuits to support new PCIe configuration requirements, optimize signal transmission paths, and improve system data processing speed and responsiveness.

[0045] This allows a single version of firmware to support multiple configuration modes, reducing the complexity of firmware version management, saving storage space, and lowering the cost of firmware upgrades and maintenance. It also automatically detects and adapts to hardware configuration changes without manual intervention, increasing system flexibility and responsiveness, significantly improving operational efficiency, especially in on-site server deployment and operation environments.

[0046] Through this application, the power module is connected to the mainboard module and the switch module. When the processor and switch are connected via a single link (single uplink), the processor can be connected to an additional board, and then the power module needs to be plugged into an additional power cord. When the processor and switch are connected via two links (dual uplink), the power module does not need to be plugged into an additional power cord. Therefore, the automatic adjustment of the firmware can be triggered by the change of the physical connection status, without relying on complex software detection logic, greatly simplifying the configuration switching process and reducing the error rate in manufacturing and on-site maintenance. Therefore, it can solve the technical problem of low configuration accuracy in the configuration switching mechanism in the related art.

[0047] In an optional embodiment, the mainboard module and the switch module are connected to a signal output port of the power module, wherein the signal output port is used to output a configuration switching signal.

[0048] In this design, a specific signal output port connection exists between the motherboard module, the switch module, and the power module to monitor and respond to configuration switching signals. When a PCIe device is connected to the power module via the power connector, a signal is triggered. This signal is detected and interpreted by the CPLD and BMC on the motherboard module. Based on the state of this signal (high or low), the system automatically determines whether a dual uplink configuration switch is required.

[0049] When a PCIe card power cable is plugged in, the signal output port remains low, indicating that the system should be in a single uplink configuration. In this case, each CPU is connected to the PCIe Switch chip via a set of PCIe x16 links, directly supporting the connection of PCIe cards. This is suitable for scenarios with a small number of devices or less stringent bandwidth requirements.

[0050] Without a PCIe card power cable plugged in, the signal output port switches to a high level, signaling the need for a dual-uplink configuration. In this configuration, each PCIe switch chip connects to two CPUs via two sets of PCIe x16 links, supporting more PCIe devices and making it suitable for bandwidth-demanding scenarios such as high-performance computing and big data processing.

[0051] In an optional embodiment, the power module includes a plurality of power connectors, the power connectors being used to insert power lines;

[0052] The switch is connected to the processor and can be one of the following:

[0053] 1) At least one switch is connected to the processor through a set of links, and the number of power connectors inserted into the power cord is greater than or equal to a preset number;

[0054] 2) At least one switch is connected to the processor through two independent links, and the number of power connectors plugged into the power cords is less than a preset number.

[0055] It's important to note that the power supply module (PSM) is a crucial component of a computer system, responsible for converting external AC (or DC) input power into the stable DC power required by various system components. The PSM may include multiple power connectors designed to plug into power cables to power PCIe devices in the system (such as graphics cards and network adapters). The number and type of power connectors can be customized based on the number of devices supported and the power requirements of the system.

[0056] A switch refers to a PCIe switch chip. At least one PCIe switch chip connects to the processor via a set of links (i.e., a PCIe uplink), providing high data transfer rates. In this configuration, the number of power connectors plugged into the power cord must be greater than or equal to a predetermined number. This predetermined number can be set based on system design goals and the expected number of connected devices.

[0057] At least one PCIe switch chip is connected to the processor via two independent links, meaning each switch has two independent PCIe uplinks connected to the processor. In a dual-uplink configuration, the number of power connectors for plugging in power cables is less than the preset number.

[0058] In an optional implementation, the single and dual uplink configurations of the PCIeSwitch are automatically switched by detecting the number of power cables plugged into the power connector. The system can intelligently select the optimal link configuration based on the number of PCIe devices actually connected and their power requirements. This dynamic configuration mechanism enables the server to better adapt to diverse usage scenarios and future hardware expansion requirements, automatically adjusting the configuration without human intervention, and enhancing the flexibility and adaptability of the system. Automatic configuration switching reduces the number of firmware versions, simplifies firmware management, and reduces the error rate in the production process. At the same time, users can more quickly determine the source of the problem when encountering it, avoiding diagnostic difficulties caused by firmware version confusion, thereby effectively reducing the maintenance cost and complexity of the system.

[0059] Through the above-mentioned implementation of the present application, the uplink of the PCIe Switch chip is dynamically configured according to the power cord insertion status, thereby realizing flexible resource allocation, performance maximization and simplified maintenance of the server system in different usage scenarios.

[0060] In an optional embodiment, the power module includes a target power connector, and the target power connector is used to indicate the configuration switching signal;

[0061] The switch is connected to the processor and can be one of the following:

[0062] 1) At least one switch is connected to the processor via a set of links, and the target power connector is plugged into the power cord;

[0063] 2) At least one switch is connected to the processor through two independent links, and the target power connector is not plugged into the power cord.

[0064] It's important to note that the target power connector is part of the power module and primarily connects to the power cables of PCIe devices (such as graphics cards and network adapters). The target power connector isn't just a simple power inlet; it also generates configuration switching signals. When a power cable is plugged into the target power connector, the power module generates a configuration switching signal.

[0065] In an optional embodiment, when the target power connector is plugged into a power cable, the system automatically switches to a single uplink configuration. If the target power connector is not plugged into a power cable, the system switches to a dual uplink configuration, where each switch is connected to the processor via two independent links, which typically means that each switch has two PCIe x16 interfaces connected to the processor.

[0066] Figure 3 is a schematic diagram of another optional configuration switching device according to an embodiment of the present application; Figure 3As shown, the power module 210 includes multiple power connectors and a target power connector 302. The target power connector 302 can be connected to the motherboard module 202 and the switch module 206. When a power line is connected to the target power connector 302, it can be considered that there is a single uplink connection between the processor 204 and the switch 208. When no power line is connected, it can be considered that there are dual uplink connections between the processor 204 and the switch 208.

[0067] The switch intelligently identifies and switches the connection mode between the switch and the processor based on the target power connector status (power cord plugged in or not), automatically adapting to the system workload and the number of PCIe devices, ensuring optimal resource utilization. Using configuration switching signals instead of traditional firmware version management and multiple configuration files effectively reduces production errors, reduces rework caused by firmware burning errors, and improves production efficiency.

[0068] The above-described implementation of this application enables automatic identification of link configurations between switches and processors, thereby simplifying system management and maintenance while meeting diverse performance requirements, improving overall system efficiency and user experience. This design is particularly suitable for high-performance servers and data center environments that require dynamic hardware configuration adjustments based on different scenarios and loads, minimizing manual operations while maximizing system performance and resource utilization.

[0069] In an optional embodiment, the mainboard module includes multiple processors, each processor is connected to at least one switch; the power supply module includes multiple power connectors, each power connector is connected to a processor;

[0070] The switch is connected to the processor and includes at least one of the following:

[0071] 1) At least one switch is connected to the first processor via a set of links, and a power connector connected to the first processor is plugged into a power cord;

[0072] 2) At least one switch is connected to the second processor via two independent links, and a power connector connected to the second processor is not plugged into a power cable.

[0073] The motherboard module contains multiple processors, each connected to at least one PCIe (Peripheral Component Interconnect Express) switch to support high-speed data transmission and device expansion. The processors and switches are connected via one or more PCIe links, which transmit data and control signals between the processors and PCIe devices.

[0074] In an optional implementation, the connection modes between the same processor and multiple connected switches may be the same, for example, the switches connected to the first processor are all single uplink connected, and the switches connected to the second processor are all dual uplink connected.

[0075] Figure 4 is a schematic diagram of an optional connection method of a configuration switching device according to an embodiment of the present application; Figure 4 As shown, the first processor 402 has a single uplink connection to the switch it is connected to, leaving the free channel available for connecting external devices. Conversely, the second processor 404 has a dual uplink connection to the switch it is connected to. This shows that when the power connector connected to the processor is plugged into an external device's power cable, the processor and switch have a single uplink connection; when no external device's power cable is plugged in, the processor and switch have a dual uplink connection.

[0076] In an optional embodiment, the power module includes a plurality of power connectors, each of which is connected to a switch;

[0077] The switch is connected to the processor and includes at least one of the following:

[0078] 1) The first switch is connected to the processor via a set of links, and a power connector connected to the first switch is plugged into a power cord;

[0079] 2) The second switch is connected to the processor through two independent links, and the power connector connected to the second switch is not plugged into a power cable.

[0080] In an optional implementation, the connection modes of multiple switches connected to the same processor may be different. For example, a processor may be connected to a first switch via a single uplink mode and to a second switch via a dual uplink mode.

[0081] Figure 5 is a schematic diagram of another optional connection method of the configuration switching device according to an embodiment of the present application; Figure 5 As shown, the same processor can be connected to the switch in two different ways. If the power connector connected to the first switch 502 is connected to the power cable of an external device, the first switch 502 can be instructed to connect to the processor via a single uplink mode. If the power connector connected to the second switch 504 is not connected to a power cable, the second switch 504 can be instructed to connect to the processor via a dual uplink mode. Furthermore, the processor can be connected to both power connectors to determine how to configure the file.

[0082] In an optional embodiment, the mainboard module includes two processors, and the switch module includes four switches; the processors are connected to the two switches respectively, and the processors are not connected to the same switch; the switch and the processor are connected through a set of links, and each processor is connected to two external boards; the power cord of the external board is inserted into the power module.

[0083] It's important to note that the motherboard module is the core of the entire system, carrying all major computing and control functions. The motherboard module is equipped with two processors (for example, CPU0 and CPU1). These are core components of high-performance computing, responsible for executing various computing tasks and system management. These two processors interact with other hardware components, including but not limited to memory, I / O devices, and PCIe switch chips, through their respective buses and interfaces.

[0084] The switch module consists of four independent switches (SW_A, SW_B, SW_C, and SW_D). These switches, based on the PCI Express (PCIe) standard, extend and manage PCIe links, enabling multiple devices to share the limited PCIe resources on the motherboard. Each switch establishes a direct communication link with at least one processor on the motherboard, enabling high-speed data transmission and device interconnection.

[0085] In an optional implementation, each processor is connected to two independent switches. This arrangement ensures that each processor has sufficient PCIe link resources to communicate with external cards while reducing contention between processors. Processors are not connected to the same switch; for example, CPU0 might be connected to SW_A and SW_B, while CPU1 is connected to SW_C and SW_D. This configuration helps balance data transmission loads and prevents a single processor or switch from becoming a system bottleneck.

[0086] A set of links represents one or more PCI Express lanes, typically PCIe x16 links, and is used to provide high-bandwidth bidirectional data transfer capabilities. Each processor is connected to two switches via a set of these links, ensuring efficient data exchange with external cards. Each processor is directly connected to two external cards (such as GPUs, network adapters, or other PCIe devices). In addition to the indirect connection through the switch, direct connections provide additional high-bandwidth links, optimizing device performance and data transfer speeds.

[0087] External cards (such as GPUs or network adapters) are equipped with dedicated power cables that connect directly to the server's power supply module. Upon detecting the insertion of the external card's power cable, the power supply module generates a corresponding configuration switch signal, which is transmitted to the processor and switch to indicate the current system configuration (single or dual uplink). The insertion of a power cable not only ensures the device's power supply needs but also serves as a key indicator for the system to detect the external device, triggering subsequent adaptive configuration.

[0088] Figure 6 This is a schematic diagram illustrating an example application of an optional configuration switching device according to an embodiment of the present application. The entire server utilizes the same architecture, namely, a single uplink connection mode. As can be seen, due to the single uplink mode, the processor is connected to additional external devices, resulting in more connection lines at the power module. The power module can send signals to the motherboard module and switch module either by comparing a preset number or by using the target power connector.

[0089] In an optional embodiment, the mainboard module includes two processors, and the switch module includes four switches; the processors are connected to the two switches respectively, and the processors are not connected to the same switch; the switches and processors are connected through two sets of independent links.

[0090] In an optional implementation, CPU0 may establish connections with SW_A and SW_B, while CPU1 communicates with SW_C and SW_D. This layout ensures that each processor has an independent PCIe resource pool, which can efficiently support the PCIe devices to which it is connected and avoid resource contention. Not connecting the processors to the same switch ensures that data transmission between processors does not pass through the same switch, preventing the occurrence of communication bottlenecks and improving the overall throughput and reliability of the system. The connection between each switch and the processor uses two independent sets of PCIe links, usually PCIe x16 interfaces. This means that even within a single switch, each processor can have at least one independent high-speed data channel, further enhancing the parallelism and flexibility of data transmission.

[0091] Figure 7 This is a schematic diagram illustrating another example application of an optional configuration switching device according to an embodiment of the present application. The entire server utilizes the same architecture, namely, a dual-uplink connection mode. As can be seen, due to the dual-uplink mode, the processor is not connected to any external devices, and thus the connection cables at the power module function normally. The power module can send signals to the motherboard module and switch module, either by comparing a preset number or by using the target power connector.

[0092] In an optional implementation, each switch is connected to two external boards via a set of links; the links between the switch, the external boards, and the processor are 16-channel links.

[0093] It's important to note that a 16-lane PCI Express (PCIe) link is referred to as a PCIe x16 link. PCIe is a high-speed serial computer expansion bus standard designed to provide high-bandwidth, low-latency data transmission capabilities. Each switch is connected to two external cards via this 16-lane link, meaning each switch can simultaneously support the high-speed data transmission needs of two external cards.

[0094] Each lane of a PCIe x16 link provides an independent data transmission path, and the total bandwidth of a 16-lane link is 16 times that of a single lane. Under the PCIe 5.0 standard, the transmission rate of each lane can reach 32Gbps, so the total bandwidth of a 16-lane link can reach 512Gbps. The number of lanes in a PCIe link can be configured according to actual needs, allowing system designers to find a balance between high performance and cost. For example, for external boards with less high bandwidth requirements, fewer lanes can be used, while for high-bandwidth devices such as GPU accelerator cards, the full 16 lanes can be allocated.

[0095] Similarly, the link between the switch and the processor is a 16-lane PCIe x16 link. This design ensures that data transmitted from the external card to the processor can be transmitted at the maximum possible bandwidth, thereby improving the overall performance of the server, especially for applications that rely on high-speed data transmission, such as artificial intelligence computing, big data analysis, or high-performance network processing.

[0096] Through the above-described implementation of the present application, by using a high-speed 16-lane link, the data transmission rate is optimized, thereby minimizing the delay between the external board and the processor, and improving the overall system performance, especially in environments that require processing large amounts of data and high-speed computing. The link configuration can be adjusted according to the actual needs of the device, which means that the server can dynamically allocate PCIe resources based on the current workload, avoiding resource waste and improving the server's operating efficiency and cost-effectiveness.

[0097] An embodiment of the present application further provides a server, comprising a chassis and the above-mentioned configuration switching device, wherein the configuration switching device is disposed in the chassis.

[0098] In an optional embodiment, during the construction of a high-performance GPU server, after determining the GPU to be used (typically, GPUs have a fixed architecture), a separate server topology can be designed for each GPU. Connections to the GPU modules can be established via switch modules. Because the GPUs have a fixed architecture, their power connectors are also fixed. Therefore, after determining the number and location of power connectors corresponding to the GPU modules in use, the remaining power connectors can be set as target power connectors, or a preset number of power connectors corresponding to the GPU modules can be set. This allows the power modules to send configuration switching signals to switch the firmware settings of each device.

[0099] Professionals will further appreciate that, in conjunction with the units of the various examples described in the embodiments disclosed herein, in order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components of each example according to function. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0100] The above is a detailed introduction to a configuration switching device and server provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A configuration switching device, characterized in that: include: A mainboard module, the mainboard module including a processor, the processor being configured to process data; A switch module, the switch module including at least one switch, the switch being connected to the processor and being used for data transmission; A power supply module is connected to the mainboard module and the switch module, respectively, and sends a configuration switching signal to the processor and the at least one switch, wherein the configuration switching signal is generated based on a power cord inserted into the power supply module, and the configuration switching signal is used to indicate a configuration file of the processor and the at least one switch.

2. The configuration switching device according to claim 1, wherein: The mainboard module and the switch module are connected to a signal output port of the power module, wherein the signal output port is used to output the configuration switching signal.

3. The configuration switching device according to claim 2, characterized in that: The power module includes a plurality of power connectors, and the power connectors are used to be inserted into the power cord; The switch is connected to the processor, and includes one of the following: The at least one switch is connected to the processor via a set of links respectively, and the number of the power connectors inserted into the power lines is greater than or equal to a preset number; The at least one switch is connected to the processor via two independent links respectively, and the number of the power connectors inserted into the power lines is less than a preset number.

4. The configuration switching device according to claim 2, wherein: The power module includes a target power connector, and the target power connector is used to indicate the configuration switching signal; The switch is connected to the processor, and includes one of the following: The at least one switch is connected to the processor via a set of links respectively, and the target power connector is plugged into the power cord; The at least one switch is connected to the processor via two independent links respectively, and the target power connector is not plugged into the power cord.

5. The configuration switching device according to claim 1, wherein: The mainboard module includes a plurality of processors, each of which is connected to at least one switch; The power module includes a plurality of power connectors, each of which is connected to the processor; The switch is connected to the processor, and includes at least one of the following: The at least one switch is connected to the first processor via a set of links respectively, and the power connector connected to the first processor is plugged into the power line; The at least one switch is connected to the second processor via two independent links respectively, and the power connector connected to the second processor is not plugged into the power cord.

6. The configuration switching device according to claim 1, wherein: The power module includes a plurality of power connectors, each of which is connected to the switch; The switch is connected to the processor, and includes at least one of the following: A first switch is connected to the processor via a set of links, and the power connector connected to the first switch is plugged into the power line; The second switch is connected to the processor through two independent links, and the power connector connected to the second switch is not plugged into the power cord.

7. The configuration switching device according to claim 1, characterized in that: The mainboard module includes two processors, and the switch module includes four switches; The processors are respectively connected to two switches, and the processors are not connected to the same switch; The switch is connected to the processor via a set of links, and each processor is connected to two external boards; The power cord of the external board is inserted into the power module.

8. The configuration switching device according to claim 1, wherein: The mainboard module includes two processors, and the switch module includes four switches; The processors are respectively connected to two switches, and the processors are not connected to the same switch; The switch is connected to the processor via two sets of independent links.

9. The configuration switching device according to claim 7 or 8, characterized in that: Each of the switches is connected to two external boards via a set of links; The link between the switch, the external board and the processor is a 16-channel link.

10. A server, characterized in that: The invention comprises a chassis and the configuration switching device according to any one of claims 1 to 9, wherein the configuration switching device is arranged in the chassis.

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